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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.29 96.81 100.00 96.79 98.71 99.52 93.25


Total test records in report: 915
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T798 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.488595847 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2024316349 ps
T27 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3699012320 Jun 07 08:28:19 PM PDT 24 Jun 07 08:28:52 PM PDT 24 22500732246 ps
T28 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2320211261 Jun 07 08:28:13 PM PDT 24 Jun 07 08:29:02 PM PDT 24 42485619236 ps
T272 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2682125856 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2123722745 ps
T799 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.335270578 Jun 07 08:28:33 PM PDT 24 Jun 07 08:28:48 PM PDT 24 2027341204 ps
T800 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1791053115 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:39 PM PDT 24 2015548108 ps
T29 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2318611190 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:28 PM PDT 24 2088880727 ps
T30 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1534227069 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:30 PM PDT 24 6074438937 ps
T801 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.830010303 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2112779659 ps
T802 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2850126458 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:28 PM PDT 24 2013846748 ps
T301 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.524156064 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:29 PM PDT 24 2068063345 ps
T18 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.4019900008 Jun 07 08:28:06 PM PDT 24 Jun 07 08:28:28 PM PDT 24 10157495546 ps
T320 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3631673320 Jun 07 08:28:20 PM PDT 24 Jun 07 08:28:53 PM PDT 24 6034991021 ps
T273 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4211573283 Jun 07 08:28:10 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2061845868 ps
T277 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.953314437 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:51 PM PDT 24 22422178508 ps
T803 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1353512449 Jun 07 08:28:25 PM PDT 24 Jun 07 08:28:47 PM PDT 24 2012302871 ps
T278 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1294326391 Jun 07 08:28:30 PM PDT 24 Jun 07 08:28:46 PM PDT 24 2158093291 ps
T279 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3514061386 Jun 07 08:28:04 PM PDT 24 Jun 07 08:28:27 PM PDT 24 22769574487 ps
T280 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3266751389 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:34 PM PDT 24 2045810967 ps
T804 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4142003358 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2079590559 ps
T19 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.38609548 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:38 PM PDT 24 4218312961 ps
T20 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2552256474 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:39 PM PDT 24 7813040099 ps
T303 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2821838314 Jun 07 08:28:14 PM PDT 24 Jun 07 08:28:38 PM PDT 24 2334808551 ps
T304 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3661736539 Jun 07 08:28:19 PM PDT 24 Jun 07 08:28:38 PM PDT 24 2206336545 ps
T805 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3280037810 Jun 07 08:28:17 PM PDT 24 Jun 07 08:28:35 PM PDT 24 2032391286 ps
T806 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2142981603 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2021194502 ps
T369 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.378617702 Jun 07 08:28:10 PM PDT 24 Jun 07 08:28:27 PM PDT 24 2245838283 ps
T305 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1633377656 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:31 PM PDT 24 2099153144 ps
T284 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3852074896 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2080719625 ps
T281 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3006455279 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:40 PM PDT 24 2131869015 ps
T282 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2734116219 Jun 07 08:28:19 PM PDT 24 Jun 07 08:28:44 PM PDT 24 2103460426 ps
T807 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.593990724 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:24 PM PDT 24 2033150383 ps
T321 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3160920312 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:28 PM PDT 24 3053302675 ps
T808 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2055550026 Jun 07 08:28:14 PM PDT 24 Jun 07 08:28:37 PM PDT 24 2065139080 ps
T317 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.4013335838 Jun 07 08:28:17 PM PDT 24 Jun 07 08:28:41 PM PDT 24 5329581598 ps
T306 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1705382340 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2330229232 ps
T809 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1616619692 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2034076659 ps
T370 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3932988549 Jun 07 08:28:17 PM PDT 24 Jun 07 08:29:34 PM PDT 24 22197306922 ps
T283 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.383408422 Jun 07 08:28:10 PM PDT 24 Jun 07 08:28:31 PM PDT 24 2049487051 ps
T339 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1169600356 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:41 PM PDT 24 22252987648 ps
T371 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1253232068 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:57 PM PDT 24 42979827351 ps
T285 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2011173620 Jun 07 08:28:17 PM PDT 24 Jun 07 08:28:40 PM PDT 24 2146271408 ps
T810 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2697881343 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2055363597 ps
T811 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.327603228 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:29 PM PDT 24 2044762595 ps
T318 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.270807468 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:41 PM PDT 24 7182289075 ps
T340 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3345965132 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:44 PM PDT 24 22266735105 ps
T307 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4067232943 Jun 07 08:28:10 PM PDT 24 Jun 07 08:28:31 PM PDT 24 4023867768 ps
T323 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3295273118 Jun 07 08:28:28 PM PDT 24 Jun 07 08:28:52 PM PDT 24 6030438817 ps
T812 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.4160984575 Jun 07 08:28:22 PM PDT 24 Jun 07 08:28:40 PM PDT 24 2027678706 ps
T813 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3816531026 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:36 PM PDT 24 2009657838 ps
T814 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1992971221 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2343794473 ps
T815 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.514815875 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:50 PM PDT 24 22390808671 ps
T319 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1225366131 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:38 PM PDT 24 9377240846 ps
T816 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3757624258 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:50 PM PDT 24 22388483394 ps
T817 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2641232606 Jun 07 08:28:13 PM PDT 24 Jun 07 08:30:13 PM PDT 24 39139723722 ps
T308 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3652666766 Jun 07 08:28:10 PM PDT 24 Jun 07 08:28:31 PM PDT 24 2044892934 ps
T309 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4139623823 Jun 07 08:28:19 PM PDT 24 Jun 07 08:28:45 PM PDT 24 14969230272 ps
T818 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3305534222 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:38 PM PDT 24 2014077284 ps
T819 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1270282726 Jun 07 08:28:10 PM PDT 24 Jun 07 08:28:29 PM PDT 24 2009632586 ps
T820 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.267202218 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:25 PM PDT 24 2104504869 ps
T821 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1343200415 Jun 07 08:28:19 PM PDT 24 Jun 07 08:28:40 PM PDT 24 2136314844 ps
T822 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1943378998 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:29 PM PDT 24 2019784765 ps
T823 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3044711422 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2038220089 ps
T824 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2587101446 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:25 PM PDT 24 2030426893 ps
T825 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.916227493 Jun 07 08:28:06 PM PDT 24 Jun 07 08:28:21 PM PDT 24 2080403571 ps
T826 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.281288837 Jun 07 08:28:14 PM PDT 24 Jun 07 08:28:34 PM PDT 24 2047616974 ps
T827 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1117021265 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:34 PM PDT 24 2024775544 ps
T828 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.906746211 Jun 07 08:28:04 PM PDT 24 Jun 07 08:28:20 PM PDT 24 2642223069 ps
T829 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2036574326 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:31 PM PDT 24 2079424035 ps
T830 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3898572272 Jun 07 08:28:11 PM PDT 24 Jun 07 08:29:24 PM PDT 24 42614325635 ps
T831 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.944666004 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:33 PM PDT 24 8548581572 ps
T832 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.230714450 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:31 PM PDT 24 2112863435 ps
T833 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3355955336 Jun 07 08:28:21 PM PDT 24 Jun 07 08:28:39 PM PDT 24 2068490850 ps
T310 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2407470126 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2056460761 ps
T834 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4095256987 Jun 07 08:28:20 PM PDT 24 Jun 07 08:28:42 PM PDT 24 2014101295 ps
T835 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2518023179 Jun 07 08:28:23 PM PDT 24 Jun 07 08:28:41 PM PDT 24 2116685875 ps
T836 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1050196139 Jun 07 08:28:22 PM PDT 24 Jun 07 08:28:41 PM PDT 24 2040541842 ps
T311 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.47401245 Jun 07 08:28:07 PM PDT 24 Jun 07 08:28:24 PM PDT 24 2047362465 ps
T837 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.814535337 Jun 07 08:28:19 PM PDT 24 Jun 07 08:28:47 PM PDT 24 5068844234 ps
T838 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.514176211 Jun 07 08:28:41 PM PDT 24 Jun 07 08:28:56 PM PDT 24 5439672935 ps
T839 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2647547734 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:36 PM PDT 24 2117398729 ps
T840 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4174632733 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:38 PM PDT 24 2014899356 ps
T841 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.367714208 Jun 07 08:28:34 PM PDT 24 Jun 07 08:28:53 PM PDT 24 2085034679 ps
T842 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1715519763 Jun 07 08:28:18 PM PDT 24 Jun 07 08:28:41 PM PDT 24 2063263079 ps
T843 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2778412794 Jun 07 08:28:09 PM PDT 24 Jun 07 08:29:28 PM PDT 24 22190567390 ps
T844 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2534241844 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:38 PM PDT 24 2011653201 ps
T845 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2459546900 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:35 PM PDT 24 9448003315 ps
T846 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3790091203 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2049998085 ps
T312 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3702297008 Jun 07 08:28:06 PM PDT 24 Jun 07 08:28:22 PM PDT 24 2085306375 ps
T341 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.76463120 Jun 07 08:28:15 PM PDT 24 Jun 07 08:29:11 PM PDT 24 42655865519 ps
T847 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.4275101958 Jun 07 08:28:14 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2277940308 ps
T848 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1441511281 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:37 PM PDT 24 2106152700 ps
T849 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1731762838 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:41 PM PDT 24 4796084741 ps
T313 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2510782337 Jun 07 08:28:06 PM PDT 24 Jun 07 08:29:02 PM PDT 24 37734409218 ps
T850 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.4043827045 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:29 PM PDT 24 2064331090 ps
T851 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1138821990 Jun 07 08:28:25 PM PDT 24 Jun 07 08:28:58 PM PDT 24 9566520257 ps
T852 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.287211847 Jun 07 08:28:17 PM PDT 24 Jun 07 08:28:39 PM PDT 24 2013677277 ps
T342 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3479926040 Jun 07 08:28:07 PM PDT 24 Jun 07 08:28:53 PM PDT 24 42820629620 ps
T853 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1637894976 Jun 07 08:28:16 PM PDT 24 Jun 07 08:29:42 PM PDT 24 42378655562 ps
T854 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2817941966 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2015370076 ps
T855 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.454114013 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2087924255 ps
T856 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1710601546 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:34 PM PDT 24 2037760498 ps
T857 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.702650260 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:28 PM PDT 24 2142578721 ps
T858 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2202507575 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:37 PM PDT 24 9110763549 ps
T859 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2015883267 Jun 07 08:28:10 PM PDT 24 Jun 07 08:28:31 PM PDT 24 2027279850 ps
T860 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2453458513 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2825987436 ps
T861 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3656709982 Jun 07 08:28:24 PM PDT 24 Jun 07 08:28:42 PM PDT 24 2038099350 ps
T862 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2664854922 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:29 PM PDT 24 2130374763 ps
T314 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1094795299 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:38 PM PDT 24 2690585247 ps
T343 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2138563682 Jun 07 08:28:11 PM PDT 24 Jun 07 08:29:21 PM PDT 24 42533302394 ps
T863 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3457962345 Jun 07 08:28:06 PM PDT 24 Jun 07 08:28:22 PM PDT 24 2364066775 ps
T864 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.316334007 Jun 07 08:28:31 PM PDT 24 Jun 07 08:28:49 PM PDT 24 2099372798 ps
T865 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.342848257 Jun 07 08:28:23 PM PDT 24 Jun 07 08:28:42 PM PDT 24 2112436231 ps
T866 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2596142169 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:31 PM PDT 24 2133084453 ps
T867 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.583017886 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:55 PM PDT 24 10347288751 ps
T868 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2895920095 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2016356341 ps
T315 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3741186041 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:29 PM PDT 24 2204897108 ps
T869 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2837521430 Jun 07 08:28:25 PM PDT 24 Jun 07 08:28:47 PM PDT 24 2012498915 ps
T316 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2570381244 Jun 07 08:28:14 PM PDT 24 Jun 07 08:28:35 PM PDT 24 3641171922 ps
T870 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3584075862 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:28 PM PDT 24 2050069732 ps
T871 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3130383428 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:30 PM PDT 24 2091713280 ps
T872 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2329874226 Jun 07 08:28:07 PM PDT 24 Jun 07 08:28:54 PM PDT 24 9611645598 ps
T873 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1293102130 Jun 07 08:28:16 PM PDT 24 Jun 07 08:29:13 PM PDT 24 10390581408 ps
T874 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1042844094 Jun 07 08:28:32 PM PDT 24 Jun 07 08:28:48 PM PDT 24 2152253498 ps
T875 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1722532556 Jun 07 08:28:06 PM PDT 24 Jun 07 08:29:38 PM PDT 24 29964475010 ps
T876 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1316033665 Jun 07 08:28:25 PM PDT 24 Jun 07 08:28:44 PM PDT 24 2015729640 ps
T877 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1481037990 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:38 PM PDT 24 2059257008 ps
T878 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1085532621 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:36 PM PDT 24 2025487831 ps
T879 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1684365963 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:34 PM PDT 24 2196559079 ps
T880 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.45258514 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2012890409 ps
T881 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2038405616 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:37 PM PDT 24 2016802283 ps
T882 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.138538113 Jun 07 08:28:20 PM PDT 24 Jun 07 08:28:48 PM PDT 24 8897694462 ps
T883 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3981255750 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:28 PM PDT 24 2037141620 ps
T884 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2925809555 Jun 07 08:28:08 PM PDT 24 Jun 07 08:28:24 PM PDT 24 2108145688 ps
T885 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.687065613 Jun 07 08:28:10 PM PDT 24 Jun 07 08:28:27 PM PDT 24 2048491310 ps
T886 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3315091647 Jun 07 08:28:11 PM PDT 24 Jun 07 08:30:17 PM PDT 24 42454782303 ps
T887 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1701543752 Jun 07 08:28:07 PM PDT 24 Jun 07 08:28:54 PM PDT 24 22200787965 ps
T888 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3492628796 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:29 PM PDT 24 2027368943 ps
T889 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2658430814 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:43 PM PDT 24 2010251550 ps
T890 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.308234392 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:39 PM PDT 24 2013816482 ps
T891 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1163782790 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2071054566 ps
T892 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1090701583 Jun 07 08:28:14 PM PDT 24 Jun 07 08:28:37 PM PDT 24 2081349153 ps
T893 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2959524383 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2011985727 ps
T894 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1570769830 Jun 07 08:28:24 PM PDT 24 Jun 07 08:28:46 PM PDT 24 2009181488 ps
T895 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1201395507 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:45 PM PDT 24 4627631071 ps
T896 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.37312979 Jun 07 08:28:04 PM PDT 24 Jun 07 08:28:20 PM PDT 24 2040672652 ps
T897 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2796048924 Jun 07 08:28:20 PM PDT 24 Jun 07 08:28:43 PM PDT 24 2013106395 ps
T898 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2323275521 Jun 07 08:28:11 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2030926409 ps
T899 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1482289025 Jun 07 08:28:14 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2028042445 ps
T900 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1680673562 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:44 PM PDT 24 7859972089 ps
T901 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2723183106 Jun 07 08:28:22 PM PDT 24 Jun 07 08:28:42 PM PDT 24 2015195511 ps
T902 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3335369524 Jun 07 08:28:13 PM PDT 24 Jun 07 08:29:32 PM PDT 24 42391905150 ps
T903 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3923866564 Jun 07 08:28:04 PM PDT 24 Jun 07 08:28:19 PM PDT 24 2186582253 ps
T904 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1314789379 Jun 07 08:28:20 PM PDT 24 Jun 07 08:28:40 PM PDT 24 2013909326 ps
T905 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3517293090 Jun 07 08:28:20 PM PDT 24 Jun 07 08:29:06 PM PDT 24 43143775162 ps
T906 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1868485047 Jun 07 08:28:13 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2070668646 ps
T907 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2570688061 Jun 07 08:28:20 PM PDT 24 Jun 07 08:28:40 PM PDT 24 2102612956 ps
T908 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1844208852 Jun 07 08:28:06 PM PDT 24 Jun 07 08:28:26 PM PDT 24 4534529200 ps
T909 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1771047531 Jun 07 08:28:12 PM PDT 24 Jun 07 08:28:33 PM PDT 24 2050963813 ps
T910 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.827539996 Jun 07 08:28:18 PM PDT 24 Jun 07 08:28:37 PM PDT 24 2119492176 ps
T911 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3796803916 Jun 07 08:28:19 PM PDT 24 Jun 07 08:28:36 PM PDT 24 2154873710 ps
T912 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.966214907 Jun 07 08:28:15 PM PDT 24 Jun 07 08:28:34 PM PDT 24 2195071314 ps
T913 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2564088118 Jun 07 08:28:14 PM PDT 24 Jun 07 08:28:32 PM PDT 24 2058533487 ps
T914 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.952291673 Jun 07 08:28:16 PM PDT 24 Jun 07 08:28:35 PM PDT 24 2026345517 ps
T915 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4118533016 Jun 07 08:28:09 PM PDT 24 Jun 07 08:28:27 PM PDT 24 6073678619 ps

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.592897844
Short name T6
Test name
Test status
Simulation time 85871816551 ps
CPU time 44.93 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:58 PM PDT 24
Peak memory 202316 kb
Host smart-ade4a9d0-7415-4341-970d-a4434ce4fe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592897844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi
th_pre_cond.592897844
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3859960791
Short name T48
Test name
Test status
Simulation time 72236211800 ps
CPU time 91.18 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:32:34 PM PDT 24
Peak memory 210616 kb
Host smart-29e2c531-bcfb-437c-9c9c-1fc3e70c8847
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859960791 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3859960791
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3811260821
Short name T35
Test name
Test status
Simulation time 5429828939 ps
CPU time 5.08 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 201988 kb
Host smart-ab63d7e7-62f5-43e7-9b46-a2fcdaaa8911
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811260821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.3811260821
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.671995385
Short name T10
Test name
Test status
Simulation time 60206992202 ps
CPU time 141.49 seconds
Started Jun 07 08:31:00 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 202292 kb
Host smart-2b5c6d1d-7a0d-49c1-8459-275463c5ce48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671995385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_st
ress_all.671995385
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2476158388
Short name T71
Test name
Test status
Simulation time 35459090282 ps
CPU time 24.59 seconds
Started Jun 07 08:29:26 PM PDT 24
Finished Jun 07 08:30:04 PM PDT 24
Peak memory 201980 kb
Host smart-b26d372c-00e0-4ee0-b873-598714cf6397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476158388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.2476158388
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.606085397
Short name T1
Test name
Test status
Simulation time 143771743465 ps
CPU time 387.47 seconds
Started Jun 07 08:29:32 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 202300 kb
Host smart-38a5d2f0-36ba-4c26-b36a-edef4224c281
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606085397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_combo_detect.606085397
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.2485356435
Short name T39
Test name
Test status
Simulation time 15500630073 ps
CPU time 10.54 seconds
Started Jun 07 08:29:58 PM PDT 24
Finished Jun 07 08:30:19 PM PDT 24
Peak memory 202092 kb
Host smart-cdbe8d67-19c1-4d86-bc11-061a07262cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485356435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.2485356435
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2320211261
Short name T28
Test name
Test status
Simulation time 42485619236 ps
CPU time 32.8 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:29:02 PM PDT 24
Peak memory 201876 kb
Host smart-0e86d8f7-c781-4f7b-8604-1df9eb93293c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320211261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.2320211261
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3862224495
Short name T155
Test name
Test status
Simulation time 86697003101 ps
CPU time 112.04 seconds
Started Jun 07 08:30:22 PM PDT 24
Finished Jun 07 08:32:22 PM PDT 24
Peak memory 210636 kb
Host smart-605cbf23-dd11-48de-b55f-3bf5b166257b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862224495 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.3862224495
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3593117552
Short name T118
Test name
Test status
Simulation time 789443463847 ps
CPU time 79.64 seconds
Started Jun 07 08:31:30 PM PDT 24
Finished Jun 07 08:32:59 PM PDT 24
Peak memory 215504 kb
Host smart-31b24e55-5583-4c53-9467-24b6fab705f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593117552 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3593117552
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2935377961
Short name T42
Test name
Test status
Simulation time 753396151016 ps
CPU time 92.62 seconds
Started Jun 07 08:29:46 PM PDT 24
Finished Jun 07 08:31:27 PM PDT 24
Peak memory 210684 kb
Host smart-660f0a3b-d7c6-440a-ae60-23f1e30c4dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935377961 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.2935377961
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2550581316
Short name T183
Test name
Test status
Simulation time 187278967734 ps
CPU time 488.12 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:38:44 PM PDT 24
Peak memory 202236 kb
Host smart-26fff3f2-d524-4fe4-b810-f65e4e6f13cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550581316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2550581316
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.2100198587
Short name T92
Test name
Test status
Simulation time 36668959322 ps
CPU time 89.76 seconds
Started Jun 07 08:31:00 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 202288 kb
Host smart-335fc896-057f-4f9e-b9ef-355882e1a224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100198587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.2100198587
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1435005225
Short name T78
Test name
Test status
Simulation time 267255073271 ps
CPU time 107.43 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:32:54 PM PDT 24
Peak memory 210648 kb
Host smart-305c8d69-58f3-4ec0-b0c4-1c165a277946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435005225 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1435005225
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.3393428663
Short name T5
Test name
Test status
Simulation time 2104672774 ps
CPU time 0.99 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 202036 kb
Host smart-0a231560-a383-4b29-90bd-53f5a082bcc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393428663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.3393428663
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2649561130
Short name T34
Test name
Test status
Simulation time 99982783060 ps
CPU time 69.13 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 08:32:09 PM PDT 24
Peak memory 202284 kb
Host smart-2336ff42-7a91-48da-ba92-bffdb12138a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649561130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2649561130
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2736987370
Short name T4
Test name
Test status
Simulation time 8399504402 ps
CPU time 4.94 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:30:20 PM PDT 24
Peak memory 201964 kb
Host smart-a9c7edcf-021f-475a-816f-20fcd5361584
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736987370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.2736987370
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2649296600
Short name T99
Test name
Test status
Simulation time 141515380077 ps
CPU time 391.56 seconds
Started Jun 07 08:30:01 PM PDT 24
Finished Jun 07 08:36:44 PM PDT 24
Peak memory 202232 kb
Host smart-4725245a-5c17-4e77-b35e-4155f3fc8a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649296600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2649296600
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3652666766
Short name T308
Test name
Test status
Simulation time 2044892934 ps
CPU time 6.05 seconds
Started Jun 07 08:28:10 PM PDT 24
Finished Jun 07 08:28:31 PM PDT 24
Peak memory 201644 kb
Host smart-5c5b2da0-c6a0-4a98-97e3-831994c79d36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652666766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3652666766
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.43531892
Short name T114
Test name
Test status
Simulation time 114665096617 ps
CPU time 16.68 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 210632 kb
Host smart-01a0d250-d57c-4bac-8ee5-aaf0c65ab93c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43531892 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.43531892
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3006455279
Short name T281
Test name
Test status
Simulation time 2131869015 ps
CPU time 7.64 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:40 PM PDT 24
Peak memory 201948 kb
Host smart-e43324ea-86fc-40c6-b22f-2e46ca1b4d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006455279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3006455279
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.1375863336
Short name T178
Test name
Test status
Simulation time 3507858733 ps
CPU time 8.43 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:30:00 PM PDT 24
Peak memory 202084 kb
Host smart-d0033b9c-6534-47f0-9df7-bf5a1da6a7ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375863336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.1375863336
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.4122155822
Short name T66
Test name
Test status
Simulation time 79010806519 ps
CPU time 48.85 seconds
Started Jun 07 08:31:27 PM PDT 24
Finished Jun 07 08:32:26 PM PDT 24
Peak memory 202284 kb
Host smart-31125d98-66d7-48b2-a6da-c46a079a410b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122155822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.4122155822
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1248033012
Short name T154
Test name
Test status
Simulation time 69012036108 ps
CPU time 66.16 seconds
Started Jun 07 08:29:36 PM PDT 24
Finished Jun 07 08:30:53 PM PDT 24
Peak memory 210660 kb
Host smart-2d769ca8-5afa-41b9-b554-95848a3b5962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248033012 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1248033012
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.1929810926
Short name T43
Test name
Test status
Simulation time 7693763303 ps
CPU time 17.91 seconds
Started Jun 07 08:30:33 PM PDT 24
Finished Jun 07 08:30:53 PM PDT 24
Peak memory 201992 kb
Host smart-4a907c63-0895-4acd-9d66-38c3ba94b6f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929810926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.1929810926
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.3841461043
Short name T185
Test name
Test status
Simulation time 47492735009 ps
CPU time 7.65 seconds
Started Jun 07 08:30:44 PM PDT 24
Finished Jun 07 08:30:58 PM PDT 24
Peak memory 202452 kb
Host smart-cd1767fc-681c-43d7-961e-c6860cbeb21c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841461043 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.3841461043
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3436674963
Short name T251
Test name
Test status
Simulation time 216483811121 ps
CPU time 128.39 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:32:54 PM PDT 24
Peak memory 218668 kb
Host smart-3fb83893-288c-4e6f-88af-ad5947481974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436674963 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.3436674963
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3947530643
Short name T287
Test name
Test status
Simulation time 22059336245 ps
CPU time 15.61 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:29:58 PM PDT 24
Peak memory 221464 kb
Host smart-33e236c9-2543-4d49-a686-7912a522d86e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947530643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3947530643
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1682408472
Short name T59
Test name
Test status
Simulation time 42334544109 ps
CPU time 28.66 seconds
Started Jun 07 08:29:27 PM PDT 24
Finished Jun 07 08:30:09 PM PDT 24
Peak memory 202008 kb
Host smart-80ba43b2-35f2-428f-ae05-0858a8b2b291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682408472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1682408472
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1440857123
Short name T67
Test name
Test status
Simulation time 72667292167 ps
CPU time 181.91 seconds
Started Jun 07 08:31:09 PM PDT 24
Finished Jun 07 08:34:25 PM PDT 24
Peak memory 202224 kb
Host smart-454407f6-f91c-475b-a27b-058935a5e852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440857123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.1440857123
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.3570358608
Short name T333
Test name
Test status
Simulation time 105092062265 ps
CPU time 230.52 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:34:53 PM PDT 24
Peak memory 202252 kb
Host smart-c7ac1de1-c7df-48e9-879a-f946359f6a7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570358608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.3570358608
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3145874006
Short name T22
Test name
Test status
Simulation time 2522915633 ps
CPU time 2.31 seconds
Started Jun 07 08:29:15 PM PDT 24
Finished Jun 07 08:29:33 PM PDT 24
Peak memory 201972 kb
Host smart-ba8540a9-b4fe-4324-92c9-5d722bacd56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145874006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.3145874006
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3775262245
Short name T9
Test name
Test status
Simulation time 94856612470 ps
CPU time 73.74 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 202236 kb
Host smart-c9b0c223-7296-4a9e-a048-e9643c2cb76f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775262245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.3775262245
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.424259870
Short name T227
Test name
Test status
Simulation time 69009932980 ps
CPU time 83.09 seconds
Started Jun 07 08:30:04 PM PDT 24
Finished Jun 07 08:31:39 PM PDT 24
Peak memory 210620 kb
Host smart-9ae1023e-a939-411d-a2c3-eafc4d908970
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424259870 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.424259870
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2654114423
Short name T329
Test name
Test status
Simulation time 165721943945 ps
CPU time 451.28 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:37:58 PM PDT 24
Peak memory 202284 kb
Host smart-3ccca4bd-7872-4884-86f7-0ed5082b3a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654114423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.2654114423
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2975730519
Short name T328
Test name
Test status
Simulation time 56484985656 ps
CPU time 144.04 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 202228 kb
Host smart-4cd9b893-9052-466b-b5f1-815c6d000a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975730519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.2975730519
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.100994580
Short name T334
Test name
Test status
Simulation time 149524061194 ps
CPU time 100.84 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:32:27 PM PDT 24
Peak memory 202272 kb
Host smart-b892e80a-42af-421b-a9f6-03d3298c0deb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100994580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_combo_detect.100994580
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3208729525
Short name T352
Test name
Test status
Simulation time 44174352862 ps
CPU time 55.25 seconds
Started Jun 07 08:31:13 PM PDT 24
Finished Jun 07 08:32:21 PM PDT 24
Peak memory 202304 kb
Host smart-2aa0e05f-783e-4d77-bec7-f7f0c04330e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208729525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.3208729525
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.2624024096
Short name T174
Test name
Test status
Simulation time 191790943160 ps
CPU time 121.42 seconds
Started Jun 07 08:30:28 PM PDT 24
Finished Jun 07 08:32:34 PM PDT 24
Peak memory 202184 kb
Host smart-8cb590c7-a301-4e9f-a6d8-842b162e8616
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624024096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.2624024096
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.141869042
Short name T336
Test name
Test status
Simulation time 112106190062 ps
CPU time 69.44 seconds
Started Jun 07 08:29:46 PM PDT 24
Finished Jun 07 08:31:04 PM PDT 24
Peak memory 202296 kb
Host smart-fa4f40bc-048b-4cd9-9b08-c746ba93828a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141869042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_str
ess_all.141869042
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3631673320
Short name T320
Test name
Test status
Simulation time 6034991021 ps
CPU time 15.43 seconds
Started Jun 07 08:28:20 PM PDT 24
Finished Jun 07 08:28:53 PM PDT 24
Peak memory 201764 kb
Host smart-85b341b1-818e-4524-a144-8d3ff9659ffe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631673320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.3631673320
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.4188214903
Short name T188
Test name
Test status
Simulation time 3167383814 ps
CPU time 8.79 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 202020 kb
Host smart-a025154c-9d01-4e6c-ab88-fdf3da8d2bac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188214903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.4188214903
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.3192755070
Short name T180
Test name
Test status
Simulation time 3733896019 ps
CPU time 1.35 seconds
Started Jun 07 08:30:06 PM PDT 24
Finished Jun 07 08:30:19 PM PDT 24
Peak memory 202000 kb
Host smart-9be08f5f-e3b2-4897-b9e0-363b8ba25418
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192755070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.3192755070
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.876938569
Short name T330
Test name
Test status
Simulation time 137304267531 ps
CPU time 352.6 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:35:51 PM PDT 24
Peak memory 202276 kb
Host smart-aae74613-519b-4e90-ba1e-438a927e3473
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876938569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.876938569
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1781015553
Short name T268
Test name
Test status
Simulation time 2535355060 ps
CPU time 2.27 seconds
Started Jun 07 08:30:04 PM PDT 24
Finished Jun 07 08:30:18 PM PDT 24
Peak memory 202036 kb
Host smart-e3926f02-6b6a-4fbd-8c54-0ef922e18831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781015553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.1781015553
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2117816318
Short name T357
Test name
Test status
Simulation time 38995642526 ps
CPU time 52.47 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:31:33 PM PDT 24
Peak memory 202276 kb
Host smart-c8fba3dc-e77f-47a7-8b32-384530dd4032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117816318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.2117816318
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.1140255912
Short name T70
Test name
Test status
Simulation time 19107387411 ps
CPU time 48.14 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:31:51 PM PDT 24
Peak memory 202072 kb
Host smart-3a47b38e-9424-4fc5-8a7b-fee35cf2206d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140255912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.1140255912
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1024498385
Short name T345
Test name
Test status
Simulation time 48282926912 ps
CPU time 25.11 seconds
Started Jun 07 08:31:05 PM PDT 24
Finished Jun 07 08:31:44 PM PDT 24
Peak memory 202232 kb
Host smart-7d40fe06-207c-4477-a33a-d5a1d7c1f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024498385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.1024498385
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1992971221
Short name T814
Test name
Test status
Simulation time 2343794473 ps
CPU time 3.23 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201904 kb
Host smart-d037eb15-52c5-4e0e-8eab-de8fb553a44f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992971221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.1992971221
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.393224816
Short name T212
Test name
Test status
Simulation time 58678482543 ps
CPU time 38.25 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:31:01 PM PDT 24
Peak memory 218916 kb
Host smart-f7ebbce7-de3e-426b-99ba-0ef7a1c2f9a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393224816 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.393224816
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3944906192
Short name T144
Test name
Test status
Simulation time 36431011071 ps
CPU time 15.97 seconds
Started Jun 07 08:30:13 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 210636 kb
Host smart-d0486132-c9c8-411d-bfe9-add31caac137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944906192 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3944906192
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.407581754
Short name T40
Test name
Test status
Simulation time 2648338577 ps
CPU time 2.41 seconds
Started Jun 07 08:30:45 PM PDT 24
Finished Jun 07 08:30:54 PM PDT 24
Peak memory 202012 kb
Host smart-c01a3fa7-6618-4629-bac4-bc3cfad2581a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407581754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctr
l_edge_detect.407581754
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2477526074
Short name T145
Test name
Test status
Simulation time 54466480168 ps
CPU time 74.01 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:32:26 PM PDT 24
Peak memory 210648 kb
Host smart-fa429649-32a8-4e34-af78-478d6079abcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477526074 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2477526074
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2518023179
Short name T835
Test name
Test status
Simulation time 2116685875 ps
CPU time 2.12 seconds
Started Jun 07 08:28:23 PM PDT 24
Finished Jun 07 08:28:41 PM PDT 24
Peak memory 201708 kb
Host smart-ef48f80b-db22-4ef4-a9ec-ef843f6b002b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518023179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2518023179
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.76463120
Short name T341
Test name
Test status
Simulation time 42655865519 ps
CPU time 38.92 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 202076 kb
Host smart-85715c2b-b70b-4792-916f-74504fb648af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76463120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_tl_intg_err.76463120
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.657156613
Short name T7
Test name
Test status
Simulation time 57589742700 ps
CPU time 40.07 seconds
Started Jun 07 08:29:23 PM PDT 24
Finished Jun 07 08:30:17 PM PDT 24
Peak memory 202300 kb
Host smart-a450d327-2d3c-4201-ac3f-259bb4b00e9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657156613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_combo_detect.657156613
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1958764843
Short name T360
Test name
Test status
Simulation time 30273015409 ps
CPU time 21.69 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:30:03 PM PDT 24
Peak memory 202292 kb
Host smart-0b03c194-4a78-4a97-b36b-b09605e157de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958764843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.1958764843
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1605515489
Short name T378
Test name
Test status
Simulation time 168841984889 ps
CPU time 98.78 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:31:39 PM PDT 24
Peak memory 202304 kb
Host smart-176656b8-d297-4223-9ebd-3604fd6b9000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605515489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1605515489
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2287179083
Short name T353
Test name
Test status
Simulation time 60986714458 ps
CPU time 163.05 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 202296 kb
Host smart-1645af28-0fb8-439e-a509-a433c3143a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287179083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.2287179083
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.437544092
Short name T363
Test name
Test status
Simulation time 104539434985 ps
CPU time 71.46 seconds
Started Jun 07 08:29:57 PM PDT 24
Finished Jun 07 08:31:19 PM PDT 24
Peak memory 202280 kb
Host smart-70c4f2dd-af88-45a0-ab2f-b6c8b36c19c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437544092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_combo_detect.437544092
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1135803030
Short name T383
Test name
Test status
Simulation time 257615254682 ps
CPU time 83.98 seconds
Started Jun 07 08:29:58 PM PDT 24
Finished Jun 07 08:31:33 PM PDT 24
Peak memory 201968 kb
Host smart-3cd4e81f-b756-44c7-9760-5e5b6aa22432
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135803030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.1135803030
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3133467626
Short name T337
Test name
Test status
Simulation time 95773310871 ps
CPU time 26.61 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:30:53 PM PDT 24
Peak memory 202244 kb
Host smart-1ac633a0-5945-4d4d-8283-ba1df664c5e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133467626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3133467626
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.608457882
Short name T116
Test name
Test status
Simulation time 60553024531 ps
CPU time 160.48 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:32:59 PM PDT 24
Peak memory 218836 kb
Host smart-304c8f49-3c56-4f2f-b5a8-58786f07ce4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608457882 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.608457882
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.3478869537
Short name T335
Test name
Test status
Simulation time 77846467042 ps
CPU time 55.65 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:31:37 PM PDT 24
Peak memory 202236 kb
Host smart-29bcae45-1443-401b-bf71-c7834d428717
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478869537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.3478869537
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.97857778
Short name T375
Test name
Test status
Simulation time 94230477552 ps
CPU time 234.71 seconds
Started Jun 07 08:31:01 PM PDT 24
Finished Jun 07 08:35:10 PM PDT 24
Peak memory 202172 kb
Host smart-9fad5d2a-318a-49c3-96c1-afe422615a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97857778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wit
h_pre_cond.97857778
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2257951510
Short name T379
Test name
Test status
Simulation time 68460849372 ps
CPU time 69.22 seconds
Started Jun 07 08:31:05 PM PDT 24
Finished Jun 07 08:32:29 PM PDT 24
Peak memory 202340 kb
Host smart-19f5819f-73c2-4d1e-858d-f10255375c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257951510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2257951510
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3214496144
Short name T350
Test name
Test status
Simulation time 80300497445 ps
CPU time 53.24 seconds
Started Jun 07 08:31:00 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 202264 kb
Host smart-0569f386-87a3-469c-bc4d-6941e72e17c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214496144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.3214496144
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.392678808
Short name T338
Test name
Test status
Simulation time 83966810799 ps
CPU time 233.51 seconds
Started Jun 07 08:31:04 PM PDT 24
Finished Jun 07 08:35:12 PM PDT 24
Peak memory 202316 kb
Host smart-7e315367-2b9c-49cb-a963-ffac37ef338b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392678808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_wi
th_pre_cond.392678808
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3712388838
Short name T376
Test name
Test status
Simulation time 93052663092 ps
CPU time 251.74 seconds
Started Jun 07 08:31:10 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 202268 kb
Host smart-fa98e884-60c4-4f81-b428-8d9d16480dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712388838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3712388838
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.814535337
Short name T837
Test name
Test status
Simulation time 5068844234 ps
CPU time 11.07 seconds
Started Jun 07 08:28:19 PM PDT 24
Finished Jun 07 08:28:47 PM PDT 24
Peak memory 201952 kb
Host smart-162b3a63-6081-40a9-b276-75f15ac8fb42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814535337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
sysrst_ctrl_same_csr_outstanding.814535337
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.66489132
Short name T454
Test name
Test status
Simulation time 10153919832 ps
CPU time 3.29 seconds
Started Jun 07 08:29:25 PM PDT 24
Finished Jun 07 08:29:42 PM PDT 24
Peak memory 201992 kb
Host smart-5a17fa38-d109-4e90-b541-fa91bb738037
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66489132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_ultra_low_pwr.66489132
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.647128124
Short name T74
Test name
Test status
Simulation time 66630128706 ps
CPU time 164.55 seconds
Started Jun 07 08:30:17 PM PDT 24
Finished Jun 07 08:33:11 PM PDT 24
Peak memory 202164 kb
Host smart-dacc150e-e197-4e35-b75d-cdd2902ed0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647128124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.647128124
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1625579197
Short name T75
Test name
Test status
Simulation time 38452899724 ps
CPU time 21.75 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:31 PM PDT 24
Peak memory 202216 kb
Host smart-3bf0920b-a7d1-414b-8d94-8ffcf6da48bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625579197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.1625579197
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1702936784
Short name T235
Test name
Test status
Simulation time 171317814040 ps
CPU time 225.67 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:33:46 PM PDT 24
Peak memory 202252 kb
Host smart-dd286667-7054-4c75-9b8b-4ccda419036e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702936784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.1702936784
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1094795299
Short name T314
Test name
Test status
Simulation time 2690585247 ps
CPU time 10.97 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201904 kb
Host smart-46019211-86a0-49b5-97bd-1e60662e4f55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094795299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.1094795299
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2570381244
Short name T316
Test name
Test status
Simulation time 3641171922 ps
CPU time 6.25 seconds
Started Jun 07 08:28:14 PM PDT 24
Finished Jun 07 08:28:35 PM PDT 24
Peak memory 201928 kb
Host smart-dc990462-0dfd-47c2-8403-462c7eaa02b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570381244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.2570381244
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2664854922
Short name T862
Test name
Test status
Simulation time 2130374763 ps
CPU time 6.99 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:29 PM PDT 24
Peak memory 201796 kb
Host smart-cba7aa37-e68c-4a98-974b-59e0d9145e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664854922 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2664854922
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.37312979
Short name T896
Test name
Test status
Simulation time 2040672652 ps
CPU time 3.31 seconds
Started Jun 07 08:28:04 PM PDT 24
Finished Jun 07 08:28:20 PM PDT 24
Peak memory 201752 kb
Host smart-014a8987-3bef-4c1e-8dd9-f1d978c1496a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37312979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.37312979
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.702650260
Short name T857
Test name
Test status
Simulation time 2142578721 ps
CPU time 1 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:28 PM PDT 24
Peak memory 201544 kb
Host smart-54f9723c-f593-4ccf-946e-233e294a6134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702650260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test
.702650260
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2329874226
Short name T872
Test name
Test status
Simulation time 9611645598 ps
CPU time 33.88 seconds
Started Jun 07 08:28:07 PM PDT 24
Finished Jun 07 08:28:54 PM PDT 24
Peak memory 201984 kb
Host smart-6c6af63a-8b88-4937-95f3-3e6ae9324325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329874226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.2329874226
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1701543752
Short name T887
Test name
Test status
Simulation time 22200787965 ps
CPU time 32.41 seconds
Started Jun 07 08:28:07 PM PDT 24
Finished Jun 07 08:28:54 PM PDT 24
Peak memory 201940 kb
Host smart-cc761bb5-750e-4451-ab7d-dbeb880411bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701543752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.1701543752
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2821838314
Short name T303
Test name
Test status
Simulation time 2334808551 ps
CPU time 7.86 seconds
Started Jun 07 08:28:14 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201984 kb
Host smart-ba770c1b-45ba-4860-b079-0b71fb4d7b08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821838314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.2821838314
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2510782337
Short name T313
Test name
Test status
Simulation time 37734409218 ps
CPU time 43.28 seconds
Started Jun 07 08:28:06 PM PDT 24
Finished Jun 07 08:29:02 PM PDT 24
Peak memory 202040 kb
Host smart-77f37265-6d9a-4167-a5ac-9ed3d38bdb22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510782337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.2510782337
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4067232943
Short name T307
Test name
Test status
Simulation time 4023867768 ps
CPU time 6.21 seconds
Started Jun 07 08:28:10 PM PDT 24
Finished Jun 07 08:28:31 PM PDT 24
Peak memory 201788 kb
Host smart-bf9225b3-9af9-4026-ab11-16e39c32cc71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067232943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.4067232943
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1771047531
Short name T909
Test name
Test status
Simulation time 2050963813 ps
CPU time 6.03 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201772 kb
Host smart-d3c8c93b-4f9c-45dd-863b-d8765880e245
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771047531 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1771047531
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.488595847
Short name T798
Test name
Test status
Simulation time 2024316349 ps
CPU time 3.65 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201344 kb
Host smart-b41c0364-b07a-40ad-aeb6-5017da295fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488595847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.488595847
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2647547734
Short name T839
Test name
Test status
Simulation time 2117398729 ps
CPU time 7.44 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:36 PM PDT 24
Peak memory 210152 kb
Host smart-dbc9930a-67a7-45f3-903e-b4ee043df31e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647547734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.2647547734
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3852074896
Short name T284
Test name
Test status
Simulation time 2080719625 ps
CPU time 2.42 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201772 kb
Host smart-a385001b-af3e-4ba2-93ac-ff5d18f32029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852074896 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3852074896
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1570769830
Short name T894
Test name
Test status
Simulation time 2009181488 ps
CPU time 5.77 seconds
Started Jun 07 08:28:24 PM PDT 24
Finished Jun 07 08:28:46 PM PDT 24
Peak memory 201408 kb
Host smart-2b042066-de8c-475d-a221-a0c5ca542dca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570769830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.1570769830
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1138821990
Short name T851
Test name
Test status
Simulation time 9566520257 ps
CPU time 17.31 seconds
Started Jun 07 08:28:25 PM PDT 24
Finished Jun 07 08:28:58 PM PDT 24
Peak memory 202016 kb
Host smart-0db372cc-8599-41b9-802e-da8f6b834829
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138821990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.1138821990
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2570688061
Short name T907
Test name
Test status
Simulation time 2102612956 ps
CPU time 4.03 seconds
Started Jun 07 08:28:20 PM PDT 24
Finished Jun 07 08:28:40 PM PDT 24
Peak memory 201896 kb
Host smart-4154430c-9a9e-4ba4-b997-8844b3dbefef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570688061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.2570688061
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3932988549
Short name T370
Test name
Test status
Simulation time 22197306922 ps
CPU time 60.75 seconds
Started Jun 07 08:28:17 PM PDT 24
Finished Jun 07 08:29:34 PM PDT 24
Peak memory 201940 kb
Host smart-8d7708e8-d2c5-41ea-8552-56c2b3ed518f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932988549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.3932988549
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2697881343
Short name T810
Test name
Test status
Simulation time 2055363597 ps
CPU time 5.97 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201704 kb
Host smart-60e28927-21c2-4623-9da4-5508e6a4f187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697881343 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2697881343
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2015883267
Short name T859
Test name
Test status
Simulation time 2027279850 ps
CPU time 5.75 seconds
Started Jun 07 08:28:10 PM PDT 24
Finished Jun 07 08:28:31 PM PDT 24
Peak memory 201744 kb
Host smart-8cff899f-297c-4a3b-9838-8ad44291a5a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015883267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.2015883267
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4174632733
Short name T840
Test name
Test status
Simulation time 2014899356 ps
CPU time 5.42 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201396 kb
Host smart-a8435d9c-a4ba-459c-8826-978102d22e6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174632733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.4174632733
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1225366131
Short name T319
Test name
Test status
Simulation time 9377240846 ps
CPU time 8.92 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201952 kb
Host smart-64018ffe-11ae-4c27-810d-f0adc31493fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225366131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.1225366131
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2011173620
Short name T285
Test name
Test status
Simulation time 2146271408 ps
CPU time 6.73 seconds
Started Jun 07 08:28:17 PM PDT 24
Finished Jun 07 08:28:40 PM PDT 24
Peak memory 201996 kb
Host smart-feacf3e8-f020-43bd-ab7c-893c9d3abafd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011173620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2011173620
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3315091647
Short name T886
Test name
Test status
Simulation time 42454782303 ps
CPU time 110.47 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:30:17 PM PDT 24
Peak memory 202008 kb
Host smart-d07a908e-0474-4c49-ac95-afca48437fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315091647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3315091647
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1441511281
Short name T848
Test name
Test status
Simulation time 2106152700 ps
CPU time 6.09 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:37 PM PDT 24
Peak memory 201560 kb
Host smart-7c5e2084-0aa8-4567-a4dc-c780159b4bbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441511281 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1441511281
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1710601546
Short name T856
Test name
Test status
Simulation time 2037760498 ps
CPU time 3.86 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:34 PM PDT 24
Peak memory 201748 kb
Host smart-5f99d5ea-33e5-4821-bcd6-a84e9d892a59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710601546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.1710601546
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2142981603
Short name T806
Test name
Test status
Simulation time 2021194502 ps
CPU time 3.04 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201388 kb
Host smart-5ad08d14-ddb3-4291-bb4c-ff3d5d811396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142981603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2142981603
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1293102130
Short name T873
Test name
Test status
Simulation time 10390581408 ps
CPU time 40.72 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:29:13 PM PDT 24
Peak memory 201904 kb
Host smart-dd760f55-890e-4bcf-b0dd-1a6c101b06b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293102130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.1293102130
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2323275521
Short name T898
Test name
Test status
Simulation time 2030926409 ps
CPU time 6.89 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201880 kb
Host smart-9b63ff4f-7780-45d1-ae18-815375d1fddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323275521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.2323275521
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.514815875
Short name T815
Test name
Test status
Simulation time 22390808671 ps
CPU time 23.29 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:50 PM PDT 24
Peak memory 202012 kb
Host smart-ded1f8d0-361b-47c0-9333-82ec4edfe1c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514815875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_tl_intg_err.514815875
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1163782790
Short name T891
Test name
Test status
Simulation time 2071054566 ps
CPU time 5.7 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201704 kb
Host smart-c5703c54-bc7c-4627-8e27-c6598fa3fc80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163782790 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1163782790
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3741186041
Short name T315
Test name
Test status
Simulation time 2204897108 ps
CPU time 1.46 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:29 PM PDT 24
Peak memory 201756 kb
Host smart-db9587c5-3b6f-4541-b5b1-0e17259a1ce9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741186041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.3741186041
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.4160984575
Short name T812
Test name
Test status
Simulation time 2027678706 ps
CPU time 2.01 seconds
Started Jun 07 08:28:22 PM PDT 24
Finished Jun 07 08:28:40 PM PDT 24
Peak memory 201588 kb
Host smart-4b4c66e4-30fe-443f-a361-9ff0725703c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160984575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.4160984575
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1201395507
Short name T895
Test name
Test status
Simulation time 4627631071 ps
CPU time 12.56 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:45 PM PDT 24
Peak memory 201956 kb
Host smart-d80d138c-3460-43d0-a34a-d25b36c1b1fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201395507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.1201395507
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2682125856
Short name T272
Test name
Test status
Simulation time 2123722745 ps
CPU time 4.3 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201928 kb
Host smart-3cb505c1-67dd-4c53-97cb-9b2206b8674c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682125856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.2682125856
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3898572272
Short name T830
Test name
Test status
Simulation time 42614325635 ps
CPU time 58.01 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:29:24 PM PDT 24
Peak memory 201948 kb
Host smart-2974bf9d-d9f3-47b3-a69d-409dfa3b7884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898572272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.3898572272
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.230714450
Short name T832
Test name
Test status
Simulation time 2112863435 ps
CPU time 1.99 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:31 PM PDT 24
Peak memory 201704 kb
Host smart-2ba9750a-b51e-4840-83fc-7f18a583ab21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230714450 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.230714450
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1633377656
Short name T305
Test name
Test status
Simulation time 2099153144 ps
CPU time 2.34 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:31 PM PDT 24
Peak memory 201748 kb
Host smart-81409686-7088-446e-84a4-2cfaee9c9199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633377656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.1633377656
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3796803916
Short name T911
Test name
Test status
Simulation time 2154873710 ps
CPU time 0.96 seconds
Started Jun 07 08:28:19 PM PDT 24
Finished Jun 07 08:28:36 PM PDT 24
Peak memory 201464 kb
Host smart-b4fbfbf1-c6b8-4ff5-97a5-7d5a40069af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796803916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.3796803916
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2552256474
Short name T20
Test name
Test status
Simulation time 7813040099 ps
CPU time 5.55 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:39 PM PDT 24
Peak memory 202012 kb
Host smart-4afd4439-17a7-47e4-8cf5-766f0f58b0ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552256474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.2552256474
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3266751389
Short name T280
Test name
Test status
Simulation time 2045810967 ps
CPU time 7.43 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:34 PM PDT 24
Peak memory 210196 kb
Host smart-175d0223-2954-4b6c-8e86-5ed2831745fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266751389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.3266751389
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3517293090
Short name T905
Test name
Test status
Simulation time 43143775162 ps
CPU time 29.21 seconds
Started Jun 07 08:28:20 PM PDT 24
Finished Jun 07 08:29:06 PM PDT 24
Peak memory 201948 kb
Host smart-b92ae9d6-ed0c-4882-822e-36a26678caa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517293090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.3517293090
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.316334007
Short name T864
Test name
Test status
Simulation time 2099372798 ps
CPU time 3.51 seconds
Started Jun 07 08:28:31 PM PDT 24
Finished Jun 07 08:28:49 PM PDT 24
Peak memory 201724 kb
Host smart-da987659-9ff7-49ab-ba99-a65b472d623b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316334007 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.316334007
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2407470126
Short name T310
Test name
Test status
Simulation time 2056460761 ps
CPU time 6.74 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201748 kb
Host smart-fcdeebc0-ef6a-4c70-96c1-f4c4d27edcef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407470126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.2407470126
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2959524383
Short name T893
Test name
Test status
Simulation time 2011985727 ps
CPU time 6.2 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201464 kb
Host smart-19eee327-b446-4096-9ecb-e54e85998338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959524383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.2959524383
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.514176211
Short name T838
Test name
Test status
Simulation time 5439672935 ps
CPU time 2.27 seconds
Started Jun 07 08:28:41 PM PDT 24
Finished Jun 07 08:28:56 PM PDT 24
Peak memory 202016 kb
Host smart-29d1a9aa-2f1e-4dd9-aedd-5a1eda18c867
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514176211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.sysrst_ctrl_same_csr_outstanding.514176211
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1868485047
Short name T906
Test name
Test status
Simulation time 2070668646 ps
CPU time 4.38 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201920 kb
Host smart-40b0bc88-ad06-4726-87b1-364412e39bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868485047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.1868485047
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3335369524
Short name T902
Test name
Test status
Simulation time 42391905150 ps
CPU time 63.23 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:29:32 PM PDT 24
Peak memory 202008 kb
Host smart-897fffb9-5d31-4e67-a087-98907df844b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335369524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.3335369524
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.367714208
Short name T841
Test name
Test status
Simulation time 2085034679 ps
CPU time 6.32 seconds
Started Jun 07 08:28:34 PM PDT 24
Finished Jun 07 08:28:53 PM PDT 24
Peak memory 201836 kb
Host smart-4e85e648-7422-4108-806e-db12398c0664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367714208 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.367714208
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1481037990
Short name T877
Test name
Test status
Simulation time 2059257008 ps
CPU time 6.22 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201704 kb
Host smart-a51e71bf-f34d-4e2f-a5ee-c5a4aac37769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481037990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.1481037990
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4095256987
Short name T834
Test name
Test status
Simulation time 2014101295 ps
CPU time 5.78 seconds
Started Jun 07 08:28:20 PM PDT 24
Finished Jun 07 08:28:42 PM PDT 24
Peak memory 201308 kb
Host smart-ec4d8c4b-337b-4943-8a2a-82b216e76ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095256987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.4095256987
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.38609548
Short name T19
Test name
Test status
Simulation time 4218312961 ps
CPU time 12.16 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201912 kb
Host smart-3659dd00-dc15-4563-8e0a-4eb7adbef29e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38609548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=
sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
sysrst_ctrl_same_csr_outstanding.38609548
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3790091203
Short name T846
Test name
Test status
Simulation time 2049998085 ps
CPU time 3.74 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201876 kb
Host smart-2a7010bd-1984-4c10-8112-33eb991dce87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790091203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.3790091203
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1637894976
Short name T853
Test name
Test status
Simulation time 42378655562 ps
CPU time 69.68 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:29:42 PM PDT 24
Peak memory 201956 kb
Host smart-3d4bc8ac-8c74-40b9-ac88-826ab778d418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637894976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.1637894976
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1715519763
Short name T842
Test name
Test status
Simulation time 2063263079 ps
CPU time 6.9 seconds
Started Jun 07 08:28:18 PM PDT 24
Finished Jun 07 08:28:41 PM PDT 24
Peak memory 201736 kb
Host smart-7e4e2a87-c265-4381-bd93-69bb6ad3b08d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715519763 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1715519763
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.342848257
Short name T865
Test name
Test status
Simulation time 2112436231 ps
CPU time 2.3 seconds
Started Jun 07 08:28:23 PM PDT 24
Finished Jun 07 08:28:42 PM PDT 24
Peak memory 201740 kb
Host smart-34888198-d103-4d68-b4d2-fd5446ab779b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342848257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_r
w.342848257
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3492628796
Short name T888
Test name
Test status
Simulation time 2027368943 ps
CPU time 3.22 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:29 PM PDT 24
Peak memory 201344 kb
Host smart-69549845-e663-403c-98a9-86fb417a6cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492628796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3492628796
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.138538113
Short name T882
Test name
Test status
Simulation time 8897694462 ps
CPU time 12.1 seconds
Started Jun 07 08:28:20 PM PDT 24
Finished Jun 07 08:28:48 PM PDT 24
Peak memory 201992 kb
Host smart-123366c9-c028-4a16-b26d-02348164c9c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138538113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.138538113
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2734116219
Short name T282
Test name
Test status
Simulation time 2103460426 ps
CPU time 7.39 seconds
Started Jun 07 08:28:19 PM PDT 24
Finished Jun 07 08:28:44 PM PDT 24
Peak memory 201884 kb
Host smart-4bea6c43-8554-474e-ae5d-3aef8c7f14db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734116219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.2734116219
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1169600356
Short name T339
Test name
Test status
Simulation time 22252987648 ps
CPU time 16.14 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:41 PM PDT 24
Peak memory 201956 kb
Host smart-218e4f3d-6dff-4f84-b81a-25b92b6bb543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169600356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.1169600356
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1343200415
Short name T821
Test name
Test status
Simulation time 2136314844 ps
CPU time 3.75 seconds
Started Jun 07 08:28:19 PM PDT 24
Finished Jun 07 08:28:40 PM PDT 24
Peak memory 201772 kb
Host smart-bf22466d-5460-4646-8102-609d1c06a873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343200415 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1343200415
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3661736539
Short name T304
Test name
Test status
Simulation time 2206336545 ps
CPU time 1.52 seconds
Started Jun 07 08:28:19 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201676 kb
Host smart-dfd4ef11-881f-4ca7-bbd2-346194d1e38f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661736539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.3661736539
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2658430814
Short name T889
Test name
Test status
Simulation time 2010251550 ps
CPU time 5.53 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:43 PM PDT 24
Peak memory 201360 kb
Host smart-a198b938-5e64-4632-8931-7dc9939f3976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658430814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2658430814
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.4013335838
Short name T317
Test name
Test status
Simulation time 5329581598 ps
CPU time 7.39 seconds
Started Jun 07 08:28:17 PM PDT 24
Finished Jun 07 08:28:41 PM PDT 24
Peak memory 201940 kb
Host smart-e624fe47-dd00-4433-9485-211f7cf3e6b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013335838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.4013335838
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2036574326
Short name T829
Test name
Test status
Simulation time 2079424035 ps
CPU time 4.82 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:31 PM PDT 24
Peak memory 210100 kb
Host smart-768404f6-2342-4cb3-acf6-68dda4240715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036574326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.2036574326
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2055550026
Short name T808
Test name
Test status
Simulation time 2065139080 ps
CPU time 6.53 seconds
Started Jun 07 08:28:14 PM PDT 24
Finished Jun 07 08:28:37 PM PDT 24
Peak memory 201800 kb
Host smart-9d7f50d8-ff8c-487a-b611-8b690e21c262
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055550026 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2055550026
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.454114013
Short name T855
Test name
Test status
Simulation time 2087924255 ps
CPU time 1.77 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201616 kb
Host smart-c5be9032-7529-40a8-bbfe-79e08f88a256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454114013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_r
w.454114013
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2796048924
Short name T897
Test name
Test status
Simulation time 2013106395 ps
CPU time 6.24 seconds
Started Jun 07 08:28:20 PM PDT 24
Finished Jun 07 08:28:43 PM PDT 24
Peak memory 201336 kb
Host smart-2942e96c-d994-4f7f-97c7-b89aeeea18c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796048924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.2796048924
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1680673562
Short name T900
Test name
Test status
Simulation time 7859972089 ps
CPU time 11.46 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:44 PM PDT 24
Peak memory 202060 kb
Host smart-9ca3b7b3-13cb-4c80-a862-b4cde7eabb3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680673562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.1680673562
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3757624258
Short name T816
Test name
Test status
Simulation time 22388483394 ps
CPU time 17.3 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:50 PM PDT 24
Peak memory 202004 kb
Host smart-333d2ee4-b0c2-4bdd-860d-ad78a9dec575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757624258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.3757624258
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3160920312
Short name T321
Test name
Test status
Simulation time 3053302675 ps
CPU time 2.87 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:28 PM PDT 24
Peak memory 201956 kb
Host smart-687bcff7-3b1c-46fa-9552-96d10b6f700f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160920312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3160920312
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2641232606
Short name T817
Test name
Test status
Simulation time 39139723722 ps
CPU time 103.5 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:30:13 PM PDT 24
Peak memory 201904 kb
Host smart-54a7d2ea-319f-49c8-877f-aa5b81a063ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641232606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.2641232606
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3295273118
Short name T323
Test name
Test status
Simulation time 6030438817 ps
CPU time 9.52 seconds
Started Jun 07 08:28:28 PM PDT 24
Finished Jun 07 08:28:52 PM PDT 24
Peak memory 201808 kb
Host smart-1737367c-fb5e-4b87-adfb-9fc08824e081
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295273118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.3295273118
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1684365963
Short name T879
Test name
Test status
Simulation time 2196559079 ps
CPU time 1.85 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:34 PM PDT 24
Peak memory 201804 kb
Host smart-329effcd-84ff-4406-a3b0-0b897ed7595f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684365963 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1684365963
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3702297008
Short name T312
Test name
Test status
Simulation time 2085306375 ps
CPU time 2.11 seconds
Started Jun 07 08:28:06 PM PDT 24
Finished Jun 07 08:28:22 PM PDT 24
Peak memory 201804 kb
Host smart-3a53cb74-7d9f-448c-8595-eb139280f656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702297008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3702297008
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.593990724
Short name T807
Test name
Test status
Simulation time 2033150383 ps
CPU time 2.02 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:24 PM PDT 24
Peak memory 201368 kb
Host smart-515d33a1-4257-40f7-be93-5d5af174e3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593990724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test
.593990724
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1844208852
Short name T908
Test name
Test status
Simulation time 4534529200 ps
CPU time 6.94 seconds
Started Jun 07 08:28:06 PM PDT 24
Finished Jun 07 08:28:26 PM PDT 24
Peak memory 201760 kb
Host smart-d0fb5283-74eb-407d-aa6e-de4e36000b9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844208852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.1844208852
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4211573283
Short name T273
Test name
Test status
Simulation time 2061845868 ps
CPU time 6.93 seconds
Started Jun 07 08:28:10 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201932 kb
Host smart-cad61b9c-2d08-47b7-a887-df477ece8e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211573283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.4211573283
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3479926040
Short name T342
Test name
Test status
Simulation time 42820629620 ps
CPU time 32.27 seconds
Started Jun 07 08:28:07 PM PDT 24
Finished Jun 07 08:28:53 PM PDT 24
Peak memory 201944 kb
Host smart-ba8dd8b1-5a84-4b7b-aeeb-60354783cfbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479926040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.3479926040
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3355955336
Short name T833
Test name
Test status
Simulation time 2068490850 ps
CPU time 1.5 seconds
Started Jun 07 08:28:21 PM PDT 24
Finished Jun 07 08:28:39 PM PDT 24
Peak memory 201372 kb
Host smart-db529f00-2ab8-4ab0-af93-9be9aa8bbaa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355955336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.3355955336
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2723183106
Short name T901
Test name
Test status
Simulation time 2015195511 ps
CPU time 3.38 seconds
Started Jun 07 08:28:22 PM PDT 24
Finished Jun 07 08:28:42 PM PDT 24
Peak memory 201336 kb
Host smart-66c86877-2681-4be6-afa7-3338a4634199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723183106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.2723183106
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4142003358
Short name T804
Test name
Test status
Simulation time 2079590559 ps
CPU time 1.21 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201644 kb
Host smart-b5973924-f44d-45e6-a606-5892ec9d2148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142003358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.4142003358
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.687065613
Short name T885
Test name
Test status
Simulation time 2048491310 ps
CPU time 1.83 seconds
Started Jun 07 08:28:10 PM PDT 24
Finished Jun 07 08:28:27 PM PDT 24
Peak memory 201604 kb
Host smart-93571cd3-04a8-4603-8684-1cc7cc5af499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687065613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_tes
t.687065613
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2038405616
Short name T881
Test name
Test status
Simulation time 2016802283 ps
CPU time 5.62 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:37 PM PDT 24
Peak memory 201364 kb
Host smart-6f28c8b7-f788-4b99-8a2d-44c988db7767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038405616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.2038405616
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2837521430
Short name T869
Test name
Test status
Simulation time 2012498915 ps
CPU time 6 seconds
Started Jun 07 08:28:25 PM PDT 24
Finished Jun 07 08:28:47 PM PDT 24
Peak memory 201540 kb
Host smart-45967d13-4db6-459a-b5cb-5f09158b60cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837521430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.2837521430
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1117021265
Short name T827
Test name
Test status
Simulation time 2024775544 ps
CPU time 3.13 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:34 PM PDT 24
Peak memory 201372 kb
Host smart-b317e0aa-9538-45b7-b925-8281a0c8fe23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117021265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.1117021265
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1791053115
Short name T800
Test name
Test status
Simulation time 2015548108 ps
CPU time 5.82 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:39 PM PDT 24
Peak memory 201424 kb
Host smart-ac6de8e9-f5ea-4680-bb9f-60e0bf085be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791053115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.1791053115
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.952291673
Short name T914
Test name
Test status
Simulation time 2026345517 ps
CPU time 1.98 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:35 PM PDT 24
Peak memory 201264 kb
Host smart-04ba96f2-cc72-4703-b967-e0cabcb892cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952291673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_tes
t.952291673
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.287211847
Short name T852
Test name
Test status
Simulation time 2013677277 ps
CPU time 5.26 seconds
Started Jun 07 08:28:17 PM PDT 24
Finished Jun 07 08:28:39 PM PDT 24
Peak memory 201312 kb
Host smart-bdb6f6e9-0cd4-4a5c-b78b-43af56e700f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287211847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_tes
t.287211847
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1705382340
Short name T306
Test name
Test status
Simulation time 2330229232 ps
CPU time 8.04 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201908 kb
Host smart-61db72cf-58b4-4e8d-87c0-19c3758f1658
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705382340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.1705382340
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4139623823
Short name T309
Test name
Test status
Simulation time 14969230272 ps
CPU time 9.13 seconds
Started Jun 07 08:28:19 PM PDT 24
Finished Jun 07 08:28:45 PM PDT 24
Peak memory 201888 kb
Host smart-ba9bf082-c5e6-4dc7-8794-4552fdd5bec3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139623823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.4139623823
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4118533016
Short name T915
Test name
Test status
Simulation time 6073678619 ps
CPU time 5.04 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:27 PM PDT 24
Peak memory 201776 kb
Host smart-bd33663f-9391-43d3-90e1-d3dbda4f03d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118533016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.4118533016
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3923866564
Short name T903
Test name
Test status
Simulation time 2186582253 ps
CPU time 2.61 seconds
Started Jun 07 08:28:04 PM PDT 24
Finished Jun 07 08:28:19 PM PDT 24
Peak memory 210304 kb
Host smart-cc576395-4ea5-4218-8ad5-10d7df4d1279
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923866564 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3923866564
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.916227493
Short name T825
Test name
Test status
Simulation time 2080403571 ps
CPU time 2.26 seconds
Started Jun 07 08:28:06 PM PDT 24
Finished Jun 07 08:28:21 PM PDT 24
Peak memory 201712 kb
Host smart-45588d0b-a6ff-4cf4-91fb-fa1e5f5908b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916227493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw
.916227493
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2587101446
Short name T824
Test name
Test status
Simulation time 2030426893 ps
CPU time 2.62 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:25 PM PDT 24
Peak memory 201592 kb
Host smart-2eb6ad63-a3b7-462c-9206-0eac7b3da1f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587101446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.2587101446
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.270807468
Short name T318
Test name
Test status
Simulation time 7182289075 ps
CPU time 18.83 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:41 PM PDT 24
Peak memory 201920 kb
Host smart-c042e895-a117-456e-a27f-bcff4f4e566b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270807468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
sysrst_ctrl_same_csr_outstanding.270807468
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3457962345
Short name T863
Test name
Test status
Simulation time 2364066775 ps
CPU time 3.17 seconds
Started Jun 07 08:28:06 PM PDT 24
Finished Jun 07 08:28:22 PM PDT 24
Peak memory 202052 kb
Host smart-b5b77bb6-3377-493e-b75f-403b00a09bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457962345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.3457962345
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2778412794
Short name T843
Test name
Test status
Simulation time 22190567390 ps
CPU time 64.58 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:29:28 PM PDT 24
Peak memory 201992 kb
Host smart-2fee00ea-95e9-4444-8228-4ba69c77972c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778412794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.2778412794
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3305534222
Short name T818
Test name
Test status
Simulation time 2014077284 ps
CPU time 3.25 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201352 kb
Host smart-052c4686-7442-4cc8-b400-57fdc43e72f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305534222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3305534222
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1482289025
Short name T899
Test name
Test status
Simulation time 2028042445 ps
CPU time 3.19 seconds
Started Jun 07 08:28:14 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201344 kb
Host smart-48aa1644-5a40-4a11-9b0e-7e7499d4ccb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482289025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.1482289025
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2850126458
Short name T802
Test name
Test status
Simulation time 2013846748 ps
CPU time 5.32 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:28 PM PDT 24
Peak memory 201396 kb
Host smart-e80a353c-d610-4337-9432-d5bbf613302f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850126458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.2850126458
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1316033665
Short name T876
Test name
Test status
Simulation time 2015729640 ps
CPU time 3.15 seconds
Started Jun 07 08:28:25 PM PDT 24
Finished Jun 07 08:28:44 PM PDT 24
Peak memory 201372 kb
Host smart-33bfd88a-5996-4f8c-b934-50ce020cdfd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316033665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.1316033665
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1085532621
Short name T878
Test name
Test status
Simulation time 2025487831 ps
CPU time 3.15 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:36 PM PDT 24
Peak memory 201428 kb
Host smart-1dfca44e-eda2-453b-bc30-35956e2078cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085532621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.1085532621
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.335270578
Short name T799
Test name
Test status
Simulation time 2027341204 ps
CPU time 2.56 seconds
Started Jun 07 08:28:33 PM PDT 24
Finished Jun 07 08:28:48 PM PDT 24
Peak memory 201392 kb
Host smart-4d5bfa81-8455-4445-bfb3-7df8a34117d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335270578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_tes
t.335270578
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2534241844
Short name T844
Test name
Test status
Simulation time 2011653201 ps
CPU time 5.66 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:38 PM PDT 24
Peak memory 201380 kb
Host smart-2c38b276-eefd-450d-8d57-f0fed0aafe3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534241844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.2534241844
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1314789379
Short name T904
Test name
Test status
Simulation time 2013909326 ps
CPU time 3.17 seconds
Started Jun 07 08:28:20 PM PDT 24
Finished Jun 07 08:28:40 PM PDT 24
Peak memory 201424 kb
Host smart-1510c603-b1f8-4313-90ad-ce9371cee0fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314789379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.1314789379
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3280037810
Short name T805
Test name
Test status
Simulation time 2032391286 ps
CPU time 1.93 seconds
Started Jun 07 08:28:17 PM PDT 24
Finished Jun 07 08:28:35 PM PDT 24
Peak memory 201376 kb
Host smart-281ec450-5f92-4e36-b56f-0989c872cd63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280037810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.3280037810
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.308234392
Short name T890
Test name
Test status
Simulation time 2013816482 ps
CPU time 5.87 seconds
Started Jun 07 08:28:16 PM PDT 24
Finished Jun 07 08:28:39 PM PDT 24
Peak memory 201248 kb
Host smart-ace14d54-11da-40ea-9548-55e927cd0267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308234392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_tes
t.308234392
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2453458513
Short name T860
Test name
Test status
Simulation time 2825987436 ps
CPU time 3.39 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201828 kb
Host smart-2be31d87-bd5d-4aae-9528-8cc2b1ef27f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453458513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.2453458513
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1722532556
Short name T875
Test name
Test status
Simulation time 29964475010 ps
CPU time 79.02 seconds
Started Jun 07 08:28:06 PM PDT 24
Finished Jun 07 08:29:38 PM PDT 24
Peak memory 201972 kb
Host smart-ab0792ea-6f5d-4194-9bcf-181cdd8b8c26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722532556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.1722532556
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1534227069
Short name T30
Test name
Test status
Simulation time 6074438937 ps
CPU time 4.45 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201828 kb
Host smart-b6462698-31b5-48e3-a894-83d104f870ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534227069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.1534227069
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1042844094
Short name T874
Test name
Test status
Simulation time 2152253498 ps
CPU time 2.4 seconds
Started Jun 07 08:28:32 PM PDT 24
Finished Jun 07 08:28:48 PM PDT 24
Peak memory 218244 kb
Host smart-8c50ca38-a5ae-4909-9eb2-0c5190cc1fd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042844094 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1042844094
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3584075862
Short name T870
Test name
Test status
Simulation time 2050069732 ps
CPU time 3.17 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:28 PM PDT 24
Peak memory 201608 kb
Host smart-3d517ca4-a603-45f4-9f08-1f9f15a18be7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584075862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3584075862
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3044711422
Short name T823
Test name
Test status
Simulation time 2038220089 ps
CPU time 1.5 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201400 kb
Host smart-4072c38b-bd01-40dd-aebf-b410729cbe78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044711422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.3044711422
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2459546900
Short name T845
Test name
Test status
Simulation time 9448003315 ps
CPU time 7.27 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:35 PM PDT 24
Peak memory 201944 kb
Host smart-e577de9b-8699-4e0e-a32c-5cb2ecfe464c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459546900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2459546900
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.4043827045
Short name T850
Test name
Test status
Simulation time 2064331090 ps
CPU time 2.91 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:29 PM PDT 24
Peak memory 201928 kb
Host smart-11ff8d76-0b1f-4bb5-96bd-5b7a00290492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043827045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.4043827045
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2138563682
Short name T343
Test name
Test status
Simulation time 42533302394 ps
CPU time 55.29 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201940 kb
Host smart-f78cdde8-2d16-45e3-bff9-06bbc6275be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138563682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.2138563682
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.45258514
Short name T880
Test name
Test status
Simulation time 2012890409 ps
CPU time 3.33 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201472 kb
Host smart-3481ee82-e073-4ac8-9230-c5d3eef36a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45258514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test
.45258514
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3816531026
Short name T813
Test name
Test status
Simulation time 2009657838 ps
CPU time 5.6 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:36 PM PDT 24
Peak memory 201176 kb
Host smart-aff4eb7f-dd29-4aeb-8df0-f14e5767243c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816531026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3816531026
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.830010303
Short name T801
Test name
Test status
Simulation time 2112779659 ps
CPU time 1.01 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201584 kb
Host smart-18d0d37a-09fb-40c6-8659-aa7200772ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830010303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_tes
t.830010303
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.327603228
Short name T811
Test name
Test status
Simulation time 2044762595 ps
CPU time 1.73 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:29 PM PDT 24
Peak memory 201376 kb
Host smart-cfd5fcdc-1cc6-4cac-ad35-ad153968729b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327603228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.327603228
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3981255750
Short name T883
Test name
Test status
Simulation time 2037141620 ps
CPU time 1.92 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:28 PM PDT 24
Peak memory 201392 kb
Host smart-d9d1a79c-6db9-444a-b8b2-c81fd4fb04ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981255750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.3981255750
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3130383428
Short name T871
Test name
Test status
Simulation time 2091713280 ps
CPU time 1.24 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:30 PM PDT 24
Peak memory 201372 kb
Host smart-50363879-7d5c-4185-ae0c-14686e72a443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130383428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.3130383428
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1353512449
Short name T803
Test name
Test status
Simulation time 2012302871 ps
CPU time 6.2 seconds
Started Jun 07 08:28:25 PM PDT 24
Finished Jun 07 08:28:47 PM PDT 24
Peak memory 201608 kb
Host smart-8056c825-565e-4957-999d-d9cd14f5864b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353512449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1353512449
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3656709982
Short name T861
Test name
Test status
Simulation time 2038099350 ps
CPU time 1.84 seconds
Started Jun 07 08:28:24 PM PDT 24
Finished Jun 07 08:28:42 PM PDT 24
Peak memory 201400 kb
Host smart-288c5625-52db-440c-8aca-cee07763380c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656709982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3656709982
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2817941966
Short name T854
Test name
Test status
Simulation time 2015370076 ps
CPU time 3.21 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201388 kb
Host smart-d3de4276-a4c0-44be-ac27-2a3c99550f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817941966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.2817941966
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1050196139
Short name T836
Test name
Test status
Simulation time 2040541842 ps
CPU time 1.83 seconds
Started Jun 07 08:28:22 PM PDT 24
Finished Jun 07 08:28:41 PM PDT 24
Peak memory 201408 kb
Host smart-ee70d551-51f7-4748-ad39-5149056521c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050196139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1050196139
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1090701583
Short name T892
Test name
Test status
Simulation time 2081349153 ps
CPU time 6.83 seconds
Started Jun 07 08:28:14 PM PDT 24
Finished Jun 07 08:28:37 PM PDT 24
Peak memory 201736 kb
Host smart-f2e1cbf2-3ac2-4742-9350-7dcc0980d3a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090701583 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1090701583
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.47401245
Short name T311
Test name
Test status
Simulation time 2047362465 ps
CPU time 3.18 seconds
Started Jun 07 08:28:07 PM PDT 24
Finished Jun 07 08:28:24 PM PDT 24
Peak memory 201648 kb
Host smart-82a1d6a4-339f-48dd-81d4-f83e352d7e20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47401245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.47401245
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2564088118
Short name T913
Test name
Test status
Simulation time 2058533487 ps
CPU time 1.13 seconds
Started Jun 07 08:28:14 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201564 kb
Host smart-2a9c0198-227e-4450-b2aa-6bca31b649b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564088118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.2564088118
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.4019900008
Short name T18
Test name
Test status
Simulation time 10157495546 ps
CPU time 9.44 seconds
Started Jun 07 08:28:06 PM PDT 24
Finished Jun 07 08:28:28 PM PDT 24
Peak memory 202008 kb
Host smart-5cafaf5a-56e9-479a-827f-793fc8836bf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019900008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.4019900008
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2925809555
Short name T884
Test name
Test status
Simulation time 2108145688 ps
CPU time 2.16 seconds
Started Jun 07 08:28:08 PM PDT 24
Finished Jun 07 08:28:24 PM PDT 24
Peak memory 201732 kb
Host smart-bfc86aab-cd4b-4b1f-b503-279ea5219e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925809555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2925809555
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.953314437
Short name T277
Test name
Test status
Simulation time 22422178508 ps
CPU time 18.89 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:51 PM PDT 24
Peak memory 201936 kb
Host smart-f099c8e1-1b53-4d77-96a2-d20ac1f0bc9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953314437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_tl_intg_err.953314437
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2596142169
Short name T866
Test name
Test status
Simulation time 2133084453 ps
CPU time 3.66 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:31 PM PDT 24
Peak memory 201780 kb
Host smart-816ac93e-254f-47ad-83bd-75a5e271e625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596142169 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2596142169
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.281288837
Short name T826
Test name
Test status
Simulation time 2047616974 ps
CPU time 3.63 seconds
Started Jun 07 08:28:14 PM PDT 24
Finished Jun 07 08:28:34 PM PDT 24
Peak memory 201564 kb
Host smart-08745ee3-248b-45dd-9bde-a3a8590240f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281288837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw
.281288837
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2895920095
Short name T868
Test name
Test status
Simulation time 2016356341 ps
CPU time 3.41 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201368 kb
Host smart-513d6c7c-0825-42f2-b415-769923cf8070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895920095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.2895920095
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.944666004
Short name T831
Test name
Test status
Simulation time 8548581572 ps
CPU time 6.34 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201956 kb
Host smart-66477370-b383-4f52-a1af-099ef90ec2dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944666004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_same_csr_outstanding.944666004
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.4275101958
Short name T847
Test name
Test status
Simulation time 2277940308 ps
CPU time 3.3 seconds
Started Jun 07 08:28:14 PM PDT 24
Finished Jun 07 08:28:33 PM PDT 24
Peak memory 201960 kb
Host smart-08966dbc-b442-4633-be32-bc924ad84f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275101958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.4275101958
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3514061386
Short name T279
Test name
Test status
Simulation time 22769574487 ps
CPU time 10.64 seconds
Started Jun 07 08:28:04 PM PDT 24
Finished Jun 07 08:28:27 PM PDT 24
Peak memory 202032 kb
Host smart-31c303af-177b-4d67-a026-a1ab1aa3212c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514061386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3514061386
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.378617702
Short name T369
Test name
Test status
Simulation time 2245838283 ps
CPU time 2.41 seconds
Started Jun 07 08:28:10 PM PDT 24
Finished Jun 07 08:28:27 PM PDT 24
Peak memory 202100 kb
Host smart-5fc67e37-7bd0-4570-afe2-18d4a0e90b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378617702 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.378617702
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.827539996
Short name T910
Test name
Test status
Simulation time 2119492176 ps
CPU time 2.02 seconds
Started Jun 07 08:28:18 PM PDT 24
Finished Jun 07 08:28:37 PM PDT 24
Peak memory 201616 kb
Host smart-0a80bb49-07bc-4922-b4fa-9c7f414caacf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827539996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw
.827539996
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1270282726
Short name T819
Test name
Test status
Simulation time 2009632586 ps
CPU time 6.06 seconds
Started Jun 07 08:28:10 PM PDT 24
Finished Jun 07 08:28:29 PM PDT 24
Peak memory 201404 kb
Host smart-5fb3e79d-638e-4694-9a32-f27a02633677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270282726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.1270282726
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1731762838
Short name T849
Test name
Test status
Simulation time 4796084741 ps
CPU time 13.29 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:41 PM PDT 24
Peak memory 201684 kb
Host smart-62be7089-f10a-46dc-85d6-f4d1d545f852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731762838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.1731762838
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1294326391
Short name T278
Test name
Test status
Simulation time 2158093291 ps
CPU time 2.59 seconds
Started Jun 07 08:28:30 PM PDT 24
Finished Jun 07 08:28:46 PM PDT 24
Peak memory 201792 kb
Host smart-60b09fa1-54df-499c-a5dc-acc14168a2c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294326391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1294326391
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3699012320
Short name T27
Test name
Test status
Simulation time 22500732246 ps
CPU time 16.2 seconds
Started Jun 07 08:28:19 PM PDT 24
Finished Jun 07 08:28:52 PM PDT 24
Peak memory 202076 kb
Host smart-bc0840e5-60d4-4194-9766-8b4968732b02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699012320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.3699012320
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.524156064
Short name T301
Test name
Test status
Simulation time 2068063345 ps
CPU time 6.14 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:29 PM PDT 24
Peak memory 201796 kb
Host smart-9a3d62aa-b9bc-457d-ae91-d68f62e27043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524156064 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.524156064
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.267202218
Short name T820
Test name
Test status
Simulation time 2104504869 ps
CPU time 1.66 seconds
Started Jun 07 08:28:09 PM PDT 24
Finished Jun 07 08:28:25 PM PDT 24
Peak memory 201700 kb
Host smart-c6073297-8de7-4a5b-8c44-4ebd2d345a79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267202218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw
.267202218
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1616619692
Short name T809
Test name
Test status
Simulation time 2034076659 ps
CPU time 1.98 seconds
Started Jun 07 08:28:13 PM PDT 24
Finished Jun 07 08:28:32 PM PDT 24
Peak memory 201356 kb
Host smart-1622e7e8-08e5-4486-b5fb-e78d7876fe41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616619692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.1616619692
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.583017886
Short name T867
Test name
Test status
Simulation time 10347288751 ps
CPU time 22.51 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:55 PM PDT 24
Peak memory 201992 kb
Host smart-f40b532e-3025-4f8d-94ef-6fc641d2efd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583017886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
sysrst_ctrl_same_csr_outstanding.583017886
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.906746211
Short name T828
Test name
Test status
Simulation time 2642223069 ps
CPU time 4.03 seconds
Started Jun 07 08:28:04 PM PDT 24
Finished Jun 07 08:28:20 PM PDT 24
Peak memory 201948 kb
Host smart-12014157-d712-49a5-88b1-3b237f25f05f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906746211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors
.906746211
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1253232068
Short name T371
Test name
Test status
Simulation time 42979827351 ps
CPU time 30.4 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:57 PM PDT 24
Peak memory 201996 kb
Host smart-36a75f97-6415-4204-93da-9ea929b155b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253232068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1253232068
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.966214907
Short name T912
Test name
Test status
Simulation time 2195071314 ps
CPU time 2.58 seconds
Started Jun 07 08:28:15 PM PDT 24
Finished Jun 07 08:28:34 PM PDT 24
Peak memory 202004 kb
Host smart-4d1a64cc-c28e-457d-9a9b-b2ac2af11f1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966214907 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.966214907
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2318611190
Short name T29
Test name
Test status
Simulation time 2088880727 ps
CPU time 1.48 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:28 PM PDT 24
Peak memory 201632 kb
Host smart-8214ba82-400e-43fa-8d76-36faa803533c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318611190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.2318611190
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1943378998
Short name T822
Test name
Test status
Simulation time 2019784765 ps
CPU time 2.88 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:29 PM PDT 24
Peak memory 201540 kb
Host smart-5834f0eb-010d-41ad-9205-67a724ff0209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943378998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.1943378998
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2202507575
Short name T858
Test name
Test status
Simulation time 9110763549 ps
CPU time 10.03 seconds
Started Jun 07 08:28:12 PM PDT 24
Finished Jun 07 08:28:37 PM PDT 24
Peak memory 201904 kb
Host smart-7b27e416-9cd6-4380-a447-030b58eb2683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202507575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.2202507575
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.383408422
Short name T283
Test name
Test status
Simulation time 2049487051 ps
CPU time 7.93 seconds
Started Jun 07 08:28:10 PM PDT 24
Finished Jun 07 08:28:31 PM PDT 24
Peak memory 201928 kb
Host smart-3d63975e-a030-455a-bc4a-9e6350075c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383408422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors
.383408422
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3345965132
Short name T340
Test name
Test status
Simulation time 22266735105 ps
CPU time 17.92 seconds
Started Jun 07 08:28:11 PM PDT 24
Finished Jun 07 08:28:44 PM PDT 24
Peak memory 201968 kb
Host smart-8b9dee4a-eebc-47ff-9b3d-993501bcae19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345965132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.3345965132
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.3846189251
Short name T794
Test name
Test status
Simulation time 2015340107 ps
CPU time 5.8 seconds
Started Jun 07 08:29:27 PM PDT 24
Finished Jun 07 08:29:46 PM PDT 24
Peak memory 201956 kb
Host smart-ae2568c9-8b9f-4920-9f57-c83eab8a582f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846189251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.3846189251
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.592118500
Short name T713
Test name
Test status
Simulation time 3321668937 ps
CPU time 7.97 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:29:51 PM PDT 24
Peak memory 202036 kb
Host smart-9bd6ded9-fc4f-46f7-9f50-efc3ed529dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592118500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.592118500
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.723528085
Short name T257
Test name
Test status
Simulation time 153630772193 ps
CPU time 100.66 seconds
Started Jun 07 08:29:43 PM PDT 24
Finished Jun 07 08:31:32 PM PDT 24
Peak memory 202176 kb
Host smart-c2a3ccfa-0c6d-4cd9-9476-a79c88ad12ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723528085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_combo_detect.723528085
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2937679467
Short name T735
Test name
Test status
Simulation time 2208486634 ps
CPU time 1.54 seconds
Started Jun 07 08:29:28 PM PDT 24
Finished Jun 07 08:29:42 PM PDT 24
Peak memory 201992 kb
Host smart-d7db983b-9508-435a-b21e-bba5a3cdc640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937679467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2937679467
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1504735241
Short name T224
Test name
Test status
Simulation time 2525966763 ps
CPU time 4.19 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:29:46 PM PDT 24
Peak memory 202108 kb
Host smart-020374ab-0d9f-48d5-8a77-ba83c9ff1578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504735241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1504735241
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.4232743869
Short name T610
Test name
Test status
Simulation time 204948135861 ps
CPU time 135.48 seconds
Started Jun 07 08:29:38 PM PDT 24
Finished Jun 07 08:32:03 PM PDT 24
Peak memory 202260 kb
Host smart-4dda60f6-5f4d-41fc-803f-659dcc2103f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232743869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.4232743869
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4129821189
Short name T469
Test name
Test status
Simulation time 3648568039 ps
CPU time 5.15 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:29:57 PM PDT 24
Peak memory 202036 kb
Host smart-ae20c66e-1ef5-4597-964d-f9cf07ccb720
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129821189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.4129821189
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.586478020
Short name T201
Test name
Test status
Simulation time 510803303897 ps
CPU time 604.6 seconds
Started Jun 07 08:29:34 PM PDT 24
Finished Jun 07 08:39:50 PM PDT 24
Peak memory 201988 kb
Host smart-7440f521-edaa-40c6-bd71-c7a5073a0867
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586478020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_edge_detect.586478020
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2804112892
Short name T468
Test name
Test status
Simulation time 2628229582 ps
CPU time 2.43 seconds
Started Jun 07 08:29:31 PM PDT 24
Finished Jun 07 08:29:45 PM PDT 24
Peak memory 201972 kb
Host smart-146d25e1-0f1f-4547-b96c-1fdfe973d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804112892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.2804112892
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3456155403
Short name T597
Test name
Test status
Simulation time 2456778132 ps
CPU time 6.62 seconds
Started Jun 07 08:29:31 PM PDT 24
Finished Jun 07 08:29:50 PM PDT 24
Peak memory 201872 kb
Host smart-dc49ae07-cf1d-4dbf-99a4-d6a15a746a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456155403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3456155403
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3749372391
Short name T83
Test name
Test status
Simulation time 2195912916 ps
CPU time 2.58 seconds
Started Jun 07 08:29:27 PM PDT 24
Finished Jun 07 08:29:43 PM PDT 24
Peak memory 202016 kb
Host smart-c767ad16-465b-4475-8293-a655f5085703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749372391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.3749372391
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2278444625
Short name T740
Test name
Test status
Simulation time 2511065437 ps
CPU time 7.44 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:29:50 PM PDT 24
Peak memory 201936 kb
Host smart-884357a3-d4f1-47c4-93d3-88484127022b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278444625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2278444625
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.3677909825
Short name T747
Test name
Test status
Simulation time 2168287051 ps
CPU time 1.34 seconds
Started Jun 07 08:29:25 PM PDT 24
Finished Jun 07 08:29:40 PM PDT 24
Peak memory 202008 kb
Host smart-27e34f74-c1d6-454a-b4dc-e940cbd76d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677909825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.3677909825
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.4136315562
Short name T228
Test name
Test status
Simulation time 16985452094 ps
CPU time 21.51 seconds
Started Jun 07 08:29:22 PM PDT 24
Finished Jun 07 08:29:58 PM PDT 24
Peak memory 201936 kb
Host smart-ef83c7c3-9115-48b0-8573-3f7a95aab9d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136315562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.4136315562
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3679896924
Short name T289
Test name
Test status
Simulation time 17946780782 ps
CPU time 24.19 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:30:06 PM PDT 24
Peak memory 202320 kb
Host smart-efea4aeb-75f3-4525-b68e-d4fca2ac7a21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679896924 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.3679896924
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1220914793
Short name T77
Test name
Test status
Simulation time 9852227063 ps
CPU time 7.38 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:29:49 PM PDT 24
Peak memory 202028 kb
Host smart-9cdd043c-360a-4ea6-988e-b2d170d07c14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220914793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.1220914793
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.805481480
Short name T424
Test name
Test status
Simulation time 2029857252 ps
CPU time 1.94 seconds
Started Jun 07 08:29:24 PM PDT 24
Finished Jun 07 08:29:39 PM PDT 24
Peak memory 202028 kb
Host smart-55c13276-012e-4afa-bdef-6a3a31e278c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805481480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test
.805481480
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3577984925
Short name T734
Test name
Test status
Simulation time 3527931708 ps
CPU time 10.28 seconds
Started Jun 07 08:29:35 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 202048 kb
Host smart-3ad5d5d0-9d3e-4848-bfc3-79021355f228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577984925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.3577984925
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1878204367
Short name T173
Test name
Test status
Simulation time 2267104283 ps
CPU time 2.15 seconds
Started Jun 07 08:29:41 PM PDT 24
Finished Jun 07 08:29:52 PM PDT 24
Peak memory 202068 kb
Host smart-8ae877a6-856c-4aad-b8a8-11c5fd76436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878204367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1878204367
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.848591753
Short name T464
Test name
Test status
Simulation time 2302662495 ps
CPU time 7.24 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:29:49 PM PDT 24
Peak memory 202108 kb
Host smart-c9d0675f-75bd-43ae-99b8-9185741a4897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848591753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.848591753
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2761637588
Short name T466
Test name
Test status
Simulation time 4101407165 ps
CPU time 3.33 seconds
Started Jun 07 08:29:26 PM PDT 24
Finished Jun 07 08:29:42 PM PDT 24
Peak memory 201980 kb
Host smart-61ef66c6-8a32-454f-b835-8dec529b39f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761637588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.2761637588
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.2004942061
Short name T38
Test name
Test status
Simulation time 4266521474 ps
CPU time 4.88 seconds
Started Jun 07 08:29:26 PM PDT 24
Finished Jun 07 08:29:44 PM PDT 24
Peak memory 202012 kb
Host smart-114fa6f7-f413-4d88-b877-ecb8e045a711
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004942061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.2004942061
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.270913427
Short name T739
Test name
Test status
Simulation time 2639259813 ps
CPU time 2.38 seconds
Started Jun 07 08:29:26 PM PDT 24
Finished Jun 07 08:29:41 PM PDT 24
Peak memory 201924 kb
Host smart-661bf734-ef86-45db-aac7-c921ad0faa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270913427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.270913427
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.724466879
Short name T404
Test name
Test status
Simulation time 2458135828 ps
CPU time 7.59 seconds
Started Jun 07 08:29:27 PM PDT 24
Finished Jun 07 08:29:48 PM PDT 24
Peak memory 202060 kb
Host smart-d5116587-5e17-4f37-be38-4fb42d69473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724466879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.724466879
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.4214939115
Short name T635
Test name
Test status
Simulation time 2240882398 ps
CPU time 6.28 seconds
Started Jun 07 08:29:37 PM PDT 24
Finished Jun 07 08:29:54 PM PDT 24
Peak memory 202020 kb
Host smart-ea5b0e56-2497-47b1-a4b4-fcb50775c04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214939115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.4214939115
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2201599267
Short name T275
Test name
Test status
Simulation time 22009594737 ps
CPU time 58.94 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 221844 kb
Host smart-5d8556b0-ae88-4114-9385-f24c0720b3b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201599267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2201599267
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2674972737
Short name T642
Test name
Test status
Simulation time 2111172559 ps
CPU time 6.27 seconds
Started Jun 07 08:29:27 PM PDT 24
Finished Jun 07 08:29:46 PM PDT 24
Peak memory 201888 kb
Host smart-851a03a0-7f6a-4430-be5a-0be73b864eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674972737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2674972737
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.2444615945
Short name T494
Test name
Test status
Simulation time 12520981678 ps
CPU time 14.33 seconds
Started Jun 07 08:29:34 PM PDT 24
Finished Jun 07 08:30:00 PM PDT 24
Peak memory 202028 kb
Host smart-17d25693-a124-4cb6-be5f-191cad3ff98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444615945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.2444615945
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3602098926
Short name T37
Test name
Test status
Simulation time 23961443178 ps
CPU time 67.13 seconds
Started Jun 07 08:29:27 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 210636 kb
Host smart-e6787592-e0ff-48fe-beb9-809eaa78e248
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602098926 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.3602098926
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.540875098
Short name T196
Test name
Test status
Simulation time 2039075976 ps
CPU time 1.97 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:30:01 PM PDT 24
Peak memory 202028 kb
Host smart-ddb1fc87-a015-4985-a6c4-6e402994fcf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540875098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_tes
t.540875098
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2704043462
Short name T573
Test name
Test status
Simulation time 3701762485 ps
CPU time 9.57 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:30:09 PM PDT 24
Peak memory 202040 kb
Host smart-13b578e9-b913-4a2f-835b-55d27b03927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704043462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2
704043462
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.4217223601
Short name T294
Test name
Test status
Simulation time 3482392212 ps
CPU time 3.13 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:30:02 PM PDT 24
Peak memory 201996 kb
Host smart-a97aea3d-8ec3-4750-8084-210b633dbbbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217223601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.4217223601
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.237710150
Short name T181
Test name
Test status
Simulation time 2469619995 ps
CPU time 3.6 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:30:03 PM PDT 24
Peak memory 202024 kb
Host smart-e4ca3618-4732-4d33-aaec-f5aa1ffc1679
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237710150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctr
l_edge_detect.237710150
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2805037702
Short name T440
Test name
Test status
Simulation time 2632575347 ps
CPU time 2.47 seconds
Started Jun 07 08:30:00 PM PDT 24
Finished Jun 07 08:30:14 PM PDT 24
Peak memory 201988 kb
Host smart-0f88a8f3-88c2-4057-a58c-6d380e34b079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805037702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2805037702
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.43887751
Short name T392
Test name
Test status
Simulation time 2475373121 ps
CPU time 4.28 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:30:04 PM PDT 24
Peak memory 201988 kb
Host smart-6cb79214-3bb6-42f6-9f23-db602e6f511e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43887751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.43887751
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.917566218
Short name T592
Test name
Test status
Simulation time 2101517920 ps
CPU time 2.47 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:30:05 PM PDT 24
Peak memory 201856 kb
Host smart-6efb2c64-2c6b-475c-b464-3db095c83032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917566218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.917566218
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1007393516
Short name T579
Test name
Test status
Simulation time 2514436829 ps
CPU time 4.24 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:30:03 PM PDT 24
Peak memory 202048 kb
Host smart-1678d294-fb37-48ba-982f-994cb57eeb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007393516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1007393516
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.2950170738
Short name T447
Test name
Test status
Simulation time 2183747013 ps
CPU time 1.18 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:30:00 PM PDT 24
Peak memory 201988 kb
Host smart-51ed94c0-43a9-4a03-a197-da44f59265d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950170738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.2950170738
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.3891153959
Short name T647
Test name
Test status
Simulation time 204242296656 ps
CPU time 547.56 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:39:07 PM PDT 24
Peak memory 202056 kb
Host smart-66cfe26c-fa0e-46a5-957d-30b45e38320b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891153959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.3891153959
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1724439114
Short name T258
Test name
Test status
Simulation time 153158257662 ps
CPU time 98.05 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:31:37 PM PDT 24
Peak memory 211856 kb
Host smart-da131baa-457d-40d6-8cf8-186d580b9355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724439114 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1724439114
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3365454762
Short name T129
Test name
Test status
Simulation time 6651787119 ps
CPU time 1.79 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:30:04 PM PDT 24
Peak memory 202032 kb
Host smart-99595f0d-5a52-41ae-8427-92ced2cc81a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365454762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.3365454762
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.132169903
Short name T788
Test name
Test status
Simulation time 2030902582 ps
CPU time 1.98 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:30:05 PM PDT 24
Peak memory 201980 kb
Host smart-58fe2bff-83a2-4b5a-aff5-561d7a2a2070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132169903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_tes
t.132169903
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2481858835
Short name T291
Test name
Test status
Simulation time 3140172035 ps
CPU time 2.67 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:09 PM PDT 24
Peak memory 202084 kb
Host smart-97f69dfa-23d6-4038-8a3e-4428913d40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481858835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
481858835
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2404154092
Short name T94
Test name
Test status
Simulation time 87653262524 ps
CPU time 60.34 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:31:04 PM PDT 24
Peak memory 202196 kb
Host smart-ea01aea2-0b9a-488a-8661-90c8b955dda0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404154092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.2404154092
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.4184440881
Short name T234
Test name
Test status
Simulation time 3459793159 ps
CPU time 2.97 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:09 PM PDT 24
Peak memory 202016 kb
Host smart-5c53d31a-183e-472f-b410-cc67ef74994f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184440881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.4184440881
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.54328206
Short name T473
Test name
Test status
Simulation time 2616896896 ps
CPU time 4.02 seconds
Started Jun 07 08:29:57 PM PDT 24
Finished Jun 07 08:30:11 PM PDT 24
Peak memory 202000 kb
Host smart-9cdf41f9-4c9d-41f1-9b2a-cb120ebe2998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54328206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.54328206
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.2784094175
Short name T533
Test name
Test status
Simulation time 2481926468 ps
CPU time 4.07 seconds
Started Jun 07 08:29:53 PM PDT 24
Finished Jun 07 08:30:06 PM PDT 24
Peak memory 201980 kb
Host smart-06fda57a-6e5b-4509-9cb0-eeaddea60eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784094175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.2784094175
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1496875599
Short name T550
Test name
Test status
Simulation time 2251596964 ps
CPU time 3.6 seconds
Started Jun 07 08:29:53 PM PDT 24
Finished Jun 07 08:30:05 PM PDT 24
Peak memory 201988 kb
Host smart-cc9bcdb0-691a-49e5-8467-5993019394e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496875599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1496875599
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3685416319
Short name T571
Test name
Test status
Simulation time 2525756328 ps
CPU time 2.29 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:08 PM PDT 24
Peak memory 202104 kb
Host smart-76b1fb58-8651-4053-b09b-4b7d2c34336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685416319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3685416319
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.2748750715
Short name T729
Test name
Test status
Simulation time 2142521029 ps
CPU time 1.82 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:30:12 PM PDT 24
Peak memory 201888 kb
Host smart-767143db-0be5-456d-87c9-aa1a0e4f2605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748750715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2748750715
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1804717246
Short name T141
Test name
Test status
Simulation time 52793555093 ps
CPU time 31.9 seconds
Started Jun 07 08:30:01 PM PDT 24
Finished Jun 07 08:30:44 PM PDT 24
Peak memory 218692 kb
Host smart-2943c06c-840d-4642-932f-c002bbb8e835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804717246 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.1804717246
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1357365884
Short name T115
Test name
Test status
Simulation time 6651709728 ps
CPU time 6.74 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:30:10 PM PDT 24
Peak memory 201984 kb
Host smart-69cd3510-245c-4aca-92eb-7e55058dcc43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357365884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1357365884
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.3280262452
Short name T731
Test name
Test status
Simulation time 2008699886 ps
CPU time 5.48 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:30:11 PM PDT 24
Peak memory 202044 kb
Host smart-0b5289e9-2139-4bfc-910d-575964039f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280262452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.3280262452
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1818348322
Short name T733
Test name
Test status
Simulation time 3158120335 ps
CPU time 4.88 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:30:08 PM PDT 24
Peak memory 202060 kb
Host smart-a80d9b1e-c9ef-4aa3-9422-7d8e80d72c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818348322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1
818348322
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3012148834
Short name T359
Test name
Test status
Simulation time 59909272472 ps
CPU time 23.14 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 202276 kb
Host smart-f01036f3-92ff-4c0a-9084-7e04e328db13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012148834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.3012148834
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.481858318
Short name T542
Test name
Test status
Simulation time 4734691909 ps
CPU time 12.37 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 202028 kb
Host smart-1a8c7623-69c9-4ff7-ba9d-a76439dd146c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481858318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ec_pwr_on_rst.481858318
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2248580243
Short name T151
Test name
Test status
Simulation time 3015741523 ps
CPU time 6.73 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:30:10 PM PDT 24
Peak memory 202012 kb
Host smart-14457a5e-dc01-4bb6-a1bb-99b4cc630e05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248580243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.2248580243
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.1473347759
Short name T623
Test name
Test status
Simulation time 2614007130 ps
CPU time 5.07 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:30:09 PM PDT 24
Peak memory 202036 kb
Host smart-2731e30a-34af-4f9b-9d9b-692793f23d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473347759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.1473347759
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.273885693
Short name T215
Test name
Test status
Simulation time 2460981210 ps
CPU time 7.24 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:14 PM PDT 24
Peak memory 202000 kb
Host smart-d661db5a-deac-414c-a5f5-f12c7a9079aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273885693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.273885693
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3337672566
Short name T538
Test name
Test status
Simulation time 2254030598 ps
CPU time 1.48 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:08 PM PDT 24
Peak memory 202020 kb
Host smart-16046d40-80d3-4a29-bae4-f78a341e246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337672566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.3337672566
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3516684903
Short name T514
Test name
Test status
Simulation time 2517859101 ps
CPU time 3.9 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:30:14 PM PDT 24
Peak memory 202036 kb
Host smart-9fdb9952-9e3a-47bd-ab56-eb86a89f41e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516684903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3516684903
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.1710761847
Short name T266
Test name
Test status
Simulation time 2114945815 ps
CPU time 6.2 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:30:10 PM PDT 24
Peak memory 201860 kb
Host smart-997793f4-48c1-4575-a5e0-d4cc4dd396a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710761847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1710761847
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.1956376832
Short name T737
Test name
Test status
Simulation time 91241565845 ps
CPU time 122.72 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 202212 kb
Host smart-7d650f1a-b951-4066-b04c-ffc5904b1e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956376832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.1956376832
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2564915296
Short name T539
Test name
Test status
Simulation time 23224194672 ps
CPU time 30.5 seconds
Started Jun 07 08:29:58 PM PDT 24
Finished Jun 07 08:30:39 PM PDT 24
Peak memory 202316 kb
Host smart-8498d767-6ff7-4d4b-be42-edc9eb59649f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564915296 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.2564915296
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.1472089745
Short name T508
Test name
Test status
Simulation time 2011178149 ps
CPU time 5.26 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:19 PM PDT 24
Peak memory 201980 kb
Host smart-d77453ea-5385-407c-8aa5-f28cae228f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472089745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.1472089745
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.556591304
Short name T577
Test name
Test status
Simulation time 3691801058 ps
CPU time 4.29 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:30:14 PM PDT 24
Peak memory 202124 kb
Host smart-a48ed549-f471-4994-a3cf-419c5c4f49c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556591304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.556591304
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1471712105
Short name T745
Test name
Test status
Simulation time 27078566115 ps
CPU time 69.25 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 202332 kb
Host smart-4886755c-ff77-4600-95cc-53c77257e167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471712105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.1471712105
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1806459538
Short name T416
Test name
Test status
Simulation time 4237283450 ps
CPU time 10.63 seconds
Started Jun 07 08:29:55 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 202016 kb
Host smart-eeee3dc2-7097-41be-afc2-00e14d8e3fe3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806459538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1806459538
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2014996184
Short name T230
Test name
Test status
Simulation time 2839656556 ps
CPU time 7.79 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:30:11 PM PDT 24
Peak memory 202028 kb
Host smart-911d7d82-fd29-4d8e-8472-d6aadea3404f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014996184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.2014996184
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1116450254
Short name T418
Test name
Test status
Simulation time 2633871881 ps
CPU time 2.29 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:30:05 PM PDT 24
Peak memory 202044 kb
Host smart-80319eee-dd79-4ca8-bb3c-a28794477783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116450254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1116450254
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.2165376934
Short name T505
Test name
Test status
Simulation time 2512318482 ps
CPU time 2.3 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:09 PM PDT 24
Peak memory 202000 kb
Host smart-d453170a-0562-49bf-b29e-bf782bdedb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165376934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.2165376934
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1103326951
Short name T456
Test name
Test status
Simulation time 2135809628 ps
CPU time 1.7 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:30:12 PM PDT 24
Peak memory 201944 kb
Host smart-834cf7f9-258a-460e-bad1-adec29c31f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103326951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1103326951
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3207776832
Short name T634
Test name
Test status
Simulation time 2544810170 ps
CPU time 1.72 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:30:04 PM PDT 24
Peak memory 202044 kb
Host smart-df149030-a6b3-4245-8305-3112ec0a2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207776832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3207776832
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.3794849998
Short name T195
Test name
Test status
Simulation time 2114544978 ps
CPU time 5.92 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 201892 kb
Host smart-0e535669-daf4-474b-8682-85b2d4af96c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794849998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3794849998
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3282197801
Short name T108
Test name
Test status
Simulation time 15269800059 ps
CPU time 37.13 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:44 PM PDT 24
Peak memory 218372 kb
Host smart-21ae3e39-6e5c-4fe3-af1f-cb01f2679f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282197801 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3282197801
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3387449972
Short name T126
Test name
Test status
Simulation time 6455698943 ps
CPU time 8.26 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:14 PM PDT 24
Peak memory 202024 kb
Host smart-b782532d-6e1d-4a5a-8811-5d0b293b9f68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387449972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.3387449972
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2471194568
Short name T478
Test name
Test status
Simulation time 2050697601 ps
CPU time 1.86 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:15 PM PDT 24
Peak memory 202044 kb
Host smart-7358ba06-7d6d-4817-af4c-b6ed840fd9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471194568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2471194568
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2847098515
Short name T419
Test name
Test status
Simulation time 3412566423 ps
CPU time 4.96 seconds
Started Jun 07 08:30:01 PM PDT 24
Finished Jun 07 08:30:18 PM PDT 24
Peak memory 202120 kb
Host smart-6541e06e-17ac-4b9b-9736-d955ba6cc8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847098515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2
847098515
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3845241178
Short name T662
Test name
Test status
Simulation time 122186609980 ps
CPU time 317.48 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 202308 kb
Host smart-0e2ffab5-78c6-488c-9ba6-09af92abd690
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845241178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3845241178
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.4120934052
Short name T678
Test name
Test status
Simulation time 2726636022 ps
CPU time 8.3 seconds
Started Jun 07 08:30:04 PM PDT 24
Finished Jun 07 08:30:24 PM PDT 24
Peak memory 201992 kb
Host smart-afac89f9-e912-42a4-8a23-c969c489f18c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120934052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.4120934052
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2618184069
Short name T203
Test name
Test status
Simulation time 3253131056 ps
CPU time 2.81 seconds
Started Jun 07 08:30:01 PM PDT 24
Finished Jun 07 08:30:15 PM PDT 24
Peak memory 202016 kb
Host smart-ca69b9f3-5a29-4955-b6bc-a07b4bbffe91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618184069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2618184069
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2447589692
Short name T715
Test name
Test status
Simulation time 2608959314 ps
CPU time 7.25 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:21 PM PDT 24
Peak memory 202028 kb
Host smart-1adc6183-7974-444c-a707-f075e2aa27bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447589692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.2447589692
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1220215865
Short name T172
Test name
Test status
Simulation time 2485519691 ps
CPU time 2.31 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 201996 kb
Host smart-840352da-45b3-4c51-87e6-cc6853f85198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220215865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1220215865
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2284805255
Short name T438
Test name
Test status
Simulation time 2253736638 ps
CPU time 6.52 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 202000 kb
Host smart-1b5ff0b6-b2e0-4f88-9e14-347e9bb7a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284805255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2284805255
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2524945149
Short name T217
Test name
Test status
Simulation time 2530487609 ps
CPU time 2.5 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 201964 kb
Host smart-c82d43d1-5df7-4670-81d0-95069770aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524945149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.2524945149
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.66852614
Short name T676
Test name
Test status
Simulation time 2107648644 ps
CPU time 5.99 seconds
Started Jun 07 08:30:01 PM PDT 24
Finished Jun 07 08:30:19 PM PDT 24
Peak memory 201912 kb
Host smart-74e4c245-dfe3-483f-9ee1-80ede5de3b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66852614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.66852614
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.2178389805
Short name T648
Test name
Test status
Simulation time 51182869676 ps
CPU time 138.31 seconds
Started Jun 07 08:30:01 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 210576 kb
Host smart-c1858b66-7eef-4c8f-a047-50d8e4c4c3d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178389805 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.2178389805
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2046023332
Short name T72
Test name
Test status
Simulation time 4640139627 ps
CPU time 2.2 seconds
Started Jun 07 08:30:06 PM PDT 24
Finished Jun 07 08:30:19 PM PDT 24
Peak memory 202036 kb
Host smart-d4778a07-886c-45e6-aa00-8d5f7b06d25a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046023332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.2046023332
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.109610079
Short name T598
Test name
Test status
Simulation time 2061663025 ps
CPU time 1.13 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:20 PM PDT 24
Peak memory 202020 kb
Host smart-a164876b-7a67-4fa0-b34d-938f4409d841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109610079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.109610079
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2190151431
Short name T407
Test name
Test status
Simulation time 3526933430 ps
CPU time 9.55 seconds
Started Jun 07 08:29:59 PM PDT 24
Finished Jun 07 08:30:20 PM PDT 24
Peak memory 202196 kb
Host smart-c692c5bd-a2dc-406b-bbb8-36fdfb412840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190151431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
190151431
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.223310796
Short name T264
Test name
Test status
Simulation time 26123191878 ps
CPU time 13.14 seconds
Started Jun 07 08:30:04 PM PDT 24
Finished Jun 07 08:30:29 PM PDT 24
Peak memory 202192 kb
Host smart-45c831dc-cb28-4a28-a918-61d70a9d470a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223310796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_combo_detect.223310796
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3832933108
Short name T714
Test name
Test status
Simulation time 4043579767 ps
CPU time 5.85 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:19 PM PDT 24
Peak memory 202012 kb
Host smart-2ca09b59-fee2-402f-8a97-e8bf35d606bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832933108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.3832933108
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1274881975
Short name T608
Test name
Test status
Simulation time 2632320556 ps
CPU time 2.37 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:30:17 PM PDT 24
Peak memory 201984 kb
Host smart-e647fc9d-3433-49bb-8781-33a77d15e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274881975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1274881975
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.279612800
Short name T400
Test name
Test status
Simulation time 2473259373 ps
CPU time 2.41 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:20 PM PDT 24
Peak memory 201992 kb
Host smart-07bb3e04-7157-42ee-b5b6-0020dfd0ffe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279612800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.279612800
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3088093307
Short name T496
Test name
Test status
Simulation time 2071650961 ps
CPU time 1.9 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:21 PM PDT 24
Peak memory 201896 kb
Host smart-39c51a69-9afb-4895-94a0-13dff1add568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088093307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3088093307
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.4095746447
Short name T558
Test name
Test status
Simulation time 2516769232 ps
CPU time 3.64 seconds
Started Jun 07 08:30:01 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 202064 kb
Host smart-ee8bbaa4-628f-4d73-b8d2-2ed35d7e6251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095746447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.4095746447
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3856941243
Short name T614
Test name
Test status
Simulation time 2135072269 ps
CPU time 1.63 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:19 PM PDT 24
Peak memory 201916 kb
Host smart-85781138-f445-4d62-b6c9-5a00e0f38402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856941243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3856941243
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.671435554
Short name T643
Test name
Test status
Simulation time 6508738951 ps
CPU time 9.57 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 202004 kb
Host smart-1c11296b-6d6c-46a5-9b29-8d44f3e292fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671435554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_st
ress_all.671435554
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1673332874
Short name T461
Test name
Test status
Simulation time 6784240901 ps
CPU time 8.85 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 202032 kb
Host smart-843b0115-20aa-42c5-a586-40ff98b1f98e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673332874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.1673332874
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.789275823
Short name T401
Test name
Test status
Simulation time 2012884875 ps
CPU time 4.74 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:24 PM PDT 24
Peak memory 202028 kb
Host smart-f01a4f2e-4636-492e-a54f-0a431ab5321c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789275823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.789275823
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1911186515
Short name T493
Test name
Test status
Simulation time 3039442960 ps
CPU time 2.59 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 202056 kb
Host smart-b3639b03-e7b6-4a74-9b78-73f8e239c208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911186515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1
911186515
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1523594775
Short name T366
Test name
Test status
Simulation time 71650359352 ps
CPU time 33.6 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:52 PM PDT 24
Peak memory 202252 kb
Host smart-50ae6b09-25d6-47d1-b979-cc5a476c53f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523594775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1523594775
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2595851158
Short name T88
Test name
Test status
Simulation time 45806380910 ps
CPU time 28.52 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:48 PM PDT 24
Peak memory 202280 kb
Host smart-b66698b5-5d61-4726-9275-a180dc1620ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595851158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2595851158
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3290866636
Short name T270
Test name
Test status
Simulation time 2939240161 ps
CPU time 2.36 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:16 PM PDT 24
Peak memory 201980 kb
Host smart-cd7dc736-bad9-42e8-9fcd-75f8e1609e78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290866636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.3290866636
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.3578921913
Short name T73
Test name
Test status
Simulation time 3552777908 ps
CPU time 10.29 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:24 PM PDT 24
Peak memory 201980 kb
Host smart-b0cb60a6-25b5-44fa-95d2-fedf7f890902
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578921913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.3578921913
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2970295224
Short name T415
Test name
Test status
Simulation time 2626319439 ps
CPU time 2.43 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 202032 kb
Host smart-f69b544b-69a7-44c1-b693-ad453092d74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970295224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.2970295224
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2960125334
Short name T457
Test name
Test status
Simulation time 2459347109 ps
CPU time 5.62 seconds
Started Jun 07 08:30:05 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 202000 kb
Host smart-ac3e1813-a379-4e61-99bb-57c42689ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960125334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2960125334
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2683094351
Short name T208
Test name
Test status
Simulation time 2239302212 ps
CPU time 1.75 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:20 PM PDT 24
Peak memory 201976 kb
Host smart-fbf16401-b0df-4666-9b3f-7b9dd4e37b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683094351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.2683094351
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.3912811911
Short name T463
Test name
Test status
Simulation time 2509803741 ps
CPU time 7.25 seconds
Started Jun 07 08:30:05 PM PDT 24
Finished Jun 07 08:30:24 PM PDT 24
Peak memory 202012 kb
Host smart-e3c61c6c-386d-4768-a816-bf4f89b69da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912811911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3912811911
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.3019579913
Short name T111
Test name
Test status
Simulation time 2116174215 ps
CPU time 3.18 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:30:17 PM PDT 24
Peak memory 201896 kb
Host smart-da4ffe84-7845-4c77-9a4a-013403c7d012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019579913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.3019579913
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.2023856587
Short name T785
Test name
Test status
Simulation time 20346421020 ps
CPU time 23.55 seconds
Started Jun 07 08:30:04 PM PDT 24
Finished Jun 07 08:30:39 PM PDT 24
Peak memory 202028 kb
Host smart-3d10b9de-edb8-4b69-8747-cf03c0005106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023856587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.2023856587
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2379313129
Short name T556
Test name
Test status
Simulation time 6238619871 ps
CPU time 2.48 seconds
Started Jun 07 08:30:01 PM PDT 24
Finished Jun 07 08:30:15 PM PDT 24
Peak memory 202008 kb
Host smart-384441c5-2bde-44b8-b75b-6d6709c7f494
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379313129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.2379313129
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.3011702053
Short name T269
Test name
Test status
Simulation time 2023535731 ps
CPU time 3.3 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:17 PM PDT 24
Peak memory 202004 kb
Host smart-fc379144-f7da-4bfd-8656-c4ac5d2421a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011702053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.3011702053
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.571041097
Short name T47
Test name
Test status
Simulation time 3052079400 ps
CPU time 8.6 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:27 PM PDT 24
Peak memory 202048 kb
Host smart-53dc528a-21e0-4dd5-875a-2a3d6fbeab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571041097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.571041097
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.4156648703
Short name T372
Test name
Test status
Simulation time 101076231550 ps
CPU time 150.45 seconds
Started Jun 07 08:30:06 PM PDT 24
Finished Jun 07 08:32:48 PM PDT 24
Peak memory 202240 kb
Host smart-64aac8aa-7d72-4cfe-9018-e44494f0ac96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156648703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.4156648703
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3605249157
Short name T575
Test name
Test status
Simulation time 135625098847 ps
CPU time 87.28 seconds
Started Jun 07 08:30:05 PM PDT 24
Finished Jun 07 08:31:44 PM PDT 24
Peak memory 202208 kb
Host smart-c6cf605a-0666-4c2f-a04f-b59064359b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605249157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.3605249157
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2043725422
Short name T288
Test name
Test status
Simulation time 3272600037 ps
CPU time 2.68 seconds
Started Jun 07 08:30:06 PM PDT 24
Finished Jun 07 08:30:19 PM PDT 24
Peak memory 202028 kb
Host smart-ae5867b3-0dd2-42b8-bdf0-f22c15aeda46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043725422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.2043725422
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.588826499
Short name T134
Test name
Test status
Simulation time 3069660066 ps
CPU time 6.34 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:20 PM PDT 24
Peak memory 202060 kb
Host smart-81d5901c-9b0b-468a-9105-37f44cf80185
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588826499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctr
l_edge_detect.588826499
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1645604790
Short name T429
Test name
Test status
Simulation time 2608028096 ps
CPU time 7.37 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 202012 kb
Host smart-e39539ac-d32a-4cfd-92e7-5a98e7a028fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645604790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.1645604790
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.983868662
Short name T191
Test name
Test status
Simulation time 2448461527 ps
CPU time 7.41 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 202012 kb
Host smart-a56ca052-faf3-4090-b35e-414df0edd584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983868662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.983868662
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3461019296
Short name T510
Test name
Test status
Simulation time 2057367230 ps
CPU time 3.28 seconds
Started Jun 07 08:30:05 PM PDT 24
Finished Jun 07 08:30:20 PM PDT 24
Peak memory 201868 kb
Host smart-512a560d-d744-4b93-aa62-724503483ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461019296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3461019296
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.439543677
Short name T576
Test name
Test status
Simulation time 2136474818 ps
CPU time 1.48 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:30:15 PM PDT 24
Peak memory 201908 kb
Host smart-50ddedbc-45c4-4a6f-a50b-577e779978a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439543677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.439543677
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.168160750
Short name T63
Test name
Test status
Simulation time 7097341392 ps
CPU time 10.47 seconds
Started Jun 07 08:30:03 PM PDT 24
Finished Jun 07 08:30:25 PM PDT 24
Peak memory 201896 kb
Host smart-8b0f87bd-2549-4f81-862a-c41bc002a561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168160750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_st
ress_all.168160750
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.4277299047
Short name T44
Test name
Test status
Simulation time 49297990205 ps
CPU time 17.89 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 210528 kb
Host smart-fbbc8b15-3292-4a69-873b-3bf744c70394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277299047 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.4277299047
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.1467596279
Short name T621
Test name
Test status
Simulation time 2013768854 ps
CPU time 5.98 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:26 PM PDT 24
Peak memory 202020 kb
Host smart-c6dc945e-db98-4755-96f6-0db92870f6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467596279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.1467596279
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.591756977
Short name T703
Test name
Test status
Simulation time 3378813718 ps
CPU time 9.59 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:29 PM PDT 24
Peak memory 202056 kb
Host smart-780615dc-9397-4a39-b2a5-e9d0d9657a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591756977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.591756977
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3186976196
Short name T213
Test name
Test status
Simulation time 152117583386 ps
CPU time 89.04 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:31:49 PM PDT 24
Peak memory 202260 kb
Host smart-fd674cb7-efbd-4c76-b4dd-75bd035bb52f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186976196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3186976196
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1603826225
Short name T570
Test name
Test status
Simulation time 4853235207 ps
CPU time 2.85 seconds
Started Jun 07 08:30:21 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 201964 kb
Host smart-03c0acb0-1e72-4cfb-a960-9c71b1b6f389
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603826225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.1603826225
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.4126708487
Short name T135
Test name
Test status
Simulation time 2635766859 ps
CPU time 2.26 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 202000 kb
Host smart-3676a0d8-6903-4e59-acfa-db20b3173eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126708487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.4126708487
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1666389152
Short name T528
Test name
Test status
Simulation time 2473219140 ps
CPU time 7.16 seconds
Started Jun 07 08:30:02 PM PDT 24
Finished Jun 07 08:30:21 PM PDT 24
Peak memory 201968 kb
Host smart-2bbf2d9c-e7dd-4b44-b4b2-38cd26c72b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666389152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1666389152
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.1326501226
Short name T572
Test name
Test status
Simulation time 2188170706 ps
CPU time 4.5 seconds
Started Jun 07 08:30:05 PM PDT 24
Finished Jun 07 08:30:21 PM PDT 24
Peak memory 202000 kb
Host smart-938e2af0-5f83-444b-9668-ab60775b848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326501226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1326501226
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2070454449
Short name T452
Test name
Test status
Simulation time 2530890264 ps
CPU time 2.4 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:21 PM PDT 24
Peak memory 201964 kb
Host smart-5ac818c6-9cba-4ec9-8fe4-e6f29352cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070454449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.2070454449
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.3260278953
Short name T177
Test name
Test status
Simulation time 2112369596 ps
CPU time 5.51 seconds
Started Jun 07 08:30:05 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 201872 kb
Host smart-14863501-b90a-4dbb-95e3-c2b6c92adec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260278953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3260278953
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.3376415985
Short name T387
Test name
Test status
Simulation time 8776390123 ps
CPU time 25.06 seconds
Started Jun 07 08:30:10 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 201944 kb
Host smart-ea80484e-fe40-46c5-b613-84625235c2f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376415985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.3376415985
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2831892201
Short name T700
Test name
Test status
Simulation time 4718500693 ps
CPU time 4.03 seconds
Started Jun 07 08:30:12 PM PDT 24
Finished Jun 07 08:30:27 PM PDT 24
Peak memory 202088 kb
Host smart-a2fac087-8660-4968-bf4d-709df2d307e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831892201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.2831892201
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1845813987
Short name T434
Test name
Test status
Simulation time 2012274361 ps
CPU time 5.44 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:26 PM PDT 24
Peak memory 202032 kb
Host smart-540689bb-5eb9-4cde-94b9-6dd5e3141b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845813987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.1845813987
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2717761053
Short name T52
Test name
Test status
Simulation time 3597476569 ps
CPU time 3.06 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:23 PM PDT 24
Peak memory 202064 kb
Host smart-36e12fe4-5584-4cf8-a006-777aea57888f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717761053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.2
717761053
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.2371526095
Short name T261
Test name
Test status
Simulation time 105610745775 ps
CPU time 302.06 seconds
Started Jun 07 08:30:10 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 202252 kb
Host smart-17e44ccc-3193-462b-9c20-6cc60d25ba02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371526095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.2371526095
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.980685218
Short name T665
Test name
Test status
Simulation time 26578295895 ps
CPU time 67.57 seconds
Started Jun 07 08:30:10 PM PDT 24
Finished Jun 07 08:31:29 PM PDT 24
Peak memory 202288 kb
Host smart-34d468e2-ddb2-48a7-be88-fc260a4003e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980685218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wi
th_pre_cond.980685218
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.859541286
Short name T184
Test name
Test status
Simulation time 4008303702 ps
CPU time 7.2 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 202016 kb
Host smart-234ae145-4ce4-4736-aef4-6a8b631b4780
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859541286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctr
l_edge_detect.859541286
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.932696256
Short name T471
Test name
Test status
Simulation time 2628409289 ps
CPU time 2.39 seconds
Started Jun 07 08:30:14 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 201936 kb
Host smart-776ad447-ce22-415b-ad6f-ce92463eb492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932696256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.932696256
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.4113534957
Short name T439
Test name
Test status
Simulation time 2490616567 ps
CPU time 2.87 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:30:26 PM PDT 24
Peak memory 202072 kb
Host smart-0956572c-ecf1-4d70-9cbd-d790e3336e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113534957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.4113534957
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2074891867
Short name T475
Test name
Test status
Simulation time 2118904718 ps
CPU time 1.88 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:21 PM PDT 24
Peak memory 201900 kb
Host smart-3bbd3c20-fcba-4dd2-8f39-d59bad788762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074891867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.2074891867
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.2123812710
Short name T544
Test name
Test status
Simulation time 2514328073 ps
CPU time 6.47 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:26 PM PDT 24
Peak memory 201988 kb
Host smart-81925812-bfea-459e-a80e-52bc64847db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123812710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.2123812710
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.3715477338
Short name T541
Test name
Test status
Simulation time 2115586324 ps
CPU time 6.01 seconds
Started Jun 07 08:30:10 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 201896 kb
Host smart-153c3d31-0ce9-4021-8edf-a7e06c848761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715477338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3715477338
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1017289865
Short name T128
Test name
Test status
Simulation time 13265957051 ps
CPU time 31.54 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:30:54 PM PDT 24
Peak memory 201984 kb
Host smart-c39703bf-2ed6-4e25-8a3c-b3fa6f475d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017289865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1017289865
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.4138642329
Short name T368
Test name
Test status
Simulation time 13632230389 ps
CPU time 37.9 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:31:03 PM PDT 24
Peak memory 210552 kb
Host smart-266fb76e-d95a-4254-954b-deaece362fa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138642329 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.4138642329
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2567100582
Short name T8
Test name
Test status
Simulation time 6415998244 ps
CPU time 2.16 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 202068 kb
Host smart-bd7922da-027e-47af-915c-fde7437699b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567100582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.2567100582
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1030695652
Short name T583
Test name
Test status
Simulation time 2020071047 ps
CPU time 3.16 seconds
Started Jun 07 08:29:28 PM PDT 24
Finished Jun 07 08:29:45 PM PDT 24
Peak memory 201964 kb
Host smart-4df78773-4cbd-41cc-a571-738b32ca7f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030695652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1030695652
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2044018659
Short name T193
Test name
Test status
Simulation time 3480130151 ps
CPU time 5.34 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:29:47 PM PDT 24
Peak memory 201984 kb
Host smart-79385e57-9334-4d41-8f88-5b571c99521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044018659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.2044018659
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.2840185743
Short name T98
Test name
Test status
Simulation time 87529489816 ps
CPU time 218.42 seconds
Started Jun 07 08:29:24 PM PDT 24
Finished Jun 07 08:33:17 PM PDT 24
Peak memory 202280 kb
Host smart-1c3e4d09-a724-4c8a-a497-87134e4ca5fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840185743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.2840185743
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1421757708
Short name T421
Test name
Test status
Simulation time 2434911145 ps
CPU time 2.13 seconds
Started Jun 07 08:29:43 PM PDT 24
Finished Jun 07 08:29:54 PM PDT 24
Peak memory 201952 kb
Host smart-1403f307-b391-4272-89e4-c766a2dae222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421757708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.1421757708
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3923634153
Short name T712
Test name
Test status
Simulation time 2540134371 ps
CPU time 6.92 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:29:51 PM PDT 24
Peak memory 202008 kb
Host smart-9e1d79ea-08c6-42af-9773-7a7f86b7b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923634153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3923634153
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2064887635
Short name T248
Test name
Test status
Simulation time 75426204693 ps
CPU time 32.47 seconds
Started Jun 07 08:29:25 PM PDT 24
Finished Jun 07 08:30:11 PM PDT 24
Peak memory 202328 kb
Host smart-2d574dfb-90d7-467f-bf6c-c14a58702f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064887635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.2064887635
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.4282355675
Short name T408
Test name
Test status
Simulation time 2987228568 ps
CPU time 1.99 seconds
Started Jun 07 08:29:31 PM PDT 24
Finished Jun 07 08:29:45 PM PDT 24
Peak memory 201984 kb
Host smart-dc2e5321-c0a4-4268-9ac9-06cc804e738a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282355675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.4282355675
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3020816461
Short name T654
Test name
Test status
Simulation time 3100731761 ps
CPU time 3.84 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:29:46 PM PDT 24
Peak memory 201280 kb
Host smart-226c6365-aeae-4cf5-85bd-7b6d28a6180f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020816461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.3020816461
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2594532030
Short name T561
Test name
Test status
Simulation time 2611717370 ps
CPU time 7.58 seconds
Started Jun 07 08:29:22 PM PDT 24
Finished Jun 07 08:29:44 PM PDT 24
Peak memory 201956 kb
Host smart-f819567d-b80e-4e04-a884-8786a6b28d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594532030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.2594532030
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.2561584237
Short name T481
Test name
Test status
Simulation time 2463189332 ps
CPU time 4.31 seconds
Started Jun 07 08:29:25 PM PDT 24
Finished Jun 07 08:29:43 PM PDT 24
Peak memory 202000 kb
Host smart-875844ca-1b7d-4425-8a99-568a21efd3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561584237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2561584237
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.78318787
Short name T490
Test name
Test status
Simulation time 2033824059 ps
CPU time 1.99 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:29:44 PM PDT 24
Peak memory 201912 kb
Host smart-1ce83b80-6a32-4969-a22a-53bceb6cc6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78318787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.78318787
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.2802001929
Short name T632
Test name
Test status
Simulation time 2512245664 ps
CPU time 6.6 seconds
Started Jun 07 08:29:23 PM PDT 24
Finished Jun 07 08:29:43 PM PDT 24
Peak memory 202060 kb
Host smart-fff2957a-1ea2-4852-9ad3-93d9b9cfd52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802001929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2802001929
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.667658352
Short name T274
Test name
Test status
Simulation time 42625442022 ps
CPU time 53.76 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 221864 kb
Host smart-2fd73929-46e9-4a11-8aea-7eb3d92a78be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667658352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.667658352
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.316185482
Short name T197
Test name
Test status
Simulation time 2122087311 ps
CPU time 2.84 seconds
Started Jun 07 08:29:25 PM PDT 24
Finished Jun 07 08:29:41 PM PDT 24
Peak memory 201880 kb
Host smart-ecc0bc57-8ca7-4382-82db-ce588cce1aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316185482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.316185482
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.2703255678
Short name T298
Test name
Test status
Simulation time 9211583418 ps
CPU time 9.11 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:29:51 PM PDT 24
Peak memory 202012 kb
Host smart-e5afa99f-62a4-48d3-87be-b9200b063277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703255678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.2703255678
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1580807056
Short name T513
Test name
Test status
Simulation time 8930526055 ps
CPU time 5.45 seconds
Started Jun 07 08:29:37 PM PDT 24
Finished Jun 07 08:29:53 PM PDT 24
Peak memory 202036 kb
Host smart-e21cadaa-0c6f-4600-9dd8-05cb5c75f7a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580807056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.1580807056
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3480663599
Short name T507
Test name
Test status
Simulation time 2014613904 ps
CPU time 3.32 seconds
Started Jun 07 08:30:10 PM PDT 24
Finished Jun 07 08:30:25 PM PDT 24
Peak memory 202020 kb
Host smart-551a8e90-24e0-4a66-ad2c-05937edafbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480663599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3480663599
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3320406379
Short name T590
Test name
Test status
Simulation time 3409069804 ps
CPU time 9.24 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:30 PM PDT 24
Peak memory 202000 kb
Host smart-31e40eeb-2226-474a-826b-5c9d4ece9879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320406379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3
320406379
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.3713082815
Short name T253
Test name
Test status
Simulation time 111743536282 ps
CPU time 307.6 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:35:34 PM PDT 24
Peak memory 202312 kb
Host smart-ab151e93-3d9d-41e7-a6c0-2afc85846c86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713082815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.3713082815
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.4169664491
Short name T771
Test name
Test status
Simulation time 26830615940 ps
CPU time 68.46 seconds
Started Jun 07 08:30:21 PM PDT 24
Finished Jun 07 08:31:38 PM PDT 24
Peak memory 202364 kb
Host smart-3ecd37ef-8919-4506-829a-dd2707af2dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169664491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.4169664491
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.4169779990
Short name T629
Test name
Test status
Simulation time 5228665121 ps
CPU time 13.72 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 201984 kb
Host smart-393afff8-b17c-443f-8b5c-ef288a658691
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169779990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.4169779990
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3461140391
Short name T150
Test name
Test status
Simulation time 2890106307 ps
CPU time 7.81 seconds
Started Jun 07 08:30:13 PM PDT 24
Finished Jun 07 08:30:32 PM PDT 24
Peak memory 201980 kb
Host smart-f2f67480-46b0-42e8-bcf1-f55e3e2e3f57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461140391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.3461140391
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2150190887
Short name T413
Test name
Test status
Simulation time 2611043924 ps
CPU time 6.92 seconds
Started Jun 07 08:30:12 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 202024 kb
Host smart-622180a7-9d46-4c4f-b71a-fcc70afa1de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150190887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.2150190887
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3671148670
Short name T389
Test name
Test status
Simulation time 2484200434 ps
CPU time 2.17 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:21 PM PDT 24
Peak memory 201976 kb
Host smart-cddaf7f8-5276-412a-94c3-f296ff57c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671148670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3671148670
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1026025020
Short name T442
Test name
Test status
Simulation time 2161880058 ps
CPU time 6.92 seconds
Started Jun 07 08:30:12 PM PDT 24
Finished Jun 07 08:30:30 PM PDT 24
Peak memory 202080 kb
Host smart-752abe24-54c2-4997-a944-75c608532023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026025020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1026025020
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.582997237
Short name T465
Test name
Test status
Simulation time 2513369569 ps
CPU time 4.07 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 201996 kb
Host smart-ba6d4dc3-2d88-496e-a026-64d4e4d18b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582997237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.582997237
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.3736660304
Short name T484
Test name
Test status
Simulation time 2132895585 ps
CPU time 1.99 seconds
Started Jun 07 08:30:07 PM PDT 24
Finished Jun 07 08:30:20 PM PDT 24
Peak memory 201968 kb
Host smart-a33882e5-de3b-4da1-b2f9-2696c5b7f47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736660304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.3736660304
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.4189677974
Short name T657
Test name
Test status
Simulation time 6549901774 ps
CPU time 9.01 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:29 PM PDT 24
Peak memory 201972 kb
Host smart-155b5dbb-4070-4fbd-8ad9-1e1d023910e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189677974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.4189677974
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2680771417
Short name T543
Test name
Test status
Simulation time 5728245135 ps
CPU time 2.13 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:23 PM PDT 24
Peak memory 201968 kb
Host smart-07d87f11-75a3-4f72-afd8-734e6638b794
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680771417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.2680771417
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.2527529975
Short name T697
Test name
Test status
Simulation time 2042708423 ps
CPU time 1.8 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:22 PM PDT 24
Peak memory 202040 kb
Host smart-ed6aa057-a6f6-41ba-8ba8-a8337b52c8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527529975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.2527529975
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.994284749
Short name T391
Test name
Test status
Simulation time 3645714820 ps
CPU time 2.22 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:30:27 PM PDT 24
Peak memory 202060 kb
Host smart-3d300d1a-bd53-4113-bd80-6561c8324938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994284749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.994284749
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.2821180994
Short name T769
Test name
Test status
Simulation time 49238549388 ps
CPU time 58.63 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:31:21 PM PDT 24
Peak memory 202220 kb
Host smart-a1db46aa-cc21-403b-9da5-8e4656f34690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821180994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.2821180994
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1842528109
Short name T664
Test name
Test status
Simulation time 3435721215 ps
CPU time 4.85 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:25 PM PDT 24
Peak memory 202016 kb
Host smart-439a9561-3440-4095-8809-3c8e6f8febe2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842528109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.1842528109
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.734480533
Short name T153
Test name
Test status
Simulation time 3322309978 ps
CPU time 1.87 seconds
Started Jun 07 08:30:32 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 202056 kb
Host smart-50e21065-495b-4be8-922e-d7b719f5fcd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734480533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctr
l_edge_detect.734480533
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.204042768
Short name T728
Test name
Test status
Simulation time 2627600255 ps
CPU time 2.4 seconds
Started Jun 07 08:30:22 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 202016 kb
Host smart-0e13fa99-b995-48b0-8d0b-30a9ee620734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204042768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.204042768
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2849477627
Short name T633
Test name
Test status
Simulation time 2482992908 ps
CPU time 2.6 seconds
Started Jun 07 08:30:21 PM PDT 24
Finished Jun 07 08:30:32 PM PDT 24
Peak memory 202016 kb
Host smart-0fc7a8ff-9534-4f9b-b2c5-f535a7aa6e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849477627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2849477627
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.674896518
Short name T567
Test name
Test status
Simulation time 2251934052 ps
CPU time 6.37 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 201992 kb
Host smart-0962398c-18bb-493f-add7-c1f20f0fc236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674896518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.674896518
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1189420804
Short name T694
Test name
Test status
Simulation time 2512934064 ps
CPU time 7.15 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 202028 kb
Host smart-86269678-41a1-4a9b-9fc8-04f6e7a64274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189420804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.1189420804
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1679371810
Short name T446
Test name
Test status
Simulation time 2113758904 ps
CPU time 6.13 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:30:32 PM PDT 24
Peak memory 201840 kb
Host smart-d3b7f44d-35b1-4cd3-a3ba-e0048da606a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679371810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1679371810
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.3423835414
Short name T674
Test name
Test status
Simulation time 13820142657 ps
CPU time 17.12 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 201980 kb
Host smart-53b596e1-1354-4733-b250-a318695a98aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423835414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.3423835414
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2135114191
Short name T93
Test name
Test status
Simulation time 84951489910 ps
CPU time 118.59 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 210628 kb
Host smart-b92bfe32-fc55-486e-9664-3ae313d614ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135114191 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2135114191
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.872214831
Short name T123
Test name
Test status
Simulation time 5636045038 ps
CPU time 2.16 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 202048 kb
Host smart-cf897824-fac6-4e32-91e3-8dc1b1441ff4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872214831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ultra_low_pwr.872214831
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.3452603221
Short name T552
Test name
Test status
Simulation time 2011890883 ps
CPU time 6.17 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:46 PM PDT 24
Peak memory 202008 kb
Host smart-9a29b004-fece-4c9a-a15f-6f06de2ba37d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452603221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.3452603221
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1905677209
Short name T97
Test name
Test status
Simulation time 3204888590 ps
CPU time 8.65 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:54 PM PDT 24
Peak memory 202000 kb
Host smart-ffa6872d-59c9-4ea9-a384-55c5a0ee5456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905677209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1
905677209
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.505116659
Short name T763
Test name
Test status
Simulation time 135427176977 ps
CPU time 383.33 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:36:45 PM PDT 24
Peak memory 202360 kb
Host smart-c02c1796-3c38-4411-a7fd-3d1a79b99631
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505116659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_combo_detect.505116659
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1368808640
Short name T425
Test name
Test status
Simulation time 1293450990281 ps
CPU time 608.33 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:40:56 PM PDT 24
Peak memory 201992 kb
Host smart-346ddbee-d38c-41a7-90d9-4152cbaccbd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368808640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.1368808640
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.684600764
Short name T182
Test name
Test status
Simulation time 645074556215 ps
CPU time 24.85 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:31:04 PM PDT 24
Peak memory 201996 kb
Host smart-b6a5520c-7f0b-4a11-a1e3-2d5f35ce6490
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684600764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctr
l_edge_detect.684600764
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.319490434
Short name T169
Test name
Test status
Simulation time 2633246427 ps
CPU time 2.29 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 201948 kb
Host smart-2b79e8dc-59c1-4865-94bd-53525734624c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319490434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.319490434
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.281511628
Short name T754
Test name
Test status
Simulation time 2479527825 ps
CPU time 4.64 seconds
Started Jun 07 08:30:25 PM PDT 24
Finished Jun 07 08:30:37 PM PDT 24
Peak memory 201944 kb
Host smart-984b955c-27e6-4347-9cf2-18a8aff64598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281511628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.281511628
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3094163509
Short name T450
Test name
Test status
Simulation time 2226827802 ps
CPU time 2.02 seconds
Started Jun 07 08:30:25 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 202024 kb
Host smart-5f7f2167-4076-44fe-909c-d2a6f122b653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094163509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3094163509
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2671386398
Short name T682
Test name
Test status
Simulation time 2526867761 ps
CPU time 2.99 seconds
Started Jun 07 08:30:30 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 202048 kb
Host smart-2a1a69a1-aef8-4f27-9eb4-e7a81f7d3550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671386398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2671386398
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.1043413051
Short name T613
Test name
Test status
Simulation time 2122898943 ps
CPU time 3.32 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:24 PM PDT 24
Peak memory 201848 kb
Host smart-4160194b-ae90-4706-8366-a1c792ac5d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043413051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1043413051
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.507633865
Short name T605
Test name
Test status
Simulation time 11689568531 ps
CPU time 31.98 seconds
Started Jun 07 08:30:24 PM PDT 24
Finished Jun 07 08:31:03 PM PDT 24
Peak memory 202052 kb
Host smart-6de3a3b4-f251-4b29-9a33-054664ac03df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507633865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.507633865
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.4257467180
Short name T706
Test name
Test status
Simulation time 118104784749 ps
CPU time 63.9 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:31:46 PM PDT 24
Peak memory 218712 kb
Host smart-9bb7c611-0d0c-499b-a213-75485f087e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257467180 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.4257467180
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3690310749
Short name T624
Test name
Test status
Simulation time 6694584725 ps
CPU time 3.72 seconds
Started Jun 07 08:30:12 PM PDT 24
Finished Jun 07 08:30:27 PM PDT 24
Peak memory 201944 kb
Host smart-8849d38d-8955-47a8-86eb-6dbf4fd9630d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690310749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3690310749
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.2534530273
Short name T670
Test name
Test status
Simulation time 2038660607 ps
CPU time 2.01 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 202008 kb
Host smart-da9b4017-81c4-4f2e-9784-ab39f4f93e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534530273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.2534530273
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3740340044
Short name T290
Test name
Test status
Simulation time 3840610552 ps
CPU time 1.6 seconds
Started Jun 07 08:30:12 PM PDT 24
Finished Jun 07 08:30:25 PM PDT 24
Peak memory 202104 kb
Host smart-75f4ffe4-8ad4-411c-ae30-99dcdf0504de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740340044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3
740340044
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.1955590237
Short name T256
Test name
Test status
Simulation time 65723969912 ps
CPU time 44.07 seconds
Started Jun 07 08:30:23 PM PDT 24
Finished Jun 07 08:31:15 PM PDT 24
Peak memory 202272 kb
Host smart-df4529cd-5d49-4add-b576-14015b99cc74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955590237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.1955590237
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1962062888
Short name T685
Test name
Test status
Simulation time 3288046571 ps
CPU time 2.76 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:43 PM PDT 24
Peak memory 202004 kb
Host smart-846e0c5d-3845-430f-bc7d-fbd621448d0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962062888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.1962062888
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3336418038
Short name T189
Test name
Test status
Simulation time 2365253917 ps
CPU time 6.42 seconds
Started Jun 07 08:30:12 PM PDT 24
Finished Jun 07 08:30:30 PM PDT 24
Peak memory 202000 kb
Host smart-030bd263-8185-4816-889d-5f6b98876360
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336418038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.3336418038
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3523938699
Short name T562
Test name
Test status
Simulation time 2621961129 ps
CPU time 3.94 seconds
Started Jun 07 08:30:18 PM PDT 24
Finished Jun 07 08:30:32 PM PDT 24
Peak memory 202024 kb
Host smart-522224ee-e8e9-410f-bb95-72a4f73888f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523938699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.3523938699
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2441642117
Short name T486
Test name
Test status
Simulation time 2477127812 ps
CPU time 2.72 seconds
Started Jun 07 08:30:32 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 201976 kb
Host smart-23e6884a-bc0f-415d-82ab-d3fb20666051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441642117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2441642117
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.688672317
Short name T736
Test name
Test status
Simulation time 2276475413 ps
CPU time 1.94 seconds
Started Jun 07 08:30:32 PM PDT 24
Finished Jun 07 08:30:37 PM PDT 24
Peak memory 201988 kb
Host smart-bd780ea2-e796-4ab1-8020-518347b96f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688672317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.688672317
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.640442415
Short name T296
Test name
Test status
Simulation time 2508577587 ps
CPU time 7.02 seconds
Started Jun 07 08:30:12 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 201964 kb
Host smart-da659d65-ac40-496a-a971-86d913351f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640442415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.640442415
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.3884592135
Short name T271
Test name
Test status
Simulation time 2111241082 ps
CPU time 5.66 seconds
Started Jun 07 08:30:35 PM PDT 24
Finished Jun 07 08:30:43 PM PDT 24
Peak memory 201876 kb
Host smart-f8a54c96-1835-4d45-b533-0267e1cc2de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884592135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3884592135
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.1861581613
Short name T738
Test name
Test status
Simulation time 15518540716 ps
CPU time 35.46 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 202108 kb
Host smart-8d9d49ec-d12c-4020-994f-8f9bf95ccad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861581613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.1861581613
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1272825877
Short name T293
Test name
Test status
Simulation time 13409291661 ps
CPU time 35.31 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:31:21 PM PDT 24
Peak memory 202472 kb
Host smart-93ba09a7-3333-43d9-956e-7b42a436ec03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272825877 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.1272825877
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3907104427
Short name T761
Test name
Test status
Simulation time 6294198848 ps
CPU time 7.58 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:54 PM PDT 24
Peak memory 202044 kb
Host smart-33e90985-9c6d-45e1-9886-edb488432529
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907104427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.3907104427
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.3874714073
Short name T689
Test name
Test status
Simulation time 2017563469 ps
CPU time 5.16 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 202020 kb
Host smart-31aeadca-e228-43e7-bc47-ff192edf5980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874714073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.3874714073
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1513267849
Short name T162
Test name
Test status
Simulation time 3233533972 ps
CPU time 3.8 seconds
Started Jun 07 08:30:23 PM PDT 24
Finished Jun 07 08:30:34 PM PDT 24
Peak memory 202124 kb
Host smart-d8064001-1897-4601-a2af-128a8dd46e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513267849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.1
513267849
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2276968548
Short name T332
Test name
Test status
Simulation time 125139378213 ps
CPU time 34.9 seconds
Started Jun 07 08:30:22 PM PDT 24
Finished Jun 07 08:31:05 PM PDT 24
Peak memory 202188 kb
Host smart-ee2bb8a7-c6af-4dcc-9105-db5030c94ee6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276968548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2276968548
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1177751916
Short name T797
Test name
Test status
Simulation time 23581110691 ps
CPU time 64.3 seconds
Started Jun 07 08:30:19 PM PDT 24
Finished Jun 07 08:31:33 PM PDT 24
Peak memory 202320 kb
Host smart-891d5fb6-4649-495e-89c2-1a9a81abfc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177751916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.1177751916
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1046656852
Short name T786
Test name
Test status
Simulation time 3116094792 ps
CPU time 2.68 seconds
Started Jun 07 08:30:28 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 201976 kb
Host smart-9a3fd066-7f12-4370-927b-3686a945797c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046656852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.1046656852
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1572183172
Short name T776
Test name
Test status
Simulation time 4070069787 ps
CPU time 2.7 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:30:39 PM PDT 24
Peak memory 202004 kb
Host smart-8cc7efc9-9ede-4da4-be66-64ea0be74b61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572183172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.1572183172
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.4046397159
Short name T637
Test name
Test status
Simulation time 2618628045 ps
CPU time 4.01 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:30:27 PM PDT 24
Peak memory 202032 kb
Host smart-be7ee322-49ab-4256-b476-6975e7823dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046397159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.4046397159
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.1279947265
Short name T557
Test name
Test status
Simulation time 2485456850 ps
CPU time 7.07 seconds
Started Jun 07 08:30:29 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 201964 kb
Host smart-bd674b12-fa38-4022-9090-321c44d181cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279947265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.1279947265
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2140992767
Short name T101
Test name
Test status
Simulation time 2199692495 ps
CPU time 6.23 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:52 PM PDT 24
Peak memory 202016 kb
Host smart-a400371d-ef39-49ba-a509-041b6a3ca2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140992767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.2140992767
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2767636047
Short name T580
Test name
Test status
Simulation time 2512327695 ps
CPU time 3.94 seconds
Started Jun 07 08:30:33 PM PDT 24
Finished Jun 07 08:30:39 PM PDT 24
Peak memory 202032 kb
Host smart-430f7361-8d39-48fb-9754-4fd7ad74d83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767636047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2767636047
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.498172547
Short name T100
Test name
Test status
Simulation time 2137146872 ps
CPU time 1.58 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 201888 kb
Host smart-7dab0e33-ce1d-489d-9fd0-a799971877ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498172547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.498172547
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.8578403
Short name T724
Test name
Test status
Simulation time 10746307443 ps
CPU time 4.6 seconds
Started Jun 07 08:30:08 PM PDT 24
Finished Jun 07 08:30:24 PM PDT 24
Peak memory 202024 kb
Host smart-aef21df1-aa31-410d-87ff-8e4609d00658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8578403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stre
ss_all.8578403
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2482300500
Short name T132
Test name
Test status
Simulation time 8047916605 ps
CPU time 7.1 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:30:34 PM PDT 24
Peak memory 202032 kb
Host smart-bc38b623-3e96-4286-8eec-6c44924f2740
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482300500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.2482300500
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.753086118
Short name T518
Test name
Test status
Simulation time 2019354755 ps
CPU time 3.16 seconds
Started Jun 07 08:30:17 PM PDT 24
Finished Jun 07 08:30:30 PM PDT 24
Peak memory 202008 kb
Host smart-8004a19e-308c-42a7-8c8f-31c20282c572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753086118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_tes
t.753086118
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.213774235
Short name T601
Test name
Test status
Simulation time 3456572821 ps
CPU time 5.22 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 202080 kb
Host smart-5725b04b-b8a9-4420-892d-f139a62df172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213774235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.213774235
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2456886358
Short name T331
Test name
Test status
Simulation time 130811892438 ps
CPU time 93.15 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:31:56 PM PDT 24
Peak memory 202304 kb
Host smart-a7885055-8431-49d4-9305-c6d48afe3d0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456886358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.2456886358
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.120501871
Short name T760
Test name
Test status
Simulation time 31186120296 ps
CPU time 87.82 seconds
Started Jun 07 08:30:18 PM PDT 24
Finished Jun 07 08:31:56 PM PDT 24
Peak memory 202204 kb
Host smart-f66a1439-a3d4-4ba9-ae7d-59f6819908c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120501871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_wi
th_pre_cond.120501871
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2237303301
Short name T535
Test name
Test status
Simulation time 3799805362 ps
CPU time 3.05 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:30:29 PM PDT 24
Peak memory 202008 kb
Host smart-5cfc353e-97ce-4f6f-b223-e09b34f900d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237303301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.2237303301
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3943841216
Short name T789
Test name
Test status
Simulation time 3236688220 ps
CPU time 2.18 seconds
Started Jun 07 08:30:18 PM PDT 24
Finished Jun 07 08:30:30 PM PDT 24
Peak memory 202040 kb
Host smart-eac8253e-b2b7-4dca-946d-c43b8c7ee11d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943841216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.3943841216
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2052401129
Short name T683
Test name
Test status
Simulation time 2623770932 ps
CPU time 2.53 seconds
Started Jun 07 08:30:28 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 202048 kb
Host smart-43947a34-2c46-4067-a5ab-efa9d3146357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052401129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.2052401129
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1064414836
Short name T58
Test name
Test status
Simulation time 2458299610 ps
CPU time 6.14 seconds
Started Jun 07 08:30:09 PM PDT 24
Finished Jun 07 08:30:26 PM PDT 24
Peak memory 202000 kb
Host smart-5fd763a3-e49f-4c2f-a553-c604679b362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064414836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1064414836
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2024116195
Short name T396
Test name
Test status
Simulation time 2168754132 ps
CPU time 3.49 seconds
Started Jun 07 08:30:18 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 202004 kb
Host smart-10b45ae9-2769-4462-9b59-179887960b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024116195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2024116195
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1056396996
Short name T57
Test name
Test status
Simulation time 2536598695 ps
CPU time 2.53 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:41 PM PDT 24
Peak memory 202040 kb
Host smart-999e724e-70f3-45ce-867e-d6be25c85499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056396996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1056396996
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2380562509
Short name T476
Test name
Test status
Simulation time 2139956191 ps
CPU time 1.88 seconds
Started Jun 07 08:30:21 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 201880 kb
Host smart-fcc600ea-732b-4033-9e32-9c08b70ef889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380562509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2380562509
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3096785736
Short name T50
Test name
Test status
Simulation time 57548970714 ps
CPU time 37.22 seconds
Started Jun 07 08:30:20 PM PDT 24
Finished Jun 07 08:31:06 PM PDT 24
Peak memory 210644 kb
Host smart-ea524555-35f8-469e-abc5-851d6c255cba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096785736 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.3096785736
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.591288404
Short name T117
Test name
Test status
Simulation time 5039244902 ps
CPU time 1.03 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:30:23 PM PDT 24
Peak memory 202128 kb
Host smart-ebad4778-516c-4ac5-ad93-105936947c88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591288404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ultra_low_pwr.591288404
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.2792528487
Short name T564
Test name
Test status
Simulation time 2010241750 ps
CPU time 5.91 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:30:29 PM PDT 24
Peak memory 201996 kb
Host smart-010d02db-5f39-4580-8640-db87e7a18a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792528487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.2792528487
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.323858267
Short name T244
Test name
Test status
Simulation time 168920529745 ps
CPU time 437.83 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:38:04 PM PDT 24
Peak memory 202040 kb
Host smart-a7127928-3056-4fdf-ad11-06200e4b17e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323858267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.323858267
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3397822392
Short name T96
Test name
Test status
Simulation time 46723684718 ps
CPU time 65.54 seconds
Started Jun 07 08:30:35 PM PDT 24
Finished Jun 07 08:31:44 PM PDT 24
Peak memory 202324 kb
Host smart-ed07ad4c-7da0-4804-8b0d-97d2d0e732f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397822392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.3397822392
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.305740791
Short name T748
Test name
Test status
Simulation time 3571597666 ps
CPU time 9.99 seconds
Started Jun 07 08:30:12 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 202008 kb
Host smart-6a7656d1-6af4-48fb-beb7-51b6b3fe35ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305740791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ec_pwr_on_rst.305740791
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.1370118533
Short name T199
Test name
Test status
Simulation time 4965387643 ps
CPU time 2.87 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:30:39 PM PDT 24
Peak memory 202084 kb
Host smart-e48cbe26-a456-4f75-b976-e3fe9c5cf1df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370118533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.1370118533
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2233658918
Short name T566
Test name
Test status
Simulation time 2610517720 ps
CPU time 7.38 seconds
Started Jun 07 08:30:28 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 202012 kb
Host smart-2bb468ed-909d-47c3-9381-977496158868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233658918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.2233658918
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.702614246
Short name T594
Test name
Test status
Simulation time 2525478603 ps
CPU time 1.18 seconds
Started Jun 07 08:30:26 PM PDT 24
Finished Jun 07 08:30:33 PM PDT 24
Peak memory 201944 kb
Host smart-afa05e9c-9192-46cf-b295-1139a6020e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702614246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.702614246
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2395542964
Short name T218
Test name
Test status
Simulation time 2197560941 ps
CPU time 2.11 seconds
Started Jun 07 08:30:30 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 201964 kb
Host smart-ee15b637-e1ad-4b41-b9b4-9131b3261d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395542964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2395542964
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3679412460
Short name T472
Test name
Test status
Simulation time 2528457626 ps
CPU time 2.6 seconds
Started Jun 07 08:30:10 PM PDT 24
Finished Jun 07 08:30:24 PM PDT 24
Peak memory 202020 kb
Host smart-ea4ac0cf-04f1-41d3-9999-4eb8d4945a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679412460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3679412460
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.3129739214
Short name T627
Test name
Test status
Simulation time 2108292106 ps
CPU time 6.57 seconds
Started Jun 07 08:30:10 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 201892 kb
Host smart-2c0061a5-2801-4425-b7b8-56c57a8a1b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129739214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3129739214
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.3950096833
Short name T554
Test name
Test status
Simulation time 8084937391 ps
CPU time 20.28 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:31:00 PM PDT 24
Peak memory 202052 kb
Host smart-c5ba42a6-298c-4c27-8e3f-67e4b6e7cf86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950096833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.3950096833
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1946230209
Short name T133
Test name
Test status
Simulation time 9274719230 ps
CPU time 8.39 seconds
Started Jun 07 08:30:30 PM PDT 24
Finished Jun 07 08:30:42 PM PDT 24
Peak memory 201996 kb
Host smart-962de24c-3471-4fab-99d5-f4f6850fec97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946230209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.1946230209
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.1769510285
Short name T523
Test name
Test status
Simulation time 2013699122 ps
CPU time 5.81 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 201996 kb
Host smart-f31ea165-1c5f-4225-b4bf-6dfde4fb274c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769510285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.1769510285
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1978022377
Short name T49
Test name
Test status
Simulation time 3741117864 ps
CPU time 10.65 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 202128 kb
Host smart-e7db0d8b-61ee-460b-b9cc-ba8c53c3e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978022377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.1
978022377
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1828550055
Short name T362
Test name
Test status
Simulation time 195368061245 ps
CPU time 221.34 seconds
Started Jun 07 08:30:18 PM PDT 24
Finished Jun 07 08:34:09 PM PDT 24
Peak memory 202240 kb
Host smart-49d0eb72-1843-48cc-aa2e-557c596e1f0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828550055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1828550055
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4023493198
Short name T719
Test name
Test status
Simulation time 2513735184 ps
CPU time 7.24 seconds
Started Jun 07 08:30:29 PM PDT 24
Finished Jun 07 08:30:41 PM PDT 24
Peak memory 202048 kb
Host smart-9844f9a4-8ef5-4ac9-ae31-adfdabe7c4e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023493198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.4023493198
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1479274410
Short name T226
Test name
Test status
Simulation time 2512488884 ps
CPU time 2.28 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:37 PM PDT 24
Peak memory 201984 kb
Host smart-835062f7-7a55-491c-b6f1-8ae07af96d18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479274410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.1479274410
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2354832697
Short name T707
Test name
Test status
Simulation time 2662089731 ps
CPU time 1.62 seconds
Started Jun 07 08:30:11 PM PDT 24
Finished Jun 07 08:30:24 PM PDT 24
Peak memory 202004 kb
Host smart-861a6227-83c1-416a-bfa4-079c8d98d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354832697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.2354832697
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.1102097516
Short name T161
Test name
Test status
Simulation time 2467599722 ps
CPU time 3.58 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:30:29 PM PDT 24
Peak memory 201972 kb
Host smart-e5ba0ab5-92f9-4924-8114-be10cd20244e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102097516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.1102097516
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.2383386670
Short name T545
Test name
Test status
Simulation time 2250659725 ps
CPU time 6.38 seconds
Started Jun 07 08:30:14 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 201996 kb
Host smart-a389c95e-e7be-4cd0-8fd3-d1ec9dac17c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383386670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.2383386670
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1031455230
Short name T680
Test name
Test status
Simulation time 2532591163 ps
CPU time 2.34 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:48 PM PDT 24
Peak memory 202028 kb
Host smart-3fb43f69-fc9b-45dd-9c75-bff8fd86e43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031455230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1031455230
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.429027153
Short name T431
Test name
Test status
Simulation time 2112297424 ps
CPU time 6.24 seconds
Started Jun 07 08:30:14 PM PDT 24
Finished Jun 07 08:30:31 PM PDT 24
Peak memory 201868 kb
Host smart-e18b3e89-8bc7-4f13-a034-9c0a68fe86db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429027153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.429027153
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1989307780
Short name T11
Test name
Test status
Simulation time 8112808290 ps
CPU time 5.07 seconds
Started Jun 07 08:30:29 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 201976 kb
Host smart-43a584f1-fc77-4311-b2d9-5af16cb9c23f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989307780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1989307780
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2360456772
Short name T616
Test name
Test status
Simulation time 49731457370 ps
CPU time 55.96 seconds
Started Jun 07 08:30:23 PM PDT 24
Finished Jun 07 08:31:26 PM PDT 24
Peak memory 218392 kb
Host smart-d88bbf7b-35a5-456a-838c-da5c2e0c631a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360456772 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.2360456772
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2569665528
Short name T759
Test name
Test status
Simulation time 2315177004462 ps
CPU time 177.35 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:33:43 PM PDT 24
Peak memory 202008 kb
Host smart-fe33f474-c2e2-448b-a37d-57af46c6d89a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569665528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.2569665528
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.2513743990
Short name T650
Test name
Test status
Simulation time 2011785133 ps
CPU time 6 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 202080 kb
Host smart-6b757654-23aa-475b-b000-64134ac805d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513743990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.2513743990
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3437759238
Short name T504
Test name
Test status
Simulation time 3520319191 ps
CPU time 9.9 seconds
Started Jun 07 08:30:25 PM PDT 24
Finished Jun 07 08:30:42 PM PDT 24
Peak memory 202092 kb
Host smart-435366d5-c282-4dab-9e77-7d2e697ebb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437759238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3
437759238
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2041137700
Short name T367
Test name
Test status
Simulation time 112197620481 ps
CPU time 274.79 seconds
Started Jun 07 08:30:21 PM PDT 24
Finished Jun 07 08:35:04 PM PDT 24
Peak memory 202244 kb
Host smart-a616a3e7-77ae-46e3-96ed-e3186f315e6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041137700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.2041137700
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2840597308
Short name T236
Test name
Test status
Simulation time 26332174528 ps
CPU time 73.34 seconds
Started Jun 07 08:30:29 PM PDT 24
Finished Jun 07 08:31:47 PM PDT 24
Peak memory 202236 kb
Host smart-9ddc6c4e-5e08-4ef2-b555-64f67e2699b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840597308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.2840597308
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.826865840
Short name T640
Test name
Test status
Simulation time 2940872448 ps
CPU time 8.12 seconds
Started Jun 07 08:30:30 PM PDT 24
Finished Jun 07 08:30:42 PM PDT 24
Peak memory 202056 kb
Host smart-5288f175-d4d1-4e18-b7dc-ecad5f99e066
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826865840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ec_pwr_on_rst.826865840
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.43416798
Short name T142
Test name
Test status
Simulation time 5131975153 ps
CPU time 12.01 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 202096 kb
Host smart-7b160653-1b79-418e-bc6d-6a6790333c28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43416798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl
_edge_detect.43416798
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3931561361
Short name T110
Test name
Test status
Simulation time 2613668002 ps
CPU time 6.58 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:30:32 PM PDT 24
Peak memory 202028 kb
Host smart-a3001eb3-b8ef-4b03-a2bd-759c44729722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931561361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.3931561361
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.4261644081
Short name T207
Test name
Test status
Simulation time 2486748137 ps
CPU time 2.19 seconds
Started Jun 07 08:30:14 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 201932 kb
Host smart-c39bb5a5-9e84-4f13-870e-132f739462ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261644081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.4261644081
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2318078342
Short name T686
Test name
Test status
Simulation time 2157329873 ps
CPU time 1.13 seconds
Started Jun 07 08:30:15 PM PDT 24
Finished Jun 07 08:30:27 PM PDT 24
Peak memory 202004 kb
Host smart-07492fc3-1bdb-4d93-a341-20d6b98362bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318078342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2318078342
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1065001576
Short name T385
Test name
Test status
Simulation time 2521444871 ps
CPU time 4.43 seconds
Started Jun 07 08:30:32 PM PDT 24
Finished Jun 07 08:30:39 PM PDT 24
Peak memory 202040 kb
Host smart-a8d0a13f-329d-4ed1-963f-f02cfd4a7dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065001576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1065001576
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.3236461421
Short name T546
Test name
Test status
Simulation time 2128417642 ps
CPU time 2.01 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 201860 kb
Host smart-0a4ed29d-bbf7-4164-b66d-7f17761d3fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236461421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3236461421
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3635306355
Short name T534
Test name
Test status
Simulation time 10410993449 ps
CPU time 18.29 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:57 PM PDT 24
Peak memory 201992 kb
Host smart-25fc7e72-526e-4e93-912f-88439872eba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635306355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3635306355
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.655801616
Short name T176
Test name
Test status
Simulation time 42896773693 ps
CPU time 14.74 seconds
Started Jun 07 08:30:24 PM PDT 24
Finished Jun 07 08:30:46 PM PDT 24
Peak memory 218764 kb
Host smart-50be0b36-6e00-45f2-9db1-7db351ab4175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655801616 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.655801616
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2927859304
Short name T767
Test name
Test status
Simulation time 7086922886 ps
CPU time 6.8 seconds
Started Jun 07 08:30:21 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 202052 kb
Host smart-9d589792-26a1-4ac6-b637-4e87856ea8ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927859304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.2927859304
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.1123601693
Short name T105
Test name
Test status
Simulation time 2015908012 ps
CPU time 3.42 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 202032 kb
Host smart-411c86d4-7527-431e-ab2c-796b4bcf1061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123601693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.1123601693
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1652003745
Short name T774
Test name
Test status
Simulation time 3110128836 ps
CPU time 4.74 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 202120 kb
Host smart-08e631ab-e7f2-4623-bc70-3f1e4f537c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652003745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
652003745
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3987751395
Short name T324
Test name
Test status
Simulation time 125970777996 ps
CPU time 170.73 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:33:38 PM PDT 24
Peak memory 202240 kb
Host smart-253cd5b7-b612-4f72-869c-38d76fedeeb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987751395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.3987751395
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1586071818
Short name T795
Test name
Test status
Simulation time 43397041922 ps
CPU time 57.84 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:31:46 PM PDT 24
Peak memory 202284 kb
Host smart-afa11ddd-0b77-4afc-98fb-d3351d106d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586071818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.1586071818
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.553166068
Short name T705
Test name
Test status
Simulation time 3773564461 ps
CPU time 5.47 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:44 PM PDT 24
Peak memory 201980 kb
Host smart-7c9c57cf-4532-45ff-b77c-a96e513d802c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553166068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_ec_pwr_on_rst.553166068
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.4212249110
Short name T628
Test name
Test status
Simulation time 3693075359 ps
CPU time 2.74 seconds
Started Jun 07 08:30:35 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 201984 kb
Host smart-68b2b953-5ed0-4a47-aa01-44453237d3c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212249110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.4212249110
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2115740627
Short name T537
Test name
Test status
Simulation time 2629982340 ps
CPU time 2.52 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 201988 kb
Host smart-7fb3485c-c946-4b4c-8c38-5192ae56a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115740627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2115740627
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2930144188
Short name T563
Test name
Test status
Simulation time 2463295817 ps
CPU time 2.29 seconds
Started Jun 07 08:30:25 PM PDT 24
Finished Jun 07 08:30:34 PM PDT 24
Peak memory 201944 kb
Host smart-cfc063a9-bc4d-46bf-8b5e-44c3bbfcb1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930144188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2930144188
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1708600584
Short name T163
Test name
Test status
Simulation time 2287039831 ps
CPU time 2.12 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 201956 kb
Host smart-67cd10ea-82b7-468e-a7d7-5b35abbbfd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708600584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1708600584
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.4018194786
Short name T692
Test name
Test status
Simulation time 2511318151 ps
CPU time 6.57 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:49 PM PDT 24
Peak memory 202012 kb
Host smart-5b4c9995-c36f-4b56-bee9-0a74e7df1c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018194786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.4018194786
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.378339906
Short name T679
Test name
Test status
Simulation time 2188726337 ps
CPU time 1.09 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:44 PM PDT 24
Peak memory 201996 kb
Host smart-78b48d8a-dfd5-4d1a-aaa2-c2ea64876c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378339906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.378339906
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3179127721
Short name T783
Test name
Test status
Simulation time 126233323256 ps
CPU time 77.83 seconds
Started Jun 07 08:30:33 PM PDT 24
Finished Jun 07 08:31:53 PM PDT 24
Peak memory 202248 kb
Host smart-7f3bb57c-e865-414a-9774-2dc83b4cb655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179127721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3179127721
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.648180088
Short name T382
Test name
Test status
Simulation time 25370838500 ps
CPU time 12.68 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 210660 kb
Host smart-3c989ff3-2226-4306-9b41-e3e85c47ece8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648180088 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.648180088
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1324413380
Short name T79
Test name
Test status
Simulation time 4298159127420 ps
CPU time 604.1 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:40:47 PM PDT 24
Peak memory 201988 kb
Host smart-45184c23-9a3a-4dc3-90af-845853539e51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324413380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.1324413380
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.4074194355
Short name T414
Test name
Test status
Simulation time 2010646281 ps
CPU time 5.64 seconds
Started Jun 07 08:29:35 PM PDT 24
Finished Jun 07 08:29:51 PM PDT 24
Peak memory 201980 kb
Host smart-5c0017da-d811-4598-bce0-c10178382b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074194355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.4074194355
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3547323291
Short name T696
Test name
Test status
Simulation time 3694016682 ps
CPU time 5.7 seconds
Started Jun 07 08:29:31 PM PDT 24
Finished Jun 07 08:29:49 PM PDT 24
Peak memory 202048 kb
Host smart-7eaf92b3-5093-4465-b298-65d24e5db929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547323291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3547323291
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.883678658
Short name T388
Test name
Test status
Simulation time 2222601583 ps
CPU time 2.15 seconds
Started Jun 07 08:29:35 PM PDT 24
Finished Jun 07 08:29:48 PM PDT 24
Peak memory 201988 kb
Host smart-f3a29160-f3a5-456d-b215-6cae240d51dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883678658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.883678658
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2808367142
Short name T31
Test name
Test status
Simulation time 2561445924 ps
CPU time 2.32 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:29:44 PM PDT 24
Peak memory 202000 kb
Host smart-3cd6f751-edf8-415c-bfd9-931f1826aadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808367142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2808367142
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3373282992
Short name T462
Test name
Test status
Simulation time 40845274185 ps
CPU time 31.62 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:30:13 PM PDT 24
Peak memory 201672 kb
Host smart-1c828781-d4fc-465b-af89-2dabf56c971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373282992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.3373282992
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.3091968708
Short name T770
Test name
Test status
Simulation time 3952298190 ps
CPU time 2.5 seconds
Started Jun 07 08:29:26 PM PDT 24
Finished Jun 07 08:29:42 PM PDT 24
Peak memory 202100 kb
Host smart-98c80868-a806-4aa9-a050-97c9ca46df81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091968708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.3091968708
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2507808034
Short name T64
Test name
Test status
Simulation time 2611092594 ps
CPU time 6.33 seconds
Started Jun 07 08:29:32 PM PDT 24
Finished Jun 07 08:29:50 PM PDT 24
Peak memory 202000 kb
Host smart-0c3b7cdc-14be-4f91-ab03-a970e097d674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507808034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2507808034
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1516662434
Short name T168
Test name
Test status
Simulation time 2445217730 ps
CPU time 3.84 seconds
Started Jun 07 08:29:34 PM PDT 24
Finished Jun 07 08:29:49 PM PDT 24
Peak memory 201992 kb
Host smart-17cf7d59-fe26-415a-8b16-561e8b1221ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516662434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1516662434
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.2636261572
Short name T160
Test name
Test status
Simulation time 2075604106 ps
CPU time 3.28 seconds
Started Jun 07 08:29:37 PM PDT 24
Finished Jun 07 08:29:51 PM PDT 24
Peak memory 201848 kb
Host smart-4ad70a92-9638-40ca-9c32-df8d1ccd233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636261572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2636261572
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2002770339
Short name T443
Test name
Test status
Simulation time 2529883681 ps
CPU time 2.45 seconds
Started Jun 07 08:29:27 PM PDT 24
Finished Jun 07 08:29:43 PM PDT 24
Peak memory 202004 kb
Host smart-eddcc00e-40f8-4ab3-9f2b-a36d69efdeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002770339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2002770339
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.149119152
Short name T286
Test name
Test status
Simulation time 42112896107 ps
CPU time 27.83 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:30:11 PM PDT 24
Peak memory 221884 kb
Host smart-77b78750-19db-4b6f-8fa3-abb0c1b23062
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149119152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.149119152
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.3571045150
Short name T136
Test name
Test status
Simulation time 2130354304 ps
CPU time 1.78 seconds
Started Jun 07 08:29:38 PM PDT 24
Finished Jun 07 08:29:50 PM PDT 24
Peak memory 201888 kb
Host smart-fa599733-a1f4-40eb-a93d-e9c5f6e2a7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571045150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.3571045150
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.3212507885
Short name T221
Test name
Test status
Simulation time 12485985297 ps
CPU time 6.54 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:29:48 PM PDT 24
Peak memory 202028 kb
Host smart-a78b8c27-2e5c-4291-a564-d19d042effd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212507885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.3212507885
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2363959429
Short name T780
Test name
Test status
Simulation time 175685079492 ps
CPU time 74.29 seconds
Started Jun 07 08:29:31 PM PDT 24
Finished Jun 07 08:30:57 PM PDT 24
Peak memory 210652 kb
Host smart-759a26cb-32c6-48f8-8754-5d9de86f6418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363959429 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2363959429
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1883372314
Short name T511
Test name
Test status
Simulation time 6968559584 ps
CPU time 2.62 seconds
Started Jun 07 08:29:37 PM PDT 24
Finished Jun 07 08:29:50 PM PDT 24
Peak memory 202104 kb
Host smart-c83263a4-3eec-4a2f-b48e-9fbb5de7f914
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883372314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.1883372314
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.1943799220
Short name T390
Test name
Test status
Simulation time 2022315382 ps
CPU time 3.23 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:37 PM PDT 24
Peak memory 202012 kb
Host smart-272bfbe2-df85-4224-85ee-6303f0674bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943799220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.1943799220
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.4144304540
Short name T778
Test name
Test status
Simulation time 3410911746 ps
CPU time 6.3 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:40 PM PDT 24
Peak memory 202088 kb
Host smart-c4154067-d1cb-43f6-9c11-f9edd67e7e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144304540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.4
144304540
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3511063730
Short name T536
Test name
Test status
Simulation time 24580222373 ps
CPU time 42.54 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 202308 kb
Host smart-a44321c7-ced2-415c-a440-9efdc01f8699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511063730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.3511063730
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1230423951
Short name T159
Test name
Test status
Simulation time 4022627553 ps
CPU time 3.91 seconds
Started Jun 07 08:30:42 PM PDT 24
Finished Jun 07 08:30:52 PM PDT 24
Peak memory 202008 kb
Host smart-96ae828f-102b-44ad-9d61-4c89700c0bc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230423951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.1230423951
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2484455274
Short name T211
Test name
Test status
Simulation time 4154113221 ps
CPU time 5.42 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:39 PM PDT 24
Peak memory 202016 kb
Host smart-0368a7d4-89d9-4665-8882-edbc0e03502b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484455274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.2484455274
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.539501263
Short name T458
Test name
Test status
Simulation time 2616014749 ps
CPU time 3.88 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:44 PM PDT 24
Peak memory 201936 kb
Host smart-44b99986-b145-47dc-b587-c26f710ad57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539501263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.539501263
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2697822334
Short name T784
Test name
Test status
Simulation time 2492053512 ps
CPU time 2.03 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 201940 kb
Host smart-056d63d9-43ec-4373-99ab-3c02918c44d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697822334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.2697822334
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3721597186
Short name T231
Test name
Test status
Simulation time 2178925557 ps
CPU time 1.88 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:49 PM PDT 24
Peak memory 201956 kb
Host smart-cb8331e3-29e0-40bc-b7dc-34ff33ef3345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721597186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3721597186
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3966692600
Short name T460
Test name
Test status
Simulation time 2513881135 ps
CPU time 6.57 seconds
Started Jun 07 08:30:30 PM PDT 24
Finished Jun 07 08:30:41 PM PDT 24
Peak memory 202024 kb
Host smart-595d7c69-da0f-4ad2-82a2-13b3a87896c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966692600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3966692600
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.2758159798
Short name T240
Test name
Test status
Simulation time 2127217051 ps
CPU time 1.9 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:48 PM PDT 24
Peak memory 201836 kb
Host smart-17de24c7-5883-4469-9b8c-4f9ac5f5b934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758159798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.2758159798
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2698602838
Short name T23
Test name
Test status
Simulation time 11005019409 ps
CPU time 6.83 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:30:43 PM PDT 24
Peak memory 201964 kb
Host smart-ee7e168b-a3f3-4082-8dd1-a3baa51e688c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698602838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2698602838
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1680459498
Short name T122
Test name
Test status
Simulation time 138260607896 ps
CPU time 98.14 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:32:24 PM PDT 24
Peak memory 210640 kb
Host smart-b0329a29-18cc-4e20-bccc-486fb8f3ae38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680459498 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1680459498
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.329829573
Short name T677
Test name
Test status
Simulation time 4327205985 ps
CPU time 2.15 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:43 PM PDT 24
Peak memory 202024 kb
Host smart-22f01eed-b915-4b82-91cf-4421167d6bbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329829573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ultra_low_pwr.329829573
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.1317882833
Short name T405
Test name
Test status
Simulation time 2033572316 ps
CPU time 1.97 seconds
Started Jun 07 08:30:43 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 201896 kb
Host smart-d62cdaac-3155-4a43-992b-7689d982396d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317882833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.1317882833
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2066492034
Short name T51
Test name
Test status
Simulation time 99767429130 ps
CPU time 63.16 seconds
Started Jun 07 08:30:22 PM PDT 24
Finished Jun 07 08:31:33 PM PDT 24
Peak memory 202092 kb
Host smart-f85b87cf-1d5f-41e8-8c96-c1e3c1d6208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066492034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.2
066492034
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3479255052
Short name T772
Test name
Test status
Simulation time 107367824634 ps
CPU time 138.02 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:33:01 PM PDT 24
Peak memory 202176 kb
Host smart-940f514a-c710-4eb2-9444-f50c5cf157d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479255052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.3479255052
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4164326865
Short name T704
Test name
Test status
Simulation time 31766492914 ps
CPU time 20.96 seconds
Started Jun 07 08:30:29 PM PDT 24
Finished Jun 07 08:30:54 PM PDT 24
Peak memory 202232 kb
Host smart-9136717c-6b79-4859-b8da-6a8197ad1c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164326865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.4164326865
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2596036703
Short name T16
Test name
Test status
Simulation time 1116648578061 ps
CPU time 727.62 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:42:42 PM PDT 24
Peak memory 202008 kb
Host smart-69a76f95-0dcf-4a3c-987e-fc7a7185c4e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596036703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.2596036703
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2465581702
Short name T152
Test name
Test status
Simulation time 6071575603 ps
CPU time 14.26 seconds
Started Jun 07 08:30:35 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 201964 kb
Host smart-f9f6e60c-ff6e-4977-82a3-858d044e0293
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465581702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.2465581702
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2558241160
Short name T710
Test name
Test status
Simulation time 2635931736 ps
CPU time 2.11 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 201972 kb
Host smart-8f44a4e5-15c2-4308-9337-745f6ce34efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558241160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2558241160
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.74296532
Short name T787
Test name
Test status
Simulation time 2473018052 ps
CPU time 2.18 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 201968 kb
Host smart-23ec92fb-9f94-4ffe-84ac-059961e1cb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74296532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.74296532
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3206213753
Short name T600
Test name
Test status
Simulation time 2311010159 ps
CPU time 1.06 seconds
Started Jun 07 08:30:28 PM PDT 24
Finished Jun 07 08:30:34 PM PDT 24
Peak memory 202020 kb
Host smart-da5b032a-51dc-460c-890b-2ca94cd9d333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206213753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3206213753
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.977355218
Short name T609
Test name
Test status
Simulation time 2510740893 ps
CPU time 7.28 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 201952 kb
Host smart-ed46543f-8d9e-4c15-98a1-c1af0dc34a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977355218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.977355218
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3757900613
Short name T398
Test name
Test status
Simulation time 2132412189 ps
CPU time 1.99 seconds
Started Jun 07 08:30:16 PM PDT 24
Finished Jun 07 08:30:28 PM PDT 24
Peak memory 201844 kb
Host smart-885e0aa7-de94-4cae-b8b6-ddd329c9c11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757900613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3757900613
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1591635063
Short name T506
Test name
Test status
Simulation time 15215309655 ps
CPU time 9.53 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 201964 kb
Host smart-dbdd8071-c59e-40aa-9855-aa1441b76132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591635063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1591635063
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1264659084
Short name T80
Test name
Test status
Simulation time 5597989263 ps
CPU time 2.35 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:42 PM PDT 24
Peak memory 201964 kb
Host smart-cc939517-4b23-42ec-98a6-e2a5dbd954c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264659084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.1264659084
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.3387901957
Short name T655
Test name
Test status
Simulation time 2021160623 ps
CPU time 3.32 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 201996 kb
Host smart-53a4b007-15aa-4189-8cc3-4c2951999e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387901957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.3387901957
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3987236031
Short name T403
Test name
Test status
Simulation time 3877383510 ps
CPU time 3.08 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 202064 kb
Host smart-447dca85-3321-4e72-8406-3631d6092d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987236031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3
987236031
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3538882863
Short name T252
Test name
Test status
Simulation time 174589855232 ps
CPU time 490.33 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:38:56 PM PDT 24
Peak memory 202200 kb
Host smart-440601ea-75d5-4730-8ad1-42ec30c6fc0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538882863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.3538882863
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1570352596
Short name T3
Test name
Test status
Simulation time 99743204896 ps
CPU time 140.8 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:33:08 PM PDT 24
Peak memory 202188 kb
Host smart-31cc4efa-9e86-4d4b-a914-ef9b03ee9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570352596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.1570352596
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2421928946
Short name T766
Test name
Test status
Simulation time 4309827006 ps
CPU time 9.93 seconds
Started Jun 07 08:30:33 PM PDT 24
Finished Jun 07 08:30:45 PM PDT 24
Peak memory 201984 kb
Host smart-c5aeae80-7b2a-4f8f-85ba-850d0d95f754
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421928946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.2421928946
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.576510927
Short name T479
Test name
Test status
Simulation time 2648916544 ps
CPU time 1.45 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:42 PM PDT 24
Peak memory 201940 kb
Host smart-99432b07-78a6-454d-80d6-3a7313d7dd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576510927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.576510927
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3370078464
Short name T602
Test name
Test status
Simulation time 2468912158 ps
CPU time 8.13 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:52 PM PDT 24
Peak memory 201932 kb
Host smart-43512d16-45dd-4a37-be9e-fbbc3d5b2118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370078464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3370078464
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.276598497
Short name T651
Test name
Test status
Simulation time 2165578350 ps
CPU time 6.13 seconds
Started Jun 07 08:30:44 PM PDT 24
Finished Jun 07 08:30:56 PM PDT 24
Peak memory 201948 kb
Host smart-9ac904cf-253e-4bc1-a4d2-1211b2a88a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276598497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.276598497
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.4069823181
Short name T386
Test name
Test status
Simulation time 2512914396 ps
CPU time 6.76 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:48 PM PDT 24
Peak memory 202012 kb
Host smart-5fbd73d7-1d9c-4589-b6df-bb282147384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069823181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.4069823181
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.11340672
Short name T681
Test name
Test status
Simulation time 2136101159 ps
CPU time 1.83 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:45 PM PDT 24
Peak memory 201832 kb
Host smart-c10edb43-358f-4679-ae4f-ae29694105e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11340672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.11340672
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.4030160890
Short name T222
Test name
Test status
Simulation time 15620689548 ps
CPU time 19 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:31:06 PM PDT 24
Peak memory 202052 kb
Host smart-f83b9dfa-16ac-477c-ab24-a389a966732c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030160890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.4030160890
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.968046090
Short name T200
Test name
Test status
Simulation time 94038438472 ps
CPU time 32.42 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:31:20 PM PDT 24
Peak memory 215392 kb
Host smart-7f88721d-519d-4db7-a26e-12fa2022a3de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968046090 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.968046090
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3193839831
Short name T717
Test name
Test status
Simulation time 3954983328 ps
CPU time 6.18 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:54 PM PDT 24
Peak memory 201948 kb
Host smart-8583f098-e7c3-4367-b2e0-9c1e52c98c97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193839831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.3193839831
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.507263969
Short name T693
Test name
Test status
Simulation time 2008484638 ps
CPU time 5.57 seconds
Started Jun 07 08:30:43 PM PDT 24
Finished Jun 07 08:30:55 PM PDT 24
Peak memory 202012 kb
Host smart-efeb524a-b99c-4edc-99ea-38e05e58c537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507263969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_tes
t.507263969
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2034267323
Short name T649
Test name
Test status
Simulation time 3568869613 ps
CPU time 1.36 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:48 PM PDT 24
Peak memory 202064 kb
Host smart-9564cfa5-bbb2-4171-9e82-8fbc1b705bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034267323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2
034267323
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3018915721
Short name T796
Test name
Test status
Simulation time 29832002289 ps
CPU time 59.79 seconds
Started Jun 07 08:30:33 PM PDT 24
Finished Jun 07 08:31:35 PM PDT 24
Peak memory 202284 kb
Host smart-b253ec3d-cf7f-451f-b1da-4a26f76d3bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018915721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.3018915721
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1781347951
Short name T412
Test name
Test status
Simulation time 3223193960 ps
CPU time 8.88 seconds
Started Jun 07 08:30:42 PM PDT 24
Finished Jun 07 08:30:57 PM PDT 24
Peak memory 202044 kb
Host smart-83e9bd3a-7174-4519-a9cd-6ad8c369c89e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781347951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.1781347951
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3476350102
Short name T156
Test name
Test status
Simulation time 4022507164 ps
CPU time 2.23 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 201996 kb
Host smart-db7573c9-41fc-4b54-ade9-48203902e5d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476350102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3476350102
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3743928302
Short name T497
Test name
Test status
Simulation time 2613397372 ps
CPU time 7.4 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:53 PM PDT 24
Peak memory 201968 kb
Host smart-882936fe-80a9-4b02-84c9-5a54bf0e5766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743928302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3743928302
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.4246299881
Short name T695
Test name
Test status
Simulation time 2508230993 ps
CPU time 2.24 seconds
Started Jun 07 08:30:17 PM PDT 24
Finished Jun 07 08:30:29 PM PDT 24
Peak memory 201932 kb
Host smart-bd7e6d64-fff6-48f2-b1b7-b50e86306a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246299881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.4246299881
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.1266079308
Short name T441
Test name
Test status
Simulation time 2239046756 ps
CPU time 2.65 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:44 PM PDT 24
Peak memory 202000 kb
Host smart-edad901a-a70e-4a9c-be16-90c4c228af7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266079308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.1266079308
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3760403825
Short name T699
Test name
Test status
Simulation time 2510036367 ps
CPU time 6.87 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:53 PM PDT 24
Peak memory 202068 kb
Host smart-0bb1d23f-deca-4b5b-a432-12c781ebfdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760403825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3760403825
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.1997792343
Short name T612
Test name
Test status
Simulation time 2133540208 ps
CPU time 1.82 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:48 PM PDT 24
Peak memory 201876 kb
Host smart-0b636c79-6b1d-4fd8-8f6b-4917b35e5dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997792343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1997792343
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.4077666719
Short name T262
Test name
Test status
Simulation time 399438004284 ps
CPU time 83.4 seconds
Started Jun 07 08:30:44 PM PDT 24
Finished Jun 07 08:32:14 PM PDT 24
Peak memory 213276 kb
Host smart-329c4f3e-f6fc-4902-b704-15724ef6c883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077666719 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.4077666719
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.969359056
Short name T791
Test name
Test status
Simulation time 2478799626876 ps
CPU time 512.57 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:39:20 PM PDT 24
Peak memory 202096 kb
Host smart-39d5bdd5-6931-4eba-b508-0c815e51ef84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969359056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ultra_low_pwr.969359056
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.285677088
Short name T219
Test name
Test status
Simulation time 2093035776 ps
CPU time 1.19 seconds
Started Jun 07 08:30:43 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 201988 kb
Host smart-2e714ca5-8d10-41b5-826a-cbfe9ce1882c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285677088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes
t.285677088
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3961664224
Short name T764
Test name
Test status
Simulation time 3276089723 ps
CPU time 1.59 seconds
Started Jun 07 08:30:35 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 202120 kb
Host smart-3f4a3528-c4cb-4365-b620-a9484c8aa430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961664224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.3
961664224
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.2720993470
Short name T91
Test name
Test status
Simulation time 56977732728 ps
CPU time 40.89 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:31:26 PM PDT 24
Peak memory 202280 kb
Host smart-fa4e1743-6060-444b-bdca-5289c45d793e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720993470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.2720993470
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1676340088
Short name T548
Test name
Test status
Simulation time 40847661377 ps
CPU time 115.37 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 202272 kb
Host smart-3d87747a-be03-4cce-aebc-878e1ddd61a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676340088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.1676340088
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.17005463
Short name T501
Test name
Test status
Simulation time 3965478129 ps
CPU time 2.35 seconds
Started Jun 07 08:30:42 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 202012 kb
Host smart-3397f78d-66b0-4bb3-a903-165df1c404cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17005463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_ec_pwr_on_rst.17005463
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2407912346
Short name T229
Test name
Test status
Simulation time 4228487050 ps
CPU time 3.54 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 202052 kb
Host smart-732136b7-7fe7-47ce-a80d-e0ba4dc6a236
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407912346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.2407912346
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1089164066
Short name T399
Test name
Test status
Simulation time 2630559154 ps
CPU time 2.4 seconds
Started Jun 07 08:30:44 PM PDT 24
Finished Jun 07 08:30:53 PM PDT 24
Peak memory 201620 kb
Host smart-541048ea-e4f0-4140-b6ba-df0d4f5776b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089164066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1089164066
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1713209118
Short name T599
Test name
Test status
Simulation time 2511845714 ps
CPU time 2.23 seconds
Started Jun 07 08:30:44 PM PDT 24
Finished Jun 07 08:30:53 PM PDT 24
Peak memory 201664 kb
Host smart-48c4b606-19ea-4894-8511-82a46c8d2e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713209118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1713209118
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.452961117
Short name T618
Test name
Test status
Simulation time 2081634031 ps
CPU time 1.79 seconds
Started Jun 07 08:30:44 PM PDT 24
Finished Jun 07 08:30:52 PM PDT 24
Peak memory 201852 kb
Host smart-50cb81d3-3e37-42f1-9371-a8b4ab9f5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452961117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.452961117
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.304130220
Short name T449
Test name
Test status
Simulation time 2511650113 ps
CPU time 7.78 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 201916 kb
Host smart-67159e42-d72a-4b21-963d-e4ab493765ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304130220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.304130220
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.3674189724
Short name T103
Test name
Test status
Simulation time 2143670278 ps
CPU time 1.56 seconds
Started Jun 07 08:30:44 PM PDT 24
Finished Jun 07 08:30:52 PM PDT 24
Peak memory 201848 kb
Host smart-30c2f65e-e61e-43c9-98e4-4081979f64fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674189724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3674189724
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.78155957
Short name T746
Test name
Test status
Simulation time 15814807017 ps
CPU time 7.09 seconds
Started Jun 07 08:30:44 PM PDT 24
Finished Jun 07 08:30:57 PM PDT 24
Peak memory 202028 kb
Host smart-86a78e11-5a7c-4c84-aa8c-46b3f0bd17d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78155957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_str
ess_all.78155957
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2777591375
Short name T645
Test name
Test status
Simulation time 10230398488 ps
CPU time 7.15 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:45 PM PDT 24
Peak memory 202020 kb
Host smart-07915728-7c30-4b96-aebc-f8926223e5aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777591375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2777591375
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.4020829947
Short name T192
Test name
Test status
Simulation time 2051141816 ps
CPU time 1.23 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:46 PM PDT 24
Peak memory 202084 kb
Host smart-8f6e2657-2836-4dff-9b81-bba77830c6a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020829947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.4020829947
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3683261922
Short name T175
Test name
Test status
Simulation time 3895910918 ps
CPU time 3.11 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:51 PM PDT 24
Peak memory 202044 kb
Host smart-42c3cb57-644d-4950-9c8c-f8d918036114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683261922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.3
683261922
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2482082897
Short name T89
Test name
Test status
Simulation time 24029879208 ps
CPU time 48.85 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:31:30 PM PDT 24
Peak memory 202260 kb
Host smart-9681e297-b3df-46cc-aa76-5ab833effcd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482082897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.2482082897
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.899225384
Short name T708
Test name
Test status
Simulation time 84821870198 ps
CPU time 56.08 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:31:43 PM PDT 24
Peak memory 202256 kb
Host smart-99a1d10f-eefc-488e-b690-77308e2dc95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899225384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wi
th_pre_cond.899225384
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1377129531
Short name T722
Test name
Test status
Simulation time 4157365597 ps
CPU time 6.26 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:48 PM PDT 24
Peak memory 202060 kb
Host smart-9628b50c-199c-422b-80a8-314a9cb0b011
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377129531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.1377129531
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.4149236722
Short name T553
Test name
Test status
Simulation time 2649783962 ps
CPU time 1.86 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 201964 kb
Host smart-27cc87fa-4f03-430f-ad50-6e99f6ead769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149236722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.4149236722
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1481405796
Short name T641
Test name
Test status
Simulation time 2454056167 ps
CPU time 6.66 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 202072 kb
Host smart-acbf9d62-45ae-497e-836e-d54aa0ec6d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481405796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1481405796
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.487761393
Short name T437
Test name
Test status
Simulation time 2144020605 ps
CPU time 1.31 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:45 PM PDT 24
Peak memory 201964 kb
Host smart-b4a86e3d-9028-41df-ad70-74dafc688a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487761393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.487761393
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2361102743
Short name T102
Test name
Test status
Simulation time 2508860732 ps
CPU time 6.64 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:46 PM PDT 24
Peak memory 202072 kb
Host smart-76942748-1bdc-4bcc-a2b8-75027ebde710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361102743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2361102743
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.1516689817
Short name T765
Test name
Test status
Simulation time 2108222486 ps
CPU time 5.98 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 201964 kb
Host smart-04f00ffe-2eec-447a-8f24-ef57820d9e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516689817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.1516689817
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.198652776
Short name T90
Test name
Test status
Simulation time 34740989966 ps
CPU time 46.79 seconds
Started Jun 07 08:30:25 PM PDT 24
Finished Jun 07 08:31:18 PM PDT 24
Peak memory 202224 kb
Host smart-9540198d-f1d9-4949-a7d6-e9f871cd451f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198652776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_st
ress_all.198652776
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.732254130
Short name T322
Test name
Test status
Simulation time 10012438125 ps
CPU time 25.76 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:31:13 PM PDT 24
Peak memory 210596 kb
Host smart-33c874d2-4806-4db7-a467-54df37e1760c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732254130 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.732254130
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.23249638
Short name T120
Test name
Test status
Simulation time 7498797533 ps
CPU time 2.39 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 201992 kb
Host smart-14c48f68-94cc-447d-bb86-59c90739619c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_ultra_low_pwr.23249638
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2144318924
Short name T749
Test name
Test status
Simulation time 3502092001 ps
CPU time 10.43 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:58 PM PDT 24
Peak memory 202120 kb
Host smart-231cf077-88af-4ec0-8c28-a49fcca11bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144318924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.2
144318924
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.1544797954
Short name T711
Test name
Test status
Simulation time 43785555147 ps
CPU time 8.73 seconds
Started Jun 07 08:30:31 PM PDT 24
Finished Jun 07 08:30:43 PM PDT 24
Peak memory 202308 kb
Host smart-58161737-2956-469f-9d70-e499f0b348e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544797954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.1544797954
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2905063480
Short name T12
Test name
Test status
Simulation time 2985165835 ps
CPU time 2.5 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 201960 kb
Host smart-6b95e52e-2fbc-4c60-8f4d-e50731be3f69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905063480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.2905063480
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3599200466
Short name T167
Test name
Test status
Simulation time 2627761972 ps
CPU time 2.41 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:49 PM PDT 24
Peak memory 201972 kb
Host smart-a76c9d50-7ea4-4974-b1da-51b57c202008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599200466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.3599200466
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3259106938
Short name T56
Test name
Test status
Simulation time 2454537476 ps
CPU time 6.48 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:53 PM PDT 24
Peak memory 202072 kb
Host smart-f68c99cf-110a-40c9-9e63-330a18f5b53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259106938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3259106938
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1279350540
Short name T406
Test name
Test status
Simulation time 2170468916 ps
CPU time 1.93 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 202028 kb
Host smart-796c70b9-556e-4daf-8ace-07e997e6325f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279350540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1279350540
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2293929998
Short name T702
Test name
Test status
Simulation time 2515147537 ps
CPU time 5.35 seconds
Started Jun 07 08:30:35 PM PDT 24
Finished Jun 07 08:30:42 PM PDT 24
Peak memory 202024 kb
Host smart-9ff40975-0676-4b1b-a8ad-50887be5694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293929998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2293929998
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.797016357
Short name T588
Test name
Test status
Simulation time 2115548753 ps
CPU time 3.99 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:46 PM PDT 24
Peak memory 201964 kb
Host smart-95ebe6e5-4212-4f1e-84c7-a1c4a74e87f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797016357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.797016357
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.2141245308
Short name T521
Test name
Test status
Simulation time 13404268768 ps
CPU time 33.38 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:31:19 PM PDT 24
Peak memory 202016 kb
Host smart-c96a73e4-3a52-4d29-8763-acf181dcc564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141245308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.2141245308
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3742872208
Short name T300
Test name
Test status
Simulation time 218991944112 ps
CPU time 76.58 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:32:01 PM PDT 24
Peak memory 210628 kb
Host smart-ae25fd38-0551-4781-866f-1cd5769b8dfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742872208 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.3742872208
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2503527054
Short name T125
Test name
Test status
Simulation time 7408556880 ps
CPU time 2.68 seconds
Started Jun 07 08:30:41 PM PDT 24
Finished Jun 07 08:30:50 PM PDT 24
Peak memory 202048 kb
Host smart-764c5476-5733-499c-afef-a6eaa3114c0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503527054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.2503527054
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.3016425834
Short name T109
Test name
Test status
Simulation time 2111575994 ps
CPU time 0.95 seconds
Started Jun 07 08:30:45 PM PDT 24
Finished Jun 07 08:30:54 PM PDT 24
Peak memory 201992 kb
Host smart-17a83850-5c0d-4571-b80f-4184bcbc692a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016425834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.3016425834
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.4106203727
Short name T82
Test name
Test status
Simulation time 3933997760 ps
CPU time 10.35 seconds
Started Jun 07 08:30:42 PM PDT 24
Finished Jun 07 08:30:59 PM PDT 24
Peak memory 202072 kb
Host smart-5d9f3018-4d6e-4442-8eb0-74ba924e0a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106203727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.4
106203727
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2565784750
Short name T374
Test name
Test status
Simulation time 159384177362 ps
CPU time 106.93 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:32:56 PM PDT 24
Peak memory 202280 kb
Host smart-02d643df-a5c9-4a40-a60b-e3c3d2cd1de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565784750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.2565784750
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3112163830
Short name T220
Test name
Test status
Simulation time 2876317640 ps
CPU time 1.85 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:07 PM PDT 24
Peak memory 201984 kb
Host smart-687c78b2-3748-4b0a-84d7-230d665e3899
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112163830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.3112163830
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1020386915
Short name T574
Test name
Test status
Simulation time 2632465545 ps
CPU time 1.98 seconds
Started Jun 07 08:30:34 PM PDT 24
Finished Jun 07 08:30:38 PM PDT 24
Peak memory 201984 kb
Host smart-dd47d82f-e156-4789-bc64-b9fd72fc67ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020386915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.1020386915
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2800893703
Short name T242
Test name
Test status
Simulation time 2486444924 ps
CPU time 3.29 seconds
Started Jun 07 08:30:40 PM PDT 24
Finished Jun 07 08:30:49 PM PDT 24
Peak memory 201956 kb
Host smart-004ed1af-e4e4-4e27-acff-4cd7b4f0d748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800893703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2800893703
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1546490813
Short name T233
Test name
Test status
Simulation time 2160283816 ps
CPU time 6.52 seconds
Started Jun 07 08:30:36 PM PDT 24
Finished Jun 07 08:30:45 PM PDT 24
Peak memory 202024 kb
Host smart-d49cc5f5-93b6-44ab-92dd-d716e1295155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546490813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.1546490813
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.536721142
Short name T757
Test name
Test status
Simulation time 2509453160 ps
CPU time 7.57 seconds
Started Jun 07 08:30:37 PM PDT 24
Finished Jun 07 08:30:48 PM PDT 24
Peak memory 201988 kb
Host smart-a91632d2-e2b0-4fb3-bf96-83c8716cdda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536721142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.536721142
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.728800319
Short name T474
Test name
Test status
Simulation time 2113251979 ps
CPU time 6.35 seconds
Started Jun 07 08:30:35 PM PDT 24
Finished Jun 07 08:30:44 PM PDT 24
Peak memory 201896 kb
Host smart-47bf5695-498f-4ead-994f-80e8cafe858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728800319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.728800319
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.3746791997
Short name T482
Test name
Test status
Simulation time 874536373232 ps
CPU time 2194.52 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 09:07:35 PM PDT 24
Peak memory 202060 kb
Host smart-d1565582-e33c-42a0-ae21-799a1f79496d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746791997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.3746791997
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1169958344
Short name T127
Test name
Test status
Simulation time 6547069844 ps
CPU time 6.38 seconds
Started Jun 07 08:30:38 PM PDT 24
Finished Jun 07 08:30:49 PM PDT 24
Peak memory 202032 kb
Host smart-e38b5f9f-34ab-44aa-8aa2-cbb32d308903
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169958344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.1169958344
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.875057112
Short name T209
Test name
Test status
Simulation time 2031753572 ps
CPU time 2.11 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 08:31:03 PM PDT 24
Peak memory 202016 kb
Host smart-6bb6391d-43d2-4450-8944-c8455daf90fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875057112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_tes
t.875057112
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1749565185
Short name T606
Test name
Test status
Simulation time 3567432570 ps
CPU time 2.81 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:07 PM PDT 24
Peak memory 202084 kb
Host smart-4a75039a-5756-46ad-9563-8a5569e630d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749565185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.1
749565185
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3156068922
Short name T377
Test name
Test status
Simulation time 72096637859 ps
CPU time 49 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:54 PM PDT 24
Peak memory 202280 kb
Host smart-5b237312-ef8c-4c08-9d52-b1919f956479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156068922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.3156068922
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2612379705
Short name T525
Test name
Test status
Simulation time 860547451957 ps
CPU time 370.14 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:37:09 PM PDT 24
Peak memory 202016 kb
Host smart-95793974-f728-49ce-8b75-cf43b4d75f22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612379705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.2612379705
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.486763467
Short name T186
Test name
Test status
Simulation time 4234586630 ps
CPU time 9.55 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:14 PM PDT 24
Peak memory 201984 kb
Host smart-ea1ecf22-2929-4cbf-871f-fc68ce23f15d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486763467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctr
l_edge_detect.486763467
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1568534375
Short name T411
Test name
Test status
Simulation time 2633244730 ps
CPU time 2.69 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:09 PM PDT 24
Peak memory 202068 kb
Host smart-1aad4091-6847-4fac-8da8-428ebc92cb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568534375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1568534375
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.4161856037
Short name T684
Test name
Test status
Simulation time 2511218319 ps
CPU time 1.36 seconds
Started Jun 07 08:31:00 PM PDT 24
Finished Jun 07 08:31:15 PM PDT 24
Peak memory 202036 kb
Host smart-3ac164d8-b7c8-4e36-a47b-8e073d1ad9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161856037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.4161856037
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3306524661
Short name T669
Test name
Test status
Simulation time 2244601695 ps
CPU time 3.64 seconds
Started Jun 07 08:30:48 PM PDT 24
Finished Jun 07 08:31:01 PM PDT 24
Peak memory 201992 kb
Host smart-e3fe3a8c-fde1-4614-9c0c-b95d4a438052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306524661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3306524661
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.4024775487
Short name T453
Test name
Test status
Simulation time 2510974419 ps
CPU time 7.56 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 202036 kb
Host smart-60df94af-e96b-45df-b216-be95f3a52b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024775487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.4024775487
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.1085973246
Short name T491
Test name
Test status
Simulation time 2111548018 ps
CPU time 6.36 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 201892 kb
Host smart-f63c53c4-9fea-4bda-88ab-963afae84fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085973246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1085973246
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1682811771
Short name T36
Test name
Test status
Simulation time 17191863803 ps
CPU time 24.56 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 08:31:25 PM PDT 24
Peak memory 202072 kb
Host smart-4f522a0f-6e35-443e-b079-46bc402bbaa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682811771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1682811771
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4069801420
Short name T299
Test name
Test status
Simulation time 3733050919 ps
CPU time 2.62 seconds
Started Jun 07 08:30:51 PM PDT 24
Finished Jun 07 08:31:05 PM PDT 24
Peak memory 201928 kb
Host smart-898f9bf6-8e61-46ad-b826-34b04929e232
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069801420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.4069801420
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3216814318
Short name T239
Test name
Test status
Simulation time 2009635000 ps
CPU time 5.94 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 202028 kb
Host smart-63c577e2-08f8-4001-907f-aecac166fb24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216814318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3216814318
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1106939908
Short name T512
Test name
Test status
Simulation time 3423706146 ps
CPU time 2.21 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 08:31:03 PM PDT 24
Peak memory 202096 kb
Host smart-c76f9c23-4ae6-422b-99b6-61181726d504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106939908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1
106939908
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.4117029413
Short name T585
Test name
Test status
Simulation time 160246421759 ps
CPU time 405.99 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:37:52 PM PDT 24
Peak memory 202116 kb
Host smart-a12220e8-7f1a-4f15-aeaf-dfb89afc98ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117029413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.4117029413
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2395641336
Short name T569
Test name
Test status
Simulation time 32131633279 ps
CPU time 39.89 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:31:43 PM PDT 24
Peak memory 202248 kb
Host smart-b99d7a03-a5da-4800-9013-3a7d8a60bfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395641336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.2395641336
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2435087820
Short name T483
Test name
Test status
Simulation time 4158700130 ps
CPU time 3.94 seconds
Started Jun 07 08:30:59 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 202008 kb
Host smart-59e6d378-ff70-435d-860f-24d0d24cb7c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435087820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.2435087820
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.1150780123
Short name T41
Test name
Test status
Simulation time 3046741058 ps
CPU time 8.73 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 202004 kb
Host smart-a977dc29-0e69-4eee-846d-e62b06a2974c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150780123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.1150780123
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3610452940
Short name T489
Test name
Test status
Simulation time 2610457927 ps
CPU time 7.55 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 202028 kb
Host smart-29a1ed82-682d-42a1-a8e7-394201538094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610452940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3610452940
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2472496708
Short name T516
Test name
Test status
Simulation time 2477139080 ps
CPU time 2.24 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:31:05 PM PDT 24
Peak memory 201992 kb
Host smart-11980c54-9e82-40ad-bae4-5fcce7e50813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472496708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2472496708
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2731654972
Short name T498
Test name
Test status
Simulation time 2134632791 ps
CPU time 6.43 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 08:31:13 PM PDT 24
Peak memory 201900 kb
Host smart-fe857f04-50b7-40af-882b-935d1eb8fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731654972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2731654972
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2228276309
Short name T297
Test name
Test status
Simulation time 2717272506 ps
CPU time 1.15 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:15 PM PDT 24
Peak memory 202024 kb
Host smart-5e94d876-bace-40e5-b531-42b3f04558b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228276309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.2228276309
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.1366519666
Short name T690
Test name
Test status
Simulation time 2110016054 ps
CPU time 5.32 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:10 PM PDT 24
Peak memory 201892 kb
Host smart-052f263f-e756-4c91-b8b1-8d1784cdd24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366519666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.1366519666
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.3669592997
Short name T381
Test name
Test status
Simulation time 9265764363 ps
CPU time 23.47 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:32 PM PDT 24
Peak memory 202064 kb
Host smart-0680eed9-03c9-4f73-b318-30bc56b995c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669592997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.3669592997
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1232864838
Short name T595
Test name
Test status
Simulation time 442717395305 ps
CPU time 11.02 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:31:09 PM PDT 24
Peak memory 202016 kb
Host smart-bfb027cd-ddde-404b-aabf-16f0601dd772
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232864838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.1232864838
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.649096985
Short name T451
Test name
Test status
Simulation time 2020843624 ps
CPU time 3.4 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:29:45 PM PDT 24
Peak memory 201964 kb
Host smart-cd744340-e4bc-48f1-93ef-5fad25b20746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649096985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test
.649096985
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2680734654
Short name T725
Test name
Test status
Simulation time 3962357686 ps
CPU time 10.43 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 201852 kb
Host smart-b20406fc-268b-405b-ab5b-f3a802079cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680734654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2680734654
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.1539432311
Short name T327
Test name
Test status
Simulation time 59552019315 ps
CPU time 153.36 seconds
Started Jun 07 08:29:39 PM PDT 24
Finished Jun 07 08:32:22 PM PDT 24
Peak memory 202228 kb
Host smart-eb7a639e-7d3d-497e-b857-5e036990088a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539432311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.1539432311
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2010064922
Short name T636
Test name
Test status
Simulation time 2199019001 ps
CPU time 2.02 seconds
Started Jun 07 08:29:36 PM PDT 24
Finished Jun 07 08:29:49 PM PDT 24
Peak memory 202008 kb
Host smart-59fb1f85-3b7b-4782-bd16-35c896e2966e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010064922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2010064922
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1343518003
Short name T502
Test name
Test status
Simulation time 2561624796 ps
CPU time 2.43 seconds
Started Jun 07 08:29:35 PM PDT 24
Finished Jun 07 08:29:48 PM PDT 24
Peak memory 202008 kb
Host smart-3d8475a7-3782-4b16-b9ea-1470611d2589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343518003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1343518003
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.316105560
Short name T326
Test name
Test status
Simulation time 58405574964 ps
CPU time 22.92 seconds
Started Jun 07 08:29:41 PM PDT 24
Finished Jun 07 08:30:13 PM PDT 24
Peak memory 202220 kb
Host smart-5b33356c-a153-4fa3-a95d-2b87c534291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316105560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wit
h_pre_cond.316105560
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2594865306
Short name T661
Test name
Test status
Simulation time 236954029533 ps
CPU time 666.5 seconds
Started Jun 07 08:29:41 PM PDT 24
Finished Jun 07 08:40:57 PM PDT 24
Peak memory 202008 kb
Host smart-1a4fbe82-3b2c-44a4-8c4e-a61487e1d372
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594865306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.2594865306
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.3587785326
Short name T210
Test name
Test status
Simulation time 3460548536 ps
CPU time 8.9 seconds
Started Jun 07 08:29:28 PM PDT 24
Finished Jun 07 08:29:50 PM PDT 24
Peak memory 202032 kb
Host smart-bbd79906-8afa-4723-bc04-a0949094111f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587785326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.3587785326
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3989310521
Short name T615
Test name
Test status
Simulation time 2621791109 ps
CPU time 2.41 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:29:47 PM PDT 24
Peak memory 201992 kb
Host smart-33de06aa-0326-4010-8331-fad4c040ef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989310521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3989310521
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.906532892
Short name T756
Test name
Test status
Simulation time 2475092831 ps
CPU time 4.11 seconds
Started Jun 07 08:29:46 PM PDT 24
Finished Jun 07 08:29:59 PM PDT 24
Peak memory 201988 kb
Host smart-50a08309-9cc2-4497-995e-fed52e25e700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906532892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.906532892
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2607904097
Short name T698
Test name
Test status
Simulation time 2057018822 ps
CPU time 5.77 seconds
Started Jun 07 08:29:47 PM PDT 24
Finished Jun 07 08:30:01 PM PDT 24
Peak memory 201896 kb
Host smart-e575ad30-9c3e-4b9f-80c0-a133e0e55d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607904097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.2607904097
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3138139320
Short name T530
Test name
Test status
Simulation time 2533987819 ps
CPU time 2.04 seconds
Started Jun 07 08:29:30 PM PDT 24
Finished Jun 07 08:29:45 PM PDT 24
Peak memory 202000 kb
Host smart-8775ac0a-41a6-47fc-b1f1-717d665ae9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138139320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3138139320
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.3906152418
Short name T276
Test name
Test status
Simulation time 22236138022 ps
CPU time 5.55 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:29:57 PM PDT 24
Peak memory 221648 kb
Host smart-ea4b4de9-bf90-4d73-bde1-4de28ff81b8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906152418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3906152418
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.3989043373
Short name T581
Test name
Test status
Simulation time 2111038273 ps
CPU time 6.45 seconds
Started Jun 07 08:29:40 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 201884 kb
Host smart-7d99bf69-117e-4493-bf9d-4546df6fc468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989043373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3989043373
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3656315394
Short name T17
Test name
Test status
Simulation time 7356303691 ps
CPU time 5.32 seconds
Started Jun 07 08:29:41 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 202052 kb
Host smart-f32f2443-85d5-4d96-956c-9c3e439a83ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656315394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3656315394
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4114894758
Short name T292
Test name
Test status
Simulation time 8836378225 ps
CPU time 25.05 seconds
Started Jun 07 08:29:40 PM PDT 24
Finished Jun 07 08:30:15 PM PDT 24
Peak memory 210392 kb
Host smart-d5485b39-cece-459d-aae3-7946c6afaa21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114894758 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.4114894758
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1513466078
Short name T777
Test name
Test status
Simulation time 9050793438 ps
CPU time 2.15 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:29:46 PM PDT 24
Peak memory 202020 kb
Host smart-abbd08b9-7dd9-4686-9480-ac0da8724490
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513466078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.1513466078
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.1021436577
Short name T691
Test name
Test status
Simulation time 2026951586 ps
CPU time 1.96 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:11 PM PDT 24
Peak memory 202032 kb
Host smart-0d18a662-60fe-4d79-86ca-8a9f013aeeea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021436577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.1021436577
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.500086599
Short name T782
Test name
Test status
Simulation time 2973566419 ps
CPU time 8.53 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:14 PM PDT 24
Peak memory 202088 kb
Host smart-b82314dd-72b2-48d6-a2cb-76ea61c1f572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500086599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.500086599
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3190549699
Short name T325
Test name
Test status
Simulation time 118582860489 ps
CPU time 84.72 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:32:29 PM PDT 24
Peak memory 202144 kb
Host smart-58b219d1-abab-435e-9fa4-3fa71cefe2f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190549699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3190549699
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1756705221
Short name T26
Test name
Test status
Simulation time 111918357626 ps
CPU time 67.6 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 202236 kb
Host smart-cc978caa-bae2-4156-94cb-f2806c1db97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756705221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.1756705221
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1502097323
Short name T435
Test name
Test status
Simulation time 3162714146 ps
CPU time 9.28 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:31:09 PM PDT 24
Peak memory 202004 kb
Host smart-4f354d15-d184-47a6-9e7e-4b97be13f19a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502097323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.1502097323
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3121826963
Short name T187
Test name
Test status
Simulation time 4637643468 ps
CPU time 3.11 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 08:31:04 PM PDT 24
Peak memory 201984 kb
Host smart-4d6b4ce8-7727-4a55-a484-631e184bf7ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121826963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.3121826963
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2639158221
Short name T522
Test name
Test status
Simulation time 2612288706 ps
CPU time 7.33 seconds
Started Jun 07 08:30:51 PM PDT 24
Finished Jun 07 08:31:10 PM PDT 24
Peak memory 202020 kb
Host smart-281572e7-2880-4fc4-ac98-064626efe928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639158221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.2639158221
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2659004907
Short name T631
Test name
Test status
Simulation time 2480539142 ps
CPU time 2.12 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:31:14 PM PDT 24
Peak memory 201936 kb
Host smart-fc59c5a9-ea7c-4bef-a750-6d99fc5f0c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659004907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2659004907
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.533398626
Short name T402
Test name
Test status
Simulation time 2226035815 ps
CPU time 1.99 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:31:05 PM PDT 24
Peak memory 201992 kb
Host smart-496006a4-ddd3-47d8-9d40-da6934b430e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533398626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.533398626
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.4122787022
Short name T409
Test name
Test status
Simulation time 2526163146 ps
CPU time 2.21 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:08 PM PDT 24
Peak memory 201968 kb
Host smart-16d031b3-fbff-43a4-8603-6e4058696870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122787022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.4122787022
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.4177629588
Short name T14
Test name
Test status
Simulation time 2132973393 ps
CPU time 1.47 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:09 PM PDT 24
Peak memory 201868 kb
Host smart-dbe17cb1-9569-41d5-9ba1-3b3c51146ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177629588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.4177629588
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.733763641
Short name T164
Test name
Test status
Simulation time 11636073625 ps
CPU time 2.27 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:31:00 PM PDT 24
Peak memory 201976 kb
Host smart-1b50a0ce-9167-40f8-96e0-6916ed41024d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733763641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_st
ress_all.733763641
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.4263811473
Short name T146
Test name
Test status
Simulation time 44274710050 ps
CPU time 88.11 seconds
Started Jun 07 08:31:06 PM PDT 24
Finished Jun 07 08:32:48 PM PDT 24
Peak memory 210600 kb
Host smart-503a688f-ed88-479e-aeab-ed1360bc6daa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263811473 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.4263811473
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3358930954
Short name T587
Test name
Test status
Simulation time 4943995104 ps
CPU time 5.88 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:14 PM PDT 24
Peak memory 202004 kb
Host smart-a85c28fe-3268-4c2a-935e-807b55a68582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358930954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.3358930954
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.3014227145
Short name T480
Test name
Test status
Simulation time 2024889378 ps
CPU time 1.97 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:09 PM PDT 24
Peak memory 202004 kb
Host smart-2425e643-0bef-40ea-b3aa-d4e41689cc20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014227145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.3014227145
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.625903750
Short name T417
Test name
Test status
Simulation time 3392027962 ps
CPU time 8.35 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:31:20 PM PDT 24
Peak memory 202072 kb
Host smart-39fa16e5-4cd0-4476-9ed1-52714b1b68ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625903750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.625903750
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3441310025
Short name T675
Test name
Test status
Simulation time 135382552366 ps
CPU time 171.56 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:33:59 PM PDT 24
Peak memory 202260 kb
Host smart-d897b6b0-d8de-4dc8-a5c0-b1f1c6ed3b52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441310025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.3441310025
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1841428168
Short name T68
Test name
Test status
Simulation time 93235091737 ps
CPU time 42.14 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:31:41 PM PDT 24
Peak memory 202244 kb
Host smart-7e0c6280-f857-4b9f-919b-583e66c471ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841428168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1841428168
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.607504140
Short name T84
Test name
Test status
Simulation time 4576554633 ps
CPU time 11.88 seconds
Started Jun 07 08:30:48 PM PDT 24
Finished Jun 07 08:31:09 PM PDT 24
Peak memory 202012 kb
Host smart-8f58cec9-cfcc-45f6-bd49-ffb03020b7b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607504140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ec_pwr_on_rst.607504140
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.2054719564
Short name T718
Test name
Test status
Simulation time 2688805754 ps
CPU time 6.55 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 201968 kb
Host smart-26f10b94-a3cf-4f66-9ff8-2528eb795c56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054719564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.2054719564
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1806179148
Short name T243
Test name
Test status
Simulation time 2611661518 ps
CPU time 7.58 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:31:23 PM PDT 24
Peak memory 202044 kb
Host smart-3cbcab08-45bc-452d-9dce-0a083d4aaac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806179148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1806179148
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.123887018
Short name T295
Test name
Test status
Simulation time 2467603169 ps
CPU time 4.03 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:31:07 PM PDT 24
Peak memory 201932 kb
Host smart-7ef630e2-a1b0-48fc-968e-49ded16c1355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123887018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.123887018
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.646798457
Short name T524
Test name
Test status
Simulation time 2246041247 ps
CPU time 6.63 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:13 PM PDT 24
Peak memory 201968 kb
Host smart-ae8c846e-726f-4a17-b665-356e205b6a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646798457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.646798457
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1143514127
Short name T652
Test name
Test status
Simulation time 2514255182 ps
CPU time 6.75 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:14 PM PDT 24
Peak memory 202048 kb
Host smart-e1d0d906-bb3c-4033-a156-d48d2383c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143514127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.1143514127
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1784512903
Short name T656
Test name
Test status
Simulation time 2120433135 ps
CPU time 3.23 seconds
Started Jun 07 08:30:59 PM PDT 24
Finished Jun 07 08:31:16 PM PDT 24
Peak memory 201852 kb
Host smart-572cabd6-a90c-4d6f-a80c-7ef7d4ab36c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784512903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1784512903
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.88035303
Short name T659
Test name
Test status
Simulation time 15572904960 ps
CPU time 40.17 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:44 PM PDT 24
Peak memory 202088 kb
Host smart-af6de151-11d2-4370-9d0b-a57d1666aa09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88035303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_str
ess_all.88035303
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3195149124
Short name T470
Test name
Test status
Simulation time 8255275762 ps
CPU time 2.79 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:08 PM PDT 24
Peak memory 202000 kb
Host smart-9d7109e2-395e-4df6-86b5-629553dbac10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195149124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.3195149124
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.624573194
Short name T526
Test name
Test status
Simulation time 2037286055 ps
CPU time 1.9 seconds
Started Jun 07 08:30:39 PM PDT 24
Finished Jun 07 08:30:47 PM PDT 24
Peak memory 201596 kb
Host smart-ea2d0920-3eaf-4056-94f9-523764a8153c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624573194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_tes
t.624573194
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1857519244
Short name T527
Test name
Test status
Simulation time 3799887034 ps
CPU time 5.25 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:10 PM PDT 24
Peak memory 202096 kb
Host smart-4e3b05db-f0cd-4661-a28c-6b858bacbd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857519244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.1
857519244
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1574260023
Short name T206
Test name
Test status
Simulation time 128453363653 ps
CPU time 171.99 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:33:56 PM PDT 24
Peak memory 202216 kb
Host smart-8a68a966-211c-4ce6-b224-8f66ceadc0eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574260023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1574260023
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.526496667
Short name T53
Test name
Test status
Simulation time 2794047393 ps
CPU time 2.27 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:09 PM PDT 24
Peak memory 201984 kb
Host smart-01dd1f3b-c4e5-44df-b34e-066a92d56b34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526496667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.526496667
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.199867583
Short name T24
Test name
Test status
Simulation time 4509984726 ps
CPU time 1.67 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:10 PM PDT 24
Peak memory 202016 kb
Host smart-f968bf06-cac1-490f-9cb6-8f9d4008c8da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199867583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctr
l_edge_detect.199867583
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1870835742
Short name T444
Test name
Test status
Simulation time 2614313569 ps
CPU time 7.15 seconds
Started Jun 07 08:31:05 PM PDT 24
Finished Jun 07 08:31:26 PM PDT 24
Peak memory 201988 kb
Host smart-34d2c741-834c-4f6e-85c0-7a9336ea176c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870835742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1870835742
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.320179239
Short name T420
Test name
Test status
Simulation time 2467813476 ps
CPU time 8.2 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:18 PM PDT 24
Peak memory 202016 kb
Host smart-f85f0198-aadf-4519-a790-6172cce17c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320179239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.320179239
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.312149423
Short name T433
Test name
Test status
Simulation time 2045768629 ps
CPU time 3.15 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:31:02 PM PDT 24
Peak memory 201828 kb
Host smart-80d2979e-88eb-482d-b77e-667b378ac0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312149423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.312149423
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3427692536
Short name T604
Test name
Test status
Simulation time 2510635957 ps
CPU time 7.84 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:31:06 PM PDT 24
Peak memory 201964 kb
Host smart-286dbf25-1d5a-44c9-bfef-5eb07c195ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427692536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.3427692536
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.331802890
Short name T549
Test name
Test status
Simulation time 2129817918 ps
CPU time 2.28 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:06 PM PDT 24
Peak memory 201904 kb
Host smart-ba4ba7c6-d3e8-486e-a51d-7d658ac0ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331802890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.331802890
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.2962643371
Short name T775
Test name
Test status
Simulation time 8557796775 ps
CPU time 21.84 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:26 PM PDT 24
Peak memory 202016 kb
Host smart-5fc078b2-c661-408d-a43c-65180cfa0c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962643371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.2962643371
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1523820642
Short name T121
Test name
Test status
Simulation time 103659125603 ps
CPU time 90.71 seconds
Started Jun 07 08:31:01 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 210592 kb
Host smart-d4273f8b-f877-475d-b47c-7f472080e933
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523820642 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.1523820642
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1278790248
Short name T721
Test name
Test status
Simulation time 8859971893 ps
CPU time 4.3 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 08:31:05 PM PDT 24
Peak memory 202024 kb
Host smart-74526e33-0904-46f3-a257-d8b84ea80472
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278790248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.1278790248
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.2129319420
Short name T499
Test name
Test status
Simulation time 2043149194 ps
CPU time 1.59 seconds
Started Jun 07 08:31:03 PM PDT 24
Finished Jun 07 08:31:18 PM PDT 24
Peak memory 201976 kb
Host smart-657f4c8c-f4fe-4fb7-8616-8cb11755a929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129319420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.2129319420
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2239345713
Short name T667
Test name
Test status
Simulation time 3223503593 ps
CPU time 1.71 seconds
Started Jun 07 08:30:51 PM PDT 24
Finished Jun 07 08:31:03 PM PDT 24
Peak memory 202024 kb
Host smart-d7d6ee78-31a7-4495-903c-29a8658c9d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239345713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2
239345713
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1036055865
Short name T658
Test name
Test status
Simulation time 144621573299 ps
CPU time 341.83 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:36:48 PM PDT 24
Peak memory 202244 kb
Host smart-6779e693-3277-4e0a-ace3-451cca4dc235
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036055865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1036055865
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2707719479
Short name T302
Test name
Test status
Simulation time 4947248226 ps
CPU time 12.92 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:18 PM PDT 24
Peak memory 202008 kb
Host smart-df7a7e5b-9938-4013-889c-5db3e714b82e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707719479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.2707719479
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.748980369
Short name T149
Test name
Test status
Simulation time 2367414883 ps
CPU time 6.3 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:14 PM PDT 24
Peak memory 201984 kb
Host smart-9284c1d9-d6b7-4c9d-b8d5-e174bf5fa15e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748980369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctr
l_edge_detect.748980369
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4030757669
Short name T104
Test name
Test status
Simulation time 2688040141 ps
CPU time 1.29 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 202108 kb
Host smart-bf7db3ee-355b-4c04-baab-1308acc4297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030757669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.4030757669
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2870493743
Short name T62
Test name
Test status
Simulation time 2474249787 ps
CPU time 3.61 seconds
Started Jun 07 08:30:49 PM PDT 24
Finished Jun 07 08:31:02 PM PDT 24
Peak memory 201928 kb
Host smart-96ec3bf1-d095-478c-a58e-fe152ccddcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870493743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.2870493743
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.352916962
Short name T492
Test name
Test status
Simulation time 2234132520 ps
CPU time 6.49 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:14 PM PDT 24
Peak memory 201984 kb
Host smart-b46c5af6-5390-4687-8dda-199e8eb79631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352916962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.352916962
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3977203359
Short name T639
Test name
Test status
Simulation time 2560418372 ps
CPU time 1.54 seconds
Started Jun 07 08:30:51 PM PDT 24
Finished Jun 07 08:31:04 PM PDT 24
Peak memory 202052 kb
Host smart-e9c5fd80-4198-41bc-9be2-e16ca3067277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977203359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3977203359
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.2795049118
Short name T673
Test name
Test status
Simulation time 2114323923 ps
CPU time 6.06 seconds
Started Jun 07 08:30:50 PM PDT 24
Finished Jun 07 08:31:06 PM PDT 24
Peak memory 201860 kb
Host smart-538f8998-d12b-4a3c-b467-0c3dc431fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795049118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2795049118
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3636632956
Short name T33
Test name
Test status
Simulation time 187155700991 ps
CPU time 128.72 seconds
Started Jun 07 08:30:52 PM PDT 24
Finished Jun 07 08:33:17 PM PDT 24
Peak memory 202208 kb
Host smart-b038f428-361f-494f-9992-4253729e648e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636632956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3636632956
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.815165595
Short name T131
Test name
Test status
Simulation time 36433553170 ps
CPU time 42.85 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:49 PM PDT 24
Peak memory 210532 kb
Host smart-7eed20a7-3f81-406d-ad4a-f25ddf79e5ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815165595 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.815165595
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.317017716
Short name T61
Test name
Test status
Simulation time 6647313321 ps
CPU time 2.98 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:31:15 PM PDT 24
Peak memory 201984 kb
Host smart-2302d824-38a0-42e4-9c76-c15dd9f3a0a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317017716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_ultra_low_pwr.317017716
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2941514617
Short name T397
Test name
Test status
Simulation time 2013082855 ps
CPU time 5.34 seconds
Started Jun 07 08:31:03 PM PDT 24
Finished Jun 07 08:31:22 PM PDT 24
Peak memory 201988 kb
Host smart-d7be9a15-0965-4f5b-8a40-eede343d10a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941514617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2941514617
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.76560737
Short name T436
Test name
Test status
Simulation time 3899300683 ps
CPU time 5.92 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:15 PM PDT 24
Peak memory 202092 kb
Host smart-e55b97b5-a48b-451c-94ae-e3de75bb2868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76560737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.76560737
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.309522082
Short name T555
Test name
Test status
Simulation time 166885656311 ps
CPU time 450.44 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:38:46 PM PDT 24
Peak memory 202368 kb
Host smart-8729d2b6-77a7-451d-a48d-404fed0b62d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309522082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_combo_detect.309522082
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1294248253
Short name T688
Test name
Test status
Simulation time 97960729627 ps
CPU time 98.04 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 202300 kb
Host smart-f4905c9a-a5ef-4692-8d91-f4600a7a8624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294248253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.1294248253
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1940849402
Short name T755
Test name
Test status
Simulation time 3827150586 ps
CPU time 5.27 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:31:16 PM PDT 24
Peak memory 202084 kb
Host smart-5a566866-999d-488a-a942-076d4481ce58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940849402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1940849402
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3415090780
Short name T190
Test name
Test status
Simulation time 2922499614 ps
CPU time 4.18 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:31:19 PM PDT 24
Peak memory 202092 kb
Host smart-01873414-703d-45f2-97ff-d04b4b10ec5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415090780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3415090780
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2721582242
Short name T426
Test name
Test status
Simulation time 2626225581 ps
CPU time 2.65 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:11 PM PDT 24
Peak memory 202044 kb
Host smart-08c979f5-6f81-482f-8b92-c4e5e8e43bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721582242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2721582242
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2070480020
Short name T21
Test name
Test status
Simulation time 2456695659 ps
CPU time 7.22 seconds
Started Jun 07 08:31:03 PM PDT 24
Finished Jun 07 08:31:24 PM PDT 24
Peak memory 201956 kb
Host smart-eb46d3fa-c887-4682-969f-522533b16edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070480020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2070480020
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3753831906
Short name T589
Test name
Test status
Simulation time 2318314000 ps
CPU time 1.06 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 202096 kb
Host smart-cd61684a-2b93-46b6-ac4b-c4b85ac1fd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753831906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3753831906
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2676800505
Short name T488
Test name
Test status
Simulation time 2523459805 ps
CPU time 2.28 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:10 PM PDT 24
Peak memory 202048 kb
Host smart-978d000a-07c4-4879-85a7-8abfeaa268d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676800505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2676800505
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.2711611591
Short name T445
Test name
Test status
Simulation time 2113135180 ps
CPU time 5.75 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:13 PM PDT 24
Peak memory 201844 kb
Host smart-e48e15ce-f70b-4ecd-877b-2ca110565ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711611591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2711611591
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.1332240037
Short name T732
Test name
Test status
Simulation time 2016026499 ps
CPU time 5.85 seconds
Started Jun 07 08:31:08 PM PDT 24
Finished Jun 07 08:31:28 PM PDT 24
Peak memory 202096 kb
Host smart-f292ba43-1f9b-417f-89f0-d1f4fd5bb05a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332240037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.1332240037
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1079591933
Short name T25
Test name
Test status
Simulation time 3413188918 ps
CPU time 10.17 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:16 PM PDT 24
Peak memory 202068 kb
Host smart-f7b511c6-dd78-43b3-b29a-a2d8ead597a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079591933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
079591933
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.2369401728
Short name T250
Test name
Test status
Simulation time 56194152934 ps
CPU time 36.71 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:44 PM PDT 24
Peak memory 202312 kb
Host smart-26bd36af-aa41-426a-aa21-418424a036e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369401728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.2369401728
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2963980775
Short name T744
Test name
Test status
Simulation time 97754817580 ps
CPU time 255.69 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 202304 kb
Host smart-8220e62c-e2f7-4bd7-ba7d-eb288d69f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963980775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.2963980775
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2110648370
Short name T216
Test name
Test status
Simulation time 4252489165 ps
CPU time 1.69 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:07 PM PDT 24
Peak memory 201988 kb
Host smart-bf30e77b-a479-47d8-a073-4e5ebc916ec7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110648370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.2110648370
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.2782489983
Short name T214
Test name
Test status
Simulation time 4213143544 ps
CPU time 2.83 seconds
Started Jun 07 08:31:08 PM PDT 24
Finished Jun 07 08:31:24 PM PDT 24
Peak memory 202096 kb
Host smart-9d2ac543-e041-43f0-9002-56170f8f1ba9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782489983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.2782489983
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.525005974
Short name T393
Test name
Test status
Simulation time 2633533419 ps
CPU time 2.45 seconds
Started Jun 07 08:30:53 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 201976 kb
Host smart-822075f5-c5ff-49a4-9650-e63b27b11a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525005974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.525005974
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.657240761
Short name T432
Test name
Test status
Simulation time 2452477129 ps
CPU time 7.32 seconds
Started Jun 07 08:31:12 PM PDT 24
Finished Jun 07 08:31:32 PM PDT 24
Peak memory 202068 kb
Host smart-34200ea9-9156-4929-a12f-e79c9ebca17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657240761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.657240761
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3735185957
Short name T668
Test name
Test status
Simulation time 2088285125 ps
CPU time 1.34 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 201856 kb
Host smart-5e966761-5249-42f9-b801-03d22957639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735185957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.3735185957
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2742903609
Short name T107
Test name
Test status
Simulation time 2530014753 ps
CPU time 2.23 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 201988 kb
Host smart-d2f89052-696b-4c14-8e92-7b23d2ada9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742903609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2742903609
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.3158154296
Short name T630
Test name
Test status
Simulation time 2133237903 ps
CPU time 2.07 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:08 PM PDT 24
Peak memory 201852 kb
Host smart-3bb2331f-9bb9-4d63-b84c-393525629234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158154296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.3158154296
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.1911313483
Short name T687
Test name
Test status
Simulation time 1862719090006 ps
CPU time 134.18 seconds
Started Jun 07 08:31:08 PM PDT 24
Finished Jun 07 08:33:36 PM PDT 24
Peak memory 202072 kb
Host smart-2d92427a-f700-488d-91ad-305de837e4ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911313483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.1911313483
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1321746454
Short name T205
Test name
Test status
Simulation time 11265530793 ps
CPU time 30.34 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:36 PM PDT 24
Peak memory 202148 kb
Host smart-1258705d-6926-4836-9cea-cffee5517e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321746454 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.1321746454
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2994857916
Short name T76
Test name
Test status
Simulation time 5441293533 ps
CPU time 2.41 seconds
Started Jun 07 08:31:12 PM PDT 24
Finished Jun 07 08:31:28 PM PDT 24
Peak memory 202088 kb
Host smart-51ccd689-3405-470c-aeb6-28210b0961bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994857916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.2994857916
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.759906263
Short name T768
Test name
Test status
Simulation time 2018813050 ps
CPU time 3.21 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:31:15 PM PDT 24
Peak memory 202044 kb
Host smart-4a3101c1-176a-42bb-be53-b113bc0fd37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759906263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_tes
t.759906263
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2411514503
Short name T477
Test name
Test status
Simulation time 3224766654 ps
CPU time 2.84 seconds
Started Jun 07 08:31:03 PM PDT 24
Finished Jun 07 08:31:19 PM PDT 24
Peak memory 202160 kb
Host smart-bbb4ecb8-ece9-41ea-b88f-141ea72c9d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411514503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.2
411514503
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.227772494
Short name T95
Test name
Test status
Simulation time 71716575827 ps
CPU time 190.27 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:34:16 PM PDT 24
Peak memory 202240 kb
Host smart-0325a84d-1193-462f-8c72-69b4665c5c74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227772494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_combo_detect.227772494
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.4082113323
Short name T540
Test name
Test status
Simulation time 70832410937 ps
CPU time 94.85 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 202276 kb
Host smart-979f1afe-a6bc-4a1a-89a2-c3a35a3542f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082113323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.4082113323
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3828152162
Short name T467
Test name
Test status
Simulation time 3513165499 ps
CPU time 1.76 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:31:18 PM PDT 24
Peak memory 202080 kb
Host smart-11dec1e4-6095-4131-a1b2-afb6a8321665
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828152162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.3828152162
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3617809920
Short name T753
Test name
Test status
Simulation time 4530828867 ps
CPU time 6.73 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:16 PM PDT 24
Peak memory 202004 kb
Host smart-2aed4980-7502-4c2f-a1dd-cc410d0fd23d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617809920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.3617809920
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3496891654
Short name T568
Test name
Test status
Simulation time 2630819157 ps
CPU time 2.33 seconds
Started Jun 07 08:31:24 PM PDT 24
Finished Jun 07 08:31:36 PM PDT 24
Peak memory 202020 kb
Host smart-6b63f0e5-b0b5-4612-b1cf-f0ae7d30ca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496891654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.3496891654
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.65109101
Short name T584
Test name
Test status
Simulation time 2491378976 ps
CPU time 2.6 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:31:18 PM PDT 24
Peak memory 202088 kb
Host smart-74f40a27-ce56-4671-a20d-c13995e919e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65109101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.65109101
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1538249860
Short name T671
Test name
Test status
Simulation time 2091883209 ps
CPU time 5.96 seconds
Started Jun 07 08:31:13 PM PDT 24
Finished Jun 07 08:31:32 PM PDT 24
Peak memory 201888 kb
Host smart-ecd79b77-f221-4328-ab7c-bcb9506f8466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538249860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1538249860
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.4019661306
Short name T430
Test name
Test status
Simulation time 2512046837 ps
CPU time 6.91 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 202044 kb
Host smart-0c5198a3-942a-44c3-9916-1a2fe94ad5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019661306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.4019661306
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.2551023363
Short name T423
Test name
Test status
Simulation time 2118184950 ps
CPU time 3.18 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 201912 kb
Host smart-2456d0c8-38bf-4574-80d4-ad12920f8e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551023363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2551023363
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3087203950
Short name T130
Test name
Test status
Simulation time 827282427258 ps
CPU time 132.56 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:33:20 PM PDT 24
Peak memory 218716 kb
Host smart-c9dfcb96-718b-4e34-84db-2dc78bc58f8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087203950 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.3087203950
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.791259814
Short name T762
Test name
Test status
Simulation time 2729654034 ps
CPU time 2.16 seconds
Started Jun 07 08:31:01 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 202064 kb
Host smart-9eb7a7bc-5020-4147-bb46-2b59f532807b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791259814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ultra_low_pwr.791259814
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.4157821793
Short name T225
Test name
Test status
Simulation time 2020368392 ps
CPU time 3.28 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:31:19 PM PDT 24
Peak memory 202060 kb
Host smart-4bd7cd59-cdbd-4fbe-abea-aad9fd7ec5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157821793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.4157821793
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1705093930
Short name T666
Test name
Test status
Simulation time 249253994631 ps
CPU time 638.38 seconds
Started Jun 07 08:31:08 PM PDT 24
Finished Jun 07 08:42:00 PM PDT 24
Peak memory 202076 kb
Host smart-d855b76a-f27f-44fe-a2a7-1a72697a805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705093930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1
705093930
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2093185896
Short name T365
Test name
Test status
Simulation time 149592782753 ps
CPU time 35.41 seconds
Started Jun 07 08:31:03 PM PDT 24
Finished Jun 07 08:31:52 PM PDT 24
Peak memory 202364 kb
Host smart-8d735fad-bf04-4065-9dfd-39307af42912
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093185896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.2093185896
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2923422306
Short name T158
Test name
Test status
Simulation time 84755930233 ps
CPU time 32.26 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:42 PM PDT 24
Peak memory 202268 kb
Host smart-df2c9862-b26e-443e-86b6-fef91a590552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923422306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2923422306
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2417113083
Short name T260
Test name
Test status
Simulation time 3113967030 ps
CPU time 2.33 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:09 PM PDT 24
Peak memory 202008 kb
Host smart-f86d8fce-5dc3-4061-b247-6e037ecaf587
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417113083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.2417113083
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.3726988111
Short name T166
Test name
Test status
Simulation time 4090342524 ps
CPU time 4.87 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:31:20 PM PDT 24
Peak memory 202024 kb
Host smart-8884843a-9c0b-407b-a255-257bf7685dc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726988111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.3726988111
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1083758613
Short name T520
Test name
Test status
Simulation time 2609664506 ps
CPU time 6.82 seconds
Started Jun 07 08:31:03 PM PDT 24
Finished Jun 07 08:31:23 PM PDT 24
Peak memory 202108 kb
Host smart-f5f138d5-f75f-4cb3-944b-d6e5d35d9a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083758613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.1083758613
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3501796039
Short name T626
Test name
Test status
Simulation time 2465152281 ps
CPU time 7.07 seconds
Started Jun 07 08:31:21 PM PDT 24
Finished Jun 07 08:31:39 PM PDT 24
Peak memory 201728 kb
Host smart-fd9ac870-5f8b-49b5-9307-4f341f36e39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501796039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.3501796039
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.792071021
Short name T620
Test name
Test status
Simulation time 2113965766 ps
CPU time 3.48 seconds
Started Jun 07 08:31:31 PM PDT 24
Finished Jun 07 08:31:45 PM PDT 24
Peak memory 201848 kb
Host smart-280755ee-ee65-4910-802b-1d5769883914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792071021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.792071021
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1613156062
Short name T723
Test name
Test status
Simulation time 2524733296 ps
CPU time 2.29 seconds
Started Jun 07 08:31:40 PM PDT 24
Finished Jun 07 08:31:55 PM PDT 24
Peak memory 201992 kb
Host smart-9177ee9c-21bc-4914-9ddd-892498a0ebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613156062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1613156062
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.732800291
Short name T428
Test name
Test status
Simulation time 2111942784 ps
CPU time 5.96 seconds
Started Jun 07 08:30:55 PM PDT 24
Finished Jun 07 08:31:13 PM PDT 24
Peak memory 201868 kb
Host smart-16b7442e-5ec6-42ea-8d09-5193763554e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732800291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.732800291
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3656240809
Short name T165
Test name
Test status
Simulation time 6999725842 ps
CPU time 16.87 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:25 PM PDT 24
Peak memory 202028 kb
Host smart-3f18c2e0-d712-4d70-af6a-2b813569b82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656240809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3656240809
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1726059435
Short name T232
Test name
Test status
Simulation time 27399495562 ps
CPU time 19.39 seconds
Started Jun 07 08:31:24 PM PDT 24
Finished Jun 07 08:31:53 PM PDT 24
Peak memory 210680 kb
Host smart-e4887a9e-f712-401a-8d27-d158b30e13d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726059435 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1726059435
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2577120839
Short name T119
Test name
Test status
Simulation time 9856884980 ps
CPU time 10.45 seconds
Started Jun 07 08:30:58 PM PDT 24
Finished Jun 07 08:31:21 PM PDT 24
Peak memory 201988 kb
Host smart-f5e99100-8ef5-4664-8bd5-9e0f6e8065ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577120839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.2577120839
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3883512411
Short name T410
Test name
Test status
Simulation time 2014218955 ps
CPU time 5.48 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:31:15 PM PDT 24
Peak memory 202028 kb
Host smart-ebdf107a-cb49-42b2-9623-3d0cadda5a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883512411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3883512411
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.685278108
Short name T727
Test name
Test status
Simulation time 200544796321 ps
CPU time 123.89 seconds
Started Jun 07 08:31:00 PM PDT 24
Finished Jun 07 08:33:17 PM PDT 24
Peak memory 202060 kb
Host smart-fa2fb67b-f6dc-4ffc-8e72-0ade7b1f8e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685278108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.685278108
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.2038366285
Short name T265
Test name
Test status
Simulation time 95797553549 ps
CPU time 124.54 seconds
Started Jun 07 08:31:25 PM PDT 24
Finished Jun 07 08:33:39 PM PDT 24
Peak memory 202272 kb
Host smart-fed07e54-d3f0-4cb4-af84-7009c20f85b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038366285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.2038366285
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4012074003
Short name T87
Test name
Test status
Simulation time 28334272313 ps
CPU time 40.34 seconds
Started Jun 07 08:31:01 PM PDT 24
Finished Jun 07 08:31:54 PM PDT 24
Peak memory 202284 kb
Host smart-e3e064a0-8c2c-4ecf-bbed-394d6df1b459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012074003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.4012074003
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.478238277
Short name T485
Test name
Test status
Simulation time 2487655633 ps
CPU time 1.91 seconds
Started Jun 07 08:31:37 PM PDT 24
Finished Jun 07 08:31:50 PM PDT 24
Peak memory 202012 kb
Host smart-91c4ee0e-a5e5-4edf-903d-0787df94b99b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478238277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_ec_pwr_on_rst.478238277
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1616220445
Short name T148
Test name
Test status
Simulation time 2519692454 ps
CPU time 3.44 seconds
Started Jun 07 08:31:25 PM PDT 24
Finished Jun 07 08:31:38 PM PDT 24
Peak memory 202008 kb
Host smart-73bdf73d-8020-4d8a-9d59-4ea326773954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616220445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1616220445
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3077401696
Short name T503
Test name
Test status
Simulation time 2631544648 ps
CPU time 2.24 seconds
Started Jun 07 08:31:02 PM PDT 24
Finished Jun 07 08:31:17 PM PDT 24
Peak memory 202036 kb
Host smart-cfe7c151-d981-4b75-838d-f7705f0d28de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077401696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3077401696
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1455919746
Short name T586
Test name
Test status
Simulation time 2467834556 ps
CPU time 1.78 seconds
Started Jun 07 08:31:05 PM PDT 24
Finished Jun 07 08:31:20 PM PDT 24
Peak memory 201956 kb
Host smart-f2a8afb1-b25f-4f74-8842-cd344bca5724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455919746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1455919746
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.576452134
Short name T395
Test name
Test status
Simulation time 2164795272 ps
CPU time 2.03 seconds
Started Jun 07 08:31:22 PM PDT 24
Finished Jun 07 08:31:34 PM PDT 24
Peak memory 201820 kb
Host smart-36cb9ff0-52b8-4c20-abaa-05445a933bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576452134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.576452134
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.870901007
Short name T560
Test name
Test status
Simulation time 2519221276 ps
CPU time 4 seconds
Started Jun 07 08:31:14 PM PDT 24
Finished Jun 07 08:31:31 PM PDT 24
Peak memory 201988 kb
Host smart-5e51f5e7-e5fd-4ffc-a9ca-977c15b7a99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870901007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.870901007
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.4095902081
Short name T726
Test name
Test status
Simulation time 2110268997 ps
CPU time 6.05 seconds
Started Jun 07 08:31:00 PM PDT 24
Finished Jun 07 08:31:19 PM PDT 24
Peak memory 201888 kb
Host smart-4436159f-7d77-4558-889a-01685f7fec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095902081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.4095902081
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2884012502
Short name T607
Test name
Test status
Simulation time 7531477378 ps
CPU time 1.94 seconds
Started Jun 07 08:31:03 PM PDT 24
Finished Jun 07 08:31:19 PM PDT 24
Peak memory 202088 kb
Host smart-692d43f9-160f-4a3f-9d4d-791c44bad269
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884012502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.2884012502
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.1908479330
Short name T194
Test name
Test status
Simulation time 2010871070 ps
CPU time 5.5 seconds
Started Jun 07 08:30:54 PM PDT 24
Finished Jun 07 08:31:12 PM PDT 24
Peak memory 202016 kb
Host smart-36ea51ae-f29f-4557-8c7b-395f6c78dbd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908479330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.1908479330
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.635173316
Short name T373
Test name
Test status
Simulation time 142538665462 ps
CPU time 96.86 seconds
Started Jun 07 08:31:33 PM PDT 24
Finished Jun 07 08:33:20 PM PDT 24
Peak memory 202252 kb
Host smart-9cbb242e-82d5-434c-9801-172374c853d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635173316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_combo_detect.635173316
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.908790371
Short name T565
Test name
Test status
Simulation time 33882576481 ps
CPU time 47.5 seconds
Started Jun 07 08:30:59 PM PDT 24
Finished Jun 07 08:32:04 PM PDT 24
Peak memory 202304 kb
Host smart-94298509-f680-4aea-8d33-7b9df5e64e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908790371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_wi
th_pre_cond.908790371
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3218727307
Short name T394
Test name
Test status
Simulation time 2709439673 ps
CPU time 7.57 seconds
Started Jun 07 08:31:29 PM PDT 24
Finished Jun 07 08:31:46 PM PDT 24
Peak memory 202020 kb
Host smart-729d8b14-6376-4202-8af4-64cfc8dd5339
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218727307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.3218727307
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.510957874
Short name T179
Test name
Test status
Simulation time 4342604818 ps
CPU time 1.11 seconds
Started Jun 07 08:30:59 PM PDT 24
Finished Jun 07 08:31:13 PM PDT 24
Peak memory 202008 kb
Host smart-eed19491-2503-4cc2-9760-66e696440243
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510957874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctr
l_edge_detect.510957874
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3212981589
Short name T625
Test name
Test status
Simulation time 2612870302 ps
CPU time 7.65 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:32:28 PM PDT 24
Peak memory 199956 kb
Host smart-8b0157fa-99b7-4d67-b144-eae600ea82d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212981589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.3212981589
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2228642816
Short name T781
Test name
Test status
Simulation time 2477968378 ps
CPU time 2.58 seconds
Started Jun 07 08:31:08 PM PDT 24
Finished Jun 07 08:31:25 PM PDT 24
Peak memory 202016 kb
Host smart-f905e34b-0d50-4775-b623-8593f8ed4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228642816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.2228642816
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3874837718
Short name T139
Test name
Test status
Simulation time 2271940281 ps
CPU time 2.16 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:10 PM PDT 24
Peak memory 202064 kb
Host smart-8a373d01-2c18-4ecd-b6a8-ad3ad7433796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874837718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3874837718
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2595231159
Short name T384
Test name
Test status
Simulation time 2511420393 ps
CPU time 7.51 seconds
Started Jun 07 08:31:34 PM PDT 24
Finished Jun 07 08:31:53 PM PDT 24
Peak memory 201988 kb
Host smart-c5eb2d92-026d-45a6-aeb4-dcf5891d89f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595231159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2595231159
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.904844870
Short name T617
Test name
Test status
Simulation time 2128918354 ps
CPU time 2.02 seconds
Started Jun 07 08:31:29 PM PDT 24
Finished Jun 07 08:31:41 PM PDT 24
Peak memory 201848 kb
Host smart-11561e15-2cd2-4a8b-b91e-379188241858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904844870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.904844870
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.3301002845
Short name T361
Test name
Test status
Simulation time 159767417924 ps
CPU time 215.49 seconds
Started Jun 07 08:31:23 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 202300 kb
Host smart-18df50f6-a5a5-4601-900a-439044447cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301002845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.3301002845
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1348422164
Short name T792
Test name
Test status
Simulation time 5470061645 ps
CPU time 6.83 seconds
Started Jun 07 08:31:14 PM PDT 24
Finished Jun 07 08:31:33 PM PDT 24
Peak memory 201976 kb
Host smart-5c971709-ac7a-4cbd-bd8b-f8431acee615
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348422164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.1348422164
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1226881977
Short name T653
Test name
Test status
Simulation time 2043650560 ps
CPU time 1.98 seconds
Started Jun 07 08:29:41 PM PDT 24
Finished Jun 07 08:29:52 PM PDT 24
Peak memory 202036 kb
Host smart-b45c7e2e-d783-4459-8881-c91851c2afc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226881977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1226881977
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1299847761
Short name T547
Test name
Test status
Simulation time 146345472979 ps
CPU time 93.84 seconds
Started Jun 07 08:29:36 PM PDT 24
Finished Jun 07 08:31:21 PM PDT 24
Peak memory 202020 kb
Host smart-5efd4292-a27d-44c4-9257-6240b4ae0de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299847761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1299847761
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.1814000579
Short name T106
Test name
Test status
Simulation time 61934447053 ps
CPU time 19.11 seconds
Started Jun 07 08:29:34 PM PDT 24
Finished Jun 07 08:30:05 PM PDT 24
Peak memory 202244 kb
Host smart-33325fdf-0c73-4887-a092-ed56f4215e1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814000579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.1814000579
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2844766341
Short name T529
Test name
Test status
Simulation time 24363009041 ps
CPU time 17.5 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:30:03 PM PDT 24
Peak memory 202336 kb
Host smart-9786dfe6-c886-47ab-8f89-b4fa5ae8d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844766341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.2844766341
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3032695756
Short name T140
Test name
Test status
Simulation time 3915031739 ps
CPU time 11.27 seconds
Started Jun 07 08:29:35 PM PDT 24
Finished Jun 07 08:29:57 PM PDT 24
Peak memory 202032 kb
Host smart-03297a39-d862-437a-b44d-04a22aace1ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032695756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.3032695756
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.4173242163
Short name T672
Test name
Test status
Simulation time 2333769068 ps
CPU time 2.12 seconds
Started Jun 07 08:29:50 PM PDT 24
Finished Jun 07 08:30:01 PM PDT 24
Peak memory 202004 kb
Host smart-90b02112-db92-4da6-94d7-c52f6e2e945f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173242163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.4173242163
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1755169992
Short name T267
Test name
Test status
Simulation time 2613479920 ps
CPU time 7.99 seconds
Started Jun 07 08:29:31 PM PDT 24
Finished Jun 07 08:29:51 PM PDT 24
Peak memory 202008 kb
Host smart-84662ee4-9c1f-4a41-99e4-12f47446b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755169992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1755169992
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2479212238
Short name T54
Test name
Test status
Simulation time 2456512063 ps
CPU time 6.62 seconds
Started Jun 07 08:29:40 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 201956 kb
Host smart-c9b1c345-9274-4057-831f-98157213c1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479212238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.2479212238
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1810821858
Short name T500
Test name
Test status
Simulation time 2263196378 ps
CPU time 2.16 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:29:46 PM PDT 24
Peak memory 201952 kb
Host smart-7cb00a16-de23-4b50-ae38-7efa10e29de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810821858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.1810821858
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2737564505
Short name T65
Test name
Test status
Simulation time 2516364315 ps
CPU time 3.92 seconds
Started Jun 07 08:29:31 PM PDT 24
Finished Jun 07 08:29:47 PM PDT 24
Peak memory 201932 kb
Host smart-13575334-31ae-464f-b83f-a217bd1f3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737564505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2737564505
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.3799306774
Short name T448
Test name
Test status
Simulation time 2121155831 ps
CPU time 2.67 seconds
Started Jun 07 08:29:32 PM PDT 24
Finished Jun 07 08:29:46 PM PDT 24
Peak memory 201972 kb
Host smart-1e468bd9-814d-4e1a-bb34-5ea691734e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799306774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.3799306774
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.2561967674
Short name T170
Test name
Test status
Simulation time 80238719262 ps
CPU time 12.19 seconds
Started Jun 07 08:29:43 PM PDT 24
Finished Jun 07 08:30:04 PM PDT 24
Peak memory 202052 kb
Host smart-42094735-b327-44a4-8bd6-9a8e98671202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561967674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.2561967674
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2523252225
Short name T198
Test name
Test status
Simulation time 13174887061 ps
CPU time 29.58 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:30:14 PM PDT 24
Peak memory 202096 kb
Host smart-f8ca78bd-b902-46e5-8c90-3427d3238ef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523252225 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.2523252225
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1232162717
Short name T559
Test name
Test status
Simulation time 12767847105 ps
CPU time 6.19 seconds
Started Jun 07 08:29:35 PM PDT 24
Finished Jun 07 08:29:52 PM PDT 24
Peak memory 202048 kb
Host smart-e0c3c601-c743-4e47-b063-340b2b803910
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232162717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.1232162717
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3680410054
Short name T171
Test name
Test status
Simulation time 91239502785 ps
CPU time 237.67 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:35:07 PM PDT 24
Peak memory 202200 kb
Host smart-089d2fa9-d25a-4037-91e3-48e58bf045dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680410054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.3680410054
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2198631824
Short name T348
Test name
Test status
Simulation time 68186807411 ps
CPU time 105.97 seconds
Started Jun 07 08:31:03 PM PDT 24
Finished Jun 07 08:33:03 PM PDT 24
Peak memory 202344 kb
Host smart-b18d6e45-4ec8-4498-819a-e294c7192fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198631824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.2198631824
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2035241354
Short name T237
Test name
Test status
Simulation time 26328794729 ps
CPU time 70.49 seconds
Started Jun 07 08:30:59 PM PDT 24
Finished Jun 07 08:32:22 PM PDT 24
Peak memory 202280 kb
Host smart-a69f5660-896b-4c58-8ec7-600234280227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035241354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.2035241354
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1178902175
Short name T619
Test name
Test status
Simulation time 20350251724 ps
CPU time 13.99 seconds
Started Jun 07 08:31:04 PM PDT 24
Finished Jun 07 08:31:32 PM PDT 24
Peak memory 202292 kb
Host smart-ae1479ea-cfa5-4373-a1bd-ef38e4bb0a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178902175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.1178902175
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1725445088
Short name T255
Test name
Test status
Simulation time 107639278729 ps
CPU time 89.37 seconds
Started Jun 07 08:31:30 PM PDT 24
Finished Jun 07 08:33:09 PM PDT 24
Peak memory 202280 kb
Host smart-9ccbfd5a-22c3-4381-a858-e8bb5058872f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725445088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.1725445088
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1276270072
Short name T779
Test name
Test status
Simulation time 98132060061 ps
CPU time 254.21 seconds
Started Jun 07 08:31:12 PM PDT 24
Finished Jun 07 08:35:39 PM PDT 24
Peak memory 202280 kb
Host smart-9e3e5e4c-cc9b-4f80-a1e4-987e20fe81c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276270072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.1276270072
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4138704211
Short name T69
Test name
Test status
Simulation time 26609049692 ps
CPU time 18.04 seconds
Started Jun 07 08:31:30 PM PDT 24
Finished Jun 07 08:31:58 PM PDT 24
Peak memory 202240 kb
Host smart-e65e6b3e-bec3-4d81-a365-d2de86b58d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138704211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.4138704211
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2103672617
Short name T346
Test name
Test status
Simulation time 126308896602 ps
CPU time 28.05 seconds
Started Jun 07 08:31:25 PM PDT 24
Finished Jun 07 08:32:02 PM PDT 24
Peak memory 202276 kb
Host smart-52eee1e2-9037-4970-aaeb-1b9aad514ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103672617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.2103672617
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.2206430477
Short name T112
Test name
Test status
Simulation time 2036132508 ps
CPU time 2.07 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:29:53 PM PDT 24
Peak memory 201956 kb
Host smart-bf7d37dc-1f88-4fe0-8656-9051acb2b60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206430477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.2206430477
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2744929332
Short name T611
Test name
Test status
Simulation time 3321560399 ps
CPU time 9.72 seconds
Started Jun 07 08:29:34 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 202068 kb
Host smart-0d0c5d2c-f256-4bae-9cf4-57a0f0d79a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744929332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.2744929332
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.3956278822
Short name T249
Test name
Test status
Simulation time 112432935290 ps
CPU time 146.39 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:32:08 PM PDT 24
Peak memory 202264 kb
Host smart-f118f3ab-bd2d-44f7-9d84-0a0637af2da6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956278822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.3956278822
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1680489537
Short name T349
Test name
Test status
Simulation time 95231913015 ps
CPU time 127.84 seconds
Started Jun 07 08:29:44 PM PDT 24
Finished Jun 07 08:32:01 PM PDT 24
Peak memory 202232 kb
Host smart-8efc47ad-06a2-48f2-a615-4e985a951476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680489537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.1680489537
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3841291413
Short name T758
Test name
Test status
Simulation time 3097307882 ps
CPU time 4.35 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:29:50 PM PDT 24
Peak memory 201808 kb
Host smart-b9a29c14-cfc2-4003-89bf-16d826a0636c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841291413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.3841291413
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.4141465705
Short name T143
Test name
Test status
Simulation time 4960338286 ps
CPU time 4.72 seconds
Started Jun 07 08:29:41 PM PDT 24
Finished Jun 07 08:29:55 PM PDT 24
Peak memory 201944 kb
Host smart-8c9d308a-a027-48ba-bf16-36b66ab600c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141465705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.4141465705
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1412853574
Short name T138
Test name
Test status
Simulation time 2614317780 ps
CPU time 7.72 seconds
Started Jun 07 08:29:43 PM PDT 24
Finished Jun 07 08:29:59 PM PDT 24
Peak memory 201892 kb
Host smart-88578237-a763-498f-9848-a45a021e70d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412853574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1412853574
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3792952425
Short name T459
Test name
Test status
Simulation time 2516227598 ps
CPU time 1.56 seconds
Started Jun 07 08:29:32 PM PDT 24
Finished Jun 07 08:29:46 PM PDT 24
Peak memory 202076 kb
Host smart-dac7605b-6866-4959-a26c-409f37d964b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792952425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.3792952425
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.45016733
Short name T422
Test name
Test status
Simulation time 2162932437 ps
CPU time 3.4 seconds
Started Jun 07 08:29:46 PM PDT 24
Finished Jun 07 08:29:58 PM PDT 24
Peak memory 201964 kb
Host smart-c0fb1766-7e30-470d-bb31-f7a966bf0272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45016733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.45016733
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1465612600
Short name T517
Test name
Test status
Simulation time 2533440626 ps
CPU time 2.58 seconds
Started Jun 07 08:29:29 PM PDT 24
Finished Jun 07 08:29:44 PM PDT 24
Peak memory 202036 kb
Host smart-f89f79d9-298d-43eb-9c50-bc4e937c92ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465612600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.1465612600
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.142997443
Short name T157
Test name
Test status
Simulation time 2115216630 ps
CPU time 4.03 seconds
Started Jun 07 08:29:36 PM PDT 24
Finished Jun 07 08:29:51 PM PDT 24
Peak memory 201912 kb
Host smart-92a6d1cf-d625-437a-b54c-d90be30e76c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142997443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.142997443
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.560541461
Short name T730
Test name
Test status
Simulation time 897408637072 ps
CPU time 251.61 seconds
Started Jun 07 08:29:47 PM PDT 24
Finished Jun 07 08:34:07 PM PDT 24
Peak memory 202020 kb
Host smart-c33fe020-b02b-4090-abdc-2591dd284c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560541461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_str
ess_all.560541461
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.971337939
Short name T2
Test name
Test status
Simulation time 639414794713 ps
CPU time 166.97 seconds
Started Jun 07 08:29:33 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 202296 kb
Host smart-819a2184-0500-4846-bbb9-3336c0758e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971337939 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.971337939
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1032804493
Short name T427
Test name
Test status
Simulation time 4864811603 ps
CPU time 7.14 seconds
Started Jun 07 08:29:36 PM PDT 24
Finished Jun 07 08:29:54 PM PDT 24
Peak memory 202040 kb
Host smart-8838e139-24f7-4c82-b83c-208aac59c4ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032804493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1032804493
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1511981987
Short name T344
Test name
Test status
Simulation time 75880959644 ps
CPU time 163.11 seconds
Started Jun 07 08:30:57 PM PDT 24
Finished Jun 07 08:33:54 PM PDT 24
Peak memory 202260 kb
Host smart-e1b57498-8a1a-4f63-868c-6a1bb62613aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511981987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.1511981987
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4139508390
Short name T720
Test name
Test status
Simulation time 24101481515 ps
CPU time 17.94 seconds
Started Jun 07 08:31:10 PM PDT 24
Finished Jun 07 08:31:42 PM PDT 24
Peak memory 202292 kb
Host smart-b9f0b80f-6ca5-4dac-9e0c-5234a85c5eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139508390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.4139508390
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4161962541
Short name T660
Test name
Test status
Simulation time 49431654578 ps
CPU time 130.87 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:34:31 PM PDT 24
Peak memory 200516 kb
Host smart-3402da24-1a83-4e58-b5f4-0765662240a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161962541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.4161962541
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2133955411
Short name T351
Test name
Test status
Simulation time 86191499837 ps
CPU time 59.33 seconds
Started Jun 07 08:31:09 PM PDT 24
Finished Jun 07 08:32:22 PM PDT 24
Peak memory 202304 kb
Host smart-842465fa-920a-449d-b0be-c149d0ed6b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133955411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.2133955411
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.1792375905
Short name T509
Test name
Test status
Simulation time 2026898538 ps
CPU time 1.96 seconds
Started Jun 07 08:29:45 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 202072 kb
Host smart-0595ff6a-ada6-43dd-b9a6-5e96eac82538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792375905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.1792375905
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.229319631
Short name T603
Test name
Test status
Simulation time 3666633447 ps
CPU time 10.66 seconds
Started Jun 07 08:29:45 PM PDT 24
Finished Jun 07 08:30:05 PM PDT 24
Peak memory 202060 kb
Host smart-1419a565-fe88-469c-94e6-a3a823081211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229319631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.229319631
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.3692324487
Short name T263
Test name
Test status
Simulation time 73775044027 ps
CPU time 47.57 seconds
Started Jun 07 08:29:39 PM PDT 24
Finished Jun 07 08:30:36 PM PDT 24
Peak memory 202196 kb
Host smart-a23c9351-4710-40ea-9abc-a74859275ed3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692324487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.3692324487
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2094877110
Short name T246
Test name
Test status
Simulation time 79210850827 ps
CPU time 195.75 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:33:07 PM PDT 24
Peak memory 202240 kb
Host smart-46436492-0523-489f-99d1-d56f37fe491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094877110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.2094877110
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.102411956
Short name T531
Test name
Test status
Simulation time 4089707295 ps
CPU time 12.43 seconds
Started Jun 07 08:29:44 PM PDT 24
Finished Jun 07 08:30:06 PM PDT 24
Peak memory 202088 kb
Host smart-9dc02539-f080-4732-a918-38b357c9e504
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102411956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ec_pwr_on_rst.102411956
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.3718738908
Short name T204
Test name
Test status
Simulation time 2389207177 ps
CPU time 3.9 seconds
Started Jun 07 08:29:44 PM PDT 24
Finished Jun 07 08:29:57 PM PDT 24
Peak memory 201968 kb
Host smart-528421c4-e5ec-41e6-bdee-ce72f711efca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718738908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.3718738908
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.319293802
Short name T495
Test name
Test status
Simulation time 2615256744 ps
CPU time 3.57 seconds
Started Jun 07 08:29:43 PM PDT 24
Finished Jun 07 08:29:55 PM PDT 24
Peak memory 201976 kb
Host smart-200569d1-ba34-4b72-81d5-c6506517c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319293802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.319293802
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3758641066
Short name T532
Test name
Test status
Simulation time 2463982088 ps
CPU time 2.5 seconds
Started Jun 07 08:29:47 PM PDT 24
Finished Jun 07 08:29:58 PM PDT 24
Peak memory 202012 kb
Host smart-4d489969-0c5c-48a6-8247-e61070146754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758641066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3758641066
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2906955211
Short name T709
Test name
Test status
Simulation time 2228818765 ps
CPU time 3.47 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:29:55 PM PDT 24
Peak memory 202088 kb
Host smart-9c7b1e9c-8bee-4bbb-916b-5ffe4d672ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906955211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.2906955211
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1663831397
Short name T701
Test name
Test status
Simulation time 2511893135 ps
CPU time 7.17 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:29:59 PM PDT 24
Peak memory 201912 kb
Host smart-41e697cb-2376-4ca3-b1ea-db68a5b303f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663831397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.1663831397
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.3845313699
Short name T137
Test name
Test status
Simulation time 2113410884 ps
CPU time 6.28 seconds
Started Jun 07 08:29:45 PM PDT 24
Finished Jun 07 08:30:00 PM PDT 24
Peak memory 201916 kb
Host smart-6b7a185a-06a4-4eba-b3d5-2c946b1c7b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845313699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.3845313699
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.1440735668
Short name T380
Test name
Test status
Simulation time 281517322257 ps
CPU time 753.58 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:42:34 PM PDT 24
Peak memory 201984 kb
Host smart-e64e1cf6-cd79-4f0a-9f75-5a81541e3971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440735668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.1440735668
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1866465569
Short name T124
Test name
Test status
Simulation time 135468766427 ps
CPU time 88.81 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:31:32 PM PDT 24
Peak memory 218740 kb
Host smart-92197aca-153a-4bdc-9d50-50b40e91acea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866465569 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1866465569
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4266419611
Short name T113
Test name
Test status
Simulation time 2107226220760 ps
CPU time 149.83 seconds
Started Jun 07 08:29:46 PM PDT 24
Finished Jun 07 08:32:24 PM PDT 24
Peak memory 202008 kb
Host smart-14807353-306d-4e0f-8d2e-2d0b245fbe6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266419611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.4266419611
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.965904558
Short name T355
Test name
Test status
Simulation time 64322170574 ps
CPU time 85.42 seconds
Started Jun 07 08:31:20 PM PDT 24
Finished Jun 07 08:32:56 PM PDT 24
Peak memory 202316 kb
Host smart-c2d69c1c-45cd-4000-93fa-d4e83c74467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965904558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_wi
th_pre_cond.965904558
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.502274174
Short name T596
Test name
Test status
Simulation time 27329072317 ps
CPU time 69.66 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:33:43 PM PDT 24
Peak memory 201888 kb
Host smart-f70045b8-7fc4-4f45-821a-a91712975fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502274174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_wi
th_pre_cond.502274174
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3407443905
Short name T752
Test name
Test status
Simulation time 92060597027 ps
CPU time 228.82 seconds
Started Jun 07 08:32:23 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 201908 kb
Host smart-ae194558-9e1e-4a3b-84bc-863b51056f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407443905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.3407443905
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1048980979
Short name T254
Test name
Test status
Simulation time 69039666530 ps
CPU time 167.68 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 199980 kb
Host smart-10b479fd-288b-46c9-abdd-6d4643cec545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048980979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.1048980979
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1527634137
Short name T45
Test name
Test status
Simulation time 56351398117 ps
CPU time 37.2 seconds
Started Jun 07 08:32:09 PM PDT 24
Finished Jun 07 08:32:57 PM PDT 24
Peak memory 200052 kb
Host smart-b5e09f67-470c-4b41-beb3-fca3ddb5d1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527634137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.1527634137
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.428962383
Short name T742
Test name
Test status
Simulation time 73112707151 ps
CPU time 191.4 seconds
Started Jun 07 08:31:10 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 202288 kb
Host smart-a75bb4b2-2d19-46dd-ab76-90182103d80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428962383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_wi
th_pre_cond.428962383
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3346484481
Short name T347
Test name
Test status
Simulation time 64718784129 ps
CPU time 43.23 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:31:51 PM PDT 24
Peak memory 202256 kb
Host smart-0338e4a0-a5b5-441b-bce5-3880a67e337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346484481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.3346484481
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2137636148
Short name T247
Test name
Test status
Simulation time 121662914554 ps
CPU time 334.85 seconds
Started Jun 07 08:30:56 PM PDT 24
Finished Jun 07 08:36:43 PM PDT 24
Peak memory 202264 kb
Host smart-7caec05d-c31a-48fb-bcd9-2f5ffdfb22ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137636148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.2137636148
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.2344239662
Short name T487
Test name
Test status
Simulation time 2017708947 ps
CPU time 3.17 seconds
Started Jun 07 08:29:40 PM PDT 24
Finished Jun 07 08:29:52 PM PDT 24
Peak memory 202012 kb
Host smart-7299ad67-f9f7-4669-9df1-0e43a629493c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344239662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.2344239662
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2989553327
Short name T644
Test name
Test status
Simulation time 3360550537 ps
CPU time 9.69 seconds
Started Jun 07 08:29:53 PM PDT 24
Finished Jun 07 08:30:12 PM PDT 24
Peak memory 202032 kb
Host smart-80c1fd99-7a63-47bb-a5d4-2c41ccc41cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989553327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2989553327
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.344595881
Short name T32
Test name
Test status
Simulation time 80890704816 ps
CPU time 54.37 seconds
Started Jun 07 08:29:46 PM PDT 24
Finished Jun 07 08:30:49 PM PDT 24
Peak memory 202204 kb
Host smart-a44c9012-e30a-430b-8cbe-5bc7988aa827
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344595881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_combo_detect.344595881
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2105084682
Short name T455
Test name
Test status
Simulation time 4182277759 ps
CPU time 5.99 seconds
Started Jun 07 08:29:43 PM PDT 24
Finished Jun 07 08:29:58 PM PDT 24
Peak memory 202008 kb
Host smart-1c8a1f7f-2cb5-4e1c-a2ed-7070238880bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105084682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.2105084682
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2866378121
Short name T147
Test name
Test status
Simulation time 3232755152 ps
CPU time 2.16 seconds
Started Jun 07 08:29:40 PM PDT 24
Finished Jun 07 08:29:52 PM PDT 24
Peak memory 201976 kb
Host smart-e0620ad3-91e7-4949-b95e-eec8bf563cd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866378121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2866378121
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3522164416
Short name T519
Test name
Test status
Simulation time 2621622172 ps
CPU time 4.05 seconds
Started Jun 07 08:29:46 PM PDT 24
Finished Jun 07 08:29:59 PM PDT 24
Peak memory 202072 kb
Host smart-08f38613-1ce2-4207-8371-049ec84570fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522164416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3522164416
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.4101747188
Short name T241
Test name
Test status
Simulation time 2468198936 ps
CPU time 7.28 seconds
Started Jun 07 08:29:43 PM PDT 24
Finished Jun 07 08:29:59 PM PDT 24
Peak memory 201968 kb
Host smart-97358a02-a4b0-466b-b24d-5e1493eee9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101747188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.4101747188
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3030739247
Short name T663
Test name
Test status
Simulation time 2162989991 ps
CPU time 6.39 seconds
Started Jun 07 08:29:44 PM PDT 24
Finished Jun 07 08:29:59 PM PDT 24
Peak memory 201976 kb
Host smart-88e49d2f-4f64-4e57-adba-d39bd348e60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030739247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3030739247
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3411632898
Short name T773
Test name
Test status
Simulation time 2525449150 ps
CPU time 2.38 seconds
Started Jun 07 08:29:45 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 202068 kb
Host smart-878fdbad-7cc0-4ebe-860b-91b9d073052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411632898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3411632898
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.468814151
Short name T578
Test name
Test status
Simulation time 2140824392 ps
CPU time 1.72 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:30:02 PM PDT 24
Peak memory 201848 kb
Host smart-92593f7c-3be7-409f-bbd6-a1a51c2252ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468814151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.468814151
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4128073591
Short name T60
Test name
Test status
Simulation time 6744270334 ps
CPU time 4.84 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 202032 kb
Host smart-00d7f44e-c0cb-483d-813f-d3c697bae269
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128073591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.4128073591
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2967255532
Short name T515
Test name
Test status
Simulation time 26829756318 ps
CPU time 75.51 seconds
Started Jun 07 08:31:12 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 202292 kb
Host smart-645549a2-01b8-40e5-b6c7-4e7ce1a77dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967255532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.2967255532
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3288719718
Short name T85
Test name
Test status
Simulation time 75236372493 ps
CPU time 194.82 seconds
Started Jun 07 08:31:30 PM PDT 24
Finished Jun 07 08:34:55 PM PDT 24
Peak memory 202208 kb
Host smart-12df153d-9864-4536-8a2b-311cc117bd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288719718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.3288719718
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1973871966
Short name T86
Test name
Test status
Simulation time 41697178733 ps
CPU time 28.62 seconds
Started Jun 07 08:31:23 PM PDT 24
Finished Jun 07 08:32:01 PM PDT 24
Peak memory 202184 kb
Host smart-6661fed8-cbd2-4b53-8693-fbaea8f73ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973871966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1973871966
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1442762164
Short name T238
Test name
Test status
Simulation time 21339509743 ps
CPU time 30.63 seconds
Started Jun 07 08:31:05 PM PDT 24
Finished Jun 07 08:31:49 PM PDT 24
Peak memory 202212 kb
Host smart-3f87d3d6-6709-4f29-a247-38cff7072785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442762164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.1442762164
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2410002798
Short name T646
Test name
Test status
Simulation time 23834935076 ps
CPU time 30.75 seconds
Started Jun 07 08:31:05 PM PDT 24
Finished Jun 07 08:31:50 PM PDT 24
Peak memory 202248 kb
Host smart-ad5d422a-5128-48ac-af43-8df042de671e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410002798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.2410002798
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3719418226
Short name T364
Test name
Test status
Simulation time 89495752167 ps
CPU time 61.16 seconds
Started Jun 07 08:31:22 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 202348 kb
Host smart-f824793f-88c6-4e58-82e6-2fd11275335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719418226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.3719418226
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1885966650
Short name T358
Test name
Test status
Simulation time 65030638777 ps
CPU time 41.5 seconds
Started Jun 07 08:31:04 PM PDT 24
Finished Jun 07 08:32:00 PM PDT 24
Peak memory 202204 kb
Host smart-a0b99ef2-1fb7-4c1d-b6d9-0cecc3bb65a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885966650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.1885966650
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3224067654
Short name T46
Test name
Test status
Simulation time 80537795784 ps
CPU time 21.65 seconds
Started Jun 07 08:31:05 PM PDT 24
Finished Jun 07 08:31:40 PM PDT 24
Peak memory 202328 kb
Host smart-9ff99f09-a0f3-47ee-be7c-83ac6dffcf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224067654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.3224067654
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3101971548
Short name T741
Test name
Test status
Simulation time 46477034823 ps
CPU time 125.02 seconds
Started Jun 07 08:31:18 PM PDT 24
Finished Jun 07 08:33:35 PM PDT 24
Peak memory 202172 kb
Host smart-ab37134c-db17-4d20-bb88-3a0eaaa63654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101971548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3101971548
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.3823088915
Short name T551
Test name
Test status
Simulation time 2035033245 ps
CPU time 1.89 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:30:01 PM PDT 24
Peak memory 201992 kb
Host smart-ef73c107-5667-4cad-a0bb-04bcc4e29199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823088915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.3823088915
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.633118942
Short name T13
Test name
Test status
Simulation time 3555429921 ps
CPU time 9.24 seconds
Started Jun 07 08:29:54 PM PDT 24
Finished Jun 07 08:30:12 PM PDT 24
Peak memory 202148 kb
Host smart-d0150162-62e5-4059-a2cc-7039b12d369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633118942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.633118942
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3172560168
Short name T716
Test name
Test status
Simulation time 131672616705 ps
CPU time 355.72 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 202240 kb
Host smart-e41bcba2-bb4f-4ea3-80b6-be4efa54b257
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172560168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3172560168
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.4049553626
Short name T591
Test name
Test status
Simulation time 46892730359 ps
CPU time 65.72 seconds
Started Jun 07 08:29:48 PM PDT 24
Finished Jun 07 08:31:02 PM PDT 24
Peak memory 202184 kb
Host smart-3b39facb-b1a3-4458-af71-4e8b8078437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049553626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.4049553626
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3323281398
Short name T622
Test name
Test status
Simulation time 2838884956 ps
CPU time 2.55 seconds
Started Jun 07 08:29:53 PM PDT 24
Finished Jun 07 08:30:04 PM PDT 24
Peak memory 202028 kb
Host smart-ce4a2fed-0369-4ced-882c-6337e47f595a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323281398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3323281398
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.495103772
Short name T202
Test name
Test status
Simulation time 5031732954 ps
CPU time 2.54 seconds
Started Jun 07 08:29:51 PM PDT 24
Finished Jun 07 08:30:02 PM PDT 24
Peak memory 202016 kb
Host smart-d4f8f433-4ad6-4815-92f9-6e734a7c5352
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495103772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl
_edge_detect.495103772
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.240596936
Short name T638
Test name
Test status
Simulation time 2628839322 ps
CPU time 2.25 seconds
Started Jun 07 08:29:42 PM PDT 24
Finished Jun 07 08:29:54 PM PDT 24
Peak memory 201932 kb
Host smart-3f0de21a-ec66-46a0-9f24-a1790c307a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240596936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.240596936
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3923041545
Short name T751
Test name
Test status
Simulation time 2551364615 ps
CPU time 1.26 seconds
Started Jun 07 08:29:45 PM PDT 24
Finished Jun 07 08:29:55 PM PDT 24
Peak memory 201956 kb
Host smart-d8ee9565-1948-40ee-8466-55fed5702e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923041545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3923041545
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.644335162
Short name T750
Test name
Test status
Simulation time 2149507629 ps
CPU time 2.05 seconds
Started Jun 07 08:29:46 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 201980 kb
Host smart-db049cf8-975c-4571-8ede-291682f97831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644335162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.644335162
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1013281228
Short name T55
Test name
Test status
Simulation time 2520958502 ps
CPU time 4.08 seconds
Started Jun 07 08:29:43 PM PDT 24
Finished Jun 07 08:29:56 PM PDT 24
Peak memory 202004 kb
Host smart-c13bb701-7fc2-4220-833f-07b079527a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013281228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.1013281228
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.3906469818
Short name T15
Test name
Test status
Simulation time 2107848318 ps
CPU time 6.29 seconds
Started Jun 07 08:29:44 PM PDT 24
Finished Jun 07 08:29:59 PM PDT 24
Peak memory 201868 kb
Host smart-fc7474d1-b859-46fb-b448-2a3167eb19ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906469818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3906469818
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.645954015
Short name T793
Test name
Test status
Simulation time 7358481947 ps
CPU time 10.01 seconds
Started Jun 07 08:29:53 PM PDT 24
Finished Jun 07 08:30:12 PM PDT 24
Peak memory 201964 kb
Host smart-d4d07543-d7d2-43e4-84e5-8e18e7facb71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645954015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_str
ess_all.645954015
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1796971742
Short name T223
Test name
Test status
Simulation time 468307076062 ps
CPU time 60.03 seconds
Started Jun 07 08:29:52 PM PDT 24
Finished Jun 07 08:31:01 PM PDT 24
Peak memory 218756 kb
Host smart-79d2dd91-6a3e-4c42-8bfd-cfc422efa529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796971742 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1796971742
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1019367138
Short name T743
Test name
Test status
Simulation time 3371143403 ps
CPU time 2.23 seconds
Started Jun 07 08:29:56 PM PDT 24
Finished Jun 07 08:30:08 PM PDT 24
Peak memory 202032 kb
Host smart-09770d7b-6a7e-452a-b573-594b05518fd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019367138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.1019367138
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2050700829
Short name T582
Test name
Test status
Simulation time 27112404776 ps
CPU time 18.36 seconds
Started Jun 07 08:31:05 PM PDT 24
Finished Jun 07 08:31:38 PM PDT 24
Peak memory 202276 kb
Host smart-e7fa41cb-eefb-4859-972e-7dee9f190d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050700829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.2050700829
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.470103714
Short name T593
Test name
Test status
Simulation time 39504047909 ps
CPU time 106.58 seconds
Started Jun 07 08:31:10 PM PDT 24
Finished Jun 07 08:33:10 PM PDT 24
Peak memory 202332 kb
Host smart-0eec4c89-81f3-4e01-814b-bbeea3cc0f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470103714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_wi
th_pre_cond.470103714
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.995821194
Short name T354
Test name
Test status
Simulation time 106617938123 ps
CPU time 72.62 seconds
Started Jun 07 08:31:04 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 202328 kb
Host smart-2a90cf10-0cda-4929-b869-2460ec5b0311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995821194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_wi
th_pre_cond.995821194
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.315729113
Short name T259
Test name
Test status
Simulation time 42987805706 ps
CPU time 35.96 seconds
Started Jun 07 08:31:18 PM PDT 24
Finished Jun 07 08:32:06 PM PDT 24
Peak memory 202336 kb
Host smart-cc89f0d5-97a8-498e-b58b-9112feb15a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315729113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_wi
th_pre_cond.315729113
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.779800237
Short name T356
Test name
Test status
Simulation time 63818267146 ps
CPU time 40.04 seconds
Started Jun 07 08:31:04 PM PDT 24
Finished Jun 07 08:31:58 PM PDT 24
Peak memory 202324 kb
Host smart-e9aa899b-4bec-42ca-8be5-361165d83561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779800237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_wi
th_pre_cond.779800237
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3637909394
Short name T245
Test name
Test status
Simulation time 36101130637 ps
CPU time 89.07 seconds
Started Jun 07 08:31:08 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 202236 kb
Host smart-a7db5653-0a8c-4dc0-83c3-70b3e3f49388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637909394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.3637909394
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3633619951
Short name T81
Test name
Test status
Simulation time 42080088082 ps
CPU time 115.36 seconds
Started Jun 07 08:31:15 PM PDT 24
Finished Jun 07 08:33:23 PM PDT 24
Peak memory 202284 kb
Host smart-0b2dc8a9-e9fd-45e5-8ab9-a284ff0ef4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633619951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.3633619951
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.4172191753
Short name T790
Test name
Test status
Simulation time 28339487420 ps
CPU time 36.79 seconds
Started Jun 07 08:31:07 PM PDT 24
Finished Jun 07 08:31:57 PM PDT 24
Peak memory 202296 kb
Host smart-a6620ad0-1a79-4423-927d-433da751dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172191753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.4172191753
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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