Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T23 |
10 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
815 |
1 |
|
|
T23 |
10 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
873 |
1 |
|
|
T23 |
14 |
|
T24 |
8 |
|
T25 |
15 |
| auto[1] |
787 |
1 |
|
|
T23 |
6 |
|
T24 |
12 |
|
T25 |
5 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T25 |
9 |
| auto[1] |
831 |
1 |
|
|
T23 |
10 |
|
T24 |
13 |
|
T25 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T23 |
10 |
|
T24 |
13 |
|
T25 |
13 |
| auto[1] |
812 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T25 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
852 |
1 |
|
|
T23 |
10 |
|
T24 |
10 |
|
T25 |
12 |
| auto[1] |
808 |
1 |
|
|
T23 |
10 |
|
T24 |
10 |
|
T25 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T23 |
10 |
|
T24 |
13 |
|
T25 |
7 |
| auto[1] |
828 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T25 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
857 |
1 |
|
|
T23 |
15 |
|
T24 |
11 |
|
T25 |
8 |
| auto[1] |
803 |
1 |
|
|
T23 |
5 |
|
T24 |
9 |
|
T25 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
870 |
1 |
|
|
T23 |
14 |
|
T24 |
11 |
|
T25 |
9 |
| auto[1] |
790 |
1 |
|
|
T23 |
6 |
|
T24 |
9 |
|
T25 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T25 |
8 |
| auto[1] |
811 |
1 |
|
|
T23 |
10 |
|
T24 |
13 |
|
T25 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T23 |
14 |
|
T24 |
10 |
|
T25 |
12 |
| auto[1] |
773 |
1 |
|
|
T23 |
6 |
|
T24 |
10 |
|
T25 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
828 |
1 |
|
|
T23 |
9 |
|
T24 |
9 |
|
T25 |
12 |
| auto[1] |
832 |
1 |
|
|
T23 |
11 |
|
T24 |
11 |
|
T25 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T23 |
9 |
|
T24 |
9 |
|
T25 |
11 |
| auto[1] |
846 |
1 |
|
|
T23 |
11 |
|
T24 |
11 |
|
T25 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T23 |
11 |
|
T24 |
9 |
|
T25 |
6 |
| auto[1] |
802 |
1 |
|
|
T23 |
9 |
|
T24 |
11 |
|
T25 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
873 |
1 |
|
|
T23 |
14 |
|
T24 |
8 |
|
T25 |
15 |
| auto[1] |
787 |
1 |
|
|
T23 |
6 |
|
T24 |
12 |
|
T25 |
5 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T23 |
7 |
|
T24 |
9 |
|
T25 |
11 |
| auto[1] |
846 |
1 |
|
|
T23 |
13 |
|
T24 |
11 |
|
T25 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T23 |
9 |
|
T24 |
11 |
|
T25 |
9 |
| auto[1] |
837 |
1 |
|
|
T23 |
11 |
|
T24 |
9 |
|
T25 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T23 |
9 |
|
T24 |
10 |
|
T25 |
9 |
| auto[1] |
807 |
1 |
|
|
T23 |
11 |
|
T24 |
10 |
|
T25 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T23 |
7 |
|
T24 |
9 |
|
T25 |
8 |
| auto[1] |
859 |
1 |
|
|
T23 |
13 |
|
T24 |
11 |
|
T25 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T23 |
11 |
|
T24 |
11 |
|
T25 |
10 |
| auto[1] |
830 |
1 |
|
|
T23 |
9 |
|
T24 |
9 |
|
T25 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
859 |
1 |
|
|
T23 |
14 |
|
T24 |
13 |
|
T25 |
11 |
| auto[1] |
801 |
1 |
|
|
T23 |
6 |
|
T24 |
7 |
|
T25 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
852 |
1 |
|
|
T23 |
11 |
|
T24 |
7 |
|
T25 |
10 |
| auto[1] |
808 |
1 |
|
|
T23 |
9 |
|
T24 |
13 |
|
T25 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T23 |
11 |
|
T24 |
9 |
|
T25 |
11 |
| auto[1] |
839 |
1 |
|
|
T23 |
9 |
|
T24 |
11 |
|
T25 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T23 |
8 |
|
T24 |
8 |
|
T25 |
13 |
| auto[1] |
826 |
1 |
|
|
T23 |
12 |
|
T24 |
12 |
|
T25 |
7 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T23 |
9 |
|
T24 |
9 |
|
T25 |
11 |
| auto[1] |
846 |
1 |
|
|
T23 |
11 |
|
T24 |
11 |
|
T25 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
412 |
1 |
|
|
T23 |
4 |
|
T24 |
3 |
|
T25 |
5 |
| auto[0] |
auto[1] |
402 |
1 |
|
|
T23 |
3 |
|
T24 |
6 |
|
T25 |
6 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T23 |
6 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T23 |
7 |
|
T24 |
7 |
|
T25 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T23 |
5 |
|
T24 |
7 |
|
T25 |
6 |
| auto[0] |
auto[1] |
397 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T25 |
3 |
| auto[1] |
auto[0] |
422 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
7 |
| auto[1] |
auto[1] |
415 |
1 |
|
|
T23 |
6 |
|
T24 |
3 |
|
T25 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T23 |
3 |
|
T24 |
4 |
|
T25 |
4 |
| auto[0] |
auto[1] |
426 |
1 |
|
|
T23 |
6 |
|
T24 |
6 |
|
T25 |
5 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T23 |
7 |
|
T24 |
6 |
|
T25 |
8 |
| auto[1] |
auto[1] |
382 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T25 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
391 |
1 |
|
|
T23 |
2 |
|
T24 |
5 |
|
T25 |
1 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
7 |
| auto[1] |
auto[0] |
441 |
1 |
|
|
T23 |
8 |
|
T24 |
8 |
|
T25 |
6 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T23 |
5 |
|
T24 |
3 |
|
T25 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
420 |
1 |
|
|
T23 |
9 |
|
T24 |
6 |
|
T25 |
4 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T23 |
2 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
auto[1] |
393 |
1 |
|
|
T23 |
3 |
|
T24 |
4 |
|
T25 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T23 |
10 |
|
T24 |
7 |
|
T25 |
5 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T23 |
4 |
|
T24 |
6 |
|
T25 |
6 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
372 |
1 |
|
|
T23 |
2 |
|
T24 |
3 |
|
T25 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
449 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
5 |
| auto[0] |
auto[1] |
372 |
1 |
|
|
T23 |
4 |
|
T24 |
4 |
|
T25 |
6 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
7 |
| auto[1] |
auto[1] |
401 |
1 |
|
|
T23 |
2 |
|
T24 |
6 |
|
T25 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T23 |
3 |
|
T24 |
4 |
|
T25 |
6 |
| auto[0] |
auto[1] |
408 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
7 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[1] |
424 |
1 |
|
|
T23 |
6 |
|
T24 |
7 |
|
T25 |
1 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T23 |
5 |
|
T24 |
4 |
|
T25 |
5 |
| auto[0] |
auto[1] |
427 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T25 |
1 |
| auto[1] |
auto[0] |
414 |
1 |
|
|
T23 |
5 |
|
T24 |
6 |
|
T25 |
6 |
| auto[1] |
auto[1] |
388 |
1 |
|
|
T23 |
4 |
|
T24 |
5 |
|
T25 |
8 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
873 |
1 |
|
|
T23 |
14 |
|
T24 |
8 |
|
T25 |
15 |
| auto[1] |
auto[1] |
787 |
1 |
|
|
T23 |
6 |
|
T24 |
12 |
|
T25 |
5 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
428 |
1 |
|
|
T23 |
4 |
|
T24 |
2 |
|
T25 |
4 |
| auto[0] |
auto[1] |
424 |
1 |
|
|
T23 |
7 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[0] |
421 |
1 |
|
|
T23 |
6 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
auto[1] |
387 |
1 |
|
|
T23 |
3 |
|
T24 |
8 |
|
T25 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
814 |
1 |
|
|
T23 |
9 |
|
T24 |
9 |
|
T25 |
11 |
| auto[1] |
auto[1] |
846 |
1 |
|
|
T23 |
11 |
|
T24 |
11 |
|
T25 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T34 |
7 |
|
T143 |
10 |
|
T82 |
9 |
| auto[1] |
112 |
1 |
|
|
T34 |
13 |
|
T143 |
10 |
|
T82 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T34 |
13 |
|
T143 |
10 |
|
T82 |
9 |
| auto[1] |
110 |
1 |
|
|
T34 |
7 |
|
T143 |
10 |
|
T82 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T34 |
9 |
|
T143 |
11 |
|
T82 |
13 |
| auto[1] |
116 |
1 |
|
|
T34 |
11 |
|
T143 |
9 |
|
T82 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T34 |
7 |
|
T143 |
7 |
|
T82 |
3 |
| auto[1] |
126 |
1 |
|
|
T34 |
13 |
|
T143 |
13 |
|
T82 |
17 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
105 |
1 |
|
|
T34 |
10 |
|
T143 |
9 |
|
T82 |
10 |
| auto[1] |
115 |
1 |
|
|
T34 |
10 |
|
T143 |
11 |
|
T82 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T34 |
8 |
|
T143 |
9 |
|
T82 |
7 |
| auto[1] |
109 |
1 |
|
|
T34 |
12 |
|
T143 |
11 |
|
T82 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T34 |
11 |
|
T143 |
10 |
|
T82 |
10 |
| auto[1] |
100 |
1 |
|
|
T34 |
9 |
|
T143 |
10 |
|
T82 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T34 |
8 |
|
T143 |
9 |
|
T82 |
13 |
| auto[1] |
110 |
1 |
|
|
T34 |
12 |
|
T143 |
11 |
|
T82 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T34 |
10 |
|
T143 |
8 |
|
T82 |
10 |
| auto[1] |
107 |
1 |
|
|
T34 |
10 |
|
T143 |
12 |
|
T82 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T34 |
11 |
|
T143 |
8 |
|
T82 |
11 |
| auto[1] |
102 |
1 |
|
|
T34 |
9 |
|
T143 |
12 |
|
T82 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T34 |
7 |
|
T143 |
12 |
|
T82 |
10 |
| auto[1] |
107 |
1 |
|
|
T34 |
13 |
|
T143 |
8 |
|
T82 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T34 |
11 |
|
T143 |
10 |
|
T82 |
8 |
| auto[1] |
107 |
1 |
|
|
T34 |
9 |
|
T143 |
10 |
|
T82 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T34 |
11 |
|
T143 |
5 |
|
T82 |
7 |
| auto[1] |
112 |
1 |
|
|
T34 |
9 |
|
T143 |
15 |
|
T82 |
13 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T34 |
13 |
|
T143 |
10 |
|
T82 |
9 |
| auto[1] |
110 |
1 |
|
|
T34 |
7 |
|
T143 |
10 |
|
T82 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T34 |
7 |
|
T143 |
14 |
|
T82 |
10 |
| auto[1] |
108 |
1 |
|
|
T34 |
13 |
|
T143 |
6 |
|
T82 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T34 |
7 |
|
T143 |
12 |
|
T82 |
14 |
| auto[1] |
108 |
1 |
|
|
T34 |
13 |
|
T143 |
8 |
|
T82 |
6 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T34 |
13 |
|
T143 |
9 |
|
T82 |
7 |
| auto[1] |
112 |
1 |
|
|
T34 |
7 |
|
T143 |
11 |
|
T82 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T34 |
9 |
|
T143 |
11 |
|
T82 |
10 |
| auto[1] |
116 |
1 |
|
|
T34 |
11 |
|
T143 |
9 |
|
T82 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T34 |
10 |
|
T143 |
7 |
|
T82 |
8 |
| auto[1] |
116 |
1 |
|
|
T34 |
10 |
|
T143 |
13 |
|
T82 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T34 |
11 |
|
T143 |
8 |
|
T82 |
9 |
| auto[1] |
108 |
1 |
|
|
T34 |
9 |
|
T143 |
12 |
|
T82 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T34 |
9 |
|
T143 |
11 |
|
T82 |
7 |
| auto[1] |
100 |
1 |
|
|
T34 |
11 |
|
T143 |
9 |
|
T82 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T34 |
9 |
|
T143 |
14 |
|
T82 |
11 |
| auto[1] |
103 |
1 |
|
|
T34 |
11 |
|
T143 |
6 |
|
T82 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
98 |
1 |
|
|
T34 |
13 |
|
T143 |
10 |
|
T82 |
8 |
| auto[1] |
122 |
1 |
|
|
T34 |
7 |
|
T143 |
10 |
|
T82 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T34 |
11 |
|
T143 |
10 |
|
T82 |
8 |
| auto[1] |
107 |
1 |
|
|
T34 |
9 |
|
T143 |
10 |
|
T82 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T34 |
2 |
|
T143 |
8 |
|
T82 |
5 |
| auto[0] |
auto[1] |
61 |
1 |
|
|
T34 |
5 |
|
T143 |
6 |
|
T82 |
5 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T34 |
7 |
|
T143 |
3 |
|
T82 |
8 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T34 |
6 |
|
T143 |
3 |
|
T82 |
2 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T34 |
1 |
|
T143 |
5 |
|
T82 |
2 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T34 |
6 |
|
T143 |
7 |
|
T82 |
12 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T34 |
6 |
|
T143 |
2 |
|
T82 |
1 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T34 |
7 |
|
T143 |
6 |
|
T82 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
49 |
1 |
|
|
T34 |
6 |
|
T143 |
3 |
|
T82 |
5 |
| auto[0] |
auto[1] |
59 |
1 |
|
|
T34 |
7 |
|
T143 |
6 |
|
T82 |
2 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T34 |
4 |
|
T143 |
6 |
|
T82 |
5 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T34 |
3 |
|
T143 |
5 |
|
T82 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
50 |
1 |
|
|
T34 |
3 |
|
T143 |
4 |
|
T82 |
5 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T34 |
6 |
|
T143 |
7 |
|
T82 |
5 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T34 |
5 |
|
T143 |
5 |
|
T82 |
2 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T34 |
6 |
|
T143 |
4 |
|
T82 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T34 |
7 |
|
T143 |
5 |
|
T82 |
3 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T34 |
3 |
|
T143 |
2 |
|
T82 |
5 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T34 |
4 |
|
T143 |
5 |
|
T82 |
7 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T34 |
6 |
|
T143 |
8 |
|
T82 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T34 |
6 |
|
T143 |
5 |
|
T82 |
5 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T34 |
5 |
|
T143 |
3 |
|
T82 |
4 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T34 |
2 |
|
T143 |
4 |
|
T82 |
8 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T34 |
7 |
|
T143 |
8 |
|
T82 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T34 |
5 |
|
T143 |
5 |
|
T82 |
6 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T34 |
4 |
|
T143 |
9 |
|
T82 |
5 |
| auto[1] |
auto[0] |
57 |
1 |
|
|
T34 |
6 |
|
T143 |
3 |
|
T82 |
5 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T34 |
5 |
|
T143 |
3 |
|
T82 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
49 |
1 |
|
|
T34 |
5 |
|
T143 |
5 |
|
T82 |
4 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T34 |
8 |
|
T143 |
5 |
|
T82 |
4 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T34 |
2 |
|
T143 |
7 |
|
T82 |
6 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T34 |
5 |
|
T143 |
3 |
|
T82 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T34 |
4 |
|
T143 |
2 |
|
T82 |
4 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T34 |
7 |
|
T143 |
3 |
|
T82 |
3 |
| auto[1] |
auto[0] |
55 |
1 |
|
|
T34 |
3 |
|
T143 |
8 |
|
T82 |
5 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T34 |
6 |
|
T143 |
7 |
|
T82 |
8 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
110 |
1 |
|
|
T34 |
13 |
|
T143 |
10 |
|
T82 |
9 |
| auto[1] |
auto[1] |
110 |
1 |
|
|
T34 |
7 |
|
T143 |
10 |
|
T82 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T34 |
7 |
|
T143 |
4 |
|
T82 |
2 |
| auto[0] |
auto[1] |
53 |
1 |
|
|
T34 |
2 |
|
T143 |
7 |
|
T82 |
5 |
| auto[1] |
auto[0] |
46 |
1 |
|
|
T34 |
3 |
|
T143 |
4 |
|
T82 |
8 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T34 |
8 |
|
T143 |
5 |
|
T82 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
113 |
1 |
|
|
T34 |
11 |
|
T143 |
10 |
|
T82 |
8 |
| auto[1] |
auto[1] |
107 |
1 |
|
|
T34 |
9 |
|
T143 |
10 |
|
T82 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T34 |
11 |
|
T143 |
6 |
|
T230 |
5 |
| auto[1] |
53 |
1 |
|
|
T34 |
9 |
|
T143 |
14 |
|
T230 |
15 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T34 |
12 |
|
T143 |
10 |
|
T230 |
10 |
| auto[1] |
50 |
1 |
|
|
T34 |
8 |
|
T143 |
10 |
|
T230 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T34 |
11 |
|
T143 |
12 |
|
T230 |
11 |
| auto[1] |
49 |
1 |
|
|
T34 |
9 |
|
T143 |
8 |
|
T230 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T34 |
9 |
|
T143 |
13 |
|
T230 |
14 |
| auto[1] |
45 |
1 |
|
|
T34 |
11 |
|
T143 |
7 |
|
T230 |
6 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T34 |
11 |
|
T143 |
7 |
|
T230 |
11 |
| auto[1] |
53 |
1 |
|
|
T34 |
9 |
|
T143 |
13 |
|
T230 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T34 |
9 |
|
T143 |
12 |
|
T230 |
9 |
| auto[1] |
52 |
1 |
|
|
T34 |
11 |
|
T143 |
8 |
|
T230 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
38 |
1 |
|
|
T34 |
9 |
|
T143 |
12 |
|
T230 |
3 |
| auto[1] |
62 |
1 |
|
|
T34 |
11 |
|
T143 |
8 |
|
T230 |
17 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T34 |
8 |
|
T143 |
12 |
|
T230 |
10 |
| auto[1] |
50 |
1 |
|
|
T34 |
12 |
|
T143 |
8 |
|
T230 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T34 |
9 |
|
T143 |
8 |
|
T230 |
13 |
| auto[1] |
44 |
1 |
|
|
T34 |
11 |
|
T143 |
12 |
|
T230 |
7 |