Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
766 |
1 |
|
|
T10 |
8 |
|
T26 |
12 |
|
T27 |
10 |
| auto[1] |
774 |
1 |
|
|
T10 |
12 |
|
T26 |
8 |
|
T27 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
747 |
1 |
|
|
T10 |
9 |
|
T26 |
9 |
|
T27 |
7 |
| auto[1] |
793 |
1 |
|
|
T10 |
11 |
|
T26 |
11 |
|
T27 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
768 |
1 |
|
|
T10 |
11 |
|
T26 |
7 |
|
T27 |
6 |
| auto[1] |
772 |
1 |
|
|
T10 |
9 |
|
T26 |
13 |
|
T27 |
14 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T10 |
11 |
|
T26 |
8 |
|
T27 |
9 |
| auto[1] |
734 |
1 |
|
|
T10 |
9 |
|
T26 |
12 |
|
T27 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
739 |
1 |
|
|
T10 |
10 |
|
T26 |
13 |
|
T27 |
7 |
| auto[1] |
801 |
1 |
|
|
T10 |
10 |
|
T26 |
7 |
|
T27 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
751 |
1 |
|
|
T10 |
10 |
|
T26 |
9 |
|
T27 |
10 |
| auto[1] |
789 |
1 |
|
|
T10 |
10 |
|
T26 |
11 |
|
T27 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
794 |
1 |
|
|
T10 |
10 |
|
T26 |
11 |
|
T27 |
11 |
| auto[1] |
746 |
1 |
|
|
T10 |
10 |
|
T26 |
9 |
|
T27 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
807 |
1 |
|
|
T10 |
10 |
|
T26 |
12 |
|
T27 |
10 |
| auto[1] |
733 |
1 |
|
|
T10 |
10 |
|
T26 |
8 |
|
T27 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
754 |
1 |
|
|
T10 |
12 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
786 |
1 |
|
|
T10 |
8 |
|
T26 |
12 |
|
T27 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
775 |
1 |
|
|
T10 |
9 |
|
T26 |
9 |
|
T27 |
11 |
| auto[1] |
765 |
1 |
|
|
T10 |
11 |
|
T26 |
11 |
|
T27 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T10 |
12 |
|
T26 |
7 |
|
T27 |
12 |
| auto[1] |
768 |
1 |
|
|
T10 |
8 |
|
T26 |
13 |
|
T27 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
778 |
1 |
|
|
T10 |
8 |
|
T26 |
6 |
|
T27 |
15 |
| auto[1] |
762 |
1 |
|
|
T10 |
12 |
|
T26 |
14 |
|
T27 |
5 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
765 |
1 |
|
|
T10 |
8 |
|
T26 |
8 |
|
T27 |
11 |
| auto[1] |
775 |
1 |
|
|
T10 |
12 |
|
T26 |
12 |
|
T27 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
747 |
1 |
|
|
T10 |
9 |
|
T26 |
9 |
|
T27 |
7 |
| auto[1] |
793 |
1 |
|
|
T10 |
11 |
|
T26 |
11 |
|
T27 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
764 |
1 |
|
|
T10 |
11 |
|
T26 |
7 |
|
T27 |
11 |
| auto[1] |
776 |
1 |
|
|
T10 |
9 |
|
T26 |
13 |
|
T27 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
746 |
1 |
|
|
T10 |
11 |
|
T26 |
10 |
|
T27 |
10 |
| auto[1] |
794 |
1 |
|
|
T10 |
9 |
|
T26 |
10 |
|
T27 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T10 |
12 |
|
T26 |
14 |
|
T27 |
12 |
| auto[1] |
745 |
1 |
|
|
T10 |
8 |
|
T26 |
6 |
|
T27 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
743 |
1 |
|
|
T10 |
12 |
|
T26 |
10 |
|
T27 |
5 |
| auto[1] |
797 |
1 |
|
|
T10 |
8 |
|
T26 |
10 |
|
T27 |
15 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
760 |
1 |
|
|
T10 |
8 |
|
T26 |
12 |
|
T27 |
9 |
| auto[1] |
780 |
1 |
|
|
T10 |
12 |
|
T26 |
8 |
|
T27 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
765 |
1 |
|
|
T10 |
6 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
775 |
1 |
|
|
T10 |
14 |
|
T26 |
9 |
|
T27 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
743 |
1 |
|
|
T10 |
9 |
|
T26 |
11 |
|
T27 |
10 |
| auto[1] |
797 |
1 |
|
|
T10 |
11 |
|
T26 |
9 |
|
T27 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T10 |
13 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
709 |
1 |
|
|
T10 |
7 |
|
T26 |
8 |
|
T27 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
788 |
1 |
|
|
T10 |
10 |
|
T26 |
6 |
|
T27 |
11 |
| auto[1] |
752 |
1 |
|
|
T10 |
10 |
|
T26 |
14 |
|
T27 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
778 |
1 |
|
|
T10 |
8 |
|
T26 |
6 |
|
T27 |
15 |
| auto[1] |
762 |
1 |
|
|
T10 |
12 |
|
T26 |
14 |
|
T27 |
5 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
371 |
1 |
|
|
T10 |
7 |
|
T26 |
2 |
|
T27 |
3 |
| auto[0] |
auto[1] |
393 |
1 |
|
|
T10 |
4 |
|
T26 |
5 |
|
T27 |
8 |
| auto[1] |
auto[0] |
397 |
1 |
|
|
T10 |
4 |
|
T26 |
5 |
|
T27 |
3 |
| auto[1] |
auto[1] |
379 |
1 |
|
|
T10 |
5 |
|
T26 |
8 |
|
T27 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
381 |
1 |
|
|
T10 |
7 |
|
T26 |
4 |
|
T27 |
4 |
| auto[0] |
auto[1] |
365 |
1 |
|
|
T10 |
4 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T10 |
4 |
|
T26 |
4 |
|
T27 |
5 |
| auto[1] |
auto[1] |
369 |
1 |
|
|
T10 |
5 |
|
T26 |
6 |
|
T27 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
363 |
1 |
|
|
T10 |
6 |
|
T26 |
9 |
|
T27 |
3 |
| auto[0] |
auto[1] |
432 |
1 |
|
|
T10 |
6 |
|
T26 |
5 |
|
T27 |
9 |
| auto[1] |
auto[0] |
376 |
1 |
|
|
T10 |
4 |
|
T26 |
4 |
|
T27 |
4 |
| auto[1] |
auto[1] |
369 |
1 |
|
|
T10 |
4 |
|
T26 |
2 |
|
T27 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
343 |
1 |
|
|
T10 |
6 |
|
T26 |
5 |
|
T27 |
1 |
| auto[0] |
auto[1] |
400 |
1 |
|
|
T10 |
6 |
|
T26 |
5 |
|
T27 |
4 |
| auto[1] |
auto[0] |
408 |
1 |
|
|
T10 |
4 |
|
T26 |
4 |
|
T27 |
9 |
| auto[1] |
auto[1] |
389 |
1 |
|
|
T10 |
4 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
388 |
1 |
|
|
T10 |
4 |
|
T26 |
6 |
|
T27 |
3 |
| auto[0] |
auto[1] |
372 |
1 |
|
|
T10 |
4 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
auto[0] |
406 |
1 |
|
|
T10 |
6 |
|
T26 |
5 |
|
T27 |
8 |
| auto[1] |
auto[1] |
374 |
1 |
|
|
T10 |
6 |
|
T26 |
3 |
|
T27 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
397 |
1 |
|
|
T10 |
3 |
|
T26 |
6 |
|
T27 |
4 |
| auto[0] |
auto[1] |
368 |
1 |
|
|
T10 |
3 |
|
T26 |
5 |
|
T27 |
8 |
| auto[1] |
auto[0] |
410 |
1 |
|
|
T10 |
7 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
auto[1] |
365 |
1 |
|
|
T10 |
7 |
|
T26 |
3 |
|
T27 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T10 |
6 |
|
T26 |
6 |
|
T27 |
7 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T10 |
7 |
|
T26 |
6 |
|
T27 |
5 |
| auto[1] |
auto[0] |
364 |
1 |
|
|
T10 |
3 |
|
T26 |
3 |
|
T27 |
4 |
| auto[1] |
auto[1] |
345 |
1 |
|
|
T10 |
4 |
|
T26 |
5 |
|
T27 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
388 |
1 |
|
|
T10 |
6 |
|
T26 |
2 |
|
T27 |
7 |
| auto[0] |
auto[1] |
400 |
1 |
|
|
T10 |
4 |
|
T26 |
4 |
|
T27 |
4 |
| auto[1] |
auto[0] |
384 |
1 |
|
|
T10 |
6 |
|
T26 |
5 |
|
T27 |
5 |
| auto[1] |
auto[1] |
368 |
1 |
|
|
T10 |
4 |
|
T26 |
9 |
|
T27 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
367 |
1 |
|
|
T10 |
1 |
|
T26 |
5 |
|
T27 |
5 |
| auto[0] |
auto[1] |
398 |
1 |
|
|
T10 |
7 |
|
T26 |
3 |
|
T27 |
6 |
| auto[1] |
auto[0] |
399 |
1 |
|
|
T10 |
7 |
|
T26 |
7 |
|
T27 |
5 |
| auto[1] |
auto[1] |
376 |
1 |
|
|
T10 |
5 |
|
T26 |
5 |
|
T27 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
747 |
1 |
|
|
T10 |
9 |
|
T26 |
9 |
|
T27 |
7 |
| auto[1] |
auto[1] |
793 |
1 |
|
|
T10 |
11 |
|
T26 |
11 |
|
T27 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
359 |
1 |
|
|
T10 |
4 |
|
T26 |
5 |
|
T27 |
7 |
| auto[0] |
auto[1] |
384 |
1 |
|
|
T10 |
5 |
|
T26 |
6 |
|
T27 |
3 |
| auto[1] |
auto[0] |
395 |
1 |
|
|
T10 |
8 |
|
T26 |
3 |
|
T27 |
5 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T10 |
3 |
|
T26 |
6 |
|
T27 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
778 |
1 |
|
|
T10 |
8 |
|
T26 |
6 |
|
T27 |
15 |
| auto[1] |
auto[1] |
762 |
1 |
|
|
T10 |
12 |
|
T26 |
14 |
|
T27 |
5 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T34 |
13 |
|
T129 |
10 |
|
T112 |
8 |
| auto[1] |
100 |
1 |
|
|
T34 |
7 |
|
T129 |
10 |
|
T112 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
106 |
1 |
|
|
T34 |
13 |
|
T129 |
9 |
|
T112 |
13 |
| auto[1] |
94 |
1 |
|
|
T34 |
7 |
|
T129 |
11 |
|
T112 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
105 |
1 |
|
|
T34 |
8 |
|
T129 |
12 |
|
T112 |
14 |
| auto[1] |
95 |
1 |
|
|
T34 |
12 |
|
T129 |
8 |
|
T112 |
6 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T34 |
10 |
|
T129 |
11 |
|
T112 |
10 |
| auto[1] |
100 |
1 |
|
|
T34 |
10 |
|
T129 |
9 |
|
T112 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T34 |
12 |
|
T129 |
12 |
|
T112 |
15 |
| auto[1] |
85 |
1 |
|
|
T34 |
8 |
|
T129 |
8 |
|
T112 |
5 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T34 |
8 |
|
T129 |
10 |
|
T112 |
10 |
| auto[1] |
99 |
1 |
|
|
T34 |
12 |
|
T129 |
10 |
|
T112 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T34 |
10 |
|
T129 |
11 |
|
T112 |
11 |
| auto[1] |
100 |
1 |
|
|
T34 |
10 |
|
T129 |
9 |
|
T112 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T34 |
9 |
|
T129 |
15 |
|
T112 |
8 |
| auto[1] |
103 |
1 |
|
|
T34 |
11 |
|
T129 |
5 |
|
T112 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
105 |
1 |
|
|
T34 |
12 |
|
T129 |
8 |
|
T112 |
9 |
| auto[1] |
95 |
1 |
|
|
T34 |
8 |
|
T129 |
12 |
|
T112 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T34 |
5 |
|
T129 |
9 |
|
T112 |
11 |
| auto[1] |
100 |
1 |
|
|
T34 |
15 |
|
T129 |
11 |
|
T112 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
105 |
1 |
|
|
T34 |
12 |
|
T129 |
9 |
|
T112 |
11 |
| auto[1] |
95 |
1 |
|
|
T34 |
8 |
|
T129 |
11 |
|
T112 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T34 |
16 |
|
T129 |
14 |
|
T112 |
8 |
| auto[1] |
91 |
1 |
|
|
T34 |
4 |
|
T129 |
6 |
|
T112 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T34 |
9 |
|
T129 |
6 |
|
T112 |
6 |
| auto[1] |
122 |
1 |
|
|
T34 |
11 |
|
T129 |
14 |
|
T112 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
106 |
1 |
|
|
T34 |
13 |
|
T129 |
9 |
|
T112 |
13 |
| auto[1] |
94 |
1 |
|
|
T34 |
7 |
|
T129 |
11 |
|
T112 |
7 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
96 |
1 |
|
|
T34 |
11 |
|
T129 |
10 |
|
T112 |
12 |
| auto[1] |
104 |
1 |
|
|
T34 |
9 |
|
T129 |
10 |
|
T112 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T34 |
5 |
|
T129 |
9 |
|
T112 |
10 |
| auto[1] |
117 |
1 |
|
|
T34 |
15 |
|
T129 |
11 |
|
T112 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
102 |
1 |
|
|
T34 |
10 |
|
T129 |
10 |
|
T112 |
7 |
| auto[1] |
98 |
1 |
|
|
T34 |
10 |
|
T129 |
10 |
|
T112 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T34 |
12 |
|
T129 |
12 |
|
T112 |
8 |
| auto[1] |
108 |
1 |
|
|
T34 |
8 |
|
T129 |
8 |
|
T112 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
102 |
1 |
|
|
T34 |
6 |
|
T129 |
11 |
|
T112 |
14 |
| auto[1] |
98 |
1 |
|
|
T34 |
14 |
|
T129 |
9 |
|
T112 |
6 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
107 |
1 |
|
|
T34 |
11 |
|
T129 |
11 |
|
T112 |
7 |
| auto[1] |
93 |
1 |
|
|
T34 |
9 |
|
T129 |
9 |
|
T112 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
105 |
1 |
|
|
T34 |
13 |
|
T129 |
9 |
|
T112 |
9 |
| auto[1] |
95 |
1 |
|
|
T34 |
7 |
|
T129 |
11 |
|
T112 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
107 |
1 |
|
|
T34 |
7 |
|
T129 |
11 |
|
T112 |
16 |
| auto[1] |
93 |
1 |
|
|
T34 |
13 |
|
T129 |
9 |
|
T112 |
4 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T34 |
8 |
|
T129 |
9 |
|
T112 |
12 |
| auto[1] |
108 |
1 |
|
|
T34 |
12 |
|
T129 |
11 |
|
T112 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T34 |
16 |
|
T129 |
14 |
|
T112 |
8 |
| auto[1] |
91 |
1 |
|
|
T34 |
4 |
|
T129 |
6 |
|
T112 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T34 |
5 |
|
T129 |
3 |
|
T112 |
7 |
| auto[0] |
auto[1] |
45 |
1 |
|
|
T34 |
6 |
|
T129 |
7 |
|
T112 |
5 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T34 |
3 |
|
T129 |
9 |
|
T112 |
7 |
| auto[1] |
auto[1] |
50 |
1 |
|
|
T34 |
6 |
|
T129 |
1 |
|
T112 |
1 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T34 |
3 |
|
T129 |
2 |
|
T112 |
4 |
| auto[0] |
auto[1] |
41 |
1 |
|
|
T34 |
2 |
|
T129 |
7 |
|
T112 |
6 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T34 |
7 |
|
T129 |
9 |
|
T112 |
6 |
| auto[1] |
auto[1] |
59 |
1 |
|
|
T34 |
8 |
|
T129 |
2 |
|
T112 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T34 |
8 |
|
T129 |
7 |
|
T112 |
5 |
| auto[0] |
auto[1] |
51 |
1 |
|
|
T34 |
2 |
|
T129 |
3 |
|
T112 |
2 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T34 |
4 |
|
T129 |
5 |
|
T112 |
10 |
| auto[1] |
auto[1] |
34 |
1 |
|
|
T34 |
6 |
|
T129 |
5 |
|
T112 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T34 |
7 |
|
T129 |
7 |
|
T112 |
3 |
| auto[0] |
auto[1] |
53 |
1 |
|
|
T34 |
5 |
|
T129 |
5 |
|
T112 |
5 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T34 |
1 |
|
T129 |
3 |
|
T112 |
7 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T34 |
7 |
|
T129 |
5 |
|
T112 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
52 |
1 |
|
|
T34 |
3 |
|
T129 |
6 |
|
T112 |
7 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T34 |
3 |
|
T129 |
5 |
|
T112 |
7 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T34 |
7 |
|
T129 |
5 |
|
T112 |
4 |
| auto[1] |
auto[1] |
50 |
1 |
|
|
T34 |
7 |
|
T129 |
4 |
|
T112 |
2 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T34 |
5 |
|
T129 |
8 |
|
T112 |
2 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T34 |
6 |
|
T129 |
3 |
|
T112 |
5 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T34 |
4 |
|
T129 |
7 |
|
T112 |
6 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T34 |
5 |
|
T129 |
2 |
|
T112 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T34 |
1 |
|
T129 |
6 |
|
T112 |
9 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T34 |
6 |
|
T129 |
5 |
|
T112 |
7 |
| auto[1] |
auto[0] |
42 |
1 |
|
|
T34 |
4 |
|
T129 |
3 |
|
T112 |
2 |
| auto[1] |
auto[1] |
51 |
1 |
|
|
T34 |
9 |
|
T129 |
6 |
|
T112 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T34 |
5 |
|
T129 |
5 |
|
T112 |
7 |
| auto[0] |
auto[1] |
39 |
1 |
|
|
T34 |
3 |
|
T129 |
4 |
|
T112 |
5 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T34 |
7 |
|
T129 |
4 |
|
T112 |
4 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T34 |
5 |
|
T129 |
7 |
|
T112 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T34 |
6 |
|
T129 |
2 |
|
T112 |
3 |
| auto[0] |
auto[1] |
36 |
1 |
|
|
T34 |
3 |
|
T129 |
4 |
|
T112 |
3 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T34 |
7 |
|
T129 |
8 |
|
T112 |
5 |
| auto[1] |
auto[1] |
64 |
1 |
|
|
T34 |
4 |
|
T129 |
6 |
|
T112 |
9 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
106 |
1 |
|
|
T34 |
13 |
|
T129 |
9 |
|
T112 |
13 |
| auto[1] |
auto[1] |
94 |
1 |
|
|
T34 |
7 |
|
T129 |
11 |
|
T112 |
7 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T34 |
9 |
|
T129 |
3 |
|
T112 |
3 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T34 |
4 |
|
T129 |
6 |
|
T112 |
6 |
| auto[1] |
auto[0] |
49 |
1 |
|
|
T34 |
3 |
|
T129 |
5 |
|
T112 |
6 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T34 |
4 |
|
T129 |
6 |
|
T112 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
109 |
1 |
|
|
T34 |
16 |
|
T129 |
14 |
|
T112 |
8 |
| auto[1] |
auto[1] |
91 |
1 |
|
|
T34 |
4 |
|
T129 |
6 |
|
T112 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T112 |
7 |
|
T366 |
7 |
|
T158 |
11 |
| auto[1] |
78 |
1 |
|
|
T112 |
13 |
|
T366 |
13 |
|
T158 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T112 |
17 |
|
T366 |
11 |
|
T158 |
11 |
| auto[1] |
59 |
1 |
|
|
T112 |
3 |
|
T366 |
9 |
|
T158 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T112 |
9 |
|
T366 |
10 |
|
T158 |
11 |
| auto[1] |
66 |
1 |
|
|
T112 |
11 |
|
T366 |
10 |
|
T158 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T112 |
7 |
|
T366 |
12 |
|
T158 |
8 |
| auto[1] |
76 |
1 |
|
|
T112 |
13 |
|
T366 |
8 |
|
T158 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
65 |
1 |
|
|
T112 |
11 |
|
T366 |
11 |
|
T158 |
11 |
| auto[1] |
75 |
1 |
|
|
T112 |
9 |
|
T366 |
9 |
|
T158 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T112 |
6 |
|
T366 |
9 |
|
T158 |
14 |
| auto[1] |
74 |
1 |
|
|
T112 |
14 |
|
T366 |
11 |
|
T158 |
6 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T112 |
6 |
|
T366 |
9 |
|
T158 |
10 |
| auto[1] |
74 |
1 |
|
|
T112 |
14 |
|
T366 |
11 |
|
T158 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
63 |
1 |
|
|
T112 |
11 |
|
T366 |
9 |
|
T158 |
13 |
| auto[1] |
77 |
1 |
|
|
T112 |
9 |
|
T366 |
11 |
|
T158 |
7 |