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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.89 99.37 96.48 100.00 98.08 98.82 99.71 92.79


Total test records in report: 917
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T795 /workspace/coverage/default/38.sysrst_ctrl_stress_all.1997410893 Jun 22 04:53:07 PM PDT 24 Jun 22 04:53:23 PM PDT 24 35363138898 ps
T796 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3583833848 Jun 22 04:53:35 PM PDT 24 Jun 22 04:54:40 PM PDT 24 26832129412 ps
T280 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3763177913 Jun 22 04:33:59 PM PDT 24 Jun 22 04:34:04 PM PDT 24 2516876450 ps
T24 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3118020150 Jun 22 04:34:02 PM PDT 24 Jun 22 04:34:06 PM PDT 24 2196304740 ps
T16 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2370852839 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:48 PM PDT 24 4562256374 ps
T25 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3225753782 Jun 22 04:33:39 PM PDT 24 Jun 22 04:33:42 PM PDT 24 2218920446 ps
T307 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2561871477 Jun 22 04:33:57 PM PDT 24 Jun 22 04:34:00 PM PDT 24 2369099354 ps
T17 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3729198648 Jun 22 04:33:36 PM PDT 24 Jun 22 04:34:03 PM PDT 24 9595445682 ps
T797 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1291087907 Jun 22 04:33:46 PM PDT 24 Jun 22 04:33:53 PM PDT 24 2010038333 ps
T281 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2812038836 Jun 22 04:33:47 PM PDT 24 Jun 22 04:33:53 PM PDT 24 2204190338 ps
T282 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.4166967336 Jun 22 04:33:50 PM PDT 24 Jun 22 04:33:56 PM PDT 24 2278302086 ps
T18 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3346586509 Jun 22 04:33:45 PM PDT 24 Jun 22 04:33:53 PM PDT 24 10237368068 ps
T308 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.794347949 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:37 PM PDT 24 2064287950 ps
T798 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1329831457 Jun 22 04:33:40 PM PDT 24 Jun 22 04:33:43 PM PDT 24 2041243323 ps
T285 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.976344562 Jun 22 04:33:50 PM PDT 24 Jun 22 04:34:17 PM PDT 24 42550653746 ps
T289 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.349482532 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:35 PM PDT 24 2120314529 ps
T286 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.678332346 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:47 PM PDT 24 22296998977 ps
T325 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2480664795 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:40 PM PDT 24 2670462314 ps
T320 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.63198865 Jun 22 04:33:35 PM PDT 24 Jun 22 04:33:52 PM PDT 24 4639477098 ps
T321 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.566294890 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:30 PM PDT 24 2060082008 ps
T366 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3667599112 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:28 PM PDT 24 2132926541 ps
T287 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2592631046 Jun 22 04:33:50 PM PDT 24 Jun 22 04:34:14 PM PDT 24 22355206180 ps
T322 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1507088495 Jun 22 04:33:37 PM PDT 24 Jun 22 04:33:44 PM PDT 24 9652817034 ps
T799 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.999507248 Jun 22 04:33:57 PM PDT 24 Jun 22 04:34:04 PM PDT 24 2015138599 ps
T294 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4219779393 Jun 22 04:33:37 PM PDT 24 Jun 22 04:33:45 PM PDT 24 2147508069 ps
T800 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3874818702 Jun 22 04:33:43 PM PDT 24 Jun 22 04:33:50 PM PDT 24 2063566072 ps
T801 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1365434431 Jun 22 04:33:59 PM PDT 24 Jun 22 04:34:05 PM PDT 24 2012436665 ps
T802 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.457941061 Jun 22 04:33:47 PM PDT 24 Jun 22 04:33:54 PM PDT 24 2013391015 ps
T290 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1429383753 Jun 22 04:33:30 PM PDT 24 Jun 22 04:33:38 PM PDT 24 2037347832 ps
T343 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.532282723 Jun 22 04:33:47 PM PDT 24 Jun 22 04:34:41 PM PDT 24 22250708491 ps
T803 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.347669143 Jun 22 04:33:39 PM PDT 24 Jun 22 04:33:43 PM PDT 24 2139179410 ps
T804 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.316657157 Jun 22 04:33:30 PM PDT 24 Jun 22 04:33:36 PM PDT 24 2013803727 ps
T805 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2128230564 Jun 22 04:34:05 PM PDT 24 Jun 22 04:34:09 PM PDT 24 2124152420 ps
T806 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3768853124 Jun 22 04:34:09 PM PDT 24 Jun 22 04:34:15 PM PDT 24 2017106699 ps
T323 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1258664555 Jun 22 04:33:34 PM PDT 24 Jun 22 04:33:36 PM PDT 24 2069564676 ps
T807 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3782912652 Jun 22 04:33:57 PM PDT 24 Jun 22 04:34:01 PM PDT 24 2151332174 ps
T293 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3121661720 Jun 22 04:33:43 PM PDT 24 Jun 22 04:35:29 PM PDT 24 42404149173 ps
T288 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2042991286 Jun 22 04:33:48 PM PDT 24 Jun 22 04:33:56 PM PDT 24 2030419046 ps
T324 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.166751116 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:46 PM PDT 24 5204516814 ps
T808 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1611021028 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:35 PM PDT 24 2010817306 ps
T809 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3355666317 Jun 22 04:33:47 PM PDT 24 Jun 22 04:33:58 PM PDT 24 5171337481 ps
T292 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3909272046 Jun 22 04:33:36 PM PDT 24 Jun 22 04:33:44 PM PDT 24 2187438761 ps
T810 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2355978489 Jun 22 04:33:55 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2063805565 ps
T811 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1424601693 Jun 22 04:33:40 PM PDT 24 Jun 22 04:33:46 PM PDT 24 4984366274 ps
T812 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.919321836 Jun 22 04:33:28 PM PDT 24 Jun 22 04:33:33 PM PDT 24 2023956026 ps
T813 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2258622589 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:43 PM PDT 24 6033344158 ps
T814 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1149879023 Jun 22 04:33:49 PM PDT 24 Jun 22 04:33:55 PM PDT 24 2011253139 ps
T309 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.895959541 Jun 22 04:33:27 PM PDT 24 Jun 22 04:33:36 PM PDT 24 2756394516 ps
T815 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1064686560 Jun 22 04:33:42 PM PDT 24 Jun 22 04:33:44 PM PDT 24 2045555873 ps
T346 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1659046574 Jun 22 04:33:27 PM PDT 24 Jun 22 04:34:31 PM PDT 24 42548135968 ps
T291 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.801281660 Jun 22 04:33:48 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2115946096 ps
T816 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3987799640 Jun 22 04:33:27 PM PDT 24 Jun 22 04:35:18 PM PDT 24 42386722891 ps
T817 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3442382284 Jun 22 04:33:50 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2014934448 ps
T818 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3391146851 Jun 22 04:33:51 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2012138109 ps
T819 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1779972417 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:31 PM PDT 24 2201586267 ps
T310 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1680683362 Jun 22 04:33:37 PM PDT 24 Jun 22 04:36:43 PM PDT 24 39383136062 ps
T820 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2943182579 Jun 22 04:33:55 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2125548388 ps
T821 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3271153328 Jun 22 04:33:42 PM PDT 24 Jun 22 04:33:44 PM PDT 24 2042957642 ps
T822 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1579365556 Jun 22 04:33:37 PM PDT 24 Jun 22 04:33:41 PM PDT 24 2103175478 ps
T823 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1359931237 Jun 22 04:33:41 PM PDT 24 Jun 22 04:33:43 PM PDT 24 2221585994 ps
T824 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2852747361 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:33 PM PDT 24 2336631865 ps
T19 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3114561888 Jun 22 04:33:45 PM PDT 24 Jun 22 04:33:53 PM PDT 24 10308052115 ps
T825 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1386011410 Jun 22 04:34:04 PM PDT 24 Jun 22 04:34:11 PM PDT 24 2016128432 ps
T826 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3396443826 Jun 22 04:33:46 PM PDT 24 Jun 22 04:33:52 PM PDT 24 2077551821 ps
T311 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2114011828 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:40 PM PDT 24 4011204302 ps
T827 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.841411848 Jun 22 04:33:40 PM PDT 24 Jun 22 04:33:44 PM PDT 24 2128789334 ps
T828 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.239759933 Jun 22 04:33:54 PM PDT 24 Jun 22 04:34:12 PM PDT 24 5258703436 ps
T829 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3159460811 Jun 22 04:33:27 PM PDT 24 Jun 22 04:34:48 PM PDT 24 75343505358 ps
T830 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2406555123 Jun 22 04:33:49 PM PDT 24 Jun 22 04:33:52 PM PDT 24 2114432959 ps
T831 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1603728819 Jun 22 04:34:03 PM PDT 24 Jun 22 04:34:07 PM PDT 24 2020067248 ps
T832 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.4045027214 Jun 22 04:33:49 PM PDT 24 Jun 22 04:33:52 PM PDT 24 2037324176 ps
T312 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2447928507 Jun 22 04:33:36 PM PDT 24 Jun 22 04:33:49 PM PDT 24 4012268566 ps
T833 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2274267986 Jun 22 04:33:38 PM PDT 24 Jun 22 04:33:45 PM PDT 24 2011567979 ps
T834 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.811333126 Jun 22 04:33:36 PM PDT 24 Jun 22 04:34:28 PM PDT 24 39382764915 ps
T835 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2362800790 Jun 22 04:33:35 PM PDT 24 Jun 22 04:33:37 PM PDT 24 2112552642 ps
T836 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2377787231 Jun 22 04:33:27 PM PDT 24 Jun 22 04:33:30 PM PDT 24 2102512567 ps
T837 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.259377131 Jun 22 04:34:02 PM PDT 24 Jun 22 04:34:05 PM PDT 24 2031142297 ps
T838 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1419392247 Jun 22 04:33:34 PM PDT 24 Jun 22 04:33:39 PM PDT 24 5432351724 ps
T839 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2604225767 Jun 22 04:33:49 PM PDT 24 Jun 22 04:33:54 PM PDT 24 2013837927 ps
T840 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4249736037 Jun 22 04:33:50 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2016662211 ps
T841 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.412524141 Jun 22 04:33:58 PM PDT 24 Jun 22 04:34:06 PM PDT 24 9062439614 ps
T313 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1283385646 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:36 PM PDT 24 2028266052 ps
T314 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1094436374 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:57 PM PDT 24 32223559728 ps
T315 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1253351399 Jun 22 04:33:47 PM PDT 24 Jun 22 04:33:54 PM PDT 24 3212412320 ps
T842 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2325094914 Jun 22 04:33:52 PM PDT 24 Jun 22 04:33:54 PM PDT 24 2157185114 ps
T843 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2578081937 Jun 22 04:33:37 PM PDT 24 Jun 22 04:34:29 PM PDT 24 42436152107 ps
T844 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.818007905 Jun 22 04:33:50 PM PDT 24 Jun 22 04:34:47 PM PDT 24 22221408208 ps
T845 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.237270158 Jun 22 04:33:28 PM PDT 24 Jun 22 04:33:36 PM PDT 24 2047312289 ps
T846 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2016700393 Jun 22 04:33:50 PM PDT 24 Jun 22 04:33:54 PM PDT 24 2018521735 ps
T847 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1917823724 Jun 22 04:33:28 PM PDT 24 Jun 22 04:33:38 PM PDT 24 2432305111 ps
T848 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1254763536 Jun 22 04:33:53 PM PDT 24 Jun 22 04:34:00 PM PDT 24 2012638939 ps
T849 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1078800890 Jun 22 04:33:56 PM PDT 24 Jun 22 04:34:15 PM PDT 24 22362895853 ps
T850 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2208131300 Jun 22 04:33:56 PM PDT 24 Jun 22 04:33:59 PM PDT 24 2041331471 ps
T851 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2134289134 Jun 22 04:33:38 PM PDT 24 Jun 22 04:33:44 PM PDT 24 2011947906 ps
T852 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2027561803 Jun 22 04:33:56 PM PDT 24 Jun 22 04:33:59 PM PDT 24 2046074916 ps
T853 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2159544271 Jun 22 04:33:53 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2067565711 ps
T316 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2831256479 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:38 PM PDT 24 2052842220 ps
T854 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2406722740 Jun 22 04:33:49 PM PDT 24 Jun 22 04:33:52 PM PDT 24 2266432673 ps
T855 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2263790792 Jun 22 04:33:24 PM PDT 24 Jun 22 04:33:29 PM PDT 24 2104312185 ps
T317 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1851776463 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:44 PM PDT 24 6040058337 ps
T318 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.944956700 Jun 22 04:33:28 PM PDT 24 Jun 22 04:33:50 PM PDT 24 3196153815 ps
T856 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3806062214 Jun 22 04:33:27 PM PDT 24 Jun 22 04:33:30 PM PDT 24 2029625240 ps
T857 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1038603541 Jun 22 04:33:35 PM PDT 24 Jun 22 04:33:38 PM PDT 24 2174878380 ps
T319 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3125691802 Jun 22 04:33:28 PM PDT 24 Jun 22 04:33:31 PM PDT 24 2114984516 ps
T858 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1628179232 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:36 PM PDT 24 2120924791 ps
T859 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2182756669 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:34 PM PDT 24 2104906437 ps
T860 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1049295199 Jun 22 04:33:50 PM PDT 24 Jun 22 04:33:53 PM PDT 24 2134761309 ps
T861 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2000575844 Jun 22 04:33:27 PM PDT 24 Jun 22 04:34:27 PM PDT 24 22225386208 ps
T862 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3516426605 Jun 22 04:33:24 PM PDT 24 Jun 22 04:33:34 PM PDT 24 6035169406 ps
T863 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.120291668 Jun 22 04:33:54 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2104308602 ps
T864 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.206453290 Jun 22 04:33:49 PM PDT 24 Jun 22 04:33:55 PM PDT 24 2011391415 ps
T865 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2263744691 Jun 22 04:33:44 PM PDT 24 Jun 22 04:33:47 PM PDT 24 2026672281 ps
T866 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.646050484 Jun 22 04:33:30 PM PDT 24 Jun 22 04:33:38 PM PDT 24 2178605984 ps
T867 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3515279611 Jun 22 04:33:54 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2050971200 ps
T868 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1813457149 Jun 22 04:34:04 PM PDT 24 Jun 22 04:34:11 PM PDT 24 2047011754 ps
T869 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2401181287 Jun 22 04:33:27 PM PDT 24 Jun 22 04:33:36 PM PDT 24 5385091724 ps
T870 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3644797857 Jun 22 04:33:35 PM PDT 24 Jun 22 04:33:43 PM PDT 24 2136517090 ps
T871 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1665002429 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:34 PM PDT 24 2146565090 ps
T872 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2970579467 Jun 22 04:33:47 PM PDT 24 Jun 22 04:33:55 PM PDT 24 2071452882 ps
T873 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3715071169 Jun 22 04:33:43 PM PDT 24 Jun 22 04:33:49 PM PDT 24 2024298991 ps
T874 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3866667608 Jun 22 04:33:43 PM PDT 24 Jun 22 04:33:53 PM PDT 24 7340348333 ps
T875 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.696674807 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:53 PM PDT 24 39915852904 ps
T876 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.872557973 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:41 PM PDT 24 8132463571 ps
T877 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1410656299 Jun 22 04:33:48 PM PDT 24 Jun 22 04:33:54 PM PDT 24 2016386883 ps
T878 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.658043510 Jun 22 04:34:04 PM PDT 24 Jun 22 04:34:18 PM PDT 24 5270806213 ps
T344 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.929319712 Jun 22 04:33:53 PM PDT 24 Jun 22 04:35:28 PM PDT 24 42512577215 ps
T347 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3087749047 Jun 22 04:33:38 PM PDT 24 Jun 22 04:34:22 PM PDT 24 22199036930 ps
T879 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2695518884 Jun 22 04:33:27 PM PDT 24 Jun 22 04:33:31 PM PDT 24 2124475735 ps
T880 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2594305090 Jun 22 04:33:30 PM PDT 24 Jun 22 04:33:37 PM PDT 24 2010309394 ps
T881 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.810440259 Jun 22 04:33:50 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2014241266 ps
T882 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2870689703 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:38 PM PDT 24 4868910022 ps
T883 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3843562030 Jun 22 04:33:38 PM PDT 24 Jun 22 04:33:44 PM PDT 24 2057802244 ps
T884 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2739853531 Jun 22 04:33:47 PM PDT 24 Jun 22 04:33:52 PM PDT 24 3362507943 ps
T885 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3279805127 Jun 22 04:33:46 PM PDT 24 Jun 22 04:33:50 PM PDT 24 2035181664 ps
T886 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1571855460 Jun 22 04:33:46 PM PDT 24 Jun 22 04:33:53 PM PDT 24 2058194280 ps
T887 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3011106364 Jun 22 04:33:32 PM PDT 24 Jun 22 04:35:22 PM PDT 24 42389244718 ps
T888 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.631111910 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:34 PM PDT 24 2015789266 ps
T889 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.706454316 Jun 22 04:33:38 PM PDT 24 Jun 22 04:33:47 PM PDT 24 7431119565 ps
T890 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.783356048 Jun 22 04:33:52 PM PDT 24 Jun 22 04:33:59 PM PDT 24 2053294847 ps
T891 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.858261918 Jun 22 04:33:49 PM PDT 24 Jun 22 04:33:54 PM PDT 24 2020133148 ps
T892 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3048277197 Jun 22 04:33:47 PM PDT 24 Jun 22 04:33:50 PM PDT 24 2066197873 ps
T893 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2581877724 Jun 22 04:33:54 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2020657916 ps
T894 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.663699667 Jun 22 04:33:27 PM PDT 24 Jun 22 04:33:46 PM PDT 24 7577782542 ps
T895 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.709665770 Jun 22 04:33:44 PM PDT 24 Jun 22 04:33:47 PM PDT 24 2020736412 ps
T896 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.51596352 Jun 22 04:33:27 PM PDT 24 Jun 22 04:33:37 PM PDT 24 2514399862 ps
T897 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3524713949 Jun 22 04:33:54 PM PDT 24 Jun 22 04:33:56 PM PDT 24 2068615414 ps
T345 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.386076415 Jun 22 04:33:53 PM PDT 24 Jun 22 04:34:25 PM PDT 24 42502907603 ps
T898 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3171319924 Jun 22 04:33:40 PM PDT 24 Jun 22 04:33:56 PM PDT 24 22263072691 ps
T899 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3450445878 Jun 22 04:33:49 PM PDT 24 Jun 22 04:33:52 PM PDT 24 2231450997 ps
T900 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1528445653 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:33 PM PDT 24 2073742302 ps
T901 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2724798229 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:28 PM PDT 24 2130832500 ps
T902 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2323141927 Jun 22 04:33:54 PM PDT 24 Jun 22 04:33:57 PM PDT 24 2072783883 ps
T903 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1514767631 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:29 PM PDT 24 2011965379 ps
T904 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3553502398 Jun 22 04:33:26 PM PDT 24 Jun 22 04:34:20 PM PDT 24 22207236859 ps
T905 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3219562995 Jun 22 04:33:46 PM PDT 24 Jun 22 04:33:49 PM PDT 24 2040660820 ps
T906 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2323417053 Jun 22 04:33:49 PM PDT 24 Jun 22 04:34:05 PM PDT 24 22407898008 ps
T907 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3619947644 Jun 22 04:33:51 PM PDT 24 Jun 22 04:33:55 PM PDT 24 4936321588 ps
T908 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2838801769 Jun 22 04:33:30 PM PDT 24 Jun 22 04:33:33 PM PDT 24 2067134012 ps
T909 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2377991035 Jun 22 04:33:52 PM PDT 24 Jun 22 04:33:58 PM PDT 24 2059224267 ps
T910 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3665503093 Jun 22 04:33:44 PM PDT 24 Jun 22 04:33:51 PM PDT 24 2087303329 ps
T911 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3020238184 Jun 22 04:33:55 PM PDT 24 Jun 22 04:34:02 PM PDT 24 2111984624 ps
T912 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.763218371 Jun 22 04:33:19 PM PDT 24 Jun 22 04:33:34 PM PDT 24 22407360187 ps
T913 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3829402792 Jun 22 04:33:46 PM PDT 24 Jun 22 04:33:48 PM PDT 24 2141508363 ps
T914 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1636596715 Jun 22 04:33:30 PM PDT 24 Jun 22 04:33:58 PM PDT 24 22531730423 ps
T915 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1027242763 Jun 22 04:33:33 PM PDT 24 Jun 22 04:33:35 PM PDT 24 2076884036 ps
T916 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3202867271 Jun 22 04:33:51 PM PDT 24 Jun 22 04:33:54 PM PDT 24 2049831123 ps
T917 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.398080864 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:30 PM PDT 24 2083897561 ps

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.4151646511
Short name T6
Test name
Test status
Simulation time 88439319075 ps
CPU time 53.62 seconds
Started Jun 22 04:52:53 PM PDT 24
Finished Jun 22 04:53:47 PM PDT 24
Peak memory 209700 kb
Host smart-962b1a31-04d7-4481-badb-9885123e9c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151646511 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.4151646511
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2060537209
Short name T41
Test name
Test status
Simulation time 131176751161 ps
CPU time 351.96 seconds
Started Jun 22 04:52:28 PM PDT 24
Finished Jun 22 04:58:20 PM PDT 24
Peak memory 201528 kb
Host smart-7dd9f2aa-968b-4c61-bd50-4dcaa42c6498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060537209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.2060537209
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2084434241
Short name T29
Test name
Test status
Simulation time 59344339978 ps
CPU time 132 seconds
Started Jun 22 04:51:54 PM PDT 24
Finished Jun 22 04:54:07 PM PDT 24
Peak memory 209732 kb
Host smart-a5cab322-08b8-49dc-9705-f2043b40b10f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084434241 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.2084434241
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3238638456
Short name T76
Test name
Test status
Simulation time 191073608544 ps
CPU time 67.61 seconds
Started Jun 22 04:52:22 PM PDT 24
Finished Jun 22 04:53:30 PM PDT 24
Peak memory 215268 kb
Host smart-743db58d-ad05-4c99-a743-8eba5ed8b313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238638456 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.3238638456
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4178073424
Short name T70
Test name
Test status
Simulation time 35241710916 ps
CPU time 84.42 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:53:00 PM PDT 24
Peak memory 201356 kb
Host smart-d064f8da-67bc-4613-8759-6a7c8eb11921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178073424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.4178073424
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1265889858
Short name T112
Test name
Test status
Simulation time 90513814448 ps
CPU time 60.89 seconds
Started Jun 22 04:52:45 PM PDT 24
Finished Jun 22 04:53:47 PM PDT 24
Peak memory 209704 kb
Host smart-7e2fbe81-cf31-45c5-9c73-c6dd6ef80d7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265889858 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1265889858
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.976344562
Short name T285
Test name
Test status
Simulation time 42550653746 ps
CPU time 25.67 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:34:17 PM PDT 24
Peak memory 201160 kb
Host smart-ebc67e69-5799-497a-bbd9-ad564683787c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976344562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_tl_intg_err.976344562
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.253159790
Short name T10
Test name
Test status
Simulation time 4449158520 ps
CPU time 2.53 seconds
Started Jun 22 04:52:28 PM PDT 24
Finished Jun 22 04:52:31 PM PDT 24
Peak memory 201248 kb
Host smart-7ddfa429-e507-4837-b965-18f2eb5272d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253159790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr
l_edge_detect.253159790
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1735573554
Short name T23
Test name
Test status
Simulation time 39095911080 ps
CPU time 51.48 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:54:42 PM PDT 24
Peak memory 201568 kb
Host smart-a15d7f45-47a1-4365-8452-e822e5865ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735573554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.1735573554
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3708220487
Short name T125
Test name
Test status
Simulation time 122532665054 ps
CPU time 65.01 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:53:48 PM PDT 24
Peak memory 215656 kb
Host smart-a064f9b0-61c3-43d1-af39-d07f81926100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708220487 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.3708220487
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.114307234
Short name T88
Test name
Test status
Simulation time 20324544697 ps
CPU time 16.02 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 201468 kb
Host smart-0684f27d-3684-4d1e-bc05-fb2813745289
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114307234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_combo_detect.114307234
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2824318205
Short name T179
Test name
Test status
Simulation time 35187410886 ps
CPU time 22.64 seconds
Started Jun 22 04:53:43 PM PDT 24
Finished Jun 22 04:54:06 PM PDT 24
Peak memory 201564 kb
Host smart-81996903-8c09-4287-a698-8e1f17b801d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824318205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2824318205
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2268582792
Short name T114
Test name
Test status
Simulation time 902378610251 ps
CPU time 381.96 seconds
Started Jun 22 04:52:09 PM PDT 24
Finished Jun 22 04:58:32 PM PDT 24
Peak memory 213492 kb
Host smart-0638cf21-c97c-4d79-bd94-f270a10954a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268582792 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.2268582792
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.890044638
Short name T244
Test name
Test status
Simulation time 109439641418 ps
CPU time 138.36 seconds
Started Jun 22 04:53:18 PM PDT 24
Finished Jun 22 04:55:37 PM PDT 24
Peak memory 201548 kb
Host smart-9e7b8e07-8606-4ac1-84a0-8fd01fa0ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890044638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.890044638
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3715858075
Short name T73
Test name
Test status
Simulation time 3808399896 ps
CPU time 5.35 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:52:41 PM PDT 24
Peak memory 201232 kb
Host smart-6be1d188-c025-459b-808f-1b59d36488b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715858075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.3715858075
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.33496979
Short name T175
Test name
Test status
Simulation time 15999399839 ps
CPU time 10.64 seconds
Started Jun 22 04:52:12 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 201188 kb
Host smart-4bf99944-478d-47a0-be2f-2aa24846fef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33496979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_str
ess_all.33496979
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.1286248085
Short name T148
Test name
Test status
Simulation time 4371633396 ps
CPU time 10.48 seconds
Started Jun 22 04:51:58 PM PDT 24
Finished Jun 22 04:52:09 PM PDT 24
Peak memory 201132 kb
Host smart-a0b795c3-f449-427f-8c89-09247c833c91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286248085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.1286248085
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.549849503
Short name T172
Test name
Test status
Simulation time 2015128012 ps
CPU time 3.09 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:38 PM PDT 24
Peak memory 201248 kb
Host smart-c5821980-b486-4b50-bd79-1e665d41f4ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549849503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.549849503
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3440286807
Short name T81
Test name
Test status
Simulation time 164201526665 ps
CPU time 112.68 seconds
Started Jun 22 04:53:13 PM PDT 24
Finished Jun 22 04:55:06 PM PDT 24
Peak memory 201424 kb
Host smart-4b6372b7-dc30-4b1f-a017-ef599df3a9c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440286807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.3440286807
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2463928841
Short name T77
Test name
Test status
Simulation time 138163234608 ps
CPU time 161.03 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:55:17 PM PDT 24
Peak memory 209956 kb
Host smart-85a8eaac-cf0e-464b-8400-ac3d97c3c4d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463928841 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2463928841
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.779286729
Short name T331
Test name
Test status
Simulation time 203148819956 ps
CPU time 501.98 seconds
Started Jun 22 04:52:01 PM PDT 24
Finished Jun 22 05:00:24 PM PDT 24
Peak memory 201436 kb
Host smart-9f458306-c2cf-41ee-96c8-ce912e6141d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779286729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_combo_detect.779286729
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1680683362
Short name T310
Test name
Test status
Simulation time 39383136062 ps
CPU time 184.73 seconds
Started Jun 22 04:33:37 PM PDT 24
Finished Jun 22 04:36:43 PM PDT 24
Peak memory 201164 kb
Host smart-82abd544-7d0e-484f-a4f1-df1edeef8dfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680683362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.1680683362
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1776040015
Short name T227
Test name
Test status
Simulation time 3235496067 ps
CPU time 4.34 seconds
Started Jun 22 04:53:28 PM PDT 24
Finished Jun 22 04:53:33 PM PDT 24
Peak memory 201248 kb
Host smart-1df728fc-1835-40b2-8ab1-325d055cc13c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776040015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1776040015
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.801281660
Short name T291
Test name
Test status
Simulation time 2115946096 ps
CPU time 7.31 seconds
Started Jun 22 04:33:48 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 201004 kb
Host smart-efaa8f4c-8125-459a-af4d-5a6edf9397e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801281660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors
.801281660
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.2956344855
Short name T72
Test name
Test status
Simulation time 5951424995 ps
CPU time 13.81 seconds
Started Jun 22 04:52:31 PM PDT 24
Finished Jun 22 04:52:45 PM PDT 24
Peak memory 201088 kb
Host smart-742330c2-eb1e-4073-baef-b8efa1d46835
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956344855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.2956344855
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2628566511
Short name T186
Test name
Test status
Simulation time 80892892459 ps
CPU time 180.17 seconds
Started Jun 22 04:53:15 PM PDT 24
Finished Jun 22 04:56:16 PM PDT 24
Peak memory 214772 kb
Host smart-514004aa-6d01-42ee-87cb-6f6a275f71e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628566511 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2628566511
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3580740733
Short name T327
Test name
Test status
Simulation time 158411191054 ps
CPU time 209.73 seconds
Started Jun 22 04:53:01 PM PDT 24
Finished Jun 22 04:56:32 PM PDT 24
Peak memory 201532 kb
Host smart-c7aa69f5-023c-4bc9-80bb-d40bef6cefaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580740733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.3580740733
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1604095005
Short name T2
Test name
Test status
Simulation time 8696090528 ps
CPU time 7.59 seconds
Started Jun 22 04:53:18 PM PDT 24
Finished Jun 22 04:53:26 PM PDT 24
Peak memory 201256 kb
Host smart-fb8a63e5-77c9-4b5e-9298-0ec939b2f282
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604095005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.1604095005
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3447981165
Short name T3
Test name
Test status
Simulation time 63587751702 ps
CPU time 40.39 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:38 PM PDT 24
Peak memory 209916 kb
Host smart-281dd08e-33aa-4093-9e57-cc91ae525f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447981165 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.3447981165
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1261240797
Short name T283
Test name
Test status
Simulation time 42098119623 ps
CPU time 27.93 seconds
Started Jun 22 04:51:36 PM PDT 24
Finished Jun 22 04:52:05 PM PDT 24
Peak memory 220864 kb
Host smart-4b8c7570-324f-4eeb-98a2-ee3cc2229900
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261240797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1261240797
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2370852839
Short name T16
Test name
Test status
Simulation time 4562256374 ps
CPU time 18.16 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:48 PM PDT 24
Peak memory 201164 kb
Host smart-d104007c-998b-4131-a4c4-6e44d9c86bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370852839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.2370852839
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3762661191
Short name T339
Test name
Test status
Simulation time 78157570157 ps
CPU time 14.82 seconds
Started Jun 22 04:53:37 PM PDT 24
Finished Jun 22 04:53:53 PM PDT 24
Peak memory 201504 kb
Host smart-f4a01b8c-33b4-46d6-99f1-244b53289792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762661191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.3762661191
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.590507986
Short name T96
Test name
Test status
Simulation time 73508377618 ps
CPU time 34.38 seconds
Started Jun 22 04:52:39 PM PDT 24
Finished Jun 22 04:53:14 PM PDT 24
Peak memory 201460 kb
Host smart-e7f23466-2fea-437b-9f8f-93bfd75cfcbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590507986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_combo_detect.590507986
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.944943484
Short name T243
Test name
Test status
Simulation time 119791565442 ps
CPU time 28.05 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:38 PM PDT 24
Peak memory 201464 kb
Host smart-a81a556b-c63b-40e7-887e-9ab3e4f51c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944943484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_wi
th_pre_cond.944943484
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1872310173
Short name T239
Test name
Test status
Simulation time 128591885235 ps
CPU time 81.36 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:54:22 PM PDT 24
Peak memory 217956 kb
Host smart-ee21fc3c-f831-405b-a15f-b5c2a7770787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872310173 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1872310173
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.593432305
Short name T4
Test name
Test status
Simulation time 24414520380 ps
CPU time 5.98 seconds
Started Jun 22 04:53:34 PM PDT 24
Finished Jun 22 04:53:40 PM PDT 24
Peak memory 201764 kb
Host smart-f110ddf5-2702-4364-a062-9c10da2eca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593432305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_wi
th_pre_cond.593432305
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.62401068
Short name T336
Test name
Test status
Simulation time 148292550155 ps
CPU time 364.27 seconds
Started Jun 22 04:51:29 PM PDT 24
Finished Jun 22 04:57:34 PM PDT 24
Peak memory 201492 kb
Host smart-09165fa3-2427-488e-ba0c-fc80f9a8481b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62401068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stre
ss_all.62401068
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2490091149
Short name T355
Test name
Test status
Simulation time 114970620720 ps
CPU time 302.42 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:57:17 PM PDT 24
Peak memory 201572 kb
Host smart-83221bce-e546-45b1-a3b0-6a1b1177bdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490091149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.2490091149
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2425315048
Short name T138
Test name
Test status
Simulation time 66418927760 ps
CPU time 43.16 seconds
Started Jun 22 04:52:53 PM PDT 24
Finished Jun 22 04:53:37 PM PDT 24
Peak memory 201472 kb
Host smart-1087800c-266a-4338-9306-c7ea55640219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425315048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.2425315048
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1993441072
Short name T164
Test name
Test status
Simulation time 1952836373888 ps
CPU time 239.08 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:55:45 PM PDT 24
Peak memory 217952 kb
Host smart-fb139ba3-f5ae-438c-91b5-62d0e71e67dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993441072 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.1993441072
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.3851630421
Short name T143
Test name
Test status
Simulation time 3170292366 ps
CPU time 8.04 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201268 kb
Host smart-136b199b-e050-42d8-a1d0-4ec1a6c065b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851630421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.3851630421
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.324718164
Short name T109
Test name
Test status
Simulation time 143994460409 ps
CPU time 380.97 seconds
Started Jun 22 04:51:36 PM PDT 24
Finished Jun 22 04:57:58 PM PDT 24
Peak memory 201404 kb
Host smart-8d2ca9a8-2edf-4c5f-a226-ca7f3e891510
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324718164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_combo_detect.324718164
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.4292420430
Short name T267
Test name
Test status
Simulation time 109844136758 ps
CPU time 71.01 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:53:22 PM PDT 24
Peak memory 201488 kb
Host smart-635626d6-d962-4783-b0ba-f761d35b0ac6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292420430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.4292420430
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3739805197
Short name T149
Test name
Test status
Simulation time 220465414080 ps
CPU time 262.41 seconds
Started Jun 22 04:52:25 PM PDT 24
Finished Jun 22 04:56:48 PM PDT 24
Peak memory 209900 kb
Host smart-77dac881-d4a1-43c1-93a6-88e1201dcd89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739805197 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.3739805197
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2200111414
Short name T151
Test name
Test status
Simulation time 908488868696 ps
CPU time 232.06 seconds
Started Jun 22 04:51:59 PM PDT 24
Finished Jun 22 04:55:52 PM PDT 24
Peak memory 201196 kb
Host smart-676ae6ef-b624-428c-961e-9a48ef801480
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200111414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.2200111414
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1427683234
Short name T242
Test name
Test status
Simulation time 98478812719 ps
CPU time 110.25 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 201520 kb
Host smart-ab6bd6d5-441a-4f8a-88ad-3543c5f0c990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427683234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1427683234
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3269455441
Short name T266
Test name
Test status
Simulation time 1466197844337 ps
CPU time 327.72 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:57:42 PM PDT 24
Peak memory 213652 kb
Host smart-31d4425d-90fd-4f4e-bf2e-ec5b3a63b1d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269455441 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.3269455441
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.4269078620
Short name T357
Test name
Test status
Simulation time 122752078068 ps
CPU time 89.38 seconds
Started Jun 22 04:52:25 PM PDT 24
Finished Jun 22 04:53:55 PM PDT 24
Peak memory 201596 kb
Host smart-425b84f7-89cd-4d27-a0cc-07072c373f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269078620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.4269078620
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1336047925
Short name T335
Test name
Test status
Simulation time 56317555178 ps
CPU time 15.04 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201596 kb
Host smart-c61d6f09-e4b3-45a2-912c-06709934e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336047925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.1336047925
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3018121732
Short name T94
Test name
Test status
Simulation time 119335009054 ps
CPU time 81.41 seconds
Started Jun 22 04:53:22 PM PDT 24
Finished Jun 22 04:54:44 PM PDT 24
Peak memory 213700 kb
Host smart-a8cfe544-17f8-4b2c-9270-db97c09baba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018121732 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.3018121732
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.4166967336
Short name T282
Test name
Test status
Simulation time 2278302086 ps
CPU time 5.2 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:33:56 PM PDT 24
Peak memory 201120 kb
Host smart-a3b56fbb-08f1-4507-bc2c-a0a0ea6b1343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166967336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.4166967336
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2816178601
Short name T51
Test name
Test status
Simulation time 3573650781 ps
CPU time 1.61 seconds
Started Jun 22 04:52:05 PM PDT 24
Finished Jun 22 04:52:07 PM PDT 24
Peak memory 201300 kb
Host smart-f6f56bb9-deb3-41fb-8156-6224c1e3902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816178601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2
816178601
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3975894082
Short name T184
Test name
Test status
Simulation time 5057034802 ps
CPU time 1.95 seconds
Started Jun 22 04:53:25 PM PDT 24
Finished Jun 22 04:53:27 PM PDT 24
Peak memory 201228 kb
Host smart-b5c4e62a-8451-4ae5-b66b-9d03c2737985
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975894082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.3975894082
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3553502398
Short name T904
Test name
Test status
Simulation time 22207236859 ps
CPU time 52.1 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:34:20 PM PDT 24
Peak memory 201188 kb
Host smart-85b69ffe-2642-46b2-8260-b3b60c5beaed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553502398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.3553502398
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.929319712
Short name T344
Test name
Test status
Simulation time 42512577215 ps
CPU time 94.47 seconds
Started Jun 22 04:33:53 PM PDT 24
Finished Jun 22 04:35:28 PM PDT 24
Peak memory 201160 kb
Host smart-5a139eb4-11bf-44dd-ae49-bf4b7f660518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929319712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_tl_intg_err.929319712
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1136569251
Short name T753
Test name
Test status
Simulation time 98766261905 ps
CPU time 27.41 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:52:39 PM PDT 24
Peak memory 201424 kb
Host smart-22d1992d-2d1a-4cca-b834-66768d3a7e0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136569251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1136569251
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.744972057
Short name T353
Test name
Test status
Simulation time 47696815204 ps
CPU time 29.81 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:42 PM PDT 24
Peak memory 201580 kb
Host smart-06b5097e-e369-4a3b-9fe0-1212e6c52640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744972057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_wi
th_pre_cond.744972057
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1460121152
Short name T340
Test name
Test status
Simulation time 67798972517 ps
CPU time 52.69 seconds
Started Jun 22 04:52:29 PM PDT 24
Finished Jun 22 04:53:23 PM PDT 24
Peak memory 201568 kb
Host smart-8c9cde46-cac9-400d-bfc9-3554740f8591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460121152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.1460121152
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1506064568
Short name T43
Test name
Test status
Simulation time 61466938926 ps
CPU time 82.81 seconds
Started Jun 22 04:53:06 PM PDT 24
Finished Jun 22 04:54:30 PM PDT 24
Peak memory 201536 kb
Host smart-17cbe5b5-47f4-4ea2-a081-eecc054b9bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506064568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.1506064568
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4040443960
Short name T342
Test name
Test status
Simulation time 133736579929 ps
CPU time 348.5 seconds
Started Jun 22 04:53:04 PM PDT 24
Finished Jun 22 04:58:54 PM PDT 24
Peak memory 201484 kb
Host smart-84408a22-3176-4994-9735-897770368331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040443960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.4040443960
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2685631517
Short name T189
Test name
Test status
Simulation time 46233211983 ps
CPU time 112.18 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:55:19 PM PDT 24
Peak memory 201592 kb
Host smart-7849060a-4bd9-46c7-bf35-0a6e64e5c204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685631517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.2685631517
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.4013809127
Short name T329
Test name
Test status
Simulation time 98527040740 ps
CPU time 34.78 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 201548 kb
Host smart-e65e0f72-001e-4021-b07d-b73791cd3bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013809127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.4013809127
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3381658098
Short name T341
Test name
Test status
Simulation time 37759134208 ps
CPU time 50.87 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:54:38 PM PDT 24
Peak memory 201580 kb
Host smart-81078c42-d23b-4461-8e7f-d66627fac8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381658098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.3381658098
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1337285055
Short name T356
Test name
Test status
Simulation time 97548023125 ps
CPU time 229.21 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:57:40 PM PDT 24
Peak memory 201468 kb
Host smart-5a019c69-d05b-4105-9e6e-6bfd2834c3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337285055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.1337285055
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2044923985
Short name T350
Test name
Test status
Simulation time 84023123369 ps
CPU time 72.71 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:55:01 PM PDT 24
Peak memory 201444 kb
Host smart-3ff6050d-d04f-4252-996c-bee4ba36878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044923985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.2044923985
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3905808067
Short name T337
Test name
Test status
Simulation time 87564354344 ps
CPU time 27.75 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 201532 kb
Host smart-6b9f4bb2-628b-4a6a-b99f-17bf1315bfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905808067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3905808067
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.277954539
Short name T71
Test name
Test status
Simulation time 36807382227 ps
CPU time 22.9 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:56 PM PDT 24
Peak memory 201360 kb
Host smart-4c41f58e-440d-43e7-96f3-7bb761750320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277954539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.277954539
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.237270158
Short name T845
Test name
Test status
Simulation time 2047312289 ps
CPU time 6.44 seconds
Started Jun 22 04:33:28 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 201036 kb
Host smart-dd6c660a-7564-4d49-ba3e-0fa5ce8c1a67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237270158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_error
s.237270158
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3114561888
Short name T19
Test name
Test status
Simulation time 10308052115 ps
CPU time 7.71 seconds
Started Jun 22 04:33:45 PM PDT 24
Finished Jun 22 04:33:53 PM PDT 24
Peak memory 201520 kb
Host smart-00a84c96-b408-4489-9d0d-ec099ad3ed88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114561888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.3114561888
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1768497724
Short name T240
Test name
Test status
Simulation time 95907961395 ps
CPU time 247.89 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:55:46 PM PDT 24
Peak memory 201432 kb
Host smart-4b7f908a-876b-4310-96b3-b157755c9eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768497724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1768497724
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.623475453
Short name T65
Test name
Test status
Simulation time 42567405558 ps
CPU time 56.74 seconds
Started Jun 22 04:51:58 PM PDT 24
Finished Jun 22 04:52:56 PM PDT 24
Peak memory 201516 kb
Host smart-1bd7c4e3-0bd2-445d-b67c-78a943f08581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623475453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_wi
th_pre_cond.623475453
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2480664795
Short name T325
Test name
Test status
Simulation time 2670462314 ps
CPU time 8.27 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:40 PM PDT 24
Peak memory 201128 kb
Host smart-f88f5601-7054-4540-adec-6e19776abb37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480664795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.2480664795
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3516426605
Short name T862
Test name
Test status
Simulation time 6035169406 ps
CPU time 8.75 seconds
Started Jun 22 04:33:24 PM PDT 24
Finished Jun 22 04:33:34 PM PDT 24
Peak memory 200976 kb
Host smart-b52f8627-7fa1-4137-b0d6-cc32678db304
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516426605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.3516426605
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3225753782
Short name T25
Test name
Test status
Simulation time 2218920446 ps
CPU time 2.28 seconds
Started Jun 22 04:33:39 PM PDT 24
Finished Jun 22 04:33:42 PM PDT 24
Peak memory 201080 kb
Host smart-c469ba14-8423-436f-a686-2de51386478c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225753782 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3225753782
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.566294890
Short name T321
Test name
Test status
Simulation time 2060082008 ps
CPU time 3.39 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 200948 kb
Host smart-d8c123a3-64b2-435e-8db3-b3b994559117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566294890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw
.566294890
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1514767631
Short name T903
Test name
Test status
Simulation time 2011965379 ps
CPU time 5.81 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 200600 kb
Host smart-d370dfad-cd8e-40a7-aabc-34c85ef95b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514767631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.1514767631
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2870689703
Short name T882
Test name
Test status
Simulation time 4868910022 ps
CPU time 12.01 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:38 PM PDT 24
Peak memory 201216 kb
Host smart-1972872c-b657-41c3-b984-52a180412b98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870689703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.2870689703
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2042991286
Short name T288
Test name
Test status
Simulation time 2030419046 ps
CPU time 6.74 seconds
Started Jun 22 04:33:48 PM PDT 24
Finished Jun 22 04:33:56 PM PDT 24
Peak memory 200992 kb
Host smart-bde885f7-ced1-4cfa-b422-b2d2cd8e840e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042991286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.2042991286
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.763218371
Short name T912
Test name
Test status
Simulation time 22407360187 ps
CPU time 14.84 seconds
Started Jun 22 04:33:19 PM PDT 24
Finished Jun 22 04:33:34 PM PDT 24
Peak memory 201220 kb
Host smart-506782da-a01f-4dc4-98de-7751a2f93a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763218371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_tl_intg_err.763218371
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1253351399
Short name T315
Test name
Test status
Simulation time 3212412320 ps
CPU time 5.54 seconds
Started Jun 22 04:33:47 PM PDT 24
Finished Jun 22 04:33:54 PM PDT 24
Peak memory 201204 kb
Host smart-96881cc3-cdca-4ab6-a2ae-c4d234892d70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253351399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.1253351399
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.696674807
Short name T875
Test name
Test status
Simulation time 39915852904 ps
CPU time 28.5 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:53 PM PDT 24
Peak memory 201160 kb
Host smart-0f30cf4d-7000-4230-9e85-b8f3da27d3c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696674807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.696674807
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1851776463
Short name T317
Test name
Test status
Simulation time 6040058337 ps
CPU time 14.6 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200956 kb
Host smart-4a4d26c0-c005-4333-946c-6232044bbf94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851776463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.1851776463
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3667599112
Short name T366
Test name
Test status
Simulation time 2132926541 ps
CPU time 1.89 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 201012 kb
Host smart-ee72bec3-5d5f-4b0b-9c24-f91836498a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667599112 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3667599112
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3843562030
Short name T883
Test name
Test status
Simulation time 2057802244 ps
CPU time 5.48 seconds
Started Jun 22 04:33:38 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200828 kb
Host smart-4924c869-4140-4e61-b7d2-dc0e15c5c5b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843562030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3843562030
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2134289134
Short name T851
Test name
Test status
Simulation time 2011947906 ps
CPU time 5.47 seconds
Started Jun 22 04:33:38 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200756 kb
Host smart-bce9acd4-a9dd-4a8c-8b0e-89a90c19cdb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134289134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.2134289134
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1424601693
Short name T811
Test name
Test status
Simulation time 4984366274 ps
CPU time 4.92 seconds
Started Jun 22 04:33:40 PM PDT 24
Finished Jun 22 04:33:46 PM PDT 24
Peak memory 201148 kb
Host smart-67f1f2bf-46b2-4c32-8b92-10026da5e774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424601693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.1424601693
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.398080864
Short name T917
Test name
Test status
Simulation time 2083897561 ps
CPU time 3.48 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 201028 kb
Host smart-934fe5f0-6ff9-4ae3-b588-d60b013cd2a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398080864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors
.398080864
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1665002429
Short name T871
Test name
Test status
Simulation time 2146565090 ps
CPU time 4.01 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:34 PM PDT 24
Peak memory 201096 kb
Host smart-50fc4115-836d-4193-9f7c-4a4194f6214c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665002429 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1665002429
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1283385646
Short name T313
Test name
Test status
Simulation time 2028266052 ps
CPU time 5.6 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 200848 kb
Host smart-fb17a69f-b8d4-4913-870c-b19afc427fc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283385646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.1283385646
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1291087907
Short name T797
Test name
Test status
Simulation time 2010038333 ps
CPU time 5.55 seconds
Started Jun 22 04:33:46 PM PDT 24
Finished Jun 22 04:33:53 PM PDT 24
Peak memory 200688 kb
Host smart-333bf467-80fc-4f71-b78e-ed5c4065ac01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291087907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.1291087907
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1507088495
Short name T322
Test name
Test status
Simulation time 9652817034 ps
CPU time 5.61 seconds
Started Jun 22 04:33:37 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 201104 kb
Host smart-189bf7c6-8143-4163-a36c-0fea76100c3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507088495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.1507088495
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1917823724
Short name T847
Test name
Test status
Simulation time 2432305111 ps
CPU time 3.65 seconds
Started Jun 22 04:33:28 PM PDT 24
Finished Jun 22 04:33:38 PM PDT 24
Peak memory 201164 kb
Host smart-ecf0f959-ff65-47f8-b34e-603f649bf14d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917823724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.1917823724
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4219779393
Short name T294
Test name
Test status
Simulation time 2147508069 ps
CPU time 6.52 seconds
Started Jun 22 04:33:37 PM PDT 24
Finished Jun 22 04:33:45 PM PDT 24
Peak memory 201424 kb
Host smart-aa6d2573-93ee-4b6f-83e8-ecea6952d4be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219779393 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4219779393
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2159544271
Short name T853
Test name
Test status
Simulation time 2067565711 ps
CPU time 3.42 seconds
Started Jun 22 04:33:53 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200840 kb
Host smart-745876a0-3625-4e90-82c6-219e02fd7907
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159544271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.2159544271
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2362800790
Short name T835
Test name
Test status
Simulation time 2112552642 ps
CPU time 1.14 seconds
Started Jun 22 04:33:35 PM PDT 24
Finished Jun 22 04:33:37 PM PDT 24
Peak memory 200772 kb
Host smart-080ac79a-191f-44bd-99ba-404d4fcbb601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362800790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.2362800790
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.872557973
Short name T876
Test name
Test status
Simulation time 8132463571 ps
CPU time 8.83 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:41 PM PDT 24
Peak memory 201180 kb
Host smart-645e995c-3a14-4f4e-a1f1-7bb624242ff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872557973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_same_csr_outstanding.872557973
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1636596715
Short name T914
Test name
Test status
Simulation time 22531730423 ps
CPU time 27.61 seconds
Started Jun 22 04:33:30 PM PDT 24
Finished Jun 22 04:33:58 PM PDT 24
Peak memory 201212 kb
Host smart-a891f2cd-7fd0-421e-9ee7-a7b7ab871ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636596715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.1636596715
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.120291668
Short name T863
Test name
Test status
Simulation time 2104308602 ps
CPU time 2.06 seconds
Started Jun 22 04:33:54 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200912 kb
Host smart-717c806e-46e0-4b52-b8d1-3df667995c46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120291668 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.120291668
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.794347949
Short name T308
Test name
Test status
Simulation time 2064287950 ps
CPU time 5.75 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:37 PM PDT 24
Peak memory 200948 kb
Host smart-5b415802-4d09-4a52-a589-ec7b56b065dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794347949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r
w.794347949
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2274267986
Short name T833
Test name
Test status
Simulation time 2011567979 ps
CPU time 5.62 seconds
Started Jun 22 04:33:38 PM PDT 24
Finished Jun 22 04:33:45 PM PDT 24
Peak memory 200540 kb
Host smart-b4c59db1-7841-45bc-9847-5ad70448ed67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274267986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2274267986
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3866667608
Short name T874
Test name
Test status
Simulation time 7340348333 ps
CPU time 10.25 seconds
Started Jun 22 04:33:43 PM PDT 24
Finished Jun 22 04:33:53 PM PDT 24
Peak memory 200872 kb
Host smart-cd927976-58b6-4d7c-ba8e-e3a047e904f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866667608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.3866667608
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.646050484
Short name T866
Test name
Test status
Simulation time 2178605984 ps
CPU time 7.05 seconds
Started Jun 22 04:33:30 PM PDT 24
Finished Jun 22 04:33:38 PM PDT 24
Peak memory 201120 kb
Host smart-569d9e32-aa42-45c8-add9-c01a74704d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646050484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_error
s.646050484
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.678332346
Short name T286
Test name
Test status
Simulation time 22296998977 ps
CPU time 15.31 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:47 PM PDT 24
Peak memory 201160 kb
Host smart-34ba5c1f-7e5f-4035-8ffd-316ccf40a2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678332346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_tl_intg_err.678332346
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3644797857
Short name T870
Test name
Test status
Simulation time 2136517090 ps
CPU time 6.57 seconds
Started Jun 22 04:33:35 PM PDT 24
Finished Jun 22 04:33:43 PM PDT 24
Peak memory 209176 kb
Host smart-44464a11-5270-421c-affa-feb030bab360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644797857 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3644797857
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2325094914
Short name T842
Test name
Test status
Simulation time 2157185114 ps
CPU time 1.37 seconds
Started Jun 22 04:33:52 PM PDT 24
Finished Jun 22 04:33:54 PM PDT 24
Peak memory 200912 kb
Host smart-9e2e90e9-eac8-4ede-b2b7-f50d40287df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325094914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.2325094914
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1149879023
Short name T814
Test name
Test status
Simulation time 2011253139 ps
CPU time 4.78 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:33:55 PM PDT 24
Peak memory 200552 kb
Host smart-063dcb12-a95d-41b0-ae34-99a8bfa1dd91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149879023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.1149879023
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1419392247
Short name T838
Test name
Test status
Simulation time 5432351724 ps
CPU time 4.61 seconds
Started Jun 22 04:33:34 PM PDT 24
Finished Jun 22 04:33:39 PM PDT 24
Peak memory 201188 kb
Host smart-92d0e47b-0fc5-4a31-9ebe-7e5ea9f2eeda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419392247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.1419392247
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.532282723
Short name T343
Test name
Test status
Simulation time 22250708491 ps
CPU time 51.97 seconds
Started Jun 22 04:33:47 PM PDT 24
Finished Jun 22 04:34:41 PM PDT 24
Peak memory 201476 kb
Host smart-fd2150d1-4ab6-4806-b294-0c53dbedaa4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532282723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_tl_intg_err.532282723
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.841411848
Short name T827
Test name
Test status
Simulation time 2128789334 ps
CPU time 3.65 seconds
Started Jun 22 04:33:40 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200988 kb
Host smart-fbf17f6c-9464-436c-bb72-ef1489d89b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841411848 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.841411848
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2852747361
Short name T824
Test name
Test status
Simulation time 2336631865 ps
CPU time 1.3 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:33 PM PDT 24
Peak memory 201060 kb
Host smart-70b84f7b-3cb9-4092-a40c-b44a03b350b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852747361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.2852747361
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1027242763
Short name T915
Test name
Test status
Simulation time 2076884036 ps
CPU time 0.98 seconds
Started Jun 22 04:33:33 PM PDT 24
Finished Jun 22 04:33:35 PM PDT 24
Peak memory 200560 kb
Host smart-d6d4aa2e-7165-4ffd-8924-64a571775588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027242763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1027242763
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2182756669
Short name T859
Test name
Test status
Simulation time 2104906437 ps
CPU time 2.33 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:34 PM PDT 24
Peak memory 201028 kb
Host smart-ea3abfa6-47b6-4081-a392-aeef02f59597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182756669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2182756669
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.347669143
Short name T803
Test name
Test status
Simulation time 2139179410 ps
CPU time 3.84 seconds
Started Jun 22 04:33:39 PM PDT 24
Finished Jun 22 04:33:43 PM PDT 24
Peak memory 200932 kb
Host smart-bc4ec008-67f1-44e8-8d52-583db11e8090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347669143 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.347669143
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3524713949
Short name T897
Test name
Test status
Simulation time 2068615414 ps
CPU time 2.04 seconds
Started Jun 22 04:33:54 PM PDT 24
Finished Jun 22 04:33:56 PM PDT 24
Peak memory 200852 kb
Host smart-7c5ceeef-054b-445a-886d-756a100f034c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524713949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.3524713949
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1064686560
Short name T815
Test name
Test status
Simulation time 2045555873 ps
CPU time 1.8 seconds
Started Jun 22 04:33:42 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200496 kb
Host smart-078f917b-ea0c-47a2-887f-cc4ed08281a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064686560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.1064686560
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3619947644
Short name T907
Test name
Test status
Simulation time 4936321588 ps
CPU time 3.44 seconds
Started Jun 22 04:33:51 PM PDT 24
Finished Jun 22 04:33:55 PM PDT 24
Peak memory 201204 kb
Host smart-6c92643f-ad14-48b1-899e-8aaf14d30673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619947644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.3619947644
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2970579467
Short name T872
Test name
Test status
Simulation time 2071452882 ps
CPU time 7.11 seconds
Started Jun 22 04:33:47 PM PDT 24
Finished Jun 22 04:33:55 PM PDT 24
Peak memory 201036 kb
Host smart-0adb627d-7913-4961-a981-950050e356cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970579467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.2970579467
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3011106364
Short name T887
Test name
Test status
Simulation time 42389244718 ps
CPU time 109.63 seconds
Started Jun 22 04:33:32 PM PDT 24
Finished Jun 22 04:35:22 PM PDT 24
Peak memory 201208 kb
Host smart-2a76d95a-f731-4760-9fd0-20dbab97dcfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011106364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.3011106364
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3450445878
Short name T899
Test name
Test status
Simulation time 2231450997 ps
CPU time 2.5 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 201216 kb
Host smart-7cb410fe-eb84-4c22-b3c3-eb65df703b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450445878 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3450445878
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1258664555
Short name T323
Test name
Test status
Simulation time 2069564676 ps
CPU time 2.02 seconds
Started Jun 22 04:33:34 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 200852 kb
Host smart-fd4fae29-4efd-4904-9ba1-b7e1bc556329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258664555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.1258664555
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.316657157
Short name T804
Test name
Test status
Simulation time 2013803727 ps
CPU time 5.37 seconds
Started Jun 22 04:33:30 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 200556 kb
Host smart-f6a5ab1b-8511-4814-a6bb-3fead99877ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316657157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_tes
t.316657157
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.412524141
Short name T841
Test name
Test status
Simulation time 9062439614 ps
CPU time 7.06 seconds
Started Jun 22 04:33:58 PM PDT 24
Finished Jun 22 04:34:06 PM PDT 24
Peak memory 201216 kb
Host smart-8a1ba283-f3d6-4f1f-99ac-9d9226bed729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412524141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.sysrst_ctrl_same_csr_outstanding.412524141
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1628179232
Short name T858
Test name
Test status
Simulation time 2120924791 ps
CPU time 4.55 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 201088 kb
Host smart-5640aaa0-d383-4a84-a94c-d4d5aa550f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628179232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1628179232
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3171319924
Short name T898
Test name
Test status
Simulation time 22263072691 ps
CPU time 15.06 seconds
Started Jun 22 04:33:40 PM PDT 24
Finished Jun 22 04:33:56 PM PDT 24
Peak memory 201204 kb
Host smart-8882e1d7-071c-4baa-8fd1-c4f772432156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171319924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.3171319924
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3118020150
Short name T24
Test name
Test status
Simulation time 2196304740 ps
CPU time 3.67 seconds
Started Jun 22 04:34:02 PM PDT 24
Finished Jun 22 04:34:06 PM PDT 24
Peak memory 201068 kb
Host smart-02bc23ba-fb5a-4fad-8e03-3c30b9dcd58b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118020150 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3118020150
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2561871477
Short name T307
Test name
Test status
Simulation time 2369099354 ps
CPU time 1.31 seconds
Started Jun 22 04:33:57 PM PDT 24
Finished Jun 22 04:34:00 PM PDT 24
Peak memory 200916 kb
Host smart-c300ff84-bd79-40b7-8f8a-548ff5ac88ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561871477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.2561871477
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4249736037
Short name T840
Test name
Test status
Simulation time 2016662211 ps
CPU time 5.8 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200564 kb
Host smart-63390b9d-6d57-4f20-83f0-4aa81b2ad29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249736037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.4249736037
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3729198648
Short name T17
Test name
Test status
Simulation time 9595445682 ps
CPU time 25.46 seconds
Started Jun 22 04:33:36 PM PDT 24
Finished Jun 22 04:34:03 PM PDT 24
Peak memory 201160 kb
Host smart-7f3f4b4a-1ced-4be5-b6d0-811fc03a9a86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729198648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.3729198648
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2406722740
Short name T854
Test name
Test status
Simulation time 2266432673 ps
CPU time 1.58 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 201116 kb
Host smart-690a9818-8635-4cae-845e-f306ba95bc2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406722740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.2406722740
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.386076415
Short name T345
Test name
Test status
Simulation time 42502907603 ps
CPU time 30.42 seconds
Started Jun 22 04:33:53 PM PDT 24
Finished Jun 22 04:34:25 PM PDT 24
Peak memory 201504 kb
Host smart-c574cab9-ef8a-426a-a1a4-88c7d33521da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386076415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.386076415
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3020238184
Short name T911
Test name
Test status
Simulation time 2111984624 ps
CPU time 6.66 seconds
Started Jun 22 04:33:55 PM PDT 24
Finished Jun 22 04:34:02 PM PDT 24
Peak memory 201016 kb
Host smart-8723e845-2a85-41e3-901b-973da5b95310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020238184 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3020238184
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3715071169
Short name T873
Test name
Test status
Simulation time 2024298991 ps
CPU time 5.78 seconds
Started Jun 22 04:33:43 PM PDT 24
Finished Jun 22 04:33:49 PM PDT 24
Peak memory 200912 kb
Host smart-0b399cea-5d58-4535-bc58-2dc8fed1434a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715071169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.3715071169
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3442382284
Short name T817
Test name
Test status
Simulation time 2014934448 ps
CPU time 5.91 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200504 kb
Host smart-17452fab-099d-492a-91d2-c984078c3f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442382284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.3442382284
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.658043510
Short name T878
Test name
Test status
Simulation time 5270806213 ps
CPU time 12.7 seconds
Started Jun 22 04:34:04 PM PDT 24
Finished Jun 22 04:34:18 PM PDT 24
Peak memory 201164 kb
Host smart-24a74f82-6ae0-428d-8bc0-64be2f32af72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658043510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.sysrst_ctrl_same_csr_outstanding.658043510
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3763177913
Short name T280
Test name
Test status
Simulation time 2516876450 ps
CPU time 4.18 seconds
Started Jun 22 04:33:59 PM PDT 24
Finished Jun 22 04:34:04 PM PDT 24
Peak memory 201184 kb
Host smart-94cd4455-c21b-4ea5-97d2-5106aae13c28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763177913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.3763177913
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.818007905
Short name T844
Test name
Test status
Simulation time 22221408208 ps
CPU time 55.87 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:34:47 PM PDT 24
Peak memory 201220 kb
Host smart-ea30d59a-2e24-4be2-ba33-c8f649a892fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818007905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_tl_intg_err.818007905
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3782912652
Short name T807
Test name
Test status
Simulation time 2151332174 ps
CPU time 2.36 seconds
Started Jun 22 04:33:57 PM PDT 24
Finished Jun 22 04:34:01 PM PDT 24
Peak memory 200992 kb
Host smart-7b5787a2-7609-4b4f-ae9b-cc866f094ab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782912652 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3782912652
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1813457149
Short name T868
Test name
Test status
Simulation time 2047011754 ps
CPU time 5.82 seconds
Started Jun 22 04:34:04 PM PDT 24
Finished Jun 22 04:34:11 PM PDT 24
Peak memory 200896 kb
Host smart-4d0dddcd-eb0e-4e57-ba99-3c8156eab0a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813457149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.1813457149
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2263744691
Short name T865
Test name
Test status
Simulation time 2026672281 ps
CPU time 1.88 seconds
Started Jun 22 04:33:44 PM PDT 24
Finished Jun 22 04:33:47 PM PDT 24
Peak memory 200480 kb
Host smart-e8cde9a1-c21b-4cd6-bcfa-afe821028ed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263744691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.2263744691
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.239759933
Short name T828
Test name
Test status
Simulation time 5258703436 ps
CPU time 17.39 seconds
Started Jun 22 04:33:54 PM PDT 24
Finished Jun 22 04:34:12 PM PDT 24
Peak memory 201144 kb
Host smart-8f724f6e-26e5-4b26-8663-884ad367a173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239759933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.sysrst_ctrl_same_csr_outstanding.239759933
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2739853531
Short name T884
Test name
Test status
Simulation time 3362507943 ps
CPU time 3.21 seconds
Started Jun 22 04:33:47 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 201524 kb
Host smart-d98534f8-a9d0-4bd4-ae38-0ca8504c210a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739853531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.2739853531
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1078800890
Short name T849
Test name
Test status
Simulation time 22362895853 ps
CPU time 17.69 seconds
Started Jun 22 04:33:56 PM PDT 24
Finished Jun 22 04:34:15 PM PDT 24
Peak memory 201132 kb
Host smart-955916ae-18f1-4b60-8227-31e889774344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078800890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.1078800890
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.895959541
Short name T309
Test name
Test status
Simulation time 2756394516 ps
CPU time 7.18 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 201064 kb
Host smart-f5cba2e5-659f-47da-bfe2-cc1955f5874b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895959541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_aliasing.895959541
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.811333126
Short name T834
Test name
Test status
Simulation time 39382764915 ps
CPU time 50.62 seconds
Started Jun 22 04:33:36 PM PDT 24
Finished Jun 22 04:34:28 PM PDT 24
Peak memory 201132 kb
Host smart-a19f455a-4940-4581-9c41-343cd062596d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811333126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_bit_bash.811333126
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2447928507
Short name T312
Test name
Test status
Simulation time 4012268566 ps
CPU time 10.98 seconds
Started Jun 22 04:33:36 PM PDT 24
Finished Jun 22 04:33:49 PM PDT 24
Peak memory 200916 kb
Host smart-d8df44cb-f8e0-4ddb-b2e2-327b5283d239
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447928507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.2447928507
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1528445653
Short name T900
Test name
Test status
Simulation time 2073742302 ps
CPU time 6.13 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:33 PM PDT 24
Peak memory 201012 kb
Host smart-52958170-b91b-4ac3-909d-846f767bcef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528445653 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1528445653
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2724798229
Short name T901
Test name
Test status
Simulation time 2130832500 ps
CPU time 1.67 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 200852 kb
Host smart-df77ffbe-cffe-4991-9eca-cd5abaf02962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724798229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.2724798229
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.631111910
Short name T888
Test name
Test status
Simulation time 2015789266 ps
CPU time 5.59 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:34 PM PDT 24
Peak memory 200556 kb
Host smart-ef4204db-6829-4491-a698-add4e62a4037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631111910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test
.631111910
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3355666317
Short name T809
Test name
Test status
Simulation time 5171337481 ps
CPU time 9.66 seconds
Started Jun 22 04:33:47 PM PDT 24
Finished Jun 22 04:33:58 PM PDT 24
Peak memory 201148 kb
Host smart-21f43631-1410-40ce-b14a-8f293f53d5b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355666317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.3355666317
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2263790792
Short name T855
Test name
Test status
Simulation time 2104312185 ps
CPU time 4.09 seconds
Started Jun 22 04:33:24 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 201116 kb
Host smart-cd1dc04a-cd52-4311-bc67-6568fa8f3d12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263790792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.2263790792
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3987799640
Short name T816
Test name
Test status
Simulation time 42386722891 ps
CPU time 105.39 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:35:18 PM PDT 24
Peak memory 201448 kb
Host smart-a8c61c29-7a41-4655-8e86-c9d46032c5e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987799640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.3987799640
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2016700393
Short name T846
Test name
Test status
Simulation time 2018521735 ps
CPU time 3.21 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:33:54 PM PDT 24
Peak memory 200772 kb
Host smart-a922eefe-4b14-4484-96e1-6b07b3b0fc07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016700393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2016700393
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2943182579
Short name T820
Test name
Test status
Simulation time 2125548388 ps
CPU time 1.06 seconds
Started Jun 22 04:33:55 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200772 kb
Host smart-34128457-660d-44a7-a6dc-609c3fbe7ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943182579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.2943182579
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2355978489
Short name T810
Test name
Test status
Simulation time 2063805565 ps
CPU time 1.35 seconds
Started Jun 22 04:33:55 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200568 kb
Host smart-e4a0d292-3d86-418b-a6a9-c5fb2622f7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355978489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2355978489
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3279805127
Short name T885
Test name
Test status
Simulation time 2035181664 ps
CPU time 2.09 seconds
Started Jun 22 04:33:46 PM PDT 24
Finished Jun 22 04:33:50 PM PDT 24
Peak memory 200772 kb
Host smart-da3b4148-9854-4623-9ffc-971a5da67aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279805127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.3279805127
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3515279611
Short name T867
Test name
Test status
Simulation time 2050971200 ps
CPU time 1.86 seconds
Started Jun 22 04:33:54 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200768 kb
Host smart-a0a0ff6e-cffd-4c99-acaa-8eb6b837469c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515279611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.3515279611
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2604225767
Short name T839
Test name
Test status
Simulation time 2013837927 ps
CPU time 3.27 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:33:54 PM PDT 24
Peak memory 200560 kb
Host smart-6204a7c5-eddc-4885-94e2-4fe0d6a7fde9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604225767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.2604225767
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3271153328
Short name T821
Test name
Test status
Simulation time 2042957642 ps
CPU time 1.84 seconds
Started Jun 22 04:33:42 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200460 kb
Host smart-dd8636d2-bfe9-4ec2-88e4-c68cb1cb2280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271153328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3271153328
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.999507248
Short name T799
Test name
Test status
Simulation time 2015138599 ps
CPU time 6.09 seconds
Started Jun 22 04:33:57 PM PDT 24
Finished Jun 22 04:34:04 PM PDT 24
Peak memory 200556 kb
Host smart-2be99529-12b4-46c4-99a8-29df559479fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999507248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_tes
t.999507248
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1386011410
Short name T825
Test name
Test status
Simulation time 2016128432 ps
CPU time 5.34 seconds
Started Jun 22 04:34:04 PM PDT 24
Finished Jun 22 04:34:11 PM PDT 24
Peak memory 200556 kb
Host smart-46a2c32f-742a-4e33-a9bc-22e7d177490e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386011410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.1386011410
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2128230564
Short name T805
Test name
Test status
Simulation time 2124152420 ps
CPU time 0.87 seconds
Started Jun 22 04:34:05 PM PDT 24
Finished Jun 22 04:34:09 PM PDT 24
Peak memory 200556 kb
Host smart-36e54030-6baa-469f-bd29-858174ecaccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128230564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.2128230564
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.944956700
Short name T318
Test name
Test status
Simulation time 3196153815 ps
CPU time 10.97 seconds
Started Jun 22 04:33:28 PM PDT 24
Finished Jun 22 04:33:50 PM PDT 24
Peak memory 201332 kb
Host smart-7ac30b32-74d4-41ac-8ecd-888320628d66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944956700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.944956700
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1094436374
Short name T314
Test name
Test status
Simulation time 32223559728 ps
CPU time 21.66 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 201144 kb
Host smart-26c72791-bd8b-4218-bccc-f3e249f3302a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094436374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.1094436374
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2114011828
Short name T311
Test name
Test status
Simulation time 4011204302 ps
CPU time 10.08 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:40 PM PDT 24
Peak memory 200916 kb
Host smart-ced55a65-150c-40dd-b2e4-bb60e3743cd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114011828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.2114011828
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2695518884
Short name T879
Test name
Test status
Simulation time 2124475735 ps
CPU time 2.39 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:33:31 PM PDT 24
Peak memory 209356 kb
Host smart-bc10a2e7-ce4c-4708-b133-aa3a245fd8fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695518884 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2695518884
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2831256479
Short name T316
Test name
Test status
Simulation time 2052842220 ps
CPU time 6.06 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:38 PM PDT 24
Peak memory 200940 kb
Host smart-949798a1-66bd-454d-b49d-23cf2045d3bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831256479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.2831256479
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1611021028
Short name T808
Test name
Test status
Simulation time 2010817306 ps
CPU time 5.63 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:35 PM PDT 24
Peak memory 200572 kb
Host smart-e9cae24d-eaba-49b6-b20b-df7932811350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611021028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1611021028
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2401181287
Short name T869
Test name
Test status
Simulation time 5385091724 ps
CPU time 7.25 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 201120 kb
Host smart-a76e9097-01b4-4ebf-8fe3-bb86811436e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401181287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.2401181287
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3909272046
Short name T292
Test name
Test status
Simulation time 2187438761 ps
CPU time 5.94 seconds
Started Jun 22 04:33:36 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200968 kb
Host smart-feac44cc-fc45-4f9d-826f-7b54a8d5caeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909272046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.3909272046
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2323417053
Short name T906
Test name
Test status
Simulation time 22407898008 ps
CPU time 15.21 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:34:05 PM PDT 24
Peak memory 201220 kb
Host smart-35d68820-2017-49c6-a352-da23b8efbcbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323417053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.2323417053
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2208131300
Short name T850
Test name
Test status
Simulation time 2041331471 ps
CPU time 1.92 seconds
Started Jun 22 04:33:56 PM PDT 24
Finished Jun 22 04:33:59 PM PDT 24
Peak memory 200572 kb
Host smart-4198669a-3391-4993-8650-38e1a99d0a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208131300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.2208131300
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.709665770
Short name T895
Test name
Test status
Simulation time 2020736412 ps
CPU time 2.77 seconds
Started Jun 22 04:33:44 PM PDT 24
Finished Jun 22 04:33:47 PM PDT 24
Peak memory 200604 kb
Host smart-042fa4a3-af72-498f-9835-707873785ce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709665770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_tes
t.709665770
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1329831457
Short name T798
Test name
Test status
Simulation time 2041243323 ps
CPU time 2.11 seconds
Started Jun 22 04:33:40 PM PDT 24
Finished Jun 22 04:33:43 PM PDT 24
Peak memory 200564 kb
Host smart-b87b2e03-a5cd-4f69-b176-3e2dda5669a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329831457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.1329831457
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3202867271
Short name T916
Test name
Test status
Simulation time 2049831123 ps
CPU time 1.62 seconds
Started Jun 22 04:33:51 PM PDT 24
Finished Jun 22 04:33:54 PM PDT 24
Peak memory 200776 kb
Host smart-a5798307-a309-4c3c-843c-7b632fc400d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202867271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.3202867271
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2581877724
Short name T893
Test name
Test status
Simulation time 2020657916 ps
CPU time 2.98 seconds
Started Jun 22 04:33:54 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200552 kb
Host smart-45cd967c-93dd-4c6f-9e06-1a85e1f2853f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581877724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.2581877724
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.457941061
Short name T802
Test name
Test status
Simulation time 2013391015 ps
CPU time 5.39 seconds
Started Jun 22 04:33:47 PM PDT 24
Finished Jun 22 04:33:54 PM PDT 24
Peak memory 200540 kb
Host smart-689349bb-a3b3-4170-882c-b4be307198a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457941061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_tes
t.457941061
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.4045027214
Short name T832
Test name
Test status
Simulation time 2037324176 ps
CPU time 1.82 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 200560 kb
Host smart-f219cfee-d2ab-457a-bbb6-52601d9327f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045027214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.4045027214
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2323141927
Short name T902
Test name
Test status
Simulation time 2072783883 ps
CPU time 1.65 seconds
Started Jun 22 04:33:54 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200600 kb
Host smart-f852e2a2-f4c1-48f8-bc95-a6925647bef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323141927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.2323141927
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1365434431
Short name T801
Test name
Test status
Simulation time 2012436665 ps
CPU time 4.32 seconds
Started Jun 22 04:33:59 PM PDT 24
Finished Jun 22 04:34:05 PM PDT 24
Peak memory 200548 kb
Host smart-70caa6ec-27bb-43ee-8621-be8e7d35f1a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365434431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.1365434431
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2027561803
Short name T852
Test name
Test status
Simulation time 2046074916 ps
CPU time 1.89 seconds
Started Jun 22 04:33:56 PM PDT 24
Finished Jun 22 04:33:59 PM PDT 24
Peak memory 200516 kb
Host smart-89cdd60c-144d-4e86-9e57-b3628b3a2085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027561803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.2027561803
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.51596352
Short name T896
Test name
Test status
Simulation time 2514399862 ps
CPU time 8.32 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:33:37 PM PDT 24
Peak memory 201108 kb
Host smart-835d48a6-f04c-42f1-a6a9-ecd00c3355f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51596352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_c
sr_aliasing.51596352
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3159460811
Short name T829
Test name
Test status
Simulation time 75343505358 ps
CPU time 79.25 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:34:48 PM PDT 24
Peak memory 201216 kb
Host smart-942f087b-76e9-4ba1-bcf9-f53ef8e328bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159460811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.3159460811
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2258622589
Short name T813
Test name
Test status
Simulation time 6033344158 ps
CPU time 15.15 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:43 PM PDT 24
Peak memory 201072 kb
Host smart-03b4635a-cdc2-4111-b39a-f207ff2426e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258622589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.2258622589
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1779972417
Short name T819
Test name
Test status
Simulation time 2201586267 ps
CPU time 1.08 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:31 PM PDT 24
Peak memory 201076 kb
Host smart-8c4caf27-eef4-434c-b49c-1dcc71fa81ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779972417 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1779972417
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3125691802
Short name T319
Test name
Test status
Simulation time 2114984516 ps
CPU time 2.11 seconds
Started Jun 22 04:33:28 PM PDT 24
Finished Jun 22 04:33:31 PM PDT 24
Peak memory 200948 kb
Host smart-62f80c8c-bb15-42a9-aa0a-b44c1ad92b1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125691802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3125691802
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2377787231
Short name T836
Test name
Test status
Simulation time 2102512567 ps
CPU time 1.19 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 200608 kb
Host smart-9c187327-5a0f-4557-82cd-a0d1425e1f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377787231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.2377787231
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3346586509
Short name T18
Test name
Test status
Simulation time 10237368068 ps
CPU time 7.39 seconds
Started Jun 22 04:33:45 PM PDT 24
Finished Jun 22 04:33:53 PM PDT 24
Peak memory 201184 kb
Host smart-9e34da41-8c11-45ac-ab75-d3fcd2aae04c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346586509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.3346586509
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1579365556
Short name T822
Test name
Test status
Simulation time 2103175478 ps
CPU time 2.96 seconds
Started Jun 22 04:33:37 PM PDT 24
Finished Jun 22 04:33:41 PM PDT 24
Peak memory 201080 kb
Host smart-9d88ee33-a538-4a7a-98d9-0ac861656a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579365556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.1579365556
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3087749047
Short name T347
Test name
Test status
Simulation time 22199036930 ps
CPU time 43.14 seconds
Started Jun 22 04:33:38 PM PDT 24
Finished Jun 22 04:34:22 PM PDT 24
Peak memory 201168 kb
Host smart-a711601b-de0c-4208-830f-fc4382c4582b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087749047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.3087749047
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3768853124
Short name T806
Test name
Test status
Simulation time 2017106699 ps
CPU time 2.98 seconds
Started Jun 22 04:34:09 PM PDT 24
Finished Jun 22 04:34:15 PM PDT 24
Peak memory 200556 kb
Host smart-abf98a32-459d-4d52-b8ec-e1a523afe48d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768853124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.3768853124
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3829402792
Short name T913
Test name
Test status
Simulation time 2141508363 ps
CPU time 0.89 seconds
Started Jun 22 04:33:46 PM PDT 24
Finished Jun 22 04:33:48 PM PDT 24
Peak memory 200836 kb
Host smart-dad69694-4be8-4499-9069-9a87534ba33b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829402792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3829402792
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.810440259
Short name T881
Test name
Test status
Simulation time 2014241266 ps
CPU time 6.04 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200548 kb
Host smart-0b44a05f-af8e-4b80-a18c-606925a9f286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810440259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_tes
t.810440259
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1254763536
Short name T848
Test name
Test status
Simulation time 2012638939 ps
CPU time 5.98 seconds
Started Jun 22 04:33:53 PM PDT 24
Finished Jun 22 04:34:00 PM PDT 24
Peak memory 200540 kb
Host smart-d830dfbf-b3cb-4a8e-b0c8-23147e3bb3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254763536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.1254763536
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3219562995
Short name T905
Test name
Test status
Simulation time 2040660820 ps
CPU time 1.57 seconds
Started Jun 22 04:33:46 PM PDT 24
Finished Jun 22 04:33:49 PM PDT 24
Peak memory 200768 kb
Host smart-f3ea137a-6941-4102-ab70-bfeae9312572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219562995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.3219562995
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.858261918
Short name T891
Test name
Test status
Simulation time 2020133148 ps
CPU time 3.16 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:33:54 PM PDT 24
Peak memory 200556 kb
Host smart-aa84e409-64a5-4ce6-b013-c88cc4ea65f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858261918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_tes
t.858261918
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.206453290
Short name T864
Test name
Test status
Simulation time 2011391415 ps
CPU time 5.22 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:33:55 PM PDT 24
Peak memory 200772 kb
Host smart-8074ae5a-9fe4-450d-b6e1-2740f45be170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206453290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_tes
t.206453290
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3391146851
Short name T818
Test name
Test status
Simulation time 2012138109 ps
CPU time 5.46 seconds
Started Jun 22 04:33:51 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200556 kb
Host smart-00d22337-c6f4-40c7-9f12-37f5765627f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391146851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3391146851
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1603728819
Short name T831
Test name
Test status
Simulation time 2020067248 ps
CPU time 3.12 seconds
Started Jun 22 04:34:03 PM PDT 24
Finished Jun 22 04:34:07 PM PDT 24
Peak memory 200556 kb
Host smart-c18657ab-6091-40f9-8ff7-fa51cec09355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603728819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.1603728819
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1410656299
Short name T877
Test name
Test status
Simulation time 2016386883 ps
CPU time 5.28 seconds
Started Jun 22 04:33:48 PM PDT 24
Finished Jun 22 04:33:54 PM PDT 24
Peak memory 200560 kb
Host smart-0849a1c1-4216-47ea-a255-b8ab4e7770c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410656299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1410656299
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2406555123
Short name T830
Test name
Test status
Simulation time 2114432959 ps
CPU time 2.12 seconds
Started Jun 22 04:33:49 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 200920 kb
Host smart-38e0bf48-cb60-46e8-ac23-2218c02559e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406555123 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2406555123
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2377991035
Short name T909
Test name
Test status
Simulation time 2059224267 ps
CPU time 6 seconds
Started Jun 22 04:33:52 PM PDT 24
Finished Jun 22 04:33:58 PM PDT 24
Peak memory 200840 kb
Host smart-68339a21-df03-49ca-9492-336a2b5aab7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377991035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.2377991035
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.919321836
Short name T812
Test name
Test status
Simulation time 2023956026 ps
CPU time 3.1 seconds
Started Jun 22 04:33:28 PM PDT 24
Finished Jun 22 04:33:33 PM PDT 24
Peak memory 200808 kb
Host smart-4686de61-f5b9-43c1-8507-fcab095c7d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919321836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.919321836
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.663699667
Short name T894
Test name
Test status
Simulation time 7577782542 ps
CPU time 17.42 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:33:46 PM PDT 24
Peak memory 201224 kb
Host smart-32d8ed23-e9d9-447c-a7ad-a1cb81a09f38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663699667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
sysrst_ctrl_same_csr_outstanding.663699667
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2812038836
Short name T281
Test name
Test status
Simulation time 2204190338 ps
CPU time 4.78 seconds
Started Jun 22 04:33:47 PM PDT 24
Finished Jun 22 04:33:53 PM PDT 24
Peak memory 209316 kb
Host smart-dbb7b29b-40a2-439b-a4e6-7b324b3c86d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812038836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2812038836
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2592631046
Short name T287
Test name
Test status
Simulation time 22355206180 ps
CPU time 23.28 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:34:14 PM PDT 24
Peak memory 201144 kb
Host smart-411e6b2e-5e5b-4e42-9889-a8014b3d2315
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592631046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.2592631046
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1359931237
Short name T823
Test name
Test status
Simulation time 2221585994 ps
CPU time 1.44 seconds
Started Jun 22 04:33:41 PM PDT 24
Finished Jun 22 04:33:43 PM PDT 24
Peak memory 201028 kb
Host smart-f96a1fcf-7925-48e4-8452-c0bf346ed304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359931237 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1359931237
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1571855460
Short name T886
Test name
Test status
Simulation time 2058194280 ps
CPU time 5.98 seconds
Started Jun 22 04:33:46 PM PDT 24
Finished Jun 22 04:33:53 PM PDT 24
Peak memory 200848 kb
Host smart-0ed4d1be-0c7a-4b3d-b6f1-6f9b428d84cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571855460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.1571855460
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.259377131
Short name T837
Test name
Test status
Simulation time 2031142297 ps
CPU time 2.07 seconds
Started Jun 22 04:34:02 PM PDT 24
Finished Jun 22 04:34:05 PM PDT 24
Peak memory 200556 kb
Host smart-ba2ccc49-2fb2-4ca7-accb-700de60f0aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259377131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test
.259377131
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.706454316
Short name T889
Test name
Test status
Simulation time 7431119565 ps
CPU time 8.62 seconds
Started Jun 22 04:33:38 PM PDT 24
Finished Jun 22 04:33:47 PM PDT 24
Peak memory 201028 kb
Host smart-19e39541-89bf-49d3-aead-c7ef3b4cbc46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706454316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_same_csr_outstanding.706454316
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2000575844
Short name T861
Test name
Test status
Simulation time 22225386208 ps
CPU time 57.52 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:34:27 PM PDT 24
Peak memory 201204 kb
Host smart-f3e608eb-ff1a-4203-b7f1-0b5716c48aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000575844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.2000575844
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3665503093
Short name T910
Test name
Test status
Simulation time 2087303329 ps
CPU time 5.73 seconds
Started Jun 22 04:33:44 PM PDT 24
Finished Jun 22 04:33:51 PM PDT 24
Peak memory 200916 kb
Host smart-f5966e4d-8641-4b6a-8d2e-9592b51e6436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665503093 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3665503093
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1049295199
Short name T860
Test name
Test status
Simulation time 2134761309 ps
CPU time 1.56 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:33:53 PM PDT 24
Peak memory 200940 kb
Host smart-f42a456a-1ab8-428e-bc62-4042bc976ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049295199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.1049295199
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2594305090
Short name T880
Test name
Test status
Simulation time 2010309394 ps
CPU time 5.86 seconds
Started Jun 22 04:33:30 PM PDT 24
Finished Jun 22 04:33:37 PM PDT 24
Peak memory 200560 kb
Host smart-4e02e0f7-d53b-4474-837b-65f94d4eeea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594305090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.2594305090
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1429383753
Short name T290
Test name
Test status
Simulation time 2037347832 ps
CPU time 7.13 seconds
Started Jun 22 04:33:30 PM PDT 24
Finished Jun 22 04:33:38 PM PDT 24
Peak memory 201012 kb
Host smart-2f1ce3f0-d722-4b62-872c-102978399d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429383753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1429383753
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3121661720
Short name T293
Test name
Test status
Simulation time 42404149173 ps
CPU time 106.32 seconds
Started Jun 22 04:33:43 PM PDT 24
Finished Jun 22 04:35:29 PM PDT 24
Peak memory 200864 kb
Host smart-23bab50d-8fad-4a8a-96ee-0a9d5d85613b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121661720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.3121661720
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3874818702
Short name T800
Test name
Test status
Simulation time 2063566072 ps
CPU time 5.72 seconds
Started Jun 22 04:33:43 PM PDT 24
Finished Jun 22 04:33:50 PM PDT 24
Peak memory 200980 kb
Host smart-82f9775d-b72f-4a8f-914f-7171a9b418b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874818702 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3874818702
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2838801769
Short name T908
Test name
Test status
Simulation time 2067134012 ps
CPU time 1.94 seconds
Started Jun 22 04:33:30 PM PDT 24
Finished Jun 22 04:33:33 PM PDT 24
Peak memory 200848 kb
Host smart-d0751e58-dfe6-47ad-9e3d-359f5b1a7c87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838801769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.2838801769
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3806062214
Short name T856
Test name
Test status
Simulation time 2029625240 ps
CPU time 1.86 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 200624 kb
Host smart-474acd76-45d0-4e7e-bb67-675eaa9d5444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806062214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.3806062214
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.166751116
Short name T324
Test name
Test status
Simulation time 5204516814 ps
CPU time 14.42 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:46 PM PDT 24
Peak memory 201164 kb
Host smart-c04856cd-c828-4716-89c7-1b7baa12c8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166751116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
sysrst_ctrl_same_csr_outstanding.166751116
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3396443826
Short name T826
Test name
Test status
Simulation time 2077551821 ps
CPU time 4.84 seconds
Started Jun 22 04:33:46 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 201036 kb
Host smart-6f314463-b7d5-4da2-9edc-6f20374ca066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396443826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.3396443826
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1659046574
Short name T346
Test name
Test status
Simulation time 42548135968 ps
CPU time 61.92 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:34:31 PM PDT 24
Peak memory 201216 kb
Host smart-a4962df8-e3d3-4d85-bab1-414d0471808f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659046574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1659046574
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1038603541
Short name T857
Test name
Test status
Simulation time 2174878380 ps
CPU time 1.94 seconds
Started Jun 22 04:33:35 PM PDT 24
Finished Jun 22 04:33:38 PM PDT 24
Peak memory 200984 kb
Host smart-aca788b9-0e5a-464e-bafd-0d7531ce6f90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038603541 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1038603541
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.783356048
Short name T890
Test name
Test status
Simulation time 2053294847 ps
CPU time 6.22 seconds
Started Jun 22 04:33:52 PM PDT 24
Finished Jun 22 04:33:59 PM PDT 24
Peak memory 200884 kb
Host smart-dc09062e-cc57-425a-9354-fff11b21eb70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783356048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw
.783356048
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3048277197
Short name T892
Test name
Test status
Simulation time 2066197873 ps
CPU time 1.4 seconds
Started Jun 22 04:33:47 PM PDT 24
Finished Jun 22 04:33:50 PM PDT 24
Peak memory 200560 kb
Host smart-832f1797-d0e4-418c-b664-36051cc4e1f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048277197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.3048277197
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.63198865
Short name T320
Test name
Test status
Simulation time 4639477098 ps
CPU time 16.64 seconds
Started Jun 22 04:33:35 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 201216 kb
Host smart-1973ffcc-b05a-447c-99dd-f98eac1c7dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63198865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=
sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
ysrst_ctrl_same_csr_outstanding.63198865
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.349482532
Short name T289
Test name
Test status
Simulation time 2120314529 ps
CPU time 3.01 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:35 PM PDT 24
Peak memory 201052 kb
Host smart-83319370-5c0a-40ed-bd9d-432641421e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349482532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors
.349482532
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2578081937
Short name T843
Test name
Test status
Simulation time 42436152107 ps
CPU time 50.65 seconds
Started Jun 22 04:33:37 PM PDT 24
Finished Jun 22 04:34:29 PM PDT 24
Peak memory 201168 kb
Host smart-89dfd51d-7ba1-430f-ac65-cbfc889a55c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578081937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2578081937
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2090767464
Short name T509
Test name
Test status
Simulation time 54224133427 ps
CPU time 124.61 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:53:37 PM PDT 24
Peak memory 201208 kb
Host smart-fbb5b9e0-ad85-4b2a-a676-cd3907b269b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090767464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.2090767464
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.1552278294
Short name T773
Test name
Test status
Simulation time 134040193398 ps
CPU time 349.6 seconds
Started Jun 22 04:51:29 PM PDT 24
Finished Jun 22 04:57:20 PM PDT 24
Peak memory 201384 kb
Host smart-72221ade-7b19-4938-bb1c-e5ed99636c15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552278294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.1552278294
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1471008720
Short name T204
Test name
Test status
Simulation time 2431856841 ps
CPU time 6.51 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201252 kb
Host smart-1df7b41e-71c8-4140-ab12-42bbcb6afa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471008720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.1471008720
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.599993800
Short name T100
Test name
Test status
Simulation time 2549393930 ps
CPU time 2.21 seconds
Started Jun 22 04:51:33 PM PDT 24
Finished Jun 22 04:51:36 PM PDT 24
Peak memory 201248 kb
Host smart-2eaa1bd9-60d9-4926-9970-c3e1449bef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599993800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.599993800
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1312008305
Short name T720
Test name
Test status
Simulation time 3508292360 ps
CPU time 5.77 seconds
Started Jun 22 04:51:35 PM PDT 24
Finished Jun 22 04:51:41 PM PDT 24
Peak memory 201076 kb
Host smart-d157bc84-a562-4a55-a99b-bdcfe2aa0856
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312008305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.1312008305
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.3165726788
Short name T728
Test name
Test status
Simulation time 6352768060 ps
CPU time 10.4 seconds
Started Jun 22 04:51:29 PM PDT 24
Finished Jun 22 04:51:41 PM PDT 24
Peak memory 201220 kb
Host smart-b7e2ae54-603b-4378-b3a5-36f7bff5e223
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165726788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.3165726788
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3459638284
Short name T788
Test name
Test status
Simulation time 2611961090 ps
CPU time 6.99 seconds
Started Jun 22 04:51:31 PM PDT 24
Finished Jun 22 04:51:39 PM PDT 24
Peak memory 201144 kb
Host smart-c9a5753d-04ad-4f17-af2c-8125dd164b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459638284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3459638284
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1782763285
Short name T554
Test name
Test status
Simulation time 2479032672 ps
CPU time 2.15 seconds
Started Jun 22 04:51:31 PM PDT 24
Finished Jun 22 04:51:34 PM PDT 24
Peak memory 201256 kb
Host smart-1ccdc03b-786f-4d29-ba03-16125db14a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782763285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1782763285
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3851925686
Short name T211
Test name
Test status
Simulation time 2230771591 ps
CPU time 1.93 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:37 PM PDT 24
Peak memory 201244 kb
Host smart-d657b085-13ba-493a-96e4-1390d8031e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851925686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.3851925686
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2943530416
Short name T273
Test name
Test status
Simulation time 2517602186 ps
CPU time 4.2 seconds
Started Jun 22 04:51:31 PM PDT 24
Finished Jun 22 04:51:36 PM PDT 24
Peak memory 201296 kb
Host smart-541aae88-ef54-4676-a4ad-90d6f3b68e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943530416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2943530416
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.1164452899
Short name T682
Test name
Test status
Simulation time 2136075778 ps
CPU time 2.14 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:37 PM PDT 24
Peak memory 201136 kb
Host smart-8bb9cf5d-3d8e-48aa-a816-83d79720c46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164452899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.1164452899
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2544983401
Short name T545
Test name
Test status
Simulation time 19221219792 ps
CPU time 36.12 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:52:22 PM PDT 24
Peak memory 209556 kb
Host smart-24a4f870-8781-4496-a9b6-b0d198766f2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544983401 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2544983401
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3916032069
Short name T202
Test name
Test status
Simulation time 11000093380 ps
CPU time 6.83 seconds
Started Jun 22 04:51:35 PM PDT 24
Finished Jun 22 04:51:43 PM PDT 24
Peak memory 201232 kb
Host smart-b1941512-3dd4-4d37-96cf-6547deba1b45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916032069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.3916032069
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.3154137966
Short name T415
Test name
Test status
Simulation time 2012369248 ps
CPU time 5.5 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:51:44 PM PDT 24
Peak memory 201232 kb
Host smart-ecb167dd-1d96-4432-a204-ee0aaa6a0c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154137966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.3154137966
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1311413289
Short name T466
Test name
Test status
Simulation time 326587853852 ps
CPU time 272.54 seconds
Started Jun 22 04:51:33 PM PDT 24
Finished Jun 22 04:56:06 PM PDT 24
Peak memory 201312 kb
Host smart-39de7925-605a-48b3-87bb-2119480468bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311413289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1311413289
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1420597288
Short name T257
Test name
Test status
Simulation time 2206231774 ps
CPU time 1.61 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:37 PM PDT 24
Peak memory 201192 kb
Host smart-58247129-7c12-46d6-ac7a-516c55bf2cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420597288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1420597288
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3248986956
Short name T527
Test name
Test status
Simulation time 2368963638 ps
CPU time 1.28 seconds
Started Jun 22 04:51:41 PM PDT 24
Finished Jun 22 04:51:43 PM PDT 24
Peak memory 201256 kb
Host smart-4fd1b96e-0f23-45b8-8bc8-4f38922d4cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248986956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3248986956
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2166499855
Short name T87
Test name
Test status
Simulation time 24106453196 ps
CPU time 16.35 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201572 kb
Host smart-6e6685a5-608c-4d2d-997a-dd10dab091af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166499855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2166499855
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.4241787642
Short name T534
Test name
Test status
Simulation time 4405872363 ps
CPU time 11.54 seconds
Started Jun 22 04:51:31 PM PDT 24
Finished Jun 22 04:51:43 PM PDT 24
Peak memory 201228 kb
Host smart-62c80b66-2b29-4f8c-864f-d5a2f2912f7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241787642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.4241787642
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.2544927583
Short name T504
Test name
Test status
Simulation time 3181713531 ps
CPU time 3.64 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:51:41 PM PDT 24
Peak memory 201268 kb
Host smart-925f56d9-c18b-4aff-ad30-fc72fc301a06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544927583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.2544927583
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.33148118
Short name T461
Test name
Test status
Simulation time 2626630949 ps
CPU time 2.03 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:37 PM PDT 24
Peak memory 201200 kb
Host smart-e8c41e69-f99e-48e4-83ec-f6143841d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33148118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.33148118
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.1410903848
Short name T738
Test name
Test status
Simulation time 2517912016 ps
CPU time 2.13 seconds
Started Jun 22 04:51:31 PM PDT 24
Finished Jun 22 04:51:34 PM PDT 24
Peak memory 201256 kb
Host smart-7c13b595-d217-489b-9fd7-0a725422764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410903848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.1410903848
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.4103688332
Short name T401
Test name
Test status
Simulation time 2241024210 ps
CPU time 6.42 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:39 PM PDT 24
Peak memory 201248 kb
Host smart-06087943-bd4e-4d62-b0bd-3ee0713b9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103688332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.4103688332
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1880896720
Short name T623
Test name
Test status
Simulation time 2512785567 ps
CPU time 6.68 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201272 kb
Host smart-b6401614-81dc-40e6-bbfa-5e29be27f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880896720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1880896720
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2315568170
Short name T139
Test name
Test status
Simulation time 42196583660 ps
CPU time 26.59 seconds
Started Jun 22 04:51:36 PM PDT 24
Finished Jun 22 04:52:04 PM PDT 24
Peak memory 220892 kb
Host smart-923d1415-ebd7-477e-bab8-2423370db8af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315568170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2315568170
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.1163456691
Short name T658
Test name
Test status
Simulation time 2127689980 ps
CPU time 2.13 seconds
Started Jun 22 04:51:29 PM PDT 24
Finished Jun 22 04:51:32 PM PDT 24
Peak memory 201164 kb
Host smart-0df3f770-7e37-4df2-8659-611d63ff03a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163456691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.1163456691
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1286428638
Short name T615
Test name
Test status
Simulation time 11533260070 ps
CPU time 28.13 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:52:13 PM PDT 24
Peak memory 201280 kb
Host smart-83e33c4e-256c-4c04-9c44-53d18a7ce39d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286428638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1286428638
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1934072337
Short name T192
Test name
Test status
Simulation time 5323686715 ps
CPU time 4.09 seconds
Started Jun 22 04:51:36 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201188 kb
Host smart-026ecaff-0c4e-460b-91c7-a9c0b4e290ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934072337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.1934072337
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.517382623
Short name T655
Test name
Test status
Simulation time 2050133103 ps
CPU time 1.29 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201224 kb
Host smart-68d213e3-7b4b-4de9-9df2-9d32217be6e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517382623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_tes
t.517382623
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2519790264
Short name T770
Test name
Test status
Simulation time 4119095878 ps
CPU time 2.48 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:51:53 PM PDT 24
Peak memory 201172 kb
Host smart-74bfbb47-189f-4ad1-aac0-c23e3fbbe2e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519790264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.2519790264
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.665976441
Short name T32
Test name
Test status
Simulation time 5216406535 ps
CPU time 6.2 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:04 PM PDT 24
Peak memory 201268 kb
Host smart-0bc25770-ab6f-408d-901c-2247f8ecb6a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665976441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctr
l_edge_detect.665976441
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.656860150
Short name T380
Test name
Test status
Simulation time 2630267292 ps
CPU time 3.06 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 201240 kb
Host smart-cb349e86-c1fa-4b94-b31d-e8cad0524bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656860150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.656860150
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3281261486
Short name T193
Test name
Test status
Simulation time 2470510558 ps
CPU time 1.83 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201236 kb
Host smart-4e93c177-efd6-4dba-9ae7-f690c7688b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281261486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.3281261486
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3839732194
Short name T540
Test name
Test status
Simulation time 2198667666 ps
CPU time 2.05 seconds
Started Jun 22 04:51:56 PM PDT 24
Finished Jun 22 04:51:59 PM PDT 24
Peak memory 201232 kb
Host smart-193f02ed-22db-4ad0-b43b-d49afde75f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839732194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3839732194
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3468877747
Short name T792
Test name
Test status
Simulation time 2528895775 ps
CPU time 2.42 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201316 kb
Host smart-2ad9f0ea-4c77-4bf1-bd2e-ddce24e5bc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468877747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3468877747
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.546054706
Short name T436
Test name
Test status
Simulation time 2112376570 ps
CPU time 5.68 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:13 PM PDT 24
Peak memory 201100 kb
Host smart-923ab91e-09e8-4e86-9c23-30ce02124f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546054706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.546054706
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.1763565126
Short name T452
Test name
Test status
Simulation time 295324765722 ps
CPU time 101.95 seconds
Started Jun 22 04:51:52 PM PDT 24
Finished Jun 22 04:53:35 PM PDT 24
Peak memory 201292 kb
Host smart-63d64e7b-c142-4b8c-ad44-d559d93a2bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763565126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.1763565126
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2421471761
Short name T118
Test name
Test status
Simulation time 1237056443681 ps
CPU time 113.63 seconds
Started Jun 22 04:51:53 PM PDT 24
Finished Jun 22 04:53:47 PM PDT 24
Peak memory 201300 kb
Host smart-64e47528-d904-4a90-98a1-ffa4bd513c97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421471761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.2421471761
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.597982769
Short name T638
Test name
Test status
Simulation time 2032921483 ps
CPU time 1.79 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201224 kb
Host smart-22f9e5d0-d62d-44a4-9217-7c67f1546142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597982769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_tes
t.597982769
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2431062075
Short name T633
Test name
Test status
Simulation time 3376369395 ps
CPU time 9.76 seconds
Started Jun 22 04:51:55 PM PDT 24
Finished Jun 22 04:52:05 PM PDT 24
Peak memory 201292 kb
Host smart-eef1beca-5cbf-48f8-b60d-cdb0e204d782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431062075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
431062075
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.41740246
Short name T264
Test name
Test status
Simulation time 127407477178 ps
CPU time 320.73 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:57:19 PM PDT 24
Peak memory 201420 kb
Host smart-134aded3-6ec3-4d49-8a53-b75024f544f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41740246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctr
l_combo_detect.41740246
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3972402357
Short name T42
Test name
Test status
Simulation time 97342663674 ps
CPU time 24.47 seconds
Started Jun 22 04:52:03 PM PDT 24
Finished Jun 22 04:52:28 PM PDT 24
Peak memory 201588 kb
Host smart-875c1fae-bdab-4c9e-a2e9-e1a6b89d9278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972402357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.3972402357
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.472941119
Short name T526
Test name
Test status
Simulation time 2757834727 ps
CPU time 2.27 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:51:53 PM PDT 24
Peak memory 201228 kb
Host smart-9250c53e-dd12-4bd3-b3f2-0b1bdd568bde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472941119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ec_pwr_on_rst.472941119
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1574766276
Short name T238
Test name
Test status
Simulation time 3853535603 ps
CPU time 2.75 seconds
Started Jun 22 04:52:02 PM PDT 24
Finished Jun 22 04:52:05 PM PDT 24
Peak memory 201196 kb
Host smart-fc86180d-1ee9-4e1c-ac18-ff3bba3583a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574766276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.1574766276
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3325658758
Short name T664
Test name
Test status
Simulation time 2613020986 ps
CPU time 3.87 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:03 PM PDT 24
Peak memory 201244 kb
Host smart-f7834b6a-bc92-40ec-8ace-b0a3d3046fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325658758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.3325658758
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1005601293
Short name T465
Test name
Test status
Simulation time 2499418994 ps
CPU time 2.23 seconds
Started Jun 22 04:51:56 PM PDT 24
Finished Jun 22 04:51:59 PM PDT 24
Peak memory 201268 kb
Host smart-4c0075c3-83a3-4bd5-8fba-59dd664e8ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005601293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1005601293
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1447288461
Short name T438
Test name
Test status
Simulation time 2090411256 ps
CPU time 3.17 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:13 PM PDT 24
Peak memory 201172 kb
Host smart-b6569797-a615-462d-9d3e-8653d11af732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447288461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1447288461
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4181037847
Short name T503
Test name
Test status
Simulation time 2559537675 ps
CPU time 1.58 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:52:13 PM PDT 24
Peak memory 201308 kb
Host smart-f1a69b5e-caa5-48d4-a806-3645f8bf9eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181037847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.4181037847
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.457370436
Short name T432
Test name
Test status
Simulation time 2109309279 ps
CPU time 5.97 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:04 PM PDT 24
Peak memory 201156 kb
Host smart-a981973d-97ed-4ab6-b302-54ee6476e269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457370436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.457370436
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.996898137
Short name T144
Test name
Test status
Simulation time 13319638283 ps
CPU time 4.78 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:52:01 PM PDT 24
Peak memory 201228 kb
Host smart-80a7f008-d44d-4fbb-888b-714f425382d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996898137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_st
ress_all.996898137
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2135774492
Short name T90
Test name
Test status
Simulation time 74810773306 ps
CPU time 48.56 seconds
Started Jun 22 04:52:05 PM PDT 24
Finished Jun 22 04:52:55 PM PDT 24
Peak memory 210052 kb
Host smart-aa0a051d-4942-4d65-a4b2-75dac74b414b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135774492 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2135774492
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1988579571
Short name T122
Test name
Test status
Simulation time 3622693364 ps
CPU time 4.21 seconds
Started Jun 22 04:51:54 PM PDT 24
Finished Jun 22 04:51:59 PM PDT 24
Peak memory 201108 kb
Host smart-fa61c578-3740-431e-86ae-64218839cad4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988579571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1988579571
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.2786382870
Short name T709
Test name
Test status
Simulation time 2016290574 ps
CPU time 5.59 seconds
Started Jun 22 04:52:00 PM PDT 24
Finished Jun 22 04:52:06 PM PDT 24
Peak memory 201120 kb
Host smart-c069ceca-dd33-4738-a094-8635ed44e88e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786382870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.2786382870
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3366539684
Short name T177
Test name
Test status
Simulation time 3946720046 ps
CPU time 10.94 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 201276 kb
Host smart-ce15ca49-8764-4e51-a726-7085e7c0e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366539684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3
366539684
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.4136592246
Short name T5
Test name
Test status
Simulation time 68029400560 ps
CPU time 42.87 seconds
Started Jun 22 04:51:53 PM PDT 24
Finished Jun 22 04:52:37 PM PDT 24
Peak memory 201312 kb
Host smart-d63f0be2-bc1e-4ec1-9041-bfa6405f098f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136592246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.4136592246
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.190532131
Short name T561
Test name
Test status
Simulation time 71560584096 ps
CPU time 174.51 seconds
Started Jun 22 04:52:04 PM PDT 24
Finished Jun 22 04:54:59 PM PDT 24
Peak memory 201528 kb
Host smart-20d2c90c-6195-4de3-ac8e-e2fd96d34112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190532131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_wi
th_pre_cond.190532131
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.971659281
Short name T730
Test name
Test status
Simulation time 2468565338 ps
CPU time 2.22 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:51:53 PM PDT 24
Peak memory 201204 kb
Host smart-32e8087d-2321-4681-be53-9002ed1e3f3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971659281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ec_pwr_on_rst.971659281
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.3024819836
Short name T142
Test name
Test status
Simulation time 3290274684 ps
CPU time 9.48 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 201220 kb
Host smart-e7f2b447-4300-4492-b2da-c24cce6e5ead
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024819836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.3024819836
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.1646785273
Short name T382
Test name
Test status
Simulation time 2613836824 ps
CPU time 7.43 seconds
Started Jun 22 04:51:52 PM PDT 24
Finished Jun 22 04:52:00 PM PDT 24
Peak memory 201248 kb
Host smart-16181ed2-acd1-4d28-b1c5-34d6b2596235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646785273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.1646785273
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2181729010
Short name T621
Test name
Test status
Simulation time 2463361177 ps
CPU time 6.72 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:51:59 PM PDT 24
Peak memory 201256 kb
Host smart-7dc50ff9-39b0-4dcc-a85e-af7b44ab8a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181729010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2181729010
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.2970380009
Short name T642
Test name
Test status
Simulation time 2097729042 ps
CPU time 3.36 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:51:55 PM PDT 24
Peak memory 201184 kb
Host smart-b708af6f-4452-42d5-a044-06ff02301724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970380009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.2970380009
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3481820242
Short name T424
Test name
Test status
Simulation time 2516781976 ps
CPU time 3.89 seconds
Started Jun 22 04:52:09 PM PDT 24
Finished Jun 22 04:52:14 PM PDT 24
Peak memory 201316 kb
Host smart-8a42c1d9-b48d-4a89-9b65-04b4eeedc5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481820242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3481820242
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.2056078566
Short name T719
Test name
Test status
Simulation time 2131942617 ps
CPU time 1.91 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:51:53 PM PDT 24
Peak memory 201168 kb
Host smart-94074e04-47fd-46a4-890b-b563cedb9328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056078566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2056078566
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.1405442539
Short name T27
Test name
Test status
Simulation time 11563906721 ps
CPU time 8.16 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:52:20 PM PDT 24
Peak memory 201240 kb
Host smart-95987224-e1c4-44a1-94ae-3e6c2e7a5b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405442539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.1405442539
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.2235099514
Short name T645
Test name
Test status
Simulation time 2039399315 ps
CPU time 1.82 seconds
Started Jun 22 04:51:56 PM PDT 24
Finished Jun 22 04:51:58 PM PDT 24
Peak memory 201248 kb
Host smart-fb541049-7e76-4328-9985-fcc38ec676f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235099514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.2235099514
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3774946087
Short name T180
Test name
Test status
Simulation time 3684652102 ps
CPU time 10.42 seconds
Started Jun 22 04:51:58 PM PDT 24
Finished Jun 22 04:52:09 PM PDT 24
Peak memory 201332 kb
Host smart-674fbec9-b27a-4996-a60b-b821e45156d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774946087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.3
774946087
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1043062387
Short name T222
Test name
Test status
Simulation time 174634272146 ps
CPU time 398.42 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:58:50 PM PDT 24
Peak memory 201076 kb
Host smart-881d46bd-166a-4e3c-9d69-81651af4a953
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043062387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1043062387
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3147435421
Short name T411
Test name
Test status
Simulation time 3253687721 ps
CPU time 8.6 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201148 kb
Host smart-41c087ee-42bc-41a1-be1a-5a57cb8859f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147435421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.3147435421
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2121167467
Short name T174
Test name
Test status
Simulation time 3089455023 ps
CPU time 2.28 seconds
Started Jun 22 04:52:03 PM PDT 24
Finished Jun 22 04:52:06 PM PDT 24
Peak memory 201216 kb
Host smart-587a44e9-92ac-43f9-b5a6-08f237e8a272
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121167467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.2121167467
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.696098583
Short name T171
Test name
Test status
Simulation time 2640544493 ps
CPU time 1.99 seconds
Started Jun 22 04:51:58 PM PDT 24
Finished Jun 22 04:52:01 PM PDT 24
Peak memory 201240 kb
Host smart-39da83d4-31c5-4803-be17-d2df7a5ad7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696098583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.696098583
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1960111538
Short name T604
Test name
Test status
Simulation time 2439552647 ps
CPU time 6.93 seconds
Started Jun 22 04:51:59 PM PDT 24
Finished Jun 22 04:52:07 PM PDT 24
Peak memory 201256 kb
Host smart-1515945d-bb12-45cc-9da7-12f091fc0640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960111538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.1960111538
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.975082409
Short name T159
Test name
Test status
Simulation time 2203025793 ps
CPU time 6.23 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201248 kb
Host smart-5f8580e7-58ec-4aa6-8f92-95b260504834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975082409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.975082409
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1627462681
Short name T129
Test name
Test status
Simulation time 2509695690 ps
CPU time 7.42 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201224 kb
Host smart-367fc3ce-7643-49d9-97ff-8c795b308ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627462681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1627462681
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.528461163
Short name T706
Test name
Test status
Simulation time 2124737559 ps
CPU time 2.61 seconds
Started Jun 22 04:51:59 PM PDT 24
Finished Jun 22 04:52:03 PM PDT 24
Peak memory 201164 kb
Host smart-f46e7e0f-c4ed-4111-bc90-9ee12afee39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528461163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.528461163
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1775964663
Short name T188
Test name
Test status
Simulation time 36057343986 ps
CPU time 86.33 seconds
Started Jun 22 04:52:04 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 214896 kb
Host smart-854930f1-9609-4203-a552-78f835940bed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775964663 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.1775964663
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.4179699501
Short name T111
Test name
Test status
Simulation time 4104661124 ps
CPU time 2.37 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:00 PM PDT 24
Peak memory 201236 kb
Host smart-1d9080c3-a7cd-4c10-9536-59c7d19445a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179699501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.4179699501
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.277685848
Short name T505
Test name
Test status
Simulation time 2028033360 ps
CPU time 1.77 seconds
Started Jun 22 04:51:58 PM PDT 24
Finished Jun 22 04:52:01 PM PDT 24
Peak memory 201144 kb
Host smart-77fbd28b-7f50-420d-aa60-3c6ba4ec7f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277685848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_tes
t.277685848
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1509022493
Short name T22
Test name
Test status
Simulation time 3053566557 ps
CPU time 2.5 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:01 PM PDT 24
Peak memory 201292 kb
Host smart-133edb06-b881-4ae0-86f8-c0122617f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509022493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
509022493
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1226327307
Short name T763
Test name
Test status
Simulation time 65656037445 ps
CPU time 61.38 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:53:09 PM PDT 24
Peak memory 201480 kb
Host smart-08df4219-f574-4cfd-af92-3eeca2ebd25f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226327307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1226327307
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3310158528
Short name T789
Test name
Test status
Simulation time 3339951276 ps
CPU time 8.85 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201232 kb
Host smart-6d830777-d28c-463b-a446-41a87096e600
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310158528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.3310158528
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.774754228
Short name T218
Test name
Test status
Simulation time 2850496967 ps
CPU time 1.94 seconds
Started Jun 22 04:52:03 PM PDT 24
Finished Jun 22 04:52:05 PM PDT 24
Peak memory 201228 kb
Host smart-06b05fc1-5a99-4a1e-9f63-7f3e174c32ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774754228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.774754228
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1371355966
Short name T101
Test name
Test status
Simulation time 2626170042 ps
CPU time 2.39 seconds
Started Jun 22 04:52:02 PM PDT 24
Finished Jun 22 04:52:05 PM PDT 24
Peak memory 201224 kb
Host smart-7e744174-e6e1-4605-a9f2-8c50939fccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371355966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1371355966
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.2484086863
Short name T764
Test name
Test status
Simulation time 2490493260 ps
CPU time 2.29 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:52:14 PM PDT 24
Peak memory 200920 kb
Host smart-11b0683f-a38a-49ae-9ddb-876abbaf4cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484086863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.2484086863
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2690223130
Short name T668
Test name
Test status
Simulation time 2159587377 ps
CPU time 2.06 seconds
Started Jun 22 04:51:59 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 201232 kb
Host smart-ba0124e9-f316-49d3-89c6-34fa37b8bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690223130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2690223130
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.4138817974
Short name T640
Test name
Test status
Simulation time 2544589207 ps
CPU time 2.06 seconds
Started Jun 22 04:52:09 PM PDT 24
Finished Jun 22 04:52:13 PM PDT 24
Peak memory 201232 kb
Host smart-69834e48-931c-4333-bc23-a8bc0df0cbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138817974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.4138817974
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3406269222
Short name T791
Test name
Test status
Simulation time 2134537150 ps
CPU time 1.88 seconds
Started Jun 22 04:52:12 PM PDT 24
Finished Jun 22 04:52:15 PM PDT 24
Peak memory 201168 kb
Host smart-af40f012-d9b9-4bdf-9c07-3558ede0aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406269222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3406269222
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.3741999792
Short name T205
Test name
Test status
Simulation time 11783073863 ps
CPU time 5.36 seconds
Started Jun 22 04:51:59 PM PDT 24
Finished Jun 22 04:52:06 PM PDT 24
Peak memory 201220 kb
Host smart-3f0a0d3e-7378-4f8e-9638-140708ab11c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741999792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.3741999792
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1743460043
Short name T98
Test name
Test status
Simulation time 57583792246 ps
CPU time 36.73 seconds
Started Jun 22 04:52:03 PM PDT 24
Finished Jun 22 04:52:41 PM PDT 24
Peak memory 201672 kb
Host smart-4b5708a1-a83f-4b23-9d2d-39fafd9762da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743460043 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1743460043
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3282717273
Short name T113
Test name
Test status
Simulation time 4462082060 ps
CPU time 2.2 seconds
Started Jun 22 04:51:59 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 201168 kb
Host smart-c190a87b-8276-4abc-a826-314a972a2d03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282717273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.3282717273
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.2114673329
Short name T400
Test name
Test status
Simulation time 2066020854 ps
CPU time 1.22 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:52:10 PM PDT 24
Peak memory 201248 kb
Host smart-871c7fd1-aaee-498b-acb8-32aba4dc2ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114673329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.2114673329
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3097222632
Short name T515
Test name
Test status
Simulation time 3361463766 ps
CPU time 1.7 seconds
Started Jun 22 04:52:05 PM PDT 24
Finished Jun 22 04:52:08 PM PDT 24
Peak memory 201236 kb
Host smart-205c0dcb-31b1-428f-8df5-03cb02778108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097222632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.3
097222632
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.39623667
Short name T271
Test name
Test status
Simulation time 73485399037 ps
CPU time 182.53 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 201348 kb
Host smart-dad12a85-9713-41fe-8979-061712325d7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39623667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctr
l_combo_detect.39623667
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3454499285
Short name T564
Test name
Test status
Simulation time 4667407714 ps
CPU time 1.43 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:52:09 PM PDT 24
Peak memory 201204 kb
Host smart-837d2aae-87f8-40a7-854d-9bfb98e34a47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454499285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.3454499285
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2046305320
Short name T569
Test name
Test status
Simulation time 2612515056 ps
CPU time 6.78 seconds
Started Jun 22 04:51:58 PM PDT 24
Finished Jun 22 04:52:06 PM PDT 24
Peak memory 201248 kb
Host smart-1a8b0da3-f423-432b-8bec-ee94a1f01ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046305320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.2046305320
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2703921999
Short name T420
Test name
Test status
Simulation time 2449770431 ps
CPU time 3.57 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:14 PM PDT 24
Peak memory 201240 kb
Host smart-d6789c1c-df43-482e-a339-7beb3b2585c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703921999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2703921999
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1522884157
Short name T279
Test name
Test status
Simulation time 2183652861 ps
CPU time 2.03 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:00 PM PDT 24
Peak memory 201220 kb
Host smart-aef1dc4f-3ba8-4613-8ec0-0dd36f3b6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522884157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1522884157
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1523293752
Short name T304
Test name
Test status
Simulation time 2538929661 ps
CPU time 2.3 seconds
Started Jun 22 04:51:58 PM PDT 24
Finished Jun 22 04:52:01 PM PDT 24
Peak memory 201320 kb
Host smart-10f5d3ad-a1c5-44c7-8170-833196ddb499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523293752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.1523293752
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.130966857
Short name T522
Test name
Test status
Simulation time 2110603333 ps
CPU time 5.7 seconds
Started Jun 22 04:52:05 PM PDT 24
Finished Jun 22 04:52:12 PM PDT 24
Peak memory 201164 kb
Host smart-064e165e-736a-467a-947a-7fc4957d892e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130966857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.130966857
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.868544375
Short name T369
Test name
Test status
Simulation time 117054138186 ps
CPU time 56.27 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:53:04 PM PDT 24
Peak memory 201356 kb
Host smart-77deb502-c453-43a2-b035-2c6817ef859e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868544375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_st
ress_all.868544375
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.4007383583
Short name T767
Test name
Test status
Simulation time 1124608975687 ps
CPU time 59.04 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:53:15 PM PDT 24
Peak memory 201524 kb
Host smart-5d4f76f4-49fb-45c5-ac97-119458e5e1b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007383583 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.4007383583
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2528562769
Short name T576
Test name
Test status
Simulation time 7356384668 ps
CPU time 2.13 seconds
Started Jun 22 04:52:00 PM PDT 24
Finished Jun 22 04:52:03 PM PDT 24
Peak memory 201228 kb
Host smart-2d28584c-0921-483d-a837-516d0dd3d755
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528562769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.2528562769
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.2135341223
Short name T255
Test name
Test status
Simulation time 2037256362 ps
CPU time 1.66 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:52:10 PM PDT 24
Peak memory 201148 kb
Host smart-42ff8faf-00db-4d83-bb42-648b8bc8f1e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135341223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.2135341223
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.4124647540
Short name T708
Test name
Test status
Simulation time 3328551298 ps
CPU time 4.71 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:17 PM PDT 24
Peak memory 201296 kb
Host smart-76e31872-f8fe-4694-8499-7eed96d4a625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124647540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.4
124647540
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1192262689
Short name T232
Test name
Test status
Simulation time 112800045674 ps
CPU time 283.1 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:56:55 PM PDT 24
Peak memory 201440 kb
Host smart-94b4ff44-5b29-434f-8767-2a43dbd87836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192262689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.1192262689
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1299103663
Short name T731
Test name
Test status
Simulation time 3322300097 ps
CPU time 2.41 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:15 PM PDT 24
Peak memory 201188 kb
Host smart-716b9adc-966f-4cf3-8e48-5eb56a8339c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299103663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.1299103663
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1989060114
Short name T531
Test name
Test status
Simulation time 2623605488 ps
CPU time 2.43 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:15 PM PDT 24
Peak memory 201148 kb
Host smart-ee901821-909a-49dd-bf9e-ea3def45c167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989060114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.1989060114
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2513916810
Short name T448
Test name
Test status
Simulation time 2459578529 ps
CPU time 7.98 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:15 PM PDT 24
Peak memory 201172 kb
Host smart-01d26202-0f4d-415e-9c63-740cb8e2d42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513916810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2513916810
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3191580994
Short name T525
Test name
Test status
Simulation time 2147181714 ps
CPU time 2 seconds
Started Jun 22 04:51:59 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 201176 kb
Host smart-b8e5132c-7d17-4421-88c5-2cbc4120f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191580994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3191580994
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.3420225322
Short name T622
Test name
Test status
Simulation time 2536326294 ps
CPU time 2.16 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:52:14 PM PDT 24
Peak memory 201288 kb
Host smart-40767bf1-c6e4-4084-9ae8-7b4a054b9bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420225322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3420225322
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.1838380356
Short name T521
Test name
Test status
Simulation time 2133506876 ps
CPU time 2.1 seconds
Started Jun 22 04:51:59 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 201124 kb
Host smart-ae111141-488d-46b5-a7df-2655cbd316a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838380356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1838380356
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.2738466866
Short name T265
Test name
Test status
Simulation time 32943880460 ps
CPU time 45.12 seconds
Started Jun 22 04:52:12 PM PDT 24
Finished Jun 22 04:52:58 PM PDT 24
Peak memory 201456 kb
Host smart-df383b89-bf8a-456c-9834-7be027f45c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738466866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.2738466866
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3273970991
Short name T57
Test name
Test status
Simulation time 4378425761 ps
CPU time 1.93 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:11 PM PDT 24
Peak memory 201128 kb
Host smart-e1664c81-beab-4d68-a263-f7d3bce87f9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273970991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.3273970991
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.2809111408
Short name T532
Test name
Test status
Simulation time 2021446698 ps
CPU time 3.13 seconds
Started Jun 22 04:52:17 PM PDT 24
Finished Jun 22 04:52:20 PM PDT 24
Peak memory 201096 kb
Host smart-d7bcb1f6-6497-4b3d-8b05-05fd3b48d903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809111408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.2809111408
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1765681148
Short name T496
Test name
Test status
Simulation time 137874971153 ps
CPU time 168.32 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:54:57 PM PDT 24
Peak memory 201276 kb
Host smart-cea88aad-d1fa-4432-add8-2577bae102cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765681148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
765681148
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.3018092523
Short name T362
Test name
Test status
Simulation time 92614395593 ps
CPU time 115.04 seconds
Started Jun 22 04:52:13 PM PDT 24
Finished Jun 22 04:54:09 PM PDT 24
Peak memory 201416 kb
Host smart-f48d5f0e-5e9e-4f63-88c5-d44908f96a1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018092523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.3018092523
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.501975166
Short name T670
Test name
Test status
Simulation time 3241152093 ps
CPU time 2.48 seconds
Started Jun 22 04:52:12 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201184 kb
Host smart-52361899-af54-44c0-876a-3fb58866aff2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501975166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ec_pwr_on_rst.501975166
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.900186698
Short name T214
Test name
Test status
Simulation time 3868472430 ps
CPU time 9.01 seconds
Started Jun 22 04:52:12 PM PDT 24
Finished Jun 22 04:52:22 PM PDT 24
Peak memory 201232 kb
Host smart-fb858e65-6912-47e7-ad47-99e1a69aa55c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900186698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctr
l_edge_detect.900186698
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2909794872
Short name T433
Test name
Test status
Simulation time 2621008933 ps
CPU time 4.14 seconds
Started Jun 22 04:52:30 PM PDT 24
Finished Jun 22 04:52:35 PM PDT 24
Peak memory 201228 kb
Host smart-42e96f16-206f-444b-a1ae-823a2d4e9e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909794872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.2909794872
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.292365855
Short name T550
Test name
Test status
Simulation time 2499545851 ps
CPU time 2.45 seconds
Started Jun 22 04:52:21 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 201244 kb
Host smart-09889254-9070-490e-b78a-2faff7e7a608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292365855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.292365855
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.4258459121
Short name T170
Test name
Test status
Simulation time 2232165128 ps
CPU time 1.85 seconds
Started Jun 22 04:52:04 PM PDT 24
Finished Jun 22 04:52:07 PM PDT 24
Peak memory 201240 kb
Host smart-0e5167a3-215b-42d4-b3bd-34b92c3e7cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258459121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.4258459121
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3171430554
Short name T512
Test name
Test status
Simulation time 2512404843 ps
CPU time 7.19 seconds
Started Jun 22 04:52:27 PM PDT 24
Finished Jun 22 04:52:34 PM PDT 24
Peak memory 201328 kb
Host smart-4b9e2e1b-561d-45c7-bf68-ad5d97630910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171430554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.3171430554
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.3227126420
Short name T574
Test name
Test status
Simulation time 2132550028 ps
CPU time 1.98 seconds
Started Jun 22 04:52:12 PM PDT 24
Finished Jun 22 04:52:15 PM PDT 24
Peak memory 201176 kb
Host smart-ae33d4b5-859a-493a-b669-fbe11e744ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227126420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3227126420
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.2508691312
Short name T368
Test name
Test status
Simulation time 151791700685 ps
CPU time 263.82 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:56:36 PM PDT 24
Peak memory 201504 kb
Host smart-6f36d0b2-fbb7-4414-b3d1-b54dc8ff4cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508691312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.2508691312
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1082706998
Short name T123
Test name
Test status
Simulation time 4913199526 ps
CPU time 2.3 seconds
Started Jun 22 04:52:27 PM PDT 24
Finished Jun 22 04:52:30 PM PDT 24
Peak memory 201216 kb
Host smart-a3efcff0-8779-42db-999e-64e85d632c50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082706998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.1082706998
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3598801913
Short name T579
Test name
Test status
Simulation time 2040317856 ps
CPU time 1.74 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:52:10 PM PDT 24
Peak memory 201248 kb
Host smart-212ddf78-b11b-439e-baf8-cd3a0e2d2b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598801913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3598801913
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3559433116
Short name T454
Test name
Test status
Simulation time 3678138250 ps
CPU time 3.11 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:13 PM PDT 24
Peak memory 201344 kb
Host smart-2c31ade6-a981-4443-bf90-085ef4843e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559433116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.3
559433116
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.2649752019
Short name T332
Test name
Test status
Simulation time 100696455950 ps
CPU time 46.48 seconds
Started Jun 22 04:52:12 PM PDT 24
Finished Jun 22 04:53:00 PM PDT 24
Peak memory 201416 kb
Host smart-9cb51c42-c03e-413b-a855-464477714e3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649752019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.2649752019
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.4119492656
Short name T567
Test name
Test status
Simulation time 104370308567 ps
CPU time 32.39 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:45 PM PDT 24
Peak memory 201568 kb
Host smart-e127bc49-1421-4a91-89ae-bfc75b631007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119492656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.4119492656
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3919536708
Short name T146
Test name
Test status
Simulation time 3484442266 ps
CPU time 9.58 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 201220 kb
Host smart-7326e990-98f2-4420-a71d-fae7cf54460c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919536708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.3919536708
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.808873053
Short name T781
Test name
Test status
Simulation time 3187944463 ps
CPU time 2.17 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:11 PM PDT 24
Peak memory 201228 kb
Host smart-ffe220b9-0187-47c2-aa0c-4f843bd39cbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808873053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctr
l_edge_detect.808873053
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.995448267
Short name T402
Test name
Test status
Simulation time 2630947778 ps
CPU time 2.06 seconds
Started Jun 22 04:52:23 PM PDT 24
Finished Jun 22 04:52:26 PM PDT 24
Peak memory 201244 kb
Host smart-1ef954e7-3a15-4319-b7c2-727dd901c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995448267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.995448267
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.713009049
Short name T751
Test name
Test status
Simulation time 2445475902 ps
CPU time 6.64 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 201248 kb
Host smart-31355432-51ff-4dd5-8192-53e5325aa652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713009049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.713009049
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3438612642
Short name T394
Test name
Test status
Simulation time 2129780519 ps
CPU time 1.86 seconds
Started Jun 22 04:52:12 PM PDT 24
Finished Jun 22 04:52:15 PM PDT 24
Peak memory 201184 kb
Host smart-f00e22ee-ca22-4a16-9025-3585d298e81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438612642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3438612642
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1558005353
Short name T777
Test name
Test status
Simulation time 2576544690 ps
CPU time 1.09 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:52:09 PM PDT 24
Peak memory 201296 kb
Host smart-98cf001d-27c8-45b0-9d14-b0fa3377b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558005353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1558005353
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.1712953756
Short name T485
Test name
Test status
Simulation time 2122917342 ps
CPU time 3.42 seconds
Started Jun 22 04:52:09 PM PDT 24
Finished Jun 22 04:52:14 PM PDT 24
Peak memory 201132 kb
Host smart-86349ce5-53e1-4919-9772-6d4959b3c225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712953756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.1712953756
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.956454029
Short name T36
Test name
Test status
Simulation time 1146976009734 ps
CPU time 66.79 seconds
Started Jun 22 04:52:10 PM PDT 24
Finished Jun 22 04:53:19 PM PDT 24
Peak memory 201128 kb
Host smart-d5fed037-8aac-40d6-a8c9-27c2b900b28f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956454029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_st
ress_all.956454029
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3790485394
Short name T762
Test name
Test status
Simulation time 67490113358 ps
CPU time 165.12 seconds
Started Jun 22 04:52:09 PM PDT 24
Finished Jun 22 04:54:56 PM PDT 24
Peak memory 209836 kb
Host smart-a174f97b-2cb5-4235-933d-c24343101012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790485394 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.3790485394
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1296498644
Short name T69
Test name
Test status
Simulation time 7551105307 ps
CPU time 1.67 seconds
Started Jun 22 04:52:15 PM PDT 24
Finished Jun 22 04:52:18 PM PDT 24
Peak memory 201128 kb
Host smart-b9219d20-ff65-47d3-94fa-9e6d8c120497
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296498644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.1296498644
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.2982827345
Short name T775
Test name
Test status
Simulation time 2027455807 ps
CPU time 1.95 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:52:11 PM PDT 24
Peak memory 201276 kb
Host smart-f0245c9c-cf20-4e90-a7fd-4aa3e08c8b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982827345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.2982827345
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3758392795
Short name T549
Test name
Test status
Simulation time 3668403315 ps
CPU time 3.08 seconds
Started Jun 22 04:52:30 PM PDT 24
Finished Jun 22 04:52:33 PM PDT 24
Peak memory 201268 kb
Host smart-0edf5157-0e95-476b-afda-d49174df2205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758392795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3
758392795
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.4156556541
Short name T7
Test name
Test status
Simulation time 88459545721 ps
CPU time 230.82 seconds
Started Jun 22 04:52:22 PM PDT 24
Finished Jun 22 04:56:13 PM PDT 24
Peak memory 201444 kb
Host smart-724d52f4-015a-4369-ac14-38754d282e80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156556541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.4156556541
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.583929089
Short name T135
Test name
Test status
Simulation time 3567419026 ps
CPU time 2.87 seconds
Started Jun 22 04:52:17 PM PDT 24
Finished Jun 22 04:52:20 PM PDT 24
Peak memory 201204 kb
Host smart-476cbcc9-3c0a-4192-b4cc-93c8cd6bcc69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583929089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.583929089
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.3153553774
Short name T34
Test name
Test status
Simulation time 3903738644 ps
CPU time 2.23 seconds
Started Jun 22 04:52:07 PM PDT 24
Finished Jun 22 04:52:11 PM PDT 24
Peak memory 201208 kb
Host smart-a3c68f89-6598-41a1-a841-d5b7af6b3046
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153553774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.3153553774
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3059426378
Short name T580
Test name
Test status
Simulation time 2675140377 ps
CPU time 1.22 seconds
Started Jun 22 04:52:18 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 201236 kb
Host smart-a7b83c40-4f16-41f5-92e6-dd2f557e0181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059426378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3059426378
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.875718024
Short name T226
Test name
Test status
Simulation time 2451995963 ps
CPU time 4.04 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201100 kb
Host smart-419700b7-f715-41a9-bfba-88efd36b83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875718024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.875718024
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.3961486778
Short name T384
Test name
Test status
Simulation time 2092630414 ps
CPU time 3.35 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201152 kb
Host smart-2dd2b888-6f0d-4d83-aeb6-5a5f6ad1da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961486778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3961486778
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3336800806
Short name T643
Test name
Test status
Simulation time 2547027018 ps
CPU time 1.97 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:52:17 PM PDT 24
Peak memory 201308 kb
Host smart-7ec9c5c3-79eb-492f-a859-168c07316455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336800806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3336800806
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.1248424873
Short name T760
Test name
Test status
Simulation time 2112920697 ps
CPU time 5.62 seconds
Started Jun 22 04:52:22 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 201128 kb
Host smart-46e8f082-c5cb-40cb-9b04-182b8a9fa8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248424873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.1248424873
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.2449274475
Short name T714
Test name
Test status
Simulation time 73150189565 ps
CPU time 83.7 seconds
Started Jun 22 04:52:09 PM PDT 24
Finished Jun 22 04:53:34 PM PDT 24
Peak memory 201384 kb
Host smart-f98e2bd9-4061-4b3d-8d67-7ecc5b64a25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449274475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.2449274475
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1070787208
Short name T530
Test name
Test status
Simulation time 7798309682 ps
CPU time 1.09 seconds
Started Jun 22 04:52:17 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 201152 kb
Host smart-8e2a9767-c192-4bd9-ad05-3a9857c46f45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070787208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.1070787208
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1204358848
Short name T685
Test name
Test status
Simulation time 2021727632 ps
CPU time 3.19 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:38 PM PDT 24
Peak memory 201100 kb
Host smart-d3cc1a76-2c52-4012-b1ad-ccb021a1c45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204358848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1204358848
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.124124951
Short name T299
Test name
Test status
Simulation time 3590357180 ps
CPU time 10.13 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:43 PM PDT 24
Peak memory 201348 kb
Host smart-a9210e11-5be7-4382-a2eb-bc84ad143c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124124951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.124124951
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.1709946358
Short name T155
Test name
Test status
Simulation time 27251468031 ps
CPU time 12.22 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:47 PM PDT 24
Peak memory 201400 kb
Host smart-6c1d51e5-5067-417d-a059-08bc502ceadc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709946358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.1709946358
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.780901612
Short name T605
Test name
Test status
Simulation time 2435958100 ps
CPU time 2.19 seconds
Started Jun 22 04:51:35 PM PDT 24
Finished Jun 22 04:51:38 PM PDT 24
Peak memory 201256 kb
Host smart-1da11fcc-8c90-4154-928f-24e8e64214e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780901612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.780901612
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2488794241
Short name T562
Test name
Test status
Simulation time 2509707118 ps
CPU time 7.27 seconds
Started Jun 22 04:52:37 PM PDT 24
Finished Jun 22 04:52:45 PM PDT 24
Peak memory 201224 kb
Host smart-206c712f-a9cf-479a-8975-9387918580bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488794241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2488794241
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3687716694
Short name T247
Test name
Test status
Simulation time 24332317578 ps
CPU time 59.22 seconds
Started Jun 22 04:51:30 PM PDT 24
Finished Jun 22 04:52:30 PM PDT 24
Peak memory 201572 kb
Host smart-c64897f6-2289-4ea7-9761-0221d68ad0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687716694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.3687716694
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.991259950
Short name T774
Test name
Test status
Simulation time 5201904726 ps
CPU time 13.54 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 201256 kb
Host smart-5de26339-1141-4340-9f94-c3ae0011f2d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991259950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ec_pwr_on_rst.991259950
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1847123778
Short name T176
Test name
Test status
Simulation time 4166633095 ps
CPU time 5.78 seconds
Started Jun 22 04:51:29 PM PDT 24
Finished Jun 22 04:51:36 PM PDT 24
Peak memory 201228 kb
Host smart-bbcabc6f-874c-4822-9b01-b6fa9ca2c5b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847123778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.1847123778
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1611991413
Short name T130
Test name
Test status
Simulation time 2620064192 ps
CPU time 4.03 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201264 kb
Host smart-2d31183c-6360-4ecf-83e8-1cb1b361a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611991413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1611991413
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1044162296
Short name T626
Test name
Test status
Simulation time 2481856131 ps
CPU time 1.92 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:35 PM PDT 24
Peak memory 201156 kb
Host smart-68b72178-4dff-4e24-9c03-a54999755719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044162296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.1044162296
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2984107788
Short name T486
Test name
Test status
Simulation time 2133352435 ps
CPU time 2.05 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:51:40 PM PDT 24
Peak memory 201132 kb
Host smart-16b04898-b212-49bb-ae46-f734b63e0297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984107788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2984107788
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3808790819
Short name T440
Test name
Test status
Simulation time 2511530371 ps
CPU time 7.05 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201268 kb
Host smart-98162f32-9655-4b4d-a308-fb3467746a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808790819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3808790819
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1267025781
Short name T295
Test name
Test status
Simulation time 22067601556 ps
CPU time 53.57 seconds
Started Jun 22 04:51:33 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 220924 kb
Host smart-430cff78-00a6-4604-8995-f3703807c235
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267025781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1267025781
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.414388067
Short name T85
Test name
Test status
Simulation time 2119722634 ps
CPU time 3.45 seconds
Started Jun 22 04:51:40 PM PDT 24
Finished Jun 22 04:51:44 PM PDT 24
Peak memory 201164 kb
Host smart-ab620083-dd1f-49d0-8ccb-bc210e29f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414388067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.414388067
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.3335366809
Short name T654
Test name
Test status
Simulation time 251663304422 ps
CPU time 154.17 seconds
Started Jun 22 04:51:34 PM PDT 24
Finished Jun 22 04:54:09 PM PDT 24
Peak memory 201264 kb
Host smart-e841d1dc-32ef-497a-b269-f9f362077178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335366809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.3335366809
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3447433103
Short name T68
Test name
Test status
Simulation time 5672578076 ps
CPU time 4.16 seconds
Started Jun 22 04:51:35 PM PDT 24
Finished Jun 22 04:51:41 PM PDT 24
Peak memory 201256 kb
Host smart-dcfe7ecd-2e2a-4737-bac7-5b45ed964797
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447433103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.3447433103
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3506374565
Short name T472
Test name
Test status
Simulation time 2028729368 ps
CPU time 1.83 seconds
Started Jun 22 04:52:17 PM PDT 24
Finished Jun 22 04:52:20 PM PDT 24
Peak memory 201156 kb
Host smart-083984c0-2ea5-460f-bbfd-058c8ee21d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506374565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3506374565
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1386537241
Short name T441
Test name
Test status
Simulation time 112234111961 ps
CPU time 264.82 seconds
Started Jun 22 04:52:15 PM PDT 24
Finished Jun 22 04:56:40 PM PDT 24
Peak memory 201332 kb
Host smart-82a75d65-afd9-4f13-abf1-812cf4df80b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386537241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.1
386537241
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.455680369
Short name T364
Test name
Test status
Simulation time 145390798535 ps
CPU time 185.93 seconds
Started Jun 22 04:52:17 PM PDT 24
Finished Jun 22 04:55:24 PM PDT 24
Peak memory 201324 kb
Host smart-c3a8f7ba-defa-42ec-b151-bca06550a792
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455680369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_combo_detect.455680369
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3763517493
Short name T598
Test name
Test status
Simulation time 3777618531 ps
CPU time 5.16 seconds
Started Jun 22 04:52:21 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 201232 kb
Host smart-4be152a6-659c-4acd-a468-23b6a2c5e538
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763517493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3763517493
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2327522937
Short name T678
Test name
Test status
Simulation time 2638975928 ps
CPU time 2.24 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:52:37 PM PDT 24
Peak memory 201248 kb
Host smart-235c74ce-0a05-4463-9639-b49f7262b623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327522937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.2327522937
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3669514832
Short name T235
Test name
Test status
Simulation time 2495080619 ps
CPU time 2.17 seconds
Started Jun 22 04:52:13 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201236 kb
Host smart-6cdbe823-8e6c-4d46-9ceb-e50c2de8da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669514832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3669514832
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1593141654
Short name T620
Test name
Test status
Simulation time 2093491532 ps
CPU time 4.41 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:17 PM PDT 24
Peak memory 201188 kb
Host smart-505a89c1-6a75-46ab-8656-38993f3a5aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593141654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1593141654
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2004979119
Short name T635
Test name
Test status
Simulation time 2508580591 ps
CPU time 7.21 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:52:41 PM PDT 24
Peak memory 201172 kb
Host smart-ca34de55-9d5f-43ad-99e9-fd21f4318eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004979119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.2004979119
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.166991034
Short name T431
Test name
Test status
Simulation time 2131985101 ps
CPU time 1.65 seconds
Started Jun 22 04:52:11 PM PDT 24
Finished Jun 22 04:52:14 PM PDT 24
Peak memory 201172 kb
Host smart-85cf5668-9e11-4bc6-9356-d553eeeb8752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166991034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.166991034
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.3674243593
Short name T365
Test name
Test status
Simulation time 172754671412 ps
CPU time 42.14 seconds
Started Jun 22 04:52:24 PM PDT 24
Finished Jun 22 04:53:07 PM PDT 24
Peak memory 201468 kb
Host smart-64ae22f6-bf57-4455-aec0-1ddf86f490e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674243593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.3674243593
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1244866998
Short name T661
Test name
Test status
Simulation time 17450014966 ps
CPU time 21.47 seconds
Started Jun 22 04:52:19 PM PDT 24
Finished Jun 22 04:52:42 PM PDT 24
Peak memory 217332 kb
Host smart-bc2d43ff-23e9-4f65-9b5d-164fa9018b4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244866998 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1244866998
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.45334611
Short name T121
Test name
Test status
Simulation time 10750879685 ps
CPU time 9.71 seconds
Started Jun 22 04:52:28 PM PDT 24
Finished Jun 22 04:52:39 PM PDT 24
Peak memory 201212 kb
Host smart-0c03b6c7-862f-4a2c-b615-bc84739a2ccf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45334611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_ultra_low_pwr.45334611
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.1731014638
Short name T133
Test name
Test status
Simulation time 2031850275 ps
CPU time 1.83 seconds
Started Jun 22 04:52:16 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 201248 kb
Host smart-502bd266-8c5b-4bc2-a648-b411093ffeef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731014638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.1731014638
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3553837484
Short name T572
Test name
Test status
Simulation time 3544324745 ps
CPU time 9.86 seconds
Started Jun 22 04:52:15 PM PDT 24
Finished Jun 22 04:52:26 PM PDT 24
Peak memory 201300 kb
Host smart-fa841dc6-9efb-43ea-8d87-97ab631d7e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553837484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.3
553837484
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3462781516
Short name T334
Test name
Test status
Simulation time 187528640575 ps
CPU time 117.51 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:54:12 PM PDT 24
Peak memory 201424 kb
Host smart-a67f6f9e-23b7-486b-849f-700958df00a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462781516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3462781516
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3324550138
Short name T468
Test name
Test status
Simulation time 4443561187 ps
CPU time 6.27 seconds
Started Jun 22 04:52:23 PM PDT 24
Finished Jun 22 04:52:30 PM PDT 24
Peak memory 201188 kb
Host smart-7a4170ef-4150-4c1e-8641-90122408701e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324550138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.3324550138
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.2312748840
Short name T396
Test name
Test status
Simulation time 2632781739 ps
CPU time 2.37 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:52:17 PM PDT 24
Peak memory 201252 kb
Host smart-41ed8b6f-e909-430f-a49c-fb928ad8f3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312748840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.2312748840
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.156888601
Short name T479
Test name
Test status
Simulation time 2492171097 ps
CPU time 2.09 seconds
Started Jun 22 04:52:16 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 201228 kb
Host smart-87795a94-8961-44b2-98e5-fd1b73dd970d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156888601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.156888601
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.1847501097
Short name T557
Test name
Test status
Simulation time 2235614660 ps
CPU time 6.27 seconds
Started Jun 22 04:52:17 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 201232 kb
Host smart-ddce906c-c11b-4854-a93d-4c10b8695979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847501097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1847501097
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3174717512
Short name T650
Test name
Test status
Simulation time 2527072778 ps
CPU time 2.43 seconds
Started Jun 22 04:52:20 PM PDT 24
Finished Jun 22 04:52:23 PM PDT 24
Peak memory 201164 kb
Host smart-06d04dcf-ca1e-4296-be52-79611a829936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174717512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3174717512
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.355148593
Short name T786
Test name
Test status
Simulation time 2120500029 ps
CPU time 2.86 seconds
Started Jun 22 04:52:15 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 201160 kb
Host smart-cd72ffcd-8f8c-4bce-910f-f3eccef7b677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355148593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.355148593
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.1976063421
Short name T64
Test name
Test status
Simulation time 8818269669 ps
CPU time 9.37 seconds
Started Jun 22 04:52:15 PM PDT 24
Finished Jun 22 04:52:25 PM PDT 24
Peak memory 201264 kb
Host smart-41a57693-eb2b-44c0-8bf3-51aab80c3cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976063421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.1976063421
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3116326460
Short name T237
Test name
Test status
Simulation time 65878560093 ps
CPU time 162.32 seconds
Started Jun 22 04:52:41 PM PDT 24
Finished Jun 22 04:55:23 PM PDT 24
Peak memory 209748 kb
Host smart-7a877999-c869-4820-a703-54c1dd9eee93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116326460 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3116326460
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.1583045289
Short name T577
Test name
Test status
Simulation time 2015880278 ps
CPU time 5.19 seconds
Started Jun 22 04:52:26 PM PDT 24
Finished Jun 22 04:52:31 PM PDT 24
Peak memory 201212 kb
Host smart-f4701b6f-1760-4461-8a7b-952d64c21562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583045289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.1583045289
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.561684871
Short name T749
Test name
Test status
Simulation time 3791838358 ps
CPU time 2.59 seconds
Started Jun 22 04:52:24 PM PDT 24
Finished Jun 22 04:52:28 PM PDT 24
Peak memory 201296 kb
Host smart-652805fb-6182-4c79-a4c2-a965c1519748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561684871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.561684871
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.4286909702
Short name T249
Test name
Test status
Simulation time 101998596742 ps
CPU time 270.55 seconds
Started Jun 22 04:52:18 PM PDT 24
Finished Jun 22 04:56:50 PM PDT 24
Peak memory 201424 kb
Host smart-84b0d47f-7f33-476b-99d6-aedbc5634d22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286909702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.4286909702
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1136143079
Short name T587
Test name
Test status
Simulation time 34151002168 ps
CPU time 21.22 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:52:36 PM PDT 24
Peak memory 201572 kb
Host smart-443bc672-9ad0-4d16-a511-8d5d9f619876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136143079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.1136143079
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.4227172759
Short name T476
Test name
Test status
Simulation time 3116169357 ps
CPU time 4.37 seconds
Started Jun 22 04:52:19 PM PDT 24
Finished Jun 22 04:52:23 PM PDT 24
Peak memory 201076 kb
Host smart-f4f61bf2-ce3f-448b-a31f-4dfab0ac3c64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227172759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.4227172759
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3635606458
Short name T606
Test name
Test status
Simulation time 2624258547 ps
CPU time 2.76 seconds
Started Jun 22 04:52:31 PM PDT 24
Finished Jun 22 04:52:34 PM PDT 24
Peak memory 201220 kb
Host smart-d677cbc0-5a4d-4b91-a774-65a841ef0c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635606458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3635606458
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.3928877346
Short name T99
Test name
Test status
Simulation time 2483818932 ps
CPU time 2.35 seconds
Started Jun 22 04:52:15 PM PDT 24
Finished Jun 22 04:52:18 PM PDT 24
Peak memory 201248 kb
Host smart-438dcb8f-c08e-4a1a-8400-d490b83d6104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928877346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3928877346
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3117222630
Short name T759
Test name
Test status
Simulation time 2084993142 ps
CPU time 2.7 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:52:18 PM PDT 24
Peak memory 201084 kb
Host smart-339cf689-e025-4382-a1cb-2889025703a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117222630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3117222630
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.793736166
Short name T412
Test name
Test status
Simulation time 2519981060 ps
CPU time 3.23 seconds
Started Jun 22 04:52:20 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 201296 kb
Host smart-b0274f64-bacb-4d2c-b89c-01c76fbef21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793736166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.793736166
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.429767352
Short name T677
Test name
Test status
Simulation time 2109698665 ps
CPU time 5.75 seconds
Started Jun 22 04:52:28 PM PDT 24
Finished Jun 22 04:52:35 PM PDT 24
Peak memory 201152 kb
Host smart-b7601043-bb8b-4e4c-acce-1905b60ce15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429767352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.429767352
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.1834449195
Short name T729
Test name
Test status
Simulation time 108756193751 ps
CPU time 284.6 seconds
Started Jun 22 04:52:28 PM PDT 24
Finished Jun 22 04:57:13 PM PDT 24
Peak memory 201420 kb
Host smart-b4e009eb-24bd-49d1-8b50-380733b60033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834449195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.1834449195
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.1846980053
Short name T162
Test name
Test status
Simulation time 47141572836 ps
CPU time 115.64 seconds
Started Jun 22 04:52:13 PM PDT 24
Finished Jun 22 04:54:09 PM PDT 24
Peak memory 217988 kb
Host smart-3e2c7e56-7efd-4dda-9fec-1387c410907a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846980053 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.1846980053
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3446224670
Short name T707
Test name
Test status
Simulation time 5954746318 ps
CPU time 2.62 seconds
Started Jun 22 04:52:14 PM PDT 24
Finished Jun 22 04:52:17 PM PDT 24
Peak memory 201268 kb
Host smart-3cf8a348-a37c-4852-9dd5-1f87086aefa7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446224670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3446224670
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.3855280985
Short name T632
Test name
Test status
Simulation time 2023484416 ps
CPU time 3.03 seconds
Started Jun 22 04:52:24 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 201148 kb
Host smart-367d7733-b6ea-495f-90f5-04535920d9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855280985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.3855280985
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.588320156
Short name T552
Test name
Test status
Simulation time 3158219236 ps
CPU time 4.49 seconds
Started Jun 22 04:52:23 PM PDT 24
Finished Jun 22 04:52:28 PM PDT 24
Peak memory 201320 kb
Host smart-18154029-8298-40f4-9751-fa569356d2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588320156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.588320156
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.233568154
Short name T251
Test name
Test status
Simulation time 80535005851 ps
CPU time 52.12 seconds
Started Jun 22 04:52:30 PM PDT 24
Finished Jun 22 04:53:23 PM PDT 24
Peak memory 201324 kb
Host smart-0903056d-d4c1-414a-a4d6-c0a802bc3abc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233568154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_combo_detect.233568154
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.4012546964
Short name T385
Test name
Test status
Simulation time 3875737328 ps
CPU time 2.27 seconds
Started Jun 22 04:52:23 PM PDT 24
Finished Jun 22 04:52:25 PM PDT 24
Peak memory 201104 kb
Host smart-a83bcc34-82b6-4de9-90bb-b7b436351ade
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012546964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.4012546964
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3905250730
Short name T224
Test name
Test status
Simulation time 3364677900 ps
CPU time 2.84 seconds
Started Jun 22 04:52:23 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 201232 kb
Host smart-acf94518-93fc-4a6b-ae3f-106d5b673e5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905250730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.3905250730
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3718230828
Short name T793
Test name
Test status
Simulation time 2609982234 ps
CPU time 6.9 seconds
Started Jun 22 04:52:27 PM PDT 24
Finished Jun 22 04:52:35 PM PDT 24
Peak memory 201220 kb
Host smart-6ccd4344-3c07-46f6-95d3-afc36b373728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718230828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.3718230828
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3208371273
Short name T473
Test name
Test status
Simulation time 2476888490 ps
CPU time 2.22 seconds
Started Jun 22 04:52:24 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 201148 kb
Host smart-554f775c-b53f-4f69-ba59-6ea746f084ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208371273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.3208371273
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3775953628
Short name T592
Test name
Test status
Simulation time 2245752913 ps
CPU time 3.63 seconds
Started Jun 22 04:52:25 PM PDT 24
Finished Jun 22 04:52:29 PM PDT 24
Peak memory 201240 kb
Host smart-b576b823-b749-4b13-9eb4-0ad314e031c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775953628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.3775953628
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2980826789
Short name T63
Test name
Test status
Simulation time 2519339628 ps
CPU time 3.81 seconds
Started Jun 22 04:52:36 PM PDT 24
Finished Jun 22 04:52:40 PM PDT 24
Peak memory 201292 kb
Host smart-11a1b376-e6a9-4b2c-a486-fcfc3da24af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980826789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2980826789
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.3174837312
Short name T403
Test name
Test status
Simulation time 2111725457 ps
CPU time 6.16 seconds
Started Jun 22 04:52:24 PM PDT 24
Finished Jun 22 04:52:30 PM PDT 24
Peak memory 201292 kb
Host smart-22d0d657-66c1-43a2-9f17-9a2e03b8152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174837312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3174837312
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.65073691
Short name T739
Test name
Test status
Simulation time 11960398679 ps
CPU time 8.66 seconds
Started Jun 22 04:52:29 PM PDT 24
Finished Jun 22 04:52:38 PM PDT 24
Peak memory 201228 kb
Host smart-cd69dc8d-334c-4802-9104-3031499effcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65073691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_str
ess_all.65073691
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2552654328
Short name T671
Test name
Test status
Simulation time 3971239849 ps
CPU time 6.61 seconds
Started Jun 22 04:52:28 PM PDT 24
Finished Jun 22 04:52:35 PM PDT 24
Peak memory 201236 kb
Host smart-cd8a961d-b4a0-4b92-a84a-e2f9de7ad2c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552654328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.2552654328
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.2978646248
Short name T646
Test name
Test status
Simulation time 2019958652 ps
CPU time 2.73 seconds
Started Jun 22 04:52:39 PM PDT 24
Finished Jun 22 04:52:42 PM PDT 24
Peak memory 201068 kb
Host smart-885fcd68-30cc-4126-ae6d-b8510dd6a831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978646248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.2978646248
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3127640393
Short name T489
Test name
Test status
Simulation time 3693094893 ps
CPU time 5.35 seconds
Started Jun 22 04:52:24 PM PDT 24
Finished Jun 22 04:52:30 PM PDT 24
Peak memory 201308 kb
Host smart-53586edb-c260-4849-80ea-43f08f9cc851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127640393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3
127640393
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.4084267448
Short name T269
Test name
Test status
Simulation time 106073156413 ps
CPU time 129.92 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:54:43 PM PDT 24
Peak memory 201292 kb
Host smart-3b313540-9efb-4738-9ff2-9011f4fac81e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084267448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.4084267448
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2016557014
Short name T611
Test name
Test status
Simulation time 3659729722 ps
CPU time 9.49 seconds
Started Jun 22 04:52:26 PM PDT 24
Finished Jun 22 04:52:36 PM PDT 24
Peak memory 201204 kb
Host smart-3d4f2d02-97cb-4827-abc7-d0fa07779258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016557014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.2016557014
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.489024921
Short name T196
Test name
Test status
Simulation time 4086843552 ps
CPU time 5.75 seconds
Started Jun 22 04:52:24 PM PDT 24
Finished Jun 22 04:52:31 PM PDT 24
Peak memory 201264 kb
Host smart-e696bb86-3ba6-4b92-b7c0-b66dd43f641b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489024921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctr
l_edge_detect.489024921
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2490206368
Short name T381
Test name
Test status
Simulation time 2618150707 ps
CPU time 3.9 seconds
Started Jun 22 04:52:25 PM PDT 24
Finished Jun 22 04:52:30 PM PDT 24
Peak memory 201252 kb
Host smart-aaa347c2-6120-4ba1-9a93-8c122e379f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490206368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.2490206368
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.235627403
Short name T524
Test name
Test status
Simulation time 2501624948 ps
CPU time 3.98 seconds
Started Jun 22 04:52:28 PM PDT 24
Finished Jun 22 04:52:33 PM PDT 24
Peak memory 201244 kb
Host smart-9cd9af87-81cb-4596-a9f2-84aee9849854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235627403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.235627403
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3096239694
Short name T506
Test name
Test status
Simulation time 2285272788 ps
CPU time 1.92 seconds
Started Jun 22 04:52:28 PM PDT 24
Finished Jun 22 04:52:31 PM PDT 24
Peak memory 201240 kb
Host smart-7dc9d3e6-bec1-45fa-902c-07c6d7bdd09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096239694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3096239694
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3662752541
Short name T588
Test name
Test status
Simulation time 2524042746 ps
CPU time 3.15 seconds
Started Jun 22 04:52:25 PM PDT 24
Finished Jun 22 04:52:29 PM PDT 24
Peak memory 201312 kb
Host smart-edc6a5bd-bf4c-4807-86f8-15152120b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662752541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.3662752541
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.2822256544
Short name T419
Test name
Test status
Simulation time 2128236823 ps
CPU time 1.75 seconds
Started Jun 22 04:52:29 PM PDT 24
Finished Jun 22 04:52:31 PM PDT 24
Peak memory 201068 kb
Host smart-a29d033a-45af-4976-a2e6-d3a88b14300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822256544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2822256544
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.1902280757
Short name T573
Test name
Test status
Simulation time 1504741165569 ps
CPU time 167.04 seconds
Started Jun 22 04:52:23 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 201324 kb
Host smart-c3b0d75f-90f7-4ab8-a6f0-3d422b085bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902280757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.1902280757
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.911124345
Short name T67
Test name
Test status
Simulation time 11768400565 ps
CPU time 8.23 seconds
Started Jun 22 04:52:23 PM PDT 24
Finished Jun 22 04:52:31 PM PDT 24
Peak memory 201204 kb
Host smart-bada0759-45a8-4e9a-a5de-5c90480d427c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911124345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ultra_low_pwr.911124345
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.3370963977
Short name T637
Test name
Test status
Simulation time 2112663759 ps
CPU time 0.94 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:52:37 PM PDT 24
Peak memory 201248 kb
Host smart-a683f19f-831c-4284-b3a9-8bb296680db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370963977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.3370963977
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.807060561
Short name T787
Test name
Test status
Simulation time 3111910262 ps
CPU time 4.83 seconds
Started Jun 22 04:52:30 PM PDT 24
Finished Jun 22 04:52:36 PM PDT 24
Peak memory 201272 kb
Host smart-d1b526de-1863-4fca-b734-3e528abae11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807060561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.807060561
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.375634557
Short name T252
Test name
Test status
Simulation time 22004092400 ps
CPU time 59.11 seconds
Started Jun 22 04:52:31 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 201484 kb
Host smart-558ab205-8d9d-421c-9081-71e6d5eb81b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375634557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_combo_detect.375634557
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3126239244
Short name T328
Test name
Test status
Simulation time 90348860419 ps
CPU time 238.84 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:56:43 PM PDT 24
Peak memory 201548 kb
Host smart-ca315199-35e2-44f1-9903-d87ebcd401f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126239244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.3126239244
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2603928689
Short name T208
Test name
Test status
Simulation time 5192697026 ps
CPU time 4 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:52:37 PM PDT 24
Peak memory 201080 kb
Host smart-b0b28937-e4e0-4bfa-be5c-2349d17811aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603928689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.2603928689
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3683747656
Short name T168
Test name
Test status
Simulation time 4311000905 ps
CPU time 5.98 seconds
Started Jun 22 04:52:41 PM PDT 24
Finished Jun 22 04:52:48 PM PDT 24
Peak memory 201212 kb
Host smart-15374f9a-33fe-4f4e-a537-f3784dba7de7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683747656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.3683747656
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3572081957
Short name T790
Test name
Test status
Simulation time 2610486670 ps
CPU time 7.41 seconds
Started Jun 22 04:52:39 PM PDT 24
Finished Jun 22 04:52:47 PM PDT 24
Peak memory 201056 kb
Host smart-b5381bd1-737c-4921-b74d-6ac419860d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572081957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3572081957
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.653872473
Short name T20
Test name
Test status
Simulation time 2517587107 ps
CPU time 1.35 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:52:35 PM PDT 24
Peak memory 201256 kb
Host smart-204cb5af-bb0f-4807-bf2c-99b544923fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653872473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.653872473
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2002002705
Short name T450
Test name
Test status
Simulation time 2077391959 ps
CPU time 5.66 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:52:39 PM PDT 24
Peak memory 201180 kb
Host smart-fcadadc7-c512-427e-9b49-a44d57bad2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002002705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2002002705
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.854963317
Short name T546
Test name
Test status
Simulation time 2510309109 ps
CPU time 7.41 seconds
Started Jun 22 04:52:30 PM PDT 24
Finished Jun 22 04:52:38 PM PDT 24
Peak memory 201300 kb
Host smart-4ff4a4bb-0e43-4a55-889c-c16eded22c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854963317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.854963317
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2189377765
Short name T391
Test name
Test status
Simulation time 2114012466 ps
CPU time 3.01 seconds
Started Jun 22 04:52:23 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 201208 kb
Host smart-0b9ba427-3deb-4737-a249-67234d255759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189377765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2189377765
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3798951661
Short name T713
Test name
Test status
Simulation time 7137480748 ps
CPU time 9.16 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 04:52:48 PM PDT 24
Peak memory 201264 kb
Host smart-7edc2407-7bde-4756-a781-9f8950874e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798951661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3798951661
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.614030540
Short name T493
Test name
Test status
Simulation time 4817059708 ps
CPU time 5.98 seconds
Started Jun 22 04:52:36 PM PDT 24
Finished Jun 22 04:52:43 PM PDT 24
Peak memory 201192 kb
Host smart-c427c56a-0802-4a93-903b-8144975bf7c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614030540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ultra_low_pwr.614030540
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.2891538482
Short name T716
Test name
Test status
Simulation time 2016443472 ps
CPU time 3.21 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 04:52:42 PM PDT 24
Peak memory 201248 kb
Host smart-5b0dca1e-694d-4c8a-a9fe-642cf5bfaa07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891538482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.2891538482
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2002462016
Short name T761
Test name
Test status
Simulation time 3814533439 ps
CPU time 5.61 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:52:39 PM PDT 24
Peak memory 201296 kb
Host smart-1acd9c2c-b07e-43fc-830a-a996ad113918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002462016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
002462016
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.418860112
Short name T539
Test name
Test status
Simulation time 83778018112 ps
CPU time 206.07 seconds
Started Jun 22 04:52:41 PM PDT 24
Finished Jun 22 04:56:08 PM PDT 24
Peak memory 201476 kb
Host smart-9575779b-6816-48cf-9ec2-dee6d49f3c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418860112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_wi
th_pre_cond.418860112
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.776144235
Short name T447
Test name
Test status
Simulation time 2722565993 ps
CPU time 7.08 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:52:40 PM PDT 24
Peak memory 201116 kb
Host smart-787608de-321b-4288-b2df-07fa84ac62f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776144235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ec_pwr_on_rst.776144235
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2595759494
Short name T140
Test name
Test status
Simulation time 4226123693 ps
CPU time 6 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:52:41 PM PDT 24
Peak memory 201212 kb
Host smart-958d8f00-9e06-4bfd-877c-e6887428108a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595759494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2595759494
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2218558062
Short name T156
Test name
Test status
Simulation time 2636531619 ps
CPU time 2.43 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:52:38 PM PDT 24
Peak memory 201224 kb
Host smart-62704414-5145-49b1-a7a8-42af9a22383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218558062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.2218558062
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.688510588
Short name T666
Test name
Test status
Simulation time 2459054500 ps
CPU time 6.98 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 201264 kb
Host smart-0a5be1bf-4eea-4f19-92da-4ae32987e26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688510588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.688510588
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2417313144
Short name T544
Test name
Test status
Simulation time 2144725190 ps
CPU time 6.28 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:52:42 PM PDT 24
Peak memory 201180 kb
Host smart-e9e91990-f2cf-4775-b322-048f9e648a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417313144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2417313144
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3809327509
Short name T691
Test name
Test status
Simulation time 2510387349 ps
CPU time 6.9 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:52:43 PM PDT 24
Peak memory 201316 kb
Host smart-42a889e6-a40f-488f-a9b7-86f54061613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809327509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3809327509
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.2794392331
Short name T507
Test name
Test status
Simulation time 2122990238 ps
CPU time 1.99 seconds
Started Jun 22 04:52:41 PM PDT 24
Finished Jun 22 04:52:44 PM PDT 24
Peak memory 201132 kb
Host smart-eb23be5f-1a3a-441d-9751-af3c13d7c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794392331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.2794392331
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2987800629
Short name T413
Test name
Test status
Simulation time 11162236248 ps
CPU time 29.3 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:53:04 PM PDT 24
Peak memory 201268 kb
Host smart-bdd8502a-2146-4a0d-97df-72ede791e3b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987800629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2987800629
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.830622495
Short name T455
Test name
Test status
Simulation time 5512457713 ps
CPU time 2.06 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:52:37 PM PDT 24
Peak memory 201204 kb
Host smart-b4571372-8767-4b7b-9773-29b956857f2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830622495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.830622495
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.946688961
Short name T397
Test name
Test status
Simulation time 2016068327 ps
CPU time 5.79 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:52:41 PM PDT 24
Peak memory 201248 kb
Host smart-a9a78007-0222-4f23-b270-f19971a8229b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946688961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_tes
t.946688961
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3971183088
Short name T434
Test name
Test status
Simulation time 3251902107 ps
CPU time 9.11 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201300 kb
Host smart-003b02b7-202b-4160-9cf0-b77ec9a1b956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971183088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3
971183088
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1442481711
Short name T182
Test name
Test status
Simulation time 161881232413 ps
CPU time 95.61 seconds
Started Jun 22 04:52:37 PM PDT 24
Finished Jun 22 04:54:13 PM PDT 24
Peak memory 201488 kb
Host smart-d24a4a2a-7789-4503-b6cc-d7693c916bfc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442481711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1442481711
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2307782239
Short name T417
Test name
Test status
Simulation time 4404509344 ps
CPU time 1.35 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 04:52:40 PM PDT 24
Peak memory 201128 kb
Host smart-97f5f696-bdc1-40f2-819f-e3fd8fe0f38c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307782239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.2307782239
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.193896740
Short name T152
Test name
Test status
Simulation time 2694178834 ps
CPU time 2.08 seconds
Started Jun 22 04:52:40 PM PDT 24
Finished Jun 22 04:52:42 PM PDT 24
Peak memory 201232 kb
Host smart-7f4f7e35-2ebe-46aa-bf75-10aa50864393
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193896740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctr
l_edge_detect.193896740
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.694375378
Short name T458
Test name
Test status
Simulation time 2612825235 ps
CPU time 4.05 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201252 kb
Host smart-6b55fd5b-9848-44f3-ac77-932354039354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694375378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.694375378
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2876585002
Short name T414
Test name
Test status
Simulation time 2477285261 ps
CPU time 7.5 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 201256 kb
Host smart-1b958760-cd87-4bcd-8d63-99621d86fdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876585002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2876585002
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3443447480
Short name T459
Test name
Test status
Simulation time 2085809692 ps
CPU time 6.35 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:52:50 PM PDT 24
Peak memory 201180 kb
Host smart-f8d3e3e7-fbec-4086-8855-579ae8782267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443447480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.3443447480
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.2599596585
Short name T647
Test name
Test status
Simulation time 2523459981 ps
CPU time 2.43 seconds
Started Jun 22 04:52:37 PM PDT 24
Finished Jun 22 04:52:40 PM PDT 24
Peak memory 201248 kb
Host smart-0ffc5974-7ff7-4484-a23d-42e87b6e72ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599596585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.2599596585
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.1628705311
Short name T625
Test name
Test status
Simulation time 2131229712 ps
CPU time 1.99 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:52:37 PM PDT 24
Peak memory 201144 kb
Host smart-61895af7-4d4d-4723-b9fd-85be04e884e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628705311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.1628705311
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.3743334562
Short name T547
Test name
Test status
Simulation time 13542219573 ps
CPU time 18.29 seconds
Started Jun 22 04:52:37 PM PDT 24
Finished Jun 22 04:52:57 PM PDT 24
Peak memory 201216 kb
Host smart-8dd57602-93d3-4a3c-b013-f8191b1a5b99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743334562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.3743334562
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2192921437
Short name T124
Test name
Test status
Simulation time 1566308699741 ps
CPU time 242.71 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:56:38 PM PDT 24
Peak memory 209808 kb
Host smart-81a7ceca-4230-481b-a01a-6ec1a6e1e6e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192921437 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.2192921437
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2022128331
Short name T126
Test name
Test status
Simulation time 7327965502 ps
CPU time 1.29 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 04:52:40 PM PDT 24
Peak memory 201164 kb
Host smart-7c02a865-04d5-47ff-bd4c-0f22d41b105e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022128331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.2022128331
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.4144599312
Short name T765
Test name
Test status
Simulation time 2022329550 ps
CPU time 3.25 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:52:47 PM PDT 24
Peak memory 201248 kb
Host smart-6239afa5-8d8c-4179-9ae8-310d77d18e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144599312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.4144599312
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3942935439
Short name T231
Test name
Test status
Simulation time 165125734349 ps
CPU time 397.16 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:59:11 PM PDT 24
Peak memory 201256 kb
Host smart-90b5b4b1-74d3-4cf0-9804-17782b4bc6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942935439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3
942935439
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.1792179321
Short name T250
Test name
Test status
Simulation time 191176624669 ps
CPU time 488.07 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 05:00:47 PM PDT 24
Peak memory 201412 kb
Host smart-d7626ffd-7d2c-443e-ae5b-58a54a214eef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792179321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.1792179321
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.748622449
Short name T351
Test name
Test status
Simulation time 147672634243 ps
CPU time 90.74 seconds
Started Jun 22 04:52:45 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 201440 kb
Host smart-d2101153-0da7-47b1-b984-645e8af7126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748622449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_wi
th_pre_cond.748622449
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1037648346
Short name T556
Test name
Test status
Simulation time 3435590138 ps
CPU time 3.9 seconds
Started Jun 22 04:52:45 PM PDT 24
Finished Jun 22 04:52:50 PM PDT 24
Peak memory 201224 kb
Host smart-28e2c0dc-3e53-4407-bea2-5be2bf5af097
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037648346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.1037648346
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1253707429
Short name T30
Test name
Test status
Simulation time 2527911395 ps
CPU time 2.79 seconds
Started Jun 22 04:52:45 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201080 kb
Host smart-92be0349-01d5-45f2-a486-787809930ad7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253707429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.1253707429
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4044296357
Short name T596
Test name
Test status
Simulation time 2634502974 ps
CPU time 2.35 seconds
Started Jun 22 04:52:37 PM PDT 24
Finished Jun 22 04:52:40 PM PDT 24
Peak memory 201164 kb
Host smart-c712a03a-036e-48ff-91c2-f0e71266691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044296357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.4044296357
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.918806563
Short name T379
Test name
Test status
Simulation time 2467557047 ps
CPU time 6.67 seconds
Started Jun 22 04:52:33 PM PDT 24
Finished Jun 22 04:52:41 PM PDT 24
Peak memory 201248 kb
Host smart-c3424cc9-a3e2-41bc-905f-7dede72c7795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918806563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.918806563
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.3814874466
Short name T84
Test name
Test status
Simulation time 2207565976 ps
CPU time 1.88 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 04:52:40 PM PDT 24
Peak memory 201228 kb
Host smart-714a1821-1845-4116-910c-73b491d33ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814874466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.3814874466
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2858654439
Short name T538
Test name
Test status
Simulation time 2513987513 ps
CPU time 4.25 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:52:47 PM PDT 24
Peak memory 201292 kb
Host smart-d90d5455-7dea-4f94-8171-2629494781b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858654439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2858654439
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.4019573727
Short name T136
Test name
Test status
Simulation time 2122373052 ps
CPU time 2.01 seconds
Started Jun 22 04:52:32 PM PDT 24
Finished Jun 22 04:52:35 PM PDT 24
Peak memory 201160 kb
Host smart-2d2ce480-beea-4bfd-820f-40fa87e57f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019573727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.4019573727
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.1887742243
Short name T367
Test name
Test status
Simulation time 105255217348 ps
CPU time 33.51 seconds
Started Jun 22 04:52:37 PM PDT 24
Finished Jun 22 04:53:11 PM PDT 24
Peak memory 201420 kb
Host smart-e9e1089f-e17f-4521-adff-3291478e78fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887742243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.1887742243
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1408414851
Short name T198
Test name
Test status
Simulation time 130240242074 ps
CPU time 151.34 seconds
Started Jun 22 04:52:41 PM PDT 24
Finished Jun 22 04:55:13 PM PDT 24
Peak memory 217368 kb
Host smart-a2d41109-6a9c-4485-95a5-afca218c9bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408414851 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.1408414851
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1283813602
Short name T430
Test name
Test status
Simulation time 6848481976 ps
CPU time 6.63 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:52:50 PM PDT 24
Peak memory 201168 kb
Host smart-242c161e-b58d-4a06-95aa-83df9faa54b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283813602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.1283813602
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.994989684
Short name T597
Test name
Test status
Simulation time 2012762833 ps
CPU time 5.86 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:52:41 PM PDT 24
Peak memory 201224 kb
Host smart-2c881077-50ef-4573-86d6-253a70709677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994989684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_tes
t.994989684
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.435642710
Short name T758
Test name
Test status
Simulation time 27682591117 ps
CPU time 67.7 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:53:52 PM PDT 24
Peak memory 201208 kb
Host smart-9091e6fd-b254-4c04-b81d-d5fcca83e08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435642710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.435642710
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.32115819
Short name T363
Test name
Test status
Simulation time 112929908126 ps
CPU time 303.2 seconds
Started Jun 22 04:52:40 PM PDT 24
Finished Jun 22 04:57:44 PM PDT 24
Peak memory 201500 kb
Host smart-427a8e2d-53f8-472d-b4e3-8bb0c8489576
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32115819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctr
l_combo_detect.32115819
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2981427360
Short name T435
Test name
Test status
Simulation time 48704033809 ps
CPU time 32.3 seconds
Started Jun 22 04:53:40 PM PDT 24
Finished Jun 22 04:54:13 PM PDT 24
Peak memory 201512 kb
Host smart-6d498bd0-742c-46f5-85fd-f48e7072c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981427360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2981427360
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2399376517
Short name T555
Test name
Test status
Simulation time 3700610724 ps
CPU time 5.1 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:52:41 PM PDT 24
Peak memory 201232 kb
Host smart-09c9c983-a101-483f-b7bf-3d7962a8f731
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399376517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.2399376517
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.3463208019
Short name T711
Test name
Test status
Simulation time 2685870764 ps
CPU time 7.48 seconds
Started Jun 22 04:52:40 PM PDT 24
Finished Jun 22 04:52:48 PM PDT 24
Peak memory 201264 kb
Host smart-ae6f8a53-837a-42d8-95e9-0a1fbb7c0125
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463208019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.3463208019
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2032276480
Short name T518
Test name
Test status
Simulation time 2618793229 ps
CPU time 4.07 seconds
Started Jun 22 04:52:34 PM PDT 24
Finished Jun 22 04:52:38 PM PDT 24
Peak memory 201248 kb
Host smart-b3fc6e84-f9a9-4ba2-8514-e806b021a8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032276480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2032276480
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2977723015
Short name T58
Test name
Test status
Simulation time 2468912667 ps
CPU time 2.14 seconds
Started Jun 22 04:52:36 PM PDT 24
Finished Jun 22 04:52:39 PM PDT 24
Peak memory 201256 kb
Host smart-460df323-43e7-4120-8432-57453985b606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977723015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2977723015
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3925893211
Short name T660
Test name
Test status
Simulation time 2219880498 ps
CPU time 6.23 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 04:52:45 PM PDT 24
Peak memory 201116 kb
Host smart-961b73e3-9a84-4b6a-8de0-1645f71bd28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925893211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.3925893211
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3446514818
Short name T686
Test name
Test status
Simulation time 2529166448 ps
CPU time 2.27 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:52:38 PM PDT 24
Peak memory 201320 kb
Host smart-b6c7d703-7c0e-472b-97f8-ccaf92c46c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446514818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3446514818
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.3175035481
Short name T571
Test name
Test status
Simulation time 2109738387 ps
CPU time 5.48 seconds
Started Jun 22 04:52:38 PM PDT 24
Finished Jun 22 04:52:44 PM PDT 24
Peak memory 201064 kb
Host smart-c4c2d260-62de-44f8-83c6-f98eb5604d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175035481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3175035481
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3456349913
Short name T371
Test name
Test status
Simulation time 14185643292 ps
CPU time 3.86 seconds
Started Jun 22 04:52:35 PM PDT 24
Finished Jun 22 04:52:39 PM PDT 24
Peak memory 201356 kb
Host smart-edde10b8-fd8b-4a9c-a242-9baa08daeed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456349913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3456349913
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2367133364
Short name T48
Test name
Test status
Simulation time 32490150414 ps
CPU time 21.93 seconds
Started Jun 22 04:52:36 PM PDT 24
Finished Jun 22 04:52:58 PM PDT 24
Peak memory 210724 kb
Host smart-2ef556a5-0930-4650-8e2b-e960940c84d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367133364 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2367133364
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.844203008
Short name T741
Test name
Test status
Simulation time 2028446568 ps
CPU time 1.87 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201240 kb
Host smart-1ea40690-3d6e-42e9-a175-730500335167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844203008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test
.844203008
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.940396157
Short name T426
Test name
Test status
Simulation time 3300802912 ps
CPU time 1.53 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:35 PM PDT 24
Peak memory 201268 kb
Host smart-f87bad79-83ad-49c0-9f8f-7adba7e9fcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940396157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.940396157
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.3419852684
Short name T361
Test name
Test status
Simulation time 145608085863 ps
CPU time 116.33 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:53:49 PM PDT 24
Peak memory 201244 kb
Host smart-0eb66b17-8e04-462c-aa4f-62f9bd4eee50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419852684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.3419852684
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3659005470
Short name T676
Test name
Test status
Simulation time 2503304945 ps
CPU time 1.08 seconds
Started Jun 22 04:51:32 PM PDT 24
Finished Jun 22 04:51:34 PM PDT 24
Peak memory 201248 kb
Host smart-4967aca8-f23a-43e0-bdce-50991a4c7b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659005470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3659005470
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3420627494
Short name T669
Test name
Test status
Simulation time 2321669376 ps
CPU time 2.12 seconds
Started Jun 22 04:51:43 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 201256 kb
Host smart-3a0d0fb2-35d6-4908-a4f1-07612a4c320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420627494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3420627494
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2271183711
Short name T92
Test name
Test status
Simulation time 25577119410 ps
CPU time 10.98 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:51:55 PM PDT 24
Peak memory 201572 kb
Host smart-9c98f4cb-2947-4dda-9d2f-3df77ee6ca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271183711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.2271183711
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2222553913
Short name T104
Test name
Test status
Simulation time 4526492433 ps
CPU time 12.55 seconds
Started Jun 22 04:51:35 PM PDT 24
Finished Jun 22 04:51:48 PM PDT 24
Peak memory 201204 kb
Host smart-5c929fdd-bbdc-4dec-9446-1fae042b4e59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222553913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.2222553913
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2652881059
Short name T9
Test name
Test status
Simulation time 5454548502 ps
CPU time 3.76 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201212 kb
Host smart-e885fa29-183a-4802-a254-4a850469756f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652881059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.2652881059
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3583760481
Short name T482
Test name
Test status
Simulation time 2614553951 ps
CPU time 6.17 seconds
Started Jun 22 04:51:35 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201148 kb
Host smart-c9925a5a-c8a1-4356-8655-d8f604a9c8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583760481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3583760481
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.4266663979
Short name T228
Test name
Test status
Simulation time 2468830344 ps
CPU time 2.4 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:50 PM PDT 24
Peak memory 201228 kb
Host smart-c13e63b3-5d96-4bac-a124-7ef5714c8a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266663979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.4266663979
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.2927940544
Short name T416
Test name
Test status
Simulation time 2057344169 ps
CPU time 3.24 seconds
Started Jun 22 04:51:33 PM PDT 24
Finished Jun 22 04:51:37 PM PDT 24
Peak memory 201164 kb
Host smart-bb00496a-9da9-47d7-ab23-63c70f65cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927940544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2927940544
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.392073882
Short name T488
Test name
Test status
Simulation time 2540094750 ps
CPU time 2.34 seconds
Started Jun 22 04:51:43 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 201308 kb
Host smart-ae7b1607-4a45-4669-87b4-4bd93fe4e4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392073882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.392073882
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2365701631
Short name T296
Test name
Test status
Simulation time 22013392310 ps
CPU time 56.72 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 220720 kb
Host smart-7317da27-ca27-4720-b9e7-7658eba5ee59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365701631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.2365701631
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.4083423151
Short name T675
Test name
Test status
Simulation time 2111897177 ps
CPU time 5.94 seconds
Started Jun 22 04:51:47 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201144 kb
Host smart-5360e4fe-bb16-459f-a88c-572691b31a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083423151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.4083423151
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.312384123
Short name T145
Test name
Test status
Simulation time 16734656259 ps
CPU time 31.26 seconds
Started Jun 22 04:51:48 PM PDT 24
Finished Jun 22 04:52:20 PM PDT 24
Peak memory 201132 kb
Host smart-3266c9e5-e6b7-40ae-b559-f00037fb0c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312384123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_str
ess_all.312384123
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.461111363
Short name T782
Test name
Test status
Simulation time 25267395598 ps
CPU time 62.81 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:52:47 PM PDT 24
Peak memory 201400 kb
Host smart-f7960e2c-f548-4694-9ca5-84ad90de4ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461111363 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.461111363
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2054991722
Short name T376
Test name
Test status
Simulation time 3173305742678 ps
CPU time 174.85 seconds
Started Jun 22 04:51:39 PM PDT 24
Finished Jun 22 04:54:34 PM PDT 24
Peak memory 201244 kb
Host smart-7b0c2a25-701e-44af-9fb4-b98534fcd964
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054991722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2054991722
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.3299956490
Short name T680
Test name
Test status
Simulation time 2013668898 ps
CPU time 6.02 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:52:51 PM PDT 24
Peak memory 201100 kb
Host smart-f4bd922d-b6bc-4e51-ba28-8179cd33ad0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299956490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.3299956490
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3426952049
Short name T45
Test name
Test status
Simulation time 2985932173 ps
CPU time 2.61 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:52:45 PM PDT 24
Peak memory 201296 kb
Host smart-a90f369d-408c-4f48-a8b2-f56fafdece65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426952049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.3
426952049
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.1192027294
Short name T26
Test name
Test status
Simulation time 81732361866 ps
CPU time 223.01 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:56:27 PM PDT 24
Peak memory 201504 kb
Host smart-53bcfda2-8fac-492e-968f-48c28bde3a09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192027294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.1192027294
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2503821772
Short name T474
Test name
Test status
Simulation time 3230400860 ps
CPU time 8.6 seconds
Started Jun 22 04:52:40 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201252 kb
Host smart-a572ef2c-248f-401e-8a5f-ffa696447145
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503821772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.2503821772
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1305261861
Short name T166
Test name
Test status
Simulation time 5152899438 ps
CPU time 11.31 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201208 kb
Host smart-ec5fec55-456c-4ada-b500-5b9dab4a6302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305261861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.1305261861
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3966431484
Short name T495
Test name
Test status
Simulation time 2628132609 ps
CPU time 2.69 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:52:45 PM PDT 24
Peak memory 201252 kb
Host smart-3cdfdfb4-923c-4d2f-92f7-c66d5bd876b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966431484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.3966431484
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1094562127
Short name T559
Test name
Test status
Simulation time 2476868202 ps
CPU time 5.45 seconds
Started Jun 22 04:52:39 PM PDT 24
Finished Jun 22 04:52:46 PM PDT 24
Peak memory 201256 kb
Host smart-19679210-dd0a-4620-b970-67f38a01850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094562127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1094562127
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.4650483
Short name T541
Test name
Test status
Simulation time 2018954154 ps
CPU time 5.56 seconds
Started Jun 22 04:52:53 PM PDT 24
Finished Jun 22 04:53:00 PM PDT 24
Peak memory 201036 kb
Host smart-e8783e39-303e-4417-937c-90c21434e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4650483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.4650483
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.31925646
Short name T469
Test name
Test status
Simulation time 2512421747 ps
CPU time 3.85 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:52:48 PM PDT 24
Peak memory 201292 kb
Host smart-9d0ce5fb-62b6-4568-9b93-ac355494336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31925646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.31925646
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.1262373361
Short name T478
Test name
Test status
Simulation time 2143735542 ps
CPU time 1.77 seconds
Started Jun 22 04:52:46 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201016 kb
Host smart-11afc94a-e348-49e2-84db-a6a27faad9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262373361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1262373361
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3691661665
Short name T725
Test name
Test status
Simulation time 18256538418 ps
CPU time 34.77 seconds
Started Jun 22 04:52:46 PM PDT 24
Finished Jun 22 04:53:21 PM PDT 24
Peak memory 201288 kb
Host smart-90dc6744-5717-4906-80c1-aaa3eed10f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691661665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.3691661665
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3475530584
Short name T712
Test name
Test status
Simulation time 12705380779 ps
CPU time 6.58 seconds
Started Jun 22 04:52:46 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201240 kb
Host smart-9cb3316a-14d5-4388-a9dc-7789fe895148
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475530584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.3475530584
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.1562195028
Short name T780
Test name
Test status
Simulation time 2013927645 ps
CPU time 6.04 seconds
Started Jun 22 04:52:47 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201148 kb
Host smart-a302d184-2b01-4539-9ebe-9fe713a2341b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562195028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.1562195028
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1577980284
Short name T566
Test name
Test status
Simulation time 3791986274 ps
CPU time 3.07 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:52:48 PM PDT 24
Peak memory 201292 kb
Host smart-5611c052-d1ca-4758-81aa-8fb951a2a504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577980284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.1
577980284
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.1220512622
Short name T270
Test name
Test status
Simulation time 63181660126 ps
CPU time 9.32 seconds
Started Jun 22 04:52:46 PM PDT 24
Finished Jun 22 04:52:56 PM PDT 24
Peak memory 201428 kb
Host smart-aaf1e6d7-a037-4da4-a150-2350bb4a1292
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220512622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.1220512622
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.837521031
Short name T348
Test name
Test status
Simulation time 33493349210 ps
CPU time 21.65 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:53:07 PM PDT 24
Peak memory 201364 kb
Host smart-1bf80a4c-f840-4a12-9aa4-2a4b71e97611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837521031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_wi
th_pre_cond.837521031
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.622360120
Short name T608
Test name
Test status
Simulation time 4962761099 ps
CPU time 12.33 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:52:57 PM PDT 24
Peak memory 201120 kb
Host smart-4f82299b-10cc-4822-bd08-e4117ed62d63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622360120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_ec_pwr_on_rst.622360120
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.818047914
Short name T35
Test name
Test status
Simulation time 2709735044 ps
CPU time 4.35 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:52:47 PM PDT 24
Peak memory 201232 kb
Host smart-2eab7c34-f1fd-42b0-acae-eec6e229270d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818047914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctr
l_edge_detect.818047914
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3332949599
Short name T727
Test name
Test status
Simulation time 2638979168 ps
CPU time 2.23 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:52:47 PM PDT 24
Peak memory 201144 kb
Host smart-43ff6cc8-1f87-467c-bba6-30acb4be707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332949599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.3332949599
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.3455836876
Short name T636
Test name
Test status
Simulation time 2500598156 ps
CPU time 2.13 seconds
Started Jun 22 04:52:53 PM PDT 24
Finished Jun 22 04:52:55 PM PDT 24
Peak memory 201104 kb
Host smart-4fd0d76e-8a2c-4763-9214-8e4bf9bf2d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455836876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.3455836876
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3053142260
Short name T203
Test name
Test status
Simulation time 2263916299 ps
CPU time 2.1 seconds
Started Jun 22 04:52:46 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201248 kb
Host smart-263e1db6-eb22-4658-a22f-51c144887902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053142260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3053142260
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2386895528
Short name T553
Test name
Test status
Simulation time 2509459222 ps
CPU time 6.61 seconds
Started Jun 22 04:52:41 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201280 kb
Host smart-551ffd1a-14d3-428d-a972-e698fc98e397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386895528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.2386895528
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.533377426
Short name T477
Test name
Test status
Simulation time 2137564620 ps
CPU time 1.29 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:52:44 PM PDT 24
Peak memory 201152 kb
Host smart-7843b9b9-97ce-4e56-bff2-265dd13f4b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533377426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.533377426
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1070620408
Short name T442
Test name
Test status
Simulation time 12007203476 ps
CPU time 8.83 seconds
Started Jun 22 04:52:42 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 201204 kb
Host smart-b0e1e885-e1d8-4151-a4d3-42984055c224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070620408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1070620408
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3621153476
Short name T1
Test name
Test status
Simulation time 8023801027 ps
CPU time 6.15 seconds
Started Jun 22 04:52:53 PM PDT 24
Finished Jun 22 04:53:00 PM PDT 24
Peak memory 201084 kb
Host smart-689705d7-5652-4965-b94d-d9c41c13317f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621153476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.3621153476
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.562428238
Short name T83
Test name
Test status
Simulation time 2013087710 ps
CPU time 5.89 seconds
Started Jun 22 04:52:46 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 201252 kb
Host smart-d2ac7e49-53eb-493b-9364-8a02556b694b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562428238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_tes
t.562428238
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2360136215
Short name T533
Test name
Test status
Simulation time 79064652477 ps
CPU time 191.87 seconds
Started Jun 22 04:52:45 PM PDT 24
Finished Jun 22 04:55:58 PM PDT 24
Peak memory 201152 kb
Host smart-53aa9eba-9b37-4c53-9f36-b98eae525b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360136215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2
360136215
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.2623166308
Short name T698
Test name
Test status
Simulation time 143265013871 ps
CPU time 351.06 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:59:40 PM PDT 24
Peak memory 201316 kb
Host smart-babbe300-efbf-4875-9b06-a5697ddd5aa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623166308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.2623166308
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.720775714
Short name T245
Test name
Test status
Simulation time 58621537514 ps
CPU time 154.26 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:55:18 PM PDT 24
Peak memory 201604 kb
Host smart-fc688746-9284-4754-8fd1-8f693ea5cf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720775714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_wi
th_pre_cond.720775714
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3889990747
Short name T464
Test name
Test status
Simulation time 1029178330442 ps
CPU time 2434.36 seconds
Started Jun 22 04:52:41 PM PDT 24
Finished Jun 22 05:33:17 PM PDT 24
Peak memory 201100 kb
Host smart-32cf08bf-99d9-4375-98b5-997776f01332
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889990747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.3889990747
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.545683666
Short name T746
Test name
Test status
Simulation time 2486939459 ps
CPU time 7.04 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 201420 kb
Host smart-296653bd-a466-4a7c-acee-977167d9495f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545683666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctr
l_edge_detect.545683666
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.764228718
Short name T128
Test name
Test status
Simulation time 2609284897 ps
CPU time 7.01 seconds
Started Jun 22 04:52:53 PM PDT 24
Finished Jun 22 04:53:01 PM PDT 24
Peak memory 201100 kb
Host smart-b874cfcb-8540-4f4a-abb3-832eb461ba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764228718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.764228718
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.285073554
Short name T302
Test name
Test status
Simulation time 2450308900 ps
CPU time 4.34 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201248 kb
Host smart-e5b5c325-1e5f-43ae-9c7a-6598ad6e7e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285073554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.285073554
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.2837277900
Short name T212
Test name
Test status
Simulation time 2085576408 ps
CPU time 1.41 seconds
Started Jun 22 04:52:45 PM PDT 24
Finished Jun 22 04:52:47 PM PDT 24
Peak memory 201180 kb
Host smart-72f83d14-accf-4370-911a-848835e807ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837277900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.2837277900
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3676469945
Short name T750
Test name
Test status
Simulation time 2510335540 ps
CPU time 6.95 seconds
Started Jun 22 04:52:41 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201320 kb
Host smart-06688e99-04dc-4e8b-b098-4b674ffc23fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676469945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.3676469945
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.2258818285
Short name T684
Test name
Test status
Simulation time 2111931849 ps
CPU time 5.52 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:52:50 PM PDT 24
Peak memory 201172 kb
Host smart-9d8a62c5-eaf0-4f3b-b50f-f638da447c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258818285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2258818285
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.1109562432
Short name T480
Test name
Test status
Simulation time 167145660303 ps
CPU time 77.78 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:54:02 PM PDT 24
Peak memory 201564 kb
Host smart-8de6710f-fd46-4893-8d87-27b48bab68cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109562432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.1109562432
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3276574021
Short name T11
Test name
Test status
Simulation time 49251098282 ps
CPU time 32.18 seconds
Started Jun 22 04:52:43 PM PDT 24
Finished Jun 22 04:53:16 PM PDT 24
Peak memory 209844 kb
Host smart-8f7e00e2-01f8-44f4-8dca-1f8a3ed50ba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276574021 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3276574021
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3129631907
Short name T119
Test name
Test status
Simulation time 6228348183 ps
CPU time 5.95 seconds
Started Jun 22 04:52:44 PM PDT 24
Finished Jun 22 04:52:51 PM PDT 24
Peak memory 201260 kb
Host smart-fda627ff-8b48-4a10-8dfb-0497af858613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129631907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.3129631907
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.3890860625
Short name T721
Test name
Test status
Simulation time 2020272618 ps
CPU time 2.95 seconds
Started Jun 22 04:52:51 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201240 kb
Host smart-3d6c5b3b-7696-499a-b803-d6fc54fa3a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890860625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.3890860625
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1928678245
Short name T395
Test name
Test status
Simulation time 3303296558 ps
CPU time 1.68 seconds
Started Jun 22 04:52:55 PM PDT 24
Finished Jun 22 04:52:57 PM PDT 24
Peak memory 201292 kb
Host smart-0c158105-6084-498e-956a-d9abf360a35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928678245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.1
928678245
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3540064110
Short name T110
Test name
Test status
Simulation time 71999419861 ps
CPU time 170.26 seconds
Started Jun 22 04:52:46 PM PDT 24
Finished Jun 22 04:55:37 PM PDT 24
Peak memory 201424 kb
Host smart-08f4a61e-241a-4956-b506-f6f5ee2333a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540064110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.3540064110
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3589645697
Short name T748
Test name
Test status
Simulation time 27839782647 ps
CPU time 32.02 seconds
Started Jun 22 04:52:49 PM PDT 24
Finished Jun 22 04:53:21 PM PDT 24
Peak memory 201560 kb
Host smart-95e37eaa-a071-4341-812b-03f563e14f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589645697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.3589645697
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3464296657
Short name T565
Test name
Test status
Simulation time 2830657877 ps
CPU time 6.67 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:04 PM PDT 24
Peak memory 201232 kb
Host smart-c0433b05-39aa-4ab8-8b95-0625703a0406
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464296657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3464296657
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1020736145
Short name T520
Test name
Test status
Simulation time 2627040342 ps
CPU time 2.47 seconds
Started Jun 22 04:52:51 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201244 kb
Host smart-5e40289f-96cf-4ac8-9f61-14d3e504c11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020736145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.1020736145
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1028636137
Short name T586
Test name
Test status
Simulation time 2480665935 ps
CPU time 6.96 seconds
Started Jun 22 04:52:51 PM PDT 24
Finished Jun 22 04:52:59 PM PDT 24
Peak memory 201248 kb
Host smart-7f9a86fc-68a3-4159-ba2f-41329b9e50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028636137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1028636137
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.4099395040
Short name T437
Test name
Test status
Simulation time 2018854060 ps
CPU time 5.77 seconds
Started Jun 22 04:52:48 PM PDT 24
Finished Jun 22 04:52:55 PM PDT 24
Peak memory 201184 kb
Host smart-6a98b15d-c587-4acf-a5d7-b1140c5bcce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099395040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.4099395040
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2611573709
Short name T107
Test name
Test status
Simulation time 2518589571 ps
CPU time 3.96 seconds
Started Jun 22 04:52:48 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 201316 kb
Host smart-1523a775-9c33-4abb-a662-be117a133685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611573709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.2611573709
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.3749243496
Short name T387
Test name
Test status
Simulation time 2139807282 ps
CPU time 1.9 seconds
Started Jun 22 04:52:47 PM PDT 24
Finished Jun 22 04:52:50 PM PDT 24
Peak memory 201148 kb
Host smart-a8804563-ab85-442d-8e22-42083f970c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749243496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.3749243496
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1343057475
Short name T39
Test name
Test status
Simulation time 75167124118 ps
CPU time 96.08 seconds
Started Jun 22 04:52:49 PM PDT 24
Finished Jun 22 04:54:26 PM PDT 24
Peak memory 209852 kb
Host smart-8489a2d6-9b5d-40c1-9c54-42444294a929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343057475 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.1343057475
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2479072231
Short name T233
Test name
Test status
Simulation time 890622689480 ps
CPU time 72.21 seconds
Started Jun 22 04:52:52 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 201268 kb
Host smart-66242f11-22e2-4ec7-9c64-e2c0542d1ed4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479072231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.2479072231
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.2846236300
Short name T704
Test name
Test status
Simulation time 2013314839 ps
CPU time 5.52 seconds
Started Jun 22 04:52:55 PM PDT 24
Finished Jun 22 04:53:01 PM PDT 24
Peak memory 201024 kb
Host smart-3833cb72-d4b5-4742-954a-9a38221686da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846236300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.2846236300
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1856275539
Short name T398
Test name
Test status
Simulation time 3561518094 ps
CPU time 2.52 seconds
Started Jun 22 04:52:47 PM PDT 24
Finished Jun 22 04:52:50 PM PDT 24
Peak memory 201296 kb
Host smart-ffecec07-e61b-416e-8df0-321c98b5c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856275539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.1
856275539
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.2338860329
Short name T268
Test name
Test status
Simulation time 156146265625 ps
CPU time 53.12 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:50 PM PDT 24
Peak memory 201488 kb
Host smart-d1f5ec86-7c20-4bfa-8b51-0d566465a487
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338860329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.2338860329
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.919027507
Short name T74
Test name
Test status
Simulation time 43021703711 ps
CPU time 33.05 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:30 PM PDT 24
Peak memory 201572 kb
Host smart-c8fabf86-9362-48d1-8779-ea0bc622622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919027507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_wi
th_pre_cond.919027507
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1619128481
Short name T52
Test name
Test status
Simulation time 398808632831 ps
CPU time 471.89 seconds
Started Jun 22 04:52:53 PM PDT 24
Finished Jun 22 05:00:46 PM PDT 24
Peak memory 201080 kb
Host smart-1eeddab1-b71b-4cca-84b3-ef8485fe6ac1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619128481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.1619128481
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.4162247293
Short name T165
Test name
Test status
Simulation time 4524526470 ps
CPU time 2.11 seconds
Started Jun 22 04:52:50 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 201232 kb
Host smart-86f1d054-c78c-4ead-b1fd-baffbbe647ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162247293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.4162247293
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3314842859
Short name T386
Test name
Test status
Simulation time 2632981912 ps
CPU time 1.95 seconds
Started Jun 22 04:52:47 PM PDT 24
Finished Jun 22 04:52:49 PM PDT 24
Peak memory 201244 kb
Host smart-6c23ca73-2333-4586-9b63-3733c2b3329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314842859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.3314842859
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1966231113
Short name T383
Test name
Test status
Simulation time 2470883353 ps
CPU time 3.62 seconds
Started Jun 22 04:52:47 PM PDT 24
Finished Jun 22 04:52:51 PM PDT 24
Peak memory 201128 kb
Host smart-6a82f8f8-df36-4167-9824-1a8399b75e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966231113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1966231113
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.4064886739
Short name T756
Test name
Test status
Simulation time 2259509922 ps
CPU time 0.92 seconds
Started Jun 22 04:52:50 PM PDT 24
Finished Jun 22 04:52:51 PM PDT 24
Peak memory 201248 kb
Host smart-37bf0044-b022-421b-93a7-2913efdbeca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064886739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.4064886739
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.2941842863
Short name T303
Test name
Test status
Simulation time 2507023616 ps
CPU time 6.95 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:04 PM PDT 24
Peak memory 201316 kb
Host smart-7384066a-2c6a-4ec0-964e-a3dbf03d90da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941842863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.2941842863
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.1684543461
Short name T584
Test name
Test status
Simulation time 2109571970 ps
CPU time 6.17 seconds
Started Jun 22 04:52:48 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201164 kb
Host smart-3e1ec175-06d5-4e3c-aa3b-d286b80e84d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684543461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.1684543461
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.2194048746
Short name T502
Test name
Test status
Simulation time 11149864146 ps
CPU time 7.98 seconds
Started Jun 22 04:52:54 PM PDT 24
Finished Jun 22 04:53:02 PM PDT 24
Peak memory 201076 kb
Host smart-f2195058-f193-4100-8b47-901ac98d8fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194048746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.2194048746
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2314323688
Short name T253
Test name
Test status
Simulation time 84508714890 ps
CPU time 25.93 seconds
Started Jun 22 04:52:54 PM PDT 24
Finished Jun 22 04:53:21 PM PDT 24
Peak memory 209836 kb
Host smart-846f7283-abcb-4730-9f4d-9df9add5e6cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314323688 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2314323688
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.970892859
Short name T8
Test name
Test status
Simulation time 8679773053 ps
CPU time 2.54 seconds
Started Jun 22 04:52:48 PM PDT 24
Finished Jun 22 04:52:51 PM PDT 24
Peak memory 201196 kb
Host smart-91404444-c142-4f67-a6a4-8a91f547a8b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970892859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ultra_low_pwr.970892859
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.1075801596
Short name T389
Test name
Test status
Simulation time 2010279790 ps
CPU time 5.82 seconds
Started Jun 22 04:52:56 PM PDT 24
Finished Jun 22 04:53:02 PM PDT 24
Peak memory 201148 kb
Host smart-ba97b78b-84e8-4bb7-8488-60645a7f76a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075801596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.1075801596
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2542560008
Short name T460
Test name
Test status
Simulation time 3033358085 ps
CPU time 4.37 seconds
Started Jun 22 04:52:46 PM PDT 24
Finished Jun 22 04:52:51 PM PDT 24
Peak memory 201292 kb
Host smart-085bcdce-e496-4ee5-8b93-cd3257937cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542560008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2
542560008
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.3222561880
Short name T28
Test name
Test status
Simulation time 138736815358 ps
CPU time 169.33 seconds
Started Jun 22 04:52:55 PM PDT 24
Finished Jun 22 04:55:45 PM PDT 24
Peak memory 201344 kb
Host smart-b1ff4673-cdea-4f91-91fb-dfc37198890f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222561880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.3222561880
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3300710684
Short name T779
Test name
Test status
Simulation time 267039012407 ps
CPU time 639.5 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 05:03:37 PM PDT 24
Peak memory 201476 kb
Host smart-6bd5d913-4628-49d9-8998-d578f454179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300710684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.3300710684
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.622392708
Short name T687
Test name
Test status
Simulation time 3169604408 ps
CPU time 9.13 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:07 PM PDT 24
Peak memory 201228 kb
Host smart-c6984891-3714-48c5-b033-1b4dbdc1cdf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622392708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ec_pwr_on_rst.622392708
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.1052373406
Short name T199
Test name
Test status
Simulation time 3238669970 ps
CPU time 3.35 seconds
Started Jun 22 04:52:55 PM PDT 24
Finished Jun 22 04:52:59 PM PDT 24
Peak memory 201208 kb
Host smart-c2207930-b90c-471f-8735-1198796cbb8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052373406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.1052373406
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3697783711
Short name T718
Test name
Test status
Simulation time 2610952839 ps
CPU time 7.08 seconds
Started Jun 22 04:52:47 PM PDT 24
Finished Jun 22 04:52:55 PM PDT 24
Peak memory 201224 kb
Host smart-49321e60-c0b9-4cff-8496-5967d3df4fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697783711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.3697783711
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1017944104
Short name T301
Test name
Test status
Simulation time 2477192971 ps
CPU time 5.61 seconds
Started Jun 22 04:52:48 PM PDT 24
Finished Jun 22 04:52:55 PM PDT 24
Peak memory 201256 kb
Host smart-82a2ae2b-c707-40f3-9747-b100b64b8359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017944104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1017944104
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1841890456
Short name T644
Test name
Test status
Simulation time 2106215937 ps
CPU time 3.15 seconds
Started Jun 22 04:52:48 PM PDT 24
Finished Jun 22 04:52:51 PM PDT 24
Peak memory 201172 kb
Host smart-126e137f-3ba3-48db-b208-ccbb289e2944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841890456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1841890456
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1528964652
Short name T408
Test name
Test status
Simulation time 2554290965 ps
CPU time 1.78 seconds
Started Jun 22 04:52:52 PM PDT 24
Finished Jun 22 04:52:54 PM PDT 24
Peak memory 201252 kb
Host smart-cb82437c-5c84-4185-a462-3613f2b31dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528964652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1528964652
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.3528649893
Short name T679
Test name
Test status
Simulation time 2144385057 ps
CPU time 1.34 seconds
Started Jun 22 04:52:49 PM PDT 24
Finished Jun 22 04:52:51 PM PDT 24
Peak memory 201208 kb
Host smart-0c733177-6204-4598-8f0f-b510b1b01aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528649893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3528649893
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.1735067663
Short name T38
Test name
Test status
Simulation time 11604527277 ps
CPU time 30.25 seconds
Started Jun 22 04:53:04 PM PDT 24
Finished Jun 22 04:53:35 PM PDT 24
Peak memory 201140 kb
Host smart-71d99e4e-1197-4403-9797-cb3ee9dd5ac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735067663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.1735067663
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3921699124
Short name T590
Test name
Test status
Simulation time 6827532495 ps
CPU time 6.95 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:05 PM PDT 24
Peak memory 201268 kb
Host smart-528070fa-2334-487c-aaed-27f70ff9703e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921699124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3921699124
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.3838186234
Short name T157
Test name
Test status
Simulation time 2021934999 ps
CPU time 5.4 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:53:07 PM PDT 24
Peak memory 201140 kb
Host smart-1d7cc4d6-b2f8-438a-a348-c9ae4acfd8f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838186234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.3838186234
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3667201037
Short name T298
Test name
Test status
Simulation time 3222101205 ps
CPU time 2.62 seconds
Started Jun 22 04:53:04 PM PDT 24
Finished Jun 22 04:53:08 PM PDT 24
Peak memory 201300 kb
Host smart-9b651296-a94e-4475-85dc-24087b17599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667201037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3
667201037
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.366483128
Short name T333
Test name
Test status
Simulation time 71954693828 ps
CPU time 44.05 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:53:45 PM PDT 24
Peak memory 201352 kb
Host smart-d097ab94-8140-43c0-b1a5-770b465943dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366483128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.366483128
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1917228854
Short name T694
Test name
Test status
Simulation time 89411477663 ps
CPU time 217.33 seconds
Started Jun 22 04:52:58 PM PDT 24
Finished Jun 22 04:56:36 PM PDT 24
Peak memory 201488 kb
Host smart-60827b8f-c23a-4124-8b4a-d1647085cbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917228854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.1917228854
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1940688462
Short name T15
Test name
Test status
Simulation time 3908230196 ps
CPU time 10.35 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:08 PM PDT 24
Peak memory 201208 kb
Host smart-67c1b369-9913-41c9-a1e4-9e09b77a4f55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940688462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.1940688462
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1100861297
Short name T690
Test name
Test status
Simulation time 3754117400 ps
CPU time 1.61 seconds
Started Jun 22 04:52:58 PM PDT 24
Finished Jun 22 04:53:00 PM PDT 24
Peak memory 201268 kb
Host smart-1bab99e3-5fa1-4ca5-bf31-dabf97ae72d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100861297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.1100861297
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3180115473
Short name T127
Test name
Test status
Simulation time 2621389702 ps
CPU time 4.12 seconds
Started Jun 22 04:52:59 PM PDT 24
Finished Jun 22 04:53:04 PM PDT 24
Peak memory 201244 kb
Host smart-d55c722f-9ee3-490c-888a-57e3dbb037d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180115473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.3180115473
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3934622005
Short name T582
Test name
Test status
Simulation time 2458122406 ps
CPU time 2.32 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:00 PM PDT 24
Peak memory 201248 kb
Host smart-14f86964-cc02-4dc9-a6ba-dc3d2785c698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934622005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3934622005
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2695436472
Short name T610
Test name
Test status
Simulation time 2233145854 ps
CPU time 3.6 seconds
Started Jun 22 04:52:57 PM PDT 24
Finished Jun 22 04:53:01 PM PDT 24
Peak memory 201228 kb
Host smart-6e56f491-7cfd-4fff-943f-58a10c5cef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695436472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2695436472
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.172943517
Short name T451
Test name
Test status
Simulation time 2531023818 ps
CPU time 1.85 seconds
Started Jun 22 04:52:56 PM PDT 24
Finished Jun 22 04:52:58 PM PDT 24
Peak memory 201300 kb
Host smart-6f214d22-1b1c-41f4-bdad-27042e96817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172943517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.172943517
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.1329926311
Short name T449
Test name
Test status
Simulation time 2115284032 ps
CPU time 3.29 seconds
Started Jun 22 04:52:56 PM PDT 24
Finished Jun 22 04:53:00 PM PDT 24
Peak memory 201132 kb
Host smart-7b66373e-0022-4d87-bf1c-4e6819d449fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329926311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1329926311
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.3702456502
Short name T463
Test name
Test status
Simulation time 11195694253 ps
CPU time 6.99 seconds
Started Jun 22 04:53:06 PM PDT 24
Finished Jun 22 04:53:14 PM PDT 24
Peak memory 201216 kb
Host smart-15a43e37-4659-4add-97c2-9a7cc45592fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702456502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.3702456502
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3380466610
Short name T377
Test name
Test status
Simulation time 1228902888989 ps
CPU time 41.09 seconds
Started Jun 22 04:52:58 PM PDT 24
Finished Jun 22 04:53:39 PM PDT 24
Peak memory 201264 kb
Host smart-28196ab5-936e-4d2c-aeea-e2541ec5f7ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380466610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.3380466610
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.3405825912
Short name T221
Test name
Test status
Simulation time 2011555510 ps
CPU time 5.77 seconds
Started Jun 22 04:53:05 PM PDT 24
Finished Jun 22 04:53:12 PM PDT 24
Peak memory 201248 kb
Host smart-22aaf834-d139-4cf9-b877-05c815ce0014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405825912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.3405825912
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3339235340
Short name T630
Test name
Test status
Simulation time 3502458639 ps
CPU time 2.92 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:53:04 PM PDT 24
Peak memory 201296 kb
Host smart-040aa77f-5b7a-40fb-a64b-33feb5085a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339235340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.3
339235340
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.969022069
Short name T258
Test name
Test status
Simulation time 72580817506 ps
CPU time 93.23 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:54:34 PM PDT 24
Peak memory 201424 kb
Host smart-3bf88912-8c5b-4cec-9fb3-b3971c0c71ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969022069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_combo_detect.969022069
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2860135133
Short name T44
Test name
Test status
Simulation time 36862342076 ps
CPU time 8.84 seconds
Started Jun 22 04:53:01 PM PDT 24
Finished Jun 22 04:53:11 PM PDT 24
Peak memory 201400 kb
Host smart-08a285d8-eac1-49fb-840e-7a6578114a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860135133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.2860135133
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.4099363503
Short name T613
Test name
Test status
Simulation time 5214399531 ps
CPU time 13.52 seconds
Started Jun 22 04:53:01 PM PDT 24
Finished Jun 22 04:53:15 PM PDT 24
Peak memory 201192 kb
Host smart-9e192121-ab7e-4500-b48c-cdbda17b815d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099363503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.4099363503
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3084330329
Short name T131
Test name
Test status
Simulation time 3486974081 ps
CPU time 2.02 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:53:03 PM PDT 24
Peak memory 201232 kb
Host smart-390bc99a-5964-4222-a4af-3129b28d858c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084330329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.3084330329
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.525307233
Short name T688
Test name
Test status
Simulation time 2625806955 ps
CPU time 2.31 seconds
Started Jun 22 04:53:01 PM PDT 24
Finished Jun 22 04:53:04 PM PDT 24
Peak memory 201252 kb
Host smart-da8f3d51-71f2-434b-8efe-00fbcb747a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525307233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.525307233
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.394629329
Short name T216
Test name
Test status
Simulation time 2447532640 ps
CPU time 7.92 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:53:08 PM PDT 24
Peak memory 201268 kb
Host smart-4476d43b-54e8-403f-91aa-434e300ab4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394629329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.394629329
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3939705380
Short name T487
Test name
Test status
Simulation time 2187917931 ps
CPU time 5.74 seconds
Started Jun 22 04:53:19 PM PDT 24
Finished Jun 22 04:53:25 PM PDT 24
Peak memory 201112 kb
Host smart-416c1a74-aec8-402e-8a78-b52c22c07f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939705380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3939705380
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2710269598
Short name T297
Test name
Test status
Simulation time 2534549376 ps
CPU time 2.34 seconds
Started Jun 22 04:52:58 PM PDT 24
Finished Jun 22 04:53:00 PM PDT 24
Peak memory 201316 kb
Host smart-7dd40a9c-a979-4ff9-b887-69eaf8c6aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710269598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2710269598
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1103434859
Short name T467
Test name
Test status
Simulation time 2117001409 ps
CPU time 3.22 seconds
Started Jun 22 04:53:04 PM PDT 24
Finished Jun 22 04:53:09 PM PDT 24
Peak memory 201004 kb
Host smart-eded3c9f-a3c6-4f45-b7ed-1af064fe6b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103434859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1103434859
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.1108531863
Short name T185
Test name
Test status
Simulation time 51899253050 ps
CPU time 128.6 seconds
Started Jun 22 04:53:01 PM PDT 24
Finished Jun 22 04:55:10 PM PDT 24
Peak memory 201420 kb
Host smart-284f8614-6509-4d55-b0a5-7c16fdc0e7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108531863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.1108531863
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2078993957
Short name T169
Test name
Test status
Simulation time 42849407723 ps
CPU time 109.21 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:54:54 PM PDT 24
Peak memory 218088 kb
Host smart-53a5e78d-7005-4658-b488-19018a267b85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078993957 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2078993957
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4064143712
Short name T56
Test name
Test status
Simulation time 3794310411 ps
CPU time 3.6 seconds
Started Jun 22 04:53:04 PM PDT 24
Finished Jun 22 04:53:09 PM PDT 24
Peak memory 201192 kb
Host smart-b8e14961-4b52-4aff-a65c-3daa773cbd6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064143712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.4064143712
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3220345441
Short name T406
Test name
Test status
Simulation time 2054068148 ps
CPU time 1.83 seconds
Started Jun 22 04:53:06 PM PDT 24
Finished Jun 22 04:53:09 PM PDT 24
Peak memory 201188 kb
Host smart-2df14089-890e-41dd-a312-8056946709e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220345441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3220345441
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1129985614
Short name T634
Test name
Test status
Simulation time 196898030076 ps
CPU time 85.25 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 201196 kb
Host smart-68a1d058-55a7-4974-8e54-2b9603a3161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129985614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.1
129985614
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2423585315
Short name T272
Test name
Test status
Simulation time 146708622069 ps
CPU time 240.05 seconds
Started Jun 22 04:53:05 PM PDT 24
Finished Jun 22 04:57:06 PM PDT 24
Peak memory 201380 kb
Host smart-4a1eb71c-1bf6-46f6-8ee6-f926c64ee09b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423585315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2423585315
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2964323351
Short name T747
Test name
Test status
Simulation time 3072950603 ps
CPU time 8.43 seconds
Started Jun 22 04:53:06 PM PDT 24
Finished Jun 22 04:53:15 PM PDT 24
Peak memory 201232 kb
Host smart-49c9ff78-cfad-4605-b7ab-c0b7a0e67a03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964323351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.2964323351
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3793086756
Short name T80
Test name
Test status
Simulation time 2621968014 ps
CPU time 5.85 seconds
Started Jun 22 04:53:06 PM PDT 24
Finished Jun 22 04:53:13 PM PDT 24
Peak memory 201208 kb
Host smart-3d910905-a548-4e28-a03d-5472759d0d62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793086756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.3793086756
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3738728111
Short name T641
Test name
Test status
Simulation time 2621462002 ps
CPU time 2.49 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:06 PM PDT 24
Peak memory 201248 kb
Host smart-8987871f-9a0c-4a69-a608-41567f7e3ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738728111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3738728111
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3622936491
Short name T757
Test name
Test status
Simulation time 2463529600 ps
CPU time 7.62 seconds
Started Jun 22 04:53:02 PM PDT 24
Finished Jun 22 04:53:11 PM PDT 24
Peak memory 201264 kb
Host smart-1fb003fe-14d6-4b2a-854b-3438aae4c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622936491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3622936491
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2969603020
Short name T752
Test name
Test status
Simulation time 2135232286 ps
CPU time 6.21 seconds
Started Jun 22 04:53:00 PM PDT 24
Finished Jun 22 04:53:07 PM PDT 24
Peak memory 201084 kb
Host smart-c0ddfb65-b1e6-49fa-819d-e6e1a1974593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969603020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.2969603020
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2747993648
Short name T724
Test name
Test status
Simulation time 2536626145 ps
CPU time 2.13 seconds
Started Jun 22 04:53:04 PM PDT 24
Finished Jun 22 04:53:08 PM PDT 24
Peak memory 201212 kb
Host smart-cfd2d38a-7f58-4dba-b053-3d84bed2d0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747993648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.2747993648
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.3180734931
Short name T542
Test name
Test status
Simulation time 2128477367 ps
CPU time 1.86 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:05 PM PDT 24
Peak memory 201168 kb
Host smart-9b7e2a9b-8a16-422f-8dd9-ec9225b819bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180734931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.3180734931
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1997410893
Short name T795
Test name
Test status
Simulation time 35363138898 ps
CPU time 14.74 seconds
Started Jun 22 04:53:07 PM PDT 24
Finished Jun 22 04:53:23 PM PDT 24
Peak memory 201340 kb
Host smart-78fd4b43-2fe2-4556-b697-430d6925e8fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997410893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1997410893
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2795235950
Short name T375
Test name
Test status
Simulation time 370254650436 ps
CPU time 8.47 seconds
Started Jun 22 04:53:05 PM PDT 24
Finished Jun 22 04:53:14 PM PDT 24
Peak memory 201228 kb
Host smart-a00293d3-8a25-46ff-bee9-eff236cafe1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795235950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.2795235950
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3688084270
Short name T745
Test name
Test status
Simulation time 2045057924 ps
CPU time 1.78 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:05 PM PDT 24
Peak memory 201248 kb
Host smart-16ae9283-d2ba-4bbd-98a8-369bb4ab67a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688084270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3688084270
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.4286555814
Short name T652
Test name
Test status
Simulation time 3157133167 ps
CPU time 8.79 seconds
Started Jun 22 04:53:02 PM PDT 24
Finished Jun 22 04:53:12 PM PDT 24
Peak memory 201196 kb
Host smart-43bfc2a9-0a9b-4a27-a447-d8dc2ae6d257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286555814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.4
286555814
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.2312018493
Short name T726
Test name
Test status
Simulation time 17388226729 ps
CPU time 12.37 seconds
Started Jun 22 04:53:07 PM PDT 24
Finished Jun 22 04:53:20 PM PDT 24
Peak memory 201372 kb
Host smart-359191e2-742e-44d8-b71f-dd1af80bcac0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312018493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.2312018493
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3169115346
Short name T697
Test name
Test status
Simulation time 3738169506 ps
CPU time 9.04 seconds
Started Jun 22 04:53:06 PM PDT 24
Finished Jun 22 04:53:15 PM PDT 24
Peak memory 201172 kb
Host smart-f3eeb8df-03c8-403e-9b5d-50d587fac2f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169115346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.3169115346
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.3137902936
Short name T494
Test name
Test status
Simulation time 397416101827 ps
CPU time 253.73 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:57:18 PM PDT 24
Peak memory 201268 kb
Host smart-62c5c9f8-2e75-4b0e-af19-5b527abf6541
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137902936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.3137902936
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2533001401
Short name T629
Test name
Test status
Simulation time 2618340479 ps
CPU time 4.21 seconds
Started Jun 22 04:53:06 PM PDT 24
Finished Jun 22 04:53:11 PM PDT 24
Peak memory 201196 kb
Host smart-f51b9425-b6a5-4215-9080-2234b9b723b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533001401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.2533001401
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2090190760
Short name T519
Test name
Test status
Simulation time 2485072423 ps
CPU time 4.22 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:08 PM PDT 24
Peak memory 201104 kb
Host smart-7792b679-1d1a-4b98-86c0-deff52a9fcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090190760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2090190760
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.1774317207
Short name T736
Test name
Test status
Simulation time 2267672063 ps
CPU time 2.05 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:05 PM PDT 24
Peak memory 201240 kb
Host smart-da1de476-1549-4b10-b0a4-52d881234cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774317207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.1774317207
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1872042687
Short name T223
Test name
Test status
Simulation time 2510493586 ps
CPU time 6.5 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:11 PM PDT 24
Peak memory 201320 kb
Host smart-7933753f-48c9-4aad-a5ed-a1299dbef6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872042687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1872042687
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.3222378045
Short name T785
Test name
Test status
Simulation time 2119064916 ps
CPU time 3.32 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:08 PM PDT 24
Peak memory 201168 kb
Host smart-dc93c2ea-f155-4c73-b1f1-614d36fbcf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222378045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3222378045
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.407727510
Short name T648
Test name
Test status
Simulation time 7629763641 ps
CPU time 5.17 seconds
Started Jun 22 04:53:01 PM PDT 24
Finished Jun 22 04:53:07 PM PDT 24
Peak memory 201100 kb
Host smart-279ab35c-1fbb-4a9d-b809-41fe64a86133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407727510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_st
ress_all.407727510
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2817693255
Short name T153
Test name
Test status
Simulation time 45942355779 ps
CPU time 29.86 seconds
Started Jun 22 04:53:04 PM PDT 24
Finished Jun 22 04:53:35 PM PDT 24
Peak memory 217624 kb
Host smart-8133df63-128f-4f64-a3df-fc0698f9f9f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817693255 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2817693255
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.867130176
Short name T55
Test name
Test status
Simulation time 7727453704 ps
CPU time 6.63 seconds
Started Jun 22 04:53:01 PM PDT 24
Finished Jun 22 04:53:09 PM PDT 24
Peak memory 201224 kb
Host smart-2ec1a557-acd4-4ca5-9737-be35a7b2e87b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867130176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_ultra_low_pwr.867130176
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.814908661
Short name T418
Test name
Test status
Simulation time 2036343621 ps
CPU time 1.8 seconds
Started Jun 22 04:51:36 PM PDT 24
Finished Jun 22 04:51:39 PM PDT 24
Peak memory 201176 kb
Host smart-0e2102a8-7906-45ed-a934-333f174088aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814908661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test
.814908661
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2019346455
Short name T404
Test name
Test status
Simulation time 3481067886 ps
CPU time 2.78 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201200 kb
Host smart-5aa44cc1-1809-426e-8927-04577de23e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019346455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2019346455
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.3480205998
Short name T535
Test name
Test status
Simulation time 95380560205 ps
CPU time 130.2 seconds
Started Jun 22 04:51:39 PM PDT 24
Finished Jun 22 04:53:50 PM PDT 24
Peak memory 201396 kb
Host smart-d0cc98ab-df67-406b-89c3-cce830c5c35b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480205998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.3480205998
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.827542631
Short name T702
Test name
Test status
Simulation time 2238230201 ps
CPU time 1.98 seconds
Started Jun 22 04:51:36 PM PDT 24
Finished Jun 22 04:51:39 PM PDT 24
Peak memory 201360 kb
Host smart-85248f39-9c29-40d0-8f59-9fcdfc46464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827542631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.827542631
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2411392271
Short name T722
Test name
Test status
Simulation time 2305411680 ps
CPU time 3.63 seconds
Started Jun 22 04:51:39 PM PDT 24
Finished Jun 22 04:51:43 PM PDT 24
Peak memory 201256 kb
Host smart-8de5f552-bae7-494f-98ae-00413fc547fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411392271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2411392271
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.104308542
Short name T160
Test name
Test status
Simulation time 50405550436 ps
CPU time 64.24 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:52:52 PM PDT 24
Peak memory 201548 kb
Host smart-709e964b-ec24-4677-9fdc-cefbe769488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104308542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wit
h_pre_cond.104308542
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3326881146
Short name T528
Test name
Test status
Simulation time 3558482022 ps
CPU time 2.66 seconds
Started Jun 22 04:51:43 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 201124 kb
Host smart-2fb6d141-9228-4942-9a62-495bfa308f82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326881146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.3326881146
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2453022786
Short name T599
Test name
Test status
Simulation time 3330153560 ps
CPU time 7.81 seconds
Started Jun 22 04:51:43 PM PDT 24
Finished Jun 22 04:51:51 PM PDT 24
Peak memory 201264 kb
Host smart-f8de09d2-0227-4b0b-b43c-bfb052669c06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453022786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.2453022786
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3715513590
Short name T409
Test name
Test status
Simulation time 2634129090 ps
CPU time 2.38 seconds
Started Jun 22 04:51:39 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201248 kb
Host smart-6270d41a-f2a2-452e-b57b-cfc71a29aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715513590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3715513590
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2769944510
Short name T603
Test name
Test status
Simulation time 2459252223 ps
CPU time 7.16 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:51:52 PM PDT 24
Peak memory 201212 kb
Host smart-0b1ee662-dfcb-4d36-9660-557a9b3b8815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769944510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.2769944510
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3959177497
Short name T443
Test name
Test status
Simulation time 2132558501 ps
CPU time 0.94 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:51:39 PM PDT 24
Peak memory 201180 kb
Host smart-3c7758b6-a594-4fc1-9b87-f261f1b4ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959177497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3959177497
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.818338709
Short name T717
Test name
Test status
Simulation time 2508952267 ps
CPU time 7 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:51:51 PM PDT 24
Peak memory 201296 kb
Host smart-3d73d771-96f6-4341-83da-818926b6f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818338709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.818338709
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2418960113
Short name T284
Test name
Test status
Simulation time 22008810515 ps
CPU time 60.33 seconds
Started Jun 22 04:51:38 PM PDT 24
Finished Jun 22 04:52:39 PM PDT 24
Peak memory 220828 kb
Host smart-d2a0aee9-d3cf-46e4-b700-dba9f6072937
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418960113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.2418960113
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.2500188215
Short name T429
Test name
Test status
Simulation time 2123534721 ps
CPU time 3.32 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201060 kb
Host smart-a993486f-7c85-46d3-aca7-27bcde5e981b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500188215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2500188215
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3394266005
Short name T14
Test name
Test status
Simulation time 10324642559 ps
CPU time 7.72 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:05 PM PDT 24
Peak memory 201128 kb
Host smart-1381894d-056e-4476-925a-3e6c793ad184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394266005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3394266005
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.878965709
Short name T209
Test name
Test status
Simulation time 2585746638 ps
CPU time 1.91 seconds
Started Jun 22 04:51:39 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201244 kb
Host smart-ce8aefd6-4ccb-4838-920c-d06ef211ba33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878965709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ultra_low_pwr.878965709
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.248724715
Short name T147
Test name
Test status
Simulation time 2012718744 ps
CPU time 5.78 seconds
Started Jun 22 04:53:02 PM PDT 24
Finished Jun 22 04:53:09 PM PDT 24
Peak memory 201152 kb
Host smart-1ec9c0ed-a0d1-4926-8335-10fc449d890c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248724715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.248724715
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3884528953
Short name T446
Test name
Test status
Simulation time 3584028809 ps
CPU time 9.69 seconds
Started Jun 22 04:53:02 PM PDT 24
Finished Jun 22 04:53:12 PM PDT 24
Peak memory 201268 kb
Host smart-c929c308-0d5d-4e65-b7ce-7f5f61ef4461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884528953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
884528953
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.313504898
Short name T102
Test name
Test status
Simulation time 90226727114 ps
CPU time 236.7 seconds
Started Jun 22 04:53:09 PM PDT 24
Finished Jun 22 04:57:07 PM PDT 24
Peak memory 201472 kb
Host smart-bd922264-4b09-4a52-a9a5-7b1a97d0fe44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313504898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_combo_detect.313504898
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2319612947
Short name T105
Test name
Test status
Simulation time 2932696074 ps
CPU time 1.05 seconds
Started Jun 22 04:53:02 PM PDT 24
Finished Jun 22 04:53:04 PM PDT 24
Peak memory 201232 kb
Host smart-956f0f19-107d-47fc-a7bc-537ef1c63f3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319612947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.2319612947
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.1724399362
Short name T150
Test name
Test status
Simulation time 3080819120 ps
CPU time 2.61 seconds
Started Jun 22 04:53:02 PM PDT 24
Finished Jun 22 04:53:05 PM PDT 24
Peak memory 201084 kb
Host smart-eabca4ff-9f47-4126-bbd2-c1cfe05e909a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724399362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.1724399362
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3636153044
Short name T390
Test name
Test status
Simulation time 2614950294 ps
CPU time 4.32 seconds
Started Jun 22 04:53:07 PM PDT 24
Finished Jun 22 04:53:12 PM PDT 24
Peak memory 201220 kb
Host smart-973300a5-831b-443e-841e-6b9f5e8956b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636153044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3636153044
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2525630703
Short name T492
Test name
Test status
Simulation time 2480893548 ps
CPU time 3.86 seconds
Started Jun 22 04:53:09 PM PDT 24
Finished Jun 22 04:53:14 PM PDT 24
Peak memory 201236 kb
Host smart-5733c582-8659-4ad6-8e0a-82d771a1e10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525630703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2525630703
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1508459501
Short name T649
Test name
Test status
Simulation time 2190786157 ps
CPU time 3.02 seconds
Started Jun 22 04:53:09 PM PDT 24
Finished Jun 22 04:53:12 PM PDT 24
Peak memory 201220 kb
Host smart-ed84a938-c5ab-4ef9-bf6c-bdf2654da1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508459501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.1508459501
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3008884417
Short name T62
Test name
Test status
Simulation time 2527729795 ps
CPU time 2.12 seconds
Started Jun 22 04:53:09 PM PDT 24
Finished Jun 22 04:53:12 PM PDT 24
Peak memory 201296 kb
Host smart-593abc21-0023-44e4-96be-5ecdb55ee81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008884417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3008884417
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.3844395063
Short name T173
Test name
Test status
Simulation time 2166572969 ps
CPU time 1.07 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:05 PM PDT 24
Peak memory 201228 kb
Host smart-a1cfc5bd-6437-4ce2-8398-d3eb0a826479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844395063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.3844395063
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.3573027319
Short name T61
Test name
Test status
Simulation time 6897020973 ps
CPU time 16.86 seconds
Started Jun 22 04:53:09 PM PDT 24
Finished Jun 22 04:53:27 PM PDT 24
Peak memory 201208 kb
Host smart-57121d1e-d973-4480-bfe0-9d82a549b4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573027319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.3573027319
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2902190946
Short name T300
Test name
Test status
Simulation time 192485148394 ps
CPU time 72.42 seconds
Started Jun 22 04:53:09 PM PDT 24
Finished Jun 22 04:54:22 PM PDT 24
Peak memory 213756 kb
Host smart-d3192afc-b0d4-4075-b742-e7abe470a605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902190946 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2902190946
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2812186494
Short name T206
Test name
Test status
Simulation time 1476446959332 ps
CPU time 80.31 seconds
Started Jun 22 04:53:07 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 201204 kb
Host smart-afa6b260-1d50-40fe-869b-b602c0d73b50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812186494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.2812186494
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.664799251
Short name T456
Test name
Test status
Simulation time 2011459206 ps
CPU time 4.55 seconds
Started Jun 22 04:53:13 PM PDT 24
Finished Jun 22 04:53:18 PM PDT 24
Peak memory 201252 kb
Host smart-a6f0854e-e37f-4973-aaf3-130f504651a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664799251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_tes
t.664799251
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.4255109316
Short name T490
Test name
Test status
Simulation time 3385145078 ps
CPU time 2.62 seconds
Started Jun 22 04:53:15 PM PDT 24
Finished Jun 22 04:53:18 PM PDT 24
Peak memory 201292 kb
Host smart-e6318f7f-bfe1-4f4e-a748-f2d5120d0e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255109316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.4
255109316
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1161760592
Short name T667
Test name
Test status
Simulation time 37403405880 ps
CPU time 102.95 seconds
Started Jun 22 04:53:11 PM PDT 24
Finished Jun 22 04:54:54 PM PDT 24
Peak memory 201696 kb
Host smart-c8d18329-dd9e-4f47-8749-35536a6e3b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161760592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1161760592
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1733414785
Short name T422
Test name
Test status
Simulation time 4246270857 ps
CPU time 2.07 seconds
Started Jun 22 04:53:16 PM PDT 24
Finished Jun 22 04:53:18 PM PDT 24
Peak memory 201204 kb
Host smart-704b1889-eb23-4b70-a4d9-0b804718b90e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733414785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.1733414785
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.2321054522
Short name T31
Test name
Test status
Simulation time 2952576805 ps
CPU time 5.85 seconds
Started Jun 22 04:53:12 PM PDT 24
Finished Jun 22 04:53:19 PM PDT 24
Peak memory 201232 kb
Host smart-64477841-f596-4f02-b5bc-c1b4a30f78bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321054522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.2321054522
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.349632301
Short name T195
Test name
Test status
Simulation time 2620680560 ps
CPU time 3.82 seconds
Started Jun 22 04:53:12 PM PDT 24
Finished Jun 22 04:53:17 PM PDT 24
Peak memory 201256 kb
Host smart-0bf1e292-9b60-45a1-8c98-4c47797d121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349632301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.349632301
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.381424952
Short name T191
Test name
Test status
Simulation time 2477115118 ps
CPU time 3.1 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:08 PM PDT 24
Peak memory 201256 kb
Host smart-db7ff3dc-0889-4512-8d63-79b31a7275d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381424952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.381424952
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3863842852
Short name T618
Test name
Test status
Simulation time 2046494586 ps
CPU time 3.26 seconds
Started Jun 22 04:53:04 PM PDT 24
Finished Jun 22 04:53:08 PM PDT 24
Peak memory 201148 kb
Host smart-a69a0e6a-a2fa-42c9-9e07-82500111175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863842852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.3863842852
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3178529794
Short name T639
Test name
Test status
Simulation time 2540620980 ps
CPU time 1.58 seconds
Started Jun 22 04:53:13 PM PDT 24
Finished Jun 22 04:53:15 PM PDT 24
Peak memory 201308 kb
Host smart-66307f42-636c-4e95-b338-d4226c58916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178529794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3178529794
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.2909814447
Short name T662
Test name
Test status
Simulation time 2117607006 ps
CPU time 3.11 seconds
Started Jun 22 04:53:03 PM PDT 24
Finished Jun 22 04:53:06 PM PDT 24
Peak memory 201152 kb
Host smart-6c33ccca-cd0d-4f5c-8eef-98e161599210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909814447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.2909814447
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.3690499082
Short name T607
Test name
Test status
Simulation time 11464927315 ps
CPU time 7.47 seconds
Started Jun 22 04:53:13 PM PDT 24
Finished Jun 22 04:53:21 PM PDT 24
Peak memory 201080 kb
Host smart-40aac255-6dc6-4924-893a-87fcdc43dd0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690499082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.3690499082
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3416595126
Short name T116
Test name
Test status
Simulation time 5288037840 ps
CPU time 7.35 seconds
Started Jun 22 04:53:10 PM PDT 24
Finished Jun 22 04:53:18 PM PDT 24
Peak memory 201392 kb
Host smart-a03ca11d-5d2f-4321-afe6-59d6678195ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416595126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.3416595126
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.3365171972
Short name T537
Test name
Test status
Simulation time 2035529511 ps
CPU time 1.86 seconds
Started Jun 22 04:53:14 PM PDT 24
Finished Jun 22 04:53:16 PM PDT 24
Peak memory 201156 kb
Host smart-40576578-50b2-4f0f-b15b-02e27d2a6f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365171972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.3365171972
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2079498111
Short name T388
Test name
Test status
Simulation time 2873656381 ps
CPU time 2.02 seconds
Started Jun 22 04:53:15 PM PDT 24
Finished Jun 22 04:53:18 PM PDT 24
Peak memory 201300 kb
Host smart-2880a16e-2fce-4f14-8217-d5503bfccd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079498111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.2
079498111
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1054893179
Short name T248
Test name
Test status
Simulation time 51900104305 ps
CPU time 24.73 seconds
Started Jun 22 04:53:14 PM PDT 24
Finished Jun 22 04:53:40 PM PDT 24
Peak memory 201400 kb
Host smart-aa05161c-e7c5-4c25-b9c6-bfbcece0c9d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054893179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1054893179
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2733457683
Short name T581
Test name
Test status
Simulation time 20861002112 ps
CPU time 10.96 seconds
Started Jun 22 04:53:15 PM PDT 24
Finished Jun 22 04:53:27 PM PDT 24
Peak memory 201604 kb
Host smart-0dce543f-8abb-4f89-9b30-39545f379bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733457683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2733457683
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.710118836
Short name T475
Test name
Test status
Simulation time 3384619474 ps
CPU time 2.58 seconds
Started Jun 22 04:53:16 PM PDT 24
Finished Jun 22 04:53:19 PM PDT 24
Peak memory 201224 kb
Host smart-1eb3cb09-8469-4cd2-9e8d-d128aee9e8d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710118836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.710118836
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.2045895990
Short name T161
Test name
Test status
Simulation time 2985890546 ps
CPU time 1.94 seconds
Started Jun 22 04:53:19 PM PDT 24
Finished Jun 22 04:53:21 PM PDT 24
Peak memory 201272 kb
Host smart-6331a391-8086-4f62-b87f-fe0164f36f01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045895990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.2045895990
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1856979259
Short name T501
Test name
Test status
Simulation time 2619200350 ps
CPU time 3.77 seconds
Started Jun 22 04:53:12 PM PDT 24
Finished Jun 22 04:53:17 PM PDT 24
Peak memory 201244 kb
Host smart-8fa0dbb1-8dbb-4d4d-bb3b-8e9cf1d7625d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856979259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1856979259
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4091944354
Short name T59
Test name
Test status
Simulation time 2465783272 ps
CPU time 3.64 seconds
Started Jun 22 04:53:14 PM PDT 24
Finished Jun 22 04:53:19 PM PDT 24
Peak memory 201152 kb
Host smart-015d2f32-3a2b-4bf2-9af8-25f71c2a6eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091944354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.4091944354
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.2101447679
Short name T428
Test name
Test status
Simulation time 2087812601 ps
CPU time 3.31 seconds
Started Jun 22 04:53:15 PM PDT 24
Finished Jun 22 04:53:19 PM PDT 24
Peak memory 201188 kb
Host smart-b9284630-26ea-4555-acbe-874b4c7a45fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101447679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.2101447679
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3974642533
Short name T378
Test name
Test status
Simulation time 2510672748 ps
CPU time 7.19 seconds
Started Jun 22 04:53:14 PM PDT 24
Finished Jun 22 04:53:22 PM PDT 24
Peak memory 201316 kb
Host smart-82e70bd2-fea8-46f8-9952-3ca9896412bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974642533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.3974642533
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.1198938541
Short name T278
Test name
Test status
Simulation time 2111804267 ps
CPU time 5.89 seconds
Started Jun 22 04:53:12 PM PDT 24
Finished Jun 22 04:53:18 PM PDT 24
Peak memory 201060 kb
Host smart-44d30908-7804-4645-bc88-af02fec0c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198938541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1198938541
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1770628054
Short name T710
Test name
Test status
Simulation time 14410271616 ps
CPU time 10.34 seconds
Started Jun 22 04:53:13 PM PDT 24
Finished Jun 22 04:53:24 PM PDT 24
Peak memory 201204 kb
Host smart-26bdab1b-0cf6-4e55-aee2-a64796fc3eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770628054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1770628054
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3020643337
Short name T78
Test name
Test status
Simulation time 153913671575 ps
CPU time 10.83 seconds
Started Jun 22 04:53:14 PM PDT 24
Finished Jun 22 04:53:26 PM PDT 24
Peak memory 201236 kb
Host smart-b9c7d29a-f45c-4093-98b7-4f2de0f09e2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020643337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.3020643337
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.71601167
Short name T672
Test name
Test status
Simulation time 2022366059 ps
CPU time 3.22 seconds
Started Jun 22 04:53:16 PM PDT 24
Finished Jun 22 04:53:19 PM PDT 24
Peak memory 201200 kb
Host smart-643e541d-8c71-4517-9a07-637e4a351398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71601167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test
.71601167
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2757870519
Short name T772
Test name
Test status
Simulation time 4016158267 ps
CPU time 9.8 seconds
Started Jun 22 04:53:14 PM PDT 24
Finished Jun 22 04:53:25 PM PDT 24
Peak memory 201232 kb
Host smart-c37fdd16-5173-4f8a-a063-2477d7f285f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757870519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2
757870519
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.4051406367
Short name T330
Test name
Test status
Simulation time 93130035114 ps
CPU time 254.52 seconds
Started Jun 22 04:53:17 PM PDT 24
Finished Jun 22 04:57:32 PM PDT 24
Peak memory 201444 kb
Host smart-728a1763-6218-4a30-93c6-1f4c5082f9cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051406367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.4051406367
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1849575028
Short name T703
Test name
Test status
Simulation time 4054643605 ps
CPU time 5.76 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:53:27 PM PDT 24
Peak memory 201224 kb
Host smart-f0e69da3-33a1-4d67-8b30-e48e6069d448
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849575028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.1849575028
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.1132069912
Short name T651
Test name
Test status
Simulation time 2946441238 ps
CPU time 2.26 seconds
Started Jun 22 04:53:16 PM PDT 24
Finished Jun 22 04:53:19 PM PDT 24
Peak memory 201192 kb
Host smart-d23b1ddc-38b1-4ff0-8cdf-8de429e0f403
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132069912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.1132069912
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3033444724
Short name T511
Test name
Test status
Simulation time 2612440176 ps
CPU time 7.55 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 201244 kb
Host smart-6c876f9a-545f-46d2-9fbc-a8ecfd93ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033444724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.3033444724
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1741668397
Short name T207
Test name
Test status
Simulation time 2467177703 ps
CPU time 6.62 seconds
Started Jun 22 04:53:24 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 201212 kb
Host smart-03cc5724-c92d-47da-8b54-4204f1b0264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741668397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.1741668397
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1917545115
Short name T737
Test name
Test status
Simulation time 2039930001 ps
CPU time 1.93 seconds
Started Jun 22 04:53:15 PM PDT 24
Finished Jun 22 04:53:17 PM PDT 24
Peak memory 201144 kb
Host smart-4ce857a4-f9d3-4ec4-a2ac-3ea290fa6fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917545115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.1917545115
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1741521720
Short name T700
Test name
Test status
Simulation time 2512143547 ps
CPU time 6.57 seconds
Started Jun 22 04:53:14 PM PDT 24
Finished Jun 22 04:53:22 PM PDT 24
Peak memory 201224 kb
Host smart-5b829ccb-efd8-4632-8b0d-c0c6ff07487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741521720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1741521720
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.4003303707
Short name T236
Test name
Test status
Simulation time 2112338887 ps
CPU time 5.68 seconds
Started Jun 22 04:53:13 PM PDT 24
Finished Jun 22 04:53:19 PM PDT 24
Peak memory 201012 kb
Host smart-b8872ac6-f74c-4eab-abdc-a909e497847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003303707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.4003303707
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.921303739
Short name T106
Test name
Test status
Simulation time 8229074733 ps
CPU time 4.6 seconds
Started Jun 22 04:53:15 PM PDT 24
Finished Jun 22 04:53:20 PM PDT 24
Peak memory 201228 kb
Host smart-fdf2be6e-a467-40d8-8e83-351f61d7bd85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921303739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_st
ress_all.921303739
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1023700228
Short name T246
Test name
Test status
Simulation time 14741964006 ps
CPU time 39.37 seconds
Started Jun 22 04:53:15 PM PDT 24
Finished Jun 22 04:53:55 PM PDT 24
Peak memory 209808 kb
Host smart-393ec129-f645-4324-a9ed-4d6d097042f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023700228 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.1023700228
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2487582140
Short name T628
Test name
Test status
Simulation time 4733420522 ps
CPU time 3.88 seconds
Started Jun 22 04:53:14 PM PDT 24
Finished Jun 22 04:53:18 PM PDT 24
Peak memory 201268 kb
Host smart-5b188088-7604-4fa0-8957-8f1d7883606b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487582140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.2487582140
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.3072887985
Short name T213
Test name
Test status
Simulation time 2013135376 ps
CPU time 5.43 seconds
Started Jun 22 04:53:19 PM PDT 24
Finished Jun 22 04:53:25 PM PDT 24
Peak memory 201072 kb
Host smart-a5ea1b85-e189-4ad2-a457-d39846e76856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072887985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.3072887985
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.244682535
Short name T47
Test name
Test status
Simulation time 3976551590 ps
CPU time 10.99 seconds
Started Jun 22 04:53:17 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 201288 kb
Host smart-4def4b00-34a5-4aed-ba22-4512576faa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244682535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.244682535
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1981384654
Short name T338
Test name
Test status
Simulation time 208217799899 ps
CPU time 177.59 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:56:20 PM PDT 24
Peak memory 201384 kb
Host smart-d293eee6-4958-43d7-8511-8b96cbb815a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981384654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1981384654
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.4224991023
Short name T234
Test name
Test status
Simulation time 61191508995 ps
CPU time 76.59 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:54:44 PM PDT 24
Peak memory 201548 kb
Host smart-072334e0-fbe1-43b4-b753-5ce85d5bd3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224991023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.4224991023
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.549987443
Short name T220
Test name
Test status
Simulation time 5095925527 ps
CPU time 12.7 seconds
Started Jun 22 04:53:18 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 201228 kb
Host smart-c45e6419-9c24-405d-b648-0d4efe74e7eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549987443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_ec_pwr_on_rst.549987443
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2599183893
Short name T681
Test name
Test status
Simulation time 424307567841 ps
CPU time 14.49 seconds
Started Jun 22 04:53:19 PM PDT 24
Finished Jun 22 04:53:34 PM PDT 24
Peak memory 201236 kb
Host smart-cd79b67e-4e98-4baa-97b2-3fbe730bc78e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599183893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.2599183893
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4222127620
Short name T601
Test name
Test status
Simulation time 2609577555 ps
CPU time 7.24 seconds
Started Jun 22 04:53:22 PM PDT 24
Finished Jun 22 04:53:30 PM PDT 24
Peak memory 201248 kb
Host smart-67e28a76-197e-4d6a-b4c8-402a2a3ca6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222127620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.4222127620
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.4074447308
Short name T277
Test name
Test status
Simulation time 2457118585 ps
CPU time 6.26 seconds
Started Jun 22 04:53:29 PM PDT 24
Finished Jun 22 04:53:36 PM PDT 24
Peak memory 201256 kb
Host smart-a80329d2-296d-44f2-be76-42a9def71c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074447308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.4074447308
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3644998890
Short name T158
Test name
Test status
Simulation time 2182123380 ps
CPU time 1.84 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 201248 kb
Host smart-98629f79-2920-4d63-ac06-1e7c78ee2207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644998890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3644998890
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2657481589
Short name T483
Test name
Test status
Simulation time 2548057965 ps
CPU time 1.58 seconds
Started Jun 22 04:53:24 PM PDT 24
Finished Jun 22 04:53:26 PM PDT 24
Peak memory 201424 kb
Host smart-057689bb-89ad-4a29-b778-f329897d8b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657481589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2657481589
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.2839751061
Short name T444
Test name
Test status
Simulation time 2108732620 ps
CPU time 5.99 seconds
Started Jun 22 04:53:17 PM PDT 24
Finished Jun 22 04:53:23 PM PDT 24
Peak memory 201168 kb
Host smart-94911cdd-e6a8-4516-9557-ef21755213c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839751061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2839751061
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.923950876
Short name T744
Test name
Test status
Simulation time 119247269747 ps
CPU time 57.18 seconds
Started Jun 22 04:53:18 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 201500 kb
Host smart-b66fc5b6-b681-4f57-a6dc-3fea6c125fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923950876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_st
ress_all.923950876
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1545660983
Short name T500
Test name
Test status
Simulation time 14118880290 ps
CPU time 38.49 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 210472 kb
Host smart-c86bfe06-1c08-4920-9ee2-9a41d92e700e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545660983 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1545660983
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.1173923753
Short name T275
Test name
Test status
Simulation time 2011756794 ps
CPU time 5.96 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:53:28 PM PDT 24
Peak memory 201248 kb
Host smart-371a9a18-f2ac-4db7-8a2e-3e6fd858fc45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173923753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.1173923753
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4046466476
Short name T50
Test name
Test status
Simulation time 3387925050 ps
CPU time 7.82 seconds
Started Jun 22 04:53:19 PM PDT 24
Finished Jun 22 04:53:27 PM PDT 24
Peak memory 201268 kb
Host smart-a1af4e3c-d918-4285-b69c-51efc627786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046466476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.4
046466476
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.4244550958
Short name T733
Test name
Test status
Simulation time 121506673125 ps
CPU time 321.77 seconds
Started Jun 22 04:53:18 PM PDT 24
Finished Jun 22 04:58:41 PM PDT 24
Peak memory 201424 kb
Host smart-55fec4ed-b643-428b-bb8b-42cfd901e6ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244550958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.4244550958
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2858924313
Short name T514
Test name
Test status
Simulation time 25848731856 ps
CPU time 17.83 seconds
Started Jun 22 04:53:34 PM PDT 24
Finished Jun 22 04:53:53 PM PDT 24
Peak memory 201572 kb
Host smart-ebefef2c-f02a-4410-aed9-a3b25925b64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858924313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.2858924313
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1064255639
Short name T421
Test name
Test status
Simulation time 3470598345 ps
CPU time 1.64 seconds
Started Jun 22 04:53:27 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 201228 kb
Host smart-b1b2b3e5-2d37-4ea5-9f0e-fc5e4bfe82f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064255639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.1064255639
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1652621410
Short name T453
Test name
Test status
Simulation time 2693710075 ps
CPU time 1.1 seconds
Started Jun 22 04:53:19 PM PDT 24
Finished Jun 22 04:53:20 PM PDT 24
Peak memory 201140 kb
Host smart-0e3a5d29-160f-45cd-894b-81c196bf006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652621410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.1652621410
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1927331258
Short name T405
Test name
Test status
Simulation time 2468755053 ps
CPU time 2.6 seconds
Started Jun 22 04:53:17 PM PDT 24
Finished Jun 22 04:53:21 PM PDT 24
Peak memory 201220 kb
Host smart-e669e425-3c7e-4631-8166-a4f93640f59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927331258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1927331258
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.661303760
Short name T614
Test name
Test status
Simulation time 2219656122 ps
CPU time 1.49 seconds
Started Jun 22 04:53:17 PM PDT 24
Finished Jun 22 04:53:18 PM PDT 24
Peak memory 201240 kb
Host smart-6817c1ff-5e64-4f9a-a906-16b91cb36364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661303760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.661303760
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1994154438
Short name T705
Test name
Test status
Simulation time 2524722974 ps
CPU time 2.32 seconds
Started Jun 22 04:53:20 PM PDT 24
Finished Jun 22 04:53:23 PM PDT 24
Peak memory 201216 kb
Host smart-6a85ba69-6884-4829-9ff2-b4d2c73e5074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994154438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.1994154438
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.1921167777
Short name T457
Test name
Test status
Simulation time 2113470066 ps
CPU time 3.35 seconds
Started Jun 22 04:53:19 PM PDT 24
Finished Jun 22 04:53:23 PM PDT 24
Peak memory 201124 kb
Host smart-72fc8a30-b1f0-4334-8ce8-8e1b245df435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921167777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.1921167777
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.4180307243
Short name T225
Test name
Test status
Simulation time 13617722498 ps
CPU time 33.53 seconds
Started Jun 22 04:53:25 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 201228 kb
Host smart-edf4afd2-a1c5-4587-bc0b-db4e5ac14164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180307243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.4180307243
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.939990153
Short name T79
Test name
Test status
Simulation time 1180013938295 ps
CPU time 205.83 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:56:47 PM PDT 24
Peak memory 201348 kb
Host smart-941bf4c9-4c6d-47a0-a2e4-6a9b56f0d6b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939990153 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.939990153
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4233874485
Short name T117
Test name
Test status
Simulation time 3877142404 ps
CPU time 1.45 seconds
Started Jun 22 04:53:22 PM PDT 24
Finished Jun 22 04:53:24 PM PDT 24
Peak memory 201232 kb
Host smart-7d7e9a8b-c509-4ad1-8da4-72ddc61dad11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233874485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.4233874485
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.3752183074
Short name T254
Test name
Test status
Simulation time 2018414681 ps
CPU time 3.11 seconds
Started Jun 22 04:53:18 PM PDT 24
Finished Jun 22 04:53:22 PM PDT 24
Peak memory 201248 kb
Host smart-4321d389-7114-432e-99c8-20897a15c7c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752183074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.3752183074
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2827818126
Short name T674
Test name
Test status
Simulation time 241798598175 ps
CPU time 119.09 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:55:23 PM PDT 24
Peak memory 201268 kb
Host smart-c87e7eee-8b54-4cd5-84f9-f40d0d2e54f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827818126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.2
827818126
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.2064437635
Short name T600
Test name
Test status
Simulation time 104816168130 ps
CPU time 56.29 seconds
Started Jun 22 04:53:22 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 201420 kb
Host smart-92e5971a-b5e4-4d8b-9ff8-3c1642f8b262
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064437635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.2064437635
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3851961272
Short name T742
Test name
Test status
Simulation time 2971797464 ps
CPU time 2.72 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:53:27 PM PDT 24
Peak memory 201220 kb
Host smart-a37cf76c-896d-41da-bb47-372c5876ef10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851961272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.3851961272
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.1503634382
Short name T201
Test name
Test status
Simulation time 4056816423 ps
CPU time 7.82 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 201200 kb
Host smart-c9ce642a-6de5-44ba-aa83-1c5ec77bb1cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503634382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.1503634382
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.496194579
Short name T740
Test name
Test status
Simulation time 2617616385 ps
CPU time 3.78 seconds
Started Jun 22 04:53:19 PM PDT 24
Finished Jun 22 04:53:24 PM PDT 24
Peak memory 201240 kb
Host smart-a413825e-d8d4-4d2b-8cd2-ec48cf8d0fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496194579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.496194579
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1616922796
Short name T523
Test name
Test status
Simulation time 2443641557 ps
CPU time 4.18 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:53:28 PM PDT 24
Peak memory 201256 kb
Host smart-ddc51f64-1439-47bf-bffb-3dd77173d976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616922796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1616922796
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.51395007
Short name T516
Test name
Test status
Simulation time 2068868103 ps
CPU time 3.43 seconds
Started Jun 22 04:53:25 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 201188 kb
Host smart-235b71e9-4fa2-45f2-9d81-2e5be42c4b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51395007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.51395007
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2203662605
Short name T471
Test name
Test status
Simulation time 2508675598 ps
CPU time 7.71 seconds
Started Jun 22 04:53:20 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 201332 kb
Host smart-0f8c3c79-619b-4991-8dcc-e5b2d17dc92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203662605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2203662605
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.3455366432
Short name T591
Test name
Test status
Simulation time 2113853869 ps
CPU time 5.71 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:53:32 PM PDT 24
Peak memory 201140 kb
Host smart-563033bb-ef35-4b2e-aa90-97179e83c826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455366432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.3455366432
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.3419362199
Short name T784
Test name
Test status
Simulation time 9194011614 ps
CPU time 11.43 seconds
Started Jun 22 04:53:22 PM PDT 24
Finished Jun 22 04:53:34 PM PDT 24
Peak memory 201200 kb
Host smart-ca41cfa0-da3d-4026-b7f8-a540aaf2026a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419362199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.3419362199
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3042443944
Short name T306
Test name
Test status
Simulation time 25114464126 ps
CPU time 58.34 seconds
Started Jun 22 04:53:20 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 209820 kb
Host smart-ee8367d6-4b56-49a4-889f-c57a0ea578ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042443944 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.3042443944
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.939536861
Short name T484
Test name
Test status
Simulation time 2027718342 ps
CPU time 1.93 seconds
Started Jun 22 04:53:32 PM PDT 24
Finished Jun 22 04:53:35 PM PDT 24
Peak memory 201212 kb
Host smart-f168edf2-4908-48a6-9c37-f5f2be3880d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939536861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_tes
t.939536861
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2117206692
Short name T46
Test name
Test status
Simulation time 3945217938 ps
CPU time 1.4 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:53:28 PM PDT 24
Peak memory 201308 kb
Host smart-3cbbdffc-4661-4c7f-867a-183819e8a046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117206692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.2
117206692
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2033374029
Short name T97
Test name
Test status
Simulation time 107726379029 ps
CPU time 262.86 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:57:47 PM PDT 24
Peak memory 201380 kb
Host smart-eea42332-12f4-4d06-b9d0-06b7671456c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033374029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.2033374029
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2680772009
Short name T602
Test name
Test status
Simulation time 78415207135 ps
CPU time 47.49 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:54:09 PM PDT 24
Peak memory 201580 kb
Host smart-a344bc96-5674-4270-928e-40cba1e73689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680772009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2680772009
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1650672256
Short name T578
Test name
Test status
Simulation time 2948035531 ps
CPU time 2.51 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:53:26 PM PDT 24
Peak memory 201216 kb
Host smart-37f41161-de63-4632-8e2f-081852ba89f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650672256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.1650672256
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.35625910
Short name T40
Test name
Test status
Simulation time 2595739793 ps
CPU time 4.19 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 201264 kb
Host smart-0af19501-7d83-4dee-823f-9dd95d6cf4b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35625910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl
_edge_detect.35625910
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.477036613
Short name T393
Test name
Test status
Simulation time 2615332571 ps
CPU time 7.64 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 201236 kb
Host smart-278ff817-5d53-4a75-9029-5d8e1f92e5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477036613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.477036613
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1962052764
Short name T768
Test name
Test status
Simulation time 2470387114 ps
CPU time 3.33 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:53:25 PM PDT 24
Peak memory 201228 kb
Host smart-5b87f7ce-ed7d-42bc-ad82-cd7a6be51dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962052764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.1962052764
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.822436338
Short name T210
Test name
Test status
Simulation time 2185169937 ps
CPU time 2.48 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:53:26 PM PDT 24
Peak memory 201236 kb
Host smart-b024652d-8d14-4474-b60f-6f92101f77cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822436338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.822436338
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1234421330
Short name T783
Test name
Test status
Simulation time 2510875676 ps
CPU time 6.69 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 201288 kb
Host smart-7216b1ee-b013-45b4-989d-c11a5b8eba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234421330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1234421330
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.2750016353
Short name T13
Test name
Test status
Simulation time 2110003853 ps
CPU time 6.14 seconds
Started Jun 22 04:53:24 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 201160 kb
Host smart-a9602512-e938-4784-9dda-e053f445f3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750016353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2750016353
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.1937943384
Short name T54
Test name
Test status
Simulation time 15441466508 ps
CPU time 9.76 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:53:36 PM PDT 24
Peak memory 201224 kb
Host smart-a1d19c33-c69e-4e71-bcd2-88c2614ae526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937943384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.1937943384
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.507918550
Short name T163
Test name
Test status
Simulation time 17722507730 ps
CPU time 42.48 seconds
Started Jun 22 04:53:21 PM PDT 24
Finished Jun 22 04:54:04 PM PDT 24
Peak memory 201500 kb
Host smart-ab3ebe04-330f-4252-aa85-99536a8c297c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507918550 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.507918550
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1654439283
Short name T563
Test name
Test status
Simulation time 6575653511 ps
CPU time 4.42 seconds
Started Jun 22 04:53:23 PM PDT 24
Finished Jun 22 04:53:27 PM PDT 24
Peak memory 201216 kb
Host smart-3b93bd92-fba5-4438-8cbc-f17211e81ad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654439283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.1654439283
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3624594153
Short name T627
Test name
Test status
Simulation time 2027700089 ps
CPU time 1.82 seconds
Started Jun 22 04:53:27 PM PDT 24
Finished Jun 22 04:53:30 PM PDT 24
Peak memory 201212 kb
Host smart-2a69ce09-405a-4a1c-af08-f954453b21da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624594153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3624594153
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1234451686
Short name T558
Test name
Test status
Simulation time 3433291252 ps
CPU time 4.72 seconds
Started Jun 22 04:53:34 PM PDT 24
Finished Jun 22 04:53:40 PM PDT 24
Peak memory 201296 kb
Host smart-12f4a5dc-65d2-457b-b7c9-9477cc9ce73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234451686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1
234451686
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.2710712222
Short name T261
Test name
Test status
Simulation time 44754451402 ps
CPU time 51.39 seconds
Started Jun 22 04:53:28 PM PDT 24
Finished Jun 22 04:54:20 PM PDT 24
Peak memory 201424 kb
Host smart-491b0ed9-2256-4da3-a27c-584a75ae483e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710712222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.2710712222
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2527007872
Short name T86
Test name
Test status
Simulation time 26580832588 ps
CPU time 66.14 seconds
Started Jun 22 04:53:28 PM PDT 24
Finished Jun 22 04:54:35 PM PDT 24
Peak memory 201572 kb
Host smart-7a1cfbce-3149-4279-9709-480cfa883407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527007872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.2527007872
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1144541871
Short name T683
Test name
Test status
Simulation time 2557196501 ps
CPU time 4.05 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:53:40 PM PDT 24
Peak memory 201080 kb
Host smart-d230ccfa-6daf-47c1-9887-ef1935dcc25b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144541871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.1144541871
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3445034217
Short name T178
Test name
Test status
Simulation time 2613443117 ps
CPU time 7.58 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:53:34 PM PDT 24
Peak memory 201244 kb
Host smart-7821556f-565e-4a8d-836b-e03ae1f109a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445034217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3445034217
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3685094964
Short name T470
Test name
Test status
Simulation time 2452533903 ps
CPU time 4.42 seconds
Started Jun 22 04:53:30 PM PDT 24
Finished Jun 22 04:53:35 PM PDT 24
Peak memory 201156 kb
Host smart-889d05bf-7f2b-47f6-b79b-0473ef502f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685094964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3685094964
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.589059941
Short name T665
Test name
Test status
Simulation time 2173893341 ps
CPU time 1.99 seconds
Started Jun 22 04:53:25 PM PDT 24
Finished Jun 22 04:53:28 PM PDT 24
Peak memory 201244 kb
Host smart-ec9d7d8d-5c69-47ca-831d-4544244ea259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589059941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.589059941
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1682946480
Short name T491
Test name
Test status
Simulation time 2538801574 ps
CPU time 2.17 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:53:29 PM PDT 24
Peak memory 201320 kb
Host smart-35c4ca46-1a14-40b3-9185-599393a6d242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682946480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.1682946480
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.1525814530
Short name T215
Test name
Test status
Simulation time 2123945081 ps
CPU time 2.58 seconds
Started Jun 22 04:53:26 PM PDT 24
Finished Jun 22 04:53:30 PM PDT 24
Peak memory 201140 kb
Host smart-c67b2b2c-245f-40af-b0bb-f77d4d1a06e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525814530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.1525814530
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.4251342060
Short name T37
Test name
Test status
Simulation time 16666480553 ps
CPU time 29.32 seconds
Started Jun 22 04:53:29 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 201296 kb
Host smart-dc482cfd-a4a8-487f-9caf-2a19d3df6659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251342060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.4251342060
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1233797069
Short name T372
Test name
Test status
Simulation time 15479529551 ps
CPU time 42.78 seconds
Started Jun 22 04:53:28 PM PDT 24
Finished Jun 22 04:54:12 PM PDT 24
Peak memory 211124 kb
Host smart-4d543c91-48d4-4abc-a476-2bde2925233f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233797069 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.1233797069
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1069126607
Short name T510
Test name
Test status
Simulation time 5033164532 ps
CPU time 3.79 seconds
Started Jun 22 04:53:25 PM PDT 24
Finished Jun 22 04:53:30 PM PDT 24
Peak memory 201228 kb
Host smart-434670d1-f13e-44ae-982a-45ea33a857ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069126607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1069126607
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.2099428057
Short name T693
Test name
Test status
Simulation time 2015477454 ps
CPU time 4.1 seconds
Started Jun 22 04:53:34 PM PDT 24
Finished Jun 22 04:53:38 PM PDT 24
Peak memory 201260 kb
Host smart-5f5993d8-9eed-40af-b07a-ec7d69f1c4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099428057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.2099428057
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.422909638
Short name T108
Test name
Test status
Simulation time 3745411596 ps
CPU time 10.03 seconds
Started Jun 22 04:53:31 PM PDT 24
Finished Jun 22 04:53:42 PM PDT 24
Peak memory 201312 kb
Host smart-fea6c8f6-a33a-4b32-b122-e8cd3b1f1f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422909638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.422909638
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.4169665061
Short name T262
Test name
Test status
Simulation time 100834797882 ps
CPU time 268.85 seconds
Started Jun 22 04:53:34 PM PDT 24
Finished Jun 22 04:58:03 PM PDT 24
Peak memory 201424 kb
Host smart-4cb40bf5-2f0e-4d36-a329-827e6b06e790
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169665061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.4169665061
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2620707925
Short name T701
Test name
Test status
Simulation time 2756204052 ps
CPU time 2.24 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:53:36 PM PDT 24
Peak memory 201204 kb
Host smart-9fa23af2-e918-4af7-aef0-de539082fcdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620707925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.2620707925
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.4101980209
Short name T33
Test name
Test status
Simulation time 3347813118 ps
CPU time 6.67 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:53:41 PM PDT 24
Peak memory 201256 kb
Host smart-c18107b1-c6bf-4d73-8582-d4b940506507
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101980209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.4101980209
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3528739217
Short name T723
Test name
Test status
Simulation time 2610783231 ps
CPU time 7.88 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:55:03 PM PDT 24
Peak memory 201224 kb
Host smart-0c2e1dff-659e-42e0-8a66-f25ee598bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528739217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.3528739217
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1044411363
Short name T734
Test name
Test status
Simulation time 2516842829 ps
CPU time 1.24 seconds
Started Jun 22 04:53:32 PM PDT 24
Finished Jun 22 04:53:34 PM PDT 24
Peak memory 201256 kb
Host smart-16b08887-bac5-47b6-a231-62c1e5a722e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044411363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.1044411363
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1523946095
Short name T548
Test name
Test status
Simulation time 2215023166 ps
CPU time 6.21 seconds
Started Jun 22 04:53:31 PM PDT 24
Finished Jun 22 04:53:38 PM PDT 24
Peak memory 201220 kb
Host smart-0bcc3954-ce30-4936-9c24-d1372822a300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523946095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1523946095
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2449893675
Short name T589
Test name
Test status
Simulation time 2525134251 ps
CPU time 2.38 seconds
Started Jun 22 04:53:30 PM PDT 24
Finished Jun 22 04:53:33 PM PDT 24
Peak memory 201320 kb
Host smart-86fb4b10-8bdd-477f-94f8-d9c53ee287f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449893675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2449893675
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.2057626645
Short name T82
Test name
Test status
Simulation time 2113423272 ps
CPU time 3.22 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:53:40 PM PDT 24
Peak memory 201136 kb
Host smart-4848f389-6ebb-4372-862b-30b422675ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057626645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.2057626645
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.1840089580
Short name T167
Test name
Test status
Simulation time 1282961771902 ps
CPU time 536.33 seconds
Started Jun 22 04:53:38 PM PDT 24
Finished Jun 22 05:02:35 PM PDT 24
Peak memory 201476 kb
Host smart-aea9c4a7-1313-4856-8178-1a80d93fc498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840089580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.1840089580
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3906039554
Short name T326
Test name
Test status
Simulation time 15160536543 ps
CPU time 41.5 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:54:15 PM PDT 24
Peak memory 201396 kb
Host smart-f6f6cf5a-4bc6-4492-934c-4141066298e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906039554 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3906039554
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.920027923
Short name T374
Test name
Test status
Simulation time 297695449289 ps
CPU time 8.61 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:53:45 PM PDT 24
Peak memory 201232 kb
Host smart-4b9234ca-9a35-4a2b-8a72-2704fcdc91f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920027923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ultra_low_pwr.920027923
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.3069276679
Short name T462
Test name
Test status
Simulation time 2015687584 ps
CPU time 5.24 seconds
Started Jun 22 04:51:41 PM PDT 24
Finished Jun 22 04:51:47 PM PDT 24
Peak memory 201148 kb
Host smart-e3a51607-09c9-4b29-8e49-49d926a9b585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069276679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.3069276679
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2567345014
Short name T585
Test name
Test status
Simulation time 3513892347 ps
CPU time 1.89 seconds
Started Jun 22 04:51:54 PM PDT 24
Finished Jun 22 04:51:57 PM PDT 24
Peak memory 201132 kb
Host smart-5c66226d-a87e-45e3-86f5-c21775df976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567345014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2567345014
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2764726454
Short name T89
Test name
Test status
Simulation time 38080021609 ps
CPU time 49.16 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:52:34 PM PDT 24
Peak memory 201456 kb
Host smart-2f82bd83-d891-4907-8f88-c2d8595ca97d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764726454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.2764726454
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2320424569
Short name T653
Test name
Test status
Simulation time 78782292556 ps
CPU time 43.32 seconds
Started Jun 22 04:51:41 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 201476 kb
Host smart-4983bd07-ddb4-4c85-82d1-12a01c3f6250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320424569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.2320424569
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3894409549
Short name T425
Test name
Test status
Simulation time 2779797094 ps
CPU time 2.25 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201216 kb
Host smart-41f3860f-598c-4bea-a131-877810a24a44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894409549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.3894409549
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1546647508
Short name T217
Test name
Test status
Simulation time 2823108812 ps
CPU time 5.88 seconds
Started Jun 22 04:51:48 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201048 kb
Host smart-f791d6df-cfdb-4713-a8c8-733e3a30fd9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546647508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.1546647508
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.4194289668
Short name T715
Test name
Test status
Simulation time 2622227626 ps
CPU time 2.33 seconds
Started Jun 22 04:51:39 PM PDT 24
Finished Jun 22 04:51:42 PM PDT 24
Peak memory 201224 kb
Host smart-93e5ddfd-4f51-487e-bb2b-2dc37d2f7d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194289668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.4194289668
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1639153654
Short name T657
Test name
Test status
Simulation time 2474215229 ps
CPU time 3.26 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:50 PM PDT 24
Peak memory 201244 kb
Host smart-1583d708-6977-444e-bdd9-70eae8fe39e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639153654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1639153654
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4086762373
Short name T755
Test name
Test status
Simulation time 2215133309 ps
CPU time 5.81 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:52 PM PDT 24
Peak memory 201240 kb
Host smart-8a0ce6f1-a5fa-4147-b770-e5212c165371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086762373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.4086762373
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.15134586
Short name T656
Test name
Test status
Simulation time 2510729736 ps
CPU time 7.2 seconds
Started Jun 22 04:51:41 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201300 kb
Host smart-f0cd7f4d-cdae-4c1d-b33e-35193408812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15134586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.15134586
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.1414348598
Short name T219
Test name
Test status
Simulation time 2133825923 ps
CPU time 1.99 seconds
Started Jun 22 04:51:37 PM PDT 24
Finished Jun 22 04:51:40 PM PDT 24
Peak memory 201148 kb
Host smart-905060b1-4961-4f33-a36b-1fc036731276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414348598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1414348598
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.4229109294
Short name T778
Test name
Test status
Simulation time 14252923631 ps
CPU time 40.41 seconds
Started Jun 22 04:51:38 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 201292 kb
Host smart-ec861a93-1b50-4763-b596-6943c3224a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229109294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.4229109294
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2919195682
Short name T120
Test name
Test status
Simulation time 83668169952 ps
CPU time 38.73 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:52:26 PM PDT 24
Peak memory 209828 kb
Host smart-ddb4a0a7-2129-4f2d-b1fa-d9eca0e5c342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919195682 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.2919195682
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1853148472
Short name T305
Test name
Test status
Simulation time 3310556011 ps
CPU time 3.48 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201224 kb
Host smart-bc1f0124-1efc-46aa-a88c-de9ab3a4d7ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853148472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.1853148472
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1976060306
Short name T137
Test name
Test status
Simulation time 57056321177 ps
CPU time 76.5 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:54:52 PM PDT 24
Peak memory 201596 kb
Host smart-97b35a06-72ad-42f8-8d9a-18d7983d31bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976060306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1976060306
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.33483131
Short name T595
Test name
Test status
Simulation time 24850630329 ps
CPU time 22.15 seconds
Started Jun 22 04:53:36 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 201592 kb
Host smart-dded4456-043b-4289-bd05-7536e62df538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33483131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_wit
h_pre_cond.33483131
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3858152381
Short name T359
Test name
Test status
Simulation time 113754209848 ps
CPU time 70.21 seconds
Started Jun 22 04:53:36 PM PDT 24
Finished Jun 22 04:54:47 PM PDT 24
Peak memory 201584 kb
Host smart-7aac7802-d294-426e-b7fb-5528299b95da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858152381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.3858152381
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3528281491
Short name T352
Test name
Test status
Simulation time 40275464573 ps
CPU time 28.4 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:54:04 PM PDT 24
Peak memory 201424 kb
Host smart-ec204067-5476-49e5-bed9-2012507ee011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528281491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.3528281491
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3321847073
Short name T695
Test name
Test status
Simulation time 68374720655 ps
CPU time 160.38 seconds
Started Jun 22 04:53:39 PM PDT 24
Finished Jun 22 04:56:20 PM PDT 24
Peak memory 201488 kb
Host smart-2972720e-0097-4bd8-82bd-603211b7c877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321847073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.3321847073
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3747868985
Short name T735
Test name
Test status
Simulation time 107945617386 ps
CPU time 142.47 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:55:57 PM PDT 24
Peak memory 201548 kb
Host smart-7aec590e-9d05-4aa9-bd68-38b3a30111ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747868985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.3747868985
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3243122273
Short name T373
Test name
Test status
Simulation time 46335651513 ps
CPU time 116.78 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:55:33 PM PDT 24
Peak memory 201616 kb
Host smart-27d87dac-f7d8-4c4a-94cc-9dec51cc6d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243122273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3243122273
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.4259953475
Short name T617
Test name
Test status
Simulation time 86958355018 ps
CPU time 201.98 seconds
Started Jun 22 04:53:32 PM PDT 24
Finished Jun 22 04:56:54 PM PDT 24
Peak memory 201408 kb
Host smart-95700d5c-ade0-4db6-89d5-9f0f936eeeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259953475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.4259953475
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.1475720594
Short name T423
Test name
Test status
Simulation time 2012637957 ps
CPU time 6.02 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:51:51 PM PDT 24
Peak memory 201144 kb
Host smart-1d1346c0-d3d7-4bd9-82fa-15c19c2fec31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475720594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.1475720594
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2046144156
Short name T771
Test name
Test status
Simulation time 3452703525 ps
CPU time 8.49 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201304 kb
Host smart-b5400611-cfb7-4f95-a189-7ebe977807e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046144156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.2046144156
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2011866910
Short name T575
Test name
Test status
Simulation time 23251631720 ps
CPU time 4.84 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:52 PM PDT 24
Peak memory 201732 kb
Host smart-1905af2a-16d3-47d7-b691-1df4aec7994c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011866910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.2011866910
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1565892259
Short name T407
Test name
Test status
Simulation time 4317856506 ps
CPU time 1.35 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201216 kb
Host smart-e492c689-2c37-437d-8428-e3dc6fabbc46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565892259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.1565892259
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.3714957772
Short name T187
Test name
Test status
Simulation time 4920062208 ps
CPU time 1.4 seconds
Started Jun 22 04:51:48 PM PDT 24
Finished Jun 22 04:51:50 PM PDT 24
Peak memory 201236 kb
Host smart-df4a5a84-b88f-46de-90e2-e7afd7de65e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714957772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.3714957772
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2482437243
Short name T513
Test name
Test status
Simulation time 2635759473 ps
CPU time 2.29 seconds
Started Jun 22 04:51:35 PM PDT 24
Finished Jun 22 04:51:38 PM PDT 24
Peak memory 201156 kb
Host smart-a6ca21a8-0b4c-4c80-bdd8-8d7926060f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482437243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.2482437243
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.758529859
Short name T60
Test name
Test status
Simulation time 2473637562 ps
CPU time 2.14 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:51:52 PM PDT 24
Peak memory 201128 kb
Host smart-15b48686-5786-4199-ac70-9210ceaf8570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758529859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.758529859
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3061665071
Short name T673
Test name
Test status
Simulation time 2173357941 ps
CPU time 2.02 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:51:56 PM PDT 24
Peak memory 201216 kb
Host smart-88a43a75-cf77-4dfe-91e1-83c588a1d8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061665071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3061665071
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1341090144
Short name T499
Test name
Test status
Simulation time 2510924730 ps
CPU time 6.94 seconds
Started Jun 22 04:51:38 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 201300 kb
Host smart-89b7235e-2bd3-449a-a5e9-1d0a69921494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341090144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.1341090144
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.1340842928
Short name T53
Test name
Test status
Simulation time 2120164982 ps
CPU time 3.2 seconds
Started Jun 22 04:51:41 PM PDT 24
Finished Jun 22 04:51:45 PM PDT 24
Peak memory 201060 kb
Host smart-48aa8926-68dd-42d1-8092-06f2a234bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340842928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.1340842928
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1812480367
Short name T256
Test name
Test status
Simulation time 14167044747 ps
CPU time 37.77 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:45 PM PDT 24
Peak memory 201564 kb
Host smart-7a8f99eb-2998-4ee2-817f-353613cb054c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812480367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1812480367
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1035531233
Short name T200
Test name
Test status
Simulation time 72146833439 ps
CPU time 43.84 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:52:28 PM PDT 24
Peak memory 211412 kb
Host smart-a30c673b-21e5-4716-af22-6a5e425309c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035531233 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1035531233
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2615129022
Short name T743
Test name
Test status
Simulation time 127667219911 ps
CPU time 159.59 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:56:22 PM PDT 24
Peak memory 201492 kb
Host smart-5fc49a95-c0c5-4c0c-8cee-bca599807f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615129022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.2615129022
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1484234674
Short name T619
Test name
Test status
Simulation time 26829835828 ps
CPU time 70.71 seconds
Started Jun 22 04:53:38 PM PDT 24
Finished Jun 22 04:54:50 PM PDT 24
Peak memory 201564 kb
Host smart-0fade903-b321-469b-a359-3b9f7bcfe2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484234674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1484234674
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.751609901
Short name T583
Test name
Test status
Simulation time 78283252769 ps
CPU time 54.17 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 201572 kb
Host smart-e137ddab-638e-4324-a7bb-0dfd882b4430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751609901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_wi
th_pre_cond.751609901
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.489429581
Short name T370
Test name
Test status
Simulation time 43279453154 ps
CPU time 28.08 seconds
Started Jun 22 04:53:41 PM PDT 24
Finished Jun 22 04:54:09 PM PDT 24
Peak memory 201548 kb
Host smart-9fc56057-2765-4176-a9bd-fedd68cddd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489429581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_wi
th_pre_cond.489429581
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2558919236
Short name T95
Test name
Test status
Simulation time 33354377204 ps
CPU time 21.88 seconds
Started Jun 22 04:53:33 PM PDT 24
Finished Jun 22 04:53:56 PM PDT 24
Peak memory 201576 kb
Host smart-b39bce5c-51e0-48a3-8b48-88bd663a1bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558919236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.2558919236
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3583833848
Short name T796
Test name
Test status
Simulation time 26832129412 ps
CPU time 63.6 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 201464 kb
Host smart-95798b5b-9b36-4b92-be98-76370e13b717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583833848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.3583833848
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.4220830525
Short name T543
Test name
Test status
Simulation time 56378949064 ps
CPU time 141.75 seconds
Started Jun 22 04:53:35 PM PDT 24
Finished Jun 22 04:55:58 PM PDT 24
Peak memory 201444 kb
Host smart-2a68b4ab-807c-4861-8f56-c6c413cd2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220830525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.4220830525
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3595459756
Short name T568
Test name
Test status
Simulation time 68056796393 ps
CPU time 170.05 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:56:37 PM PDT 24
Peak memory 201440 kb
Host smart-2231db0d-eae1-4f00-a6c3-7d755688787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595459756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.3595459756
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.4052565449
Short name T754
Test name
Test status
Simulation time 35701867034 ps
CPU time 23.29 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:54:11 PM PDT 24
Peak memory 201576 kb
Host smart-275ea643-0932-419e-9063-c4cc81eb28fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052565449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.4052565449
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.3728281031
Short name T190
Test name
Test status
Simulation time 2021090549 ps
CPU time 3.21 seconds
Started Jun 22 04:51:51 PM PDT 24
Finished Jun 22 04:51:58 PM PDT 24
Peak memory 201224 kb
Host smart-8626694c-0dcc-417b-a051-e559caa9dce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728281031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.3728281031
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.165219509
Short name T410
Test name
Test status
Simulation time 3347707436 ps
CPU time 2.47 seconds
Started Jun 22 04:51:43 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 201348 kb
Host smart-6736784b-216e-4074-bd0d-b247b51ccf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165219509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.165219509
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.66047383
Short name T776
Test name
Test status
Simulation time 127998914195 ps
CPU time 343.54 seconds
Started Jun 22 04:51:47 PM PDT 24
Finished Jun 22 04:57:31 PM PDT 24
Peak memory 201508 kb
Host smart-5bc37738-527e-48a5-971c-20f756d5b2d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66047383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl
_combo_detect.66047383
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1859884700
Short name T93
Test name
Test status
Simulation time 26601242332 ps
CPU time 22.9 seconds
Started Jun 22 04:51:53 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 201544 kb
Host smart-a30aef77-57e3-4c11-9b6a-32905d49005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859884700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.1859884700
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.4086772546
Short name T624
Test name
Test status
Simulation time 2596163849 ps
CPU time 1.89 seconds
Started Jun 22 04:51:44 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 201124 kb
Host smart-e6107b5f-d1cc-4e2d-9663-f5ca85ff53bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086772546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.4086772546
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2780622524
Short name T399
Test name
Test status
Simulation time 2633576223 ps
CPU time 2.51 seconds
Started Jun 22 04:51:47 PM PDT 24
Finished Jun 22 04:51:50 PM PDT 24
Peak memory 201168 kb
Host smart-84b9f639-b99f-4fa0-8a6e-d750153e13a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780622524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2780622524
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3919898241
Short name T663
Test name
Test status
Simulation time 2434940168 ps
CPU time 7.64 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:55 PM PDT 24
Peak memory 201256 kb
Host smart-4006ddd0-397b-499b-a2f9-212de7e6840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919898241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3919898241
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2399845835
Short name T445
Test name
Test status
Simulation time 2105523565 ps
CPU time 2.11 seconds
Started Jun 22 04:51:55 PM PDT 24
Finished Jun 22 04:51:58 PM PDT 24
Peak memory 201352 kb
Host smart-428828a4-f0ac-47b2-929f-d6b7cc8ad852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399845835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.2399845835
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2126186407
Short name T699
Test name
Test status
Simulation time 2520687605 ps
CPU time 3.68 seconds
Started Jun 22 04:51:47 PM PDT 24
Finished Jun 22 04:51:51 PM PDT 24
Peak memory 201296 kb
Host smart-65c8fbcd-6ed5-491a-983c-f7ead1938728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126186407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2126186407
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.1602381592
Short name T427
Test name
Test status
Simulation time 2117760230 ps
CPU time 3.22 seconds
Started Jun 22 04:51:58 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 201152 kb
Host smart-56bb2d17-1f9c-4f0f-b5a2-f1f52915ccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602381592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1602381592
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.2078982511
Short name T181
Test name
Test status
Simulation time 7039884237 ps
CPU time 17.92 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:52:09 PM PDT 24
Peak memory 201228 kb
Host smart-4bbbaac6-ae04-4270-9b50-0f1aac28c9db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078982511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.2078982511
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.489740464
Short name T609
Test name
Test status
Simulation time 263398849030 ps
CPU time 34.58 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:52:22 PM PDT 24
Peak memory 209812 kb
Host smart-352e7b27-430d-40ba-a057-8c5956615f1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489740464 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.489740464
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.547954891
Short name T594
Test name
Test status
Simulation time 9236462362 ps
CPU time 4.52 seconds
Started Jun 22 04:52:00 PM PDT 24
Finished Jun 22 04:52:06 PM PDT 24
Peak memory 201204 kb
Host smart-2604de5b-04e7-4caf-98f4-6fa11f5071a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547954891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ultra_low_pwr.547954891
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2641506128
Short name T229
Test name
Test status
Simulation time 35217786040 ps
CPU time 94.43 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:55:21 PM PDT 24
Peak memory 201612 kb
Host smart-587e6602-c32c-46f0-8af6-cf36b3cb6948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641506128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2641506128
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3924369414
Short name T263
Test name
Test status
Simulation time 40604115746 ps
CPU time 12.24 seconds
Started Jun 22 04:53:42 PM PDT 24
Finished Jun 22 04:53:55 PM PDT 24
Peak memory 201568 kb
Host smart-6a8613cd-24c1-4c75-9a1c-66edc4c0bb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924369414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.3924369414
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3198230420
Short name T692
Test name
Test status
Simulation time 39571628345 ps
CPU time 27.57 seconds
Started Jun 22 04:53:45 PM PDT 24
Finished Jun 22 04:54:13 PM PDT 24
Peak memory 201520 kb
Host smart-5386762a-ba2a-4a14-938e-64615432703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198230420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.3198230420
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3679361859
Short name T75
Test name
Test status
Simulation time 78679053386 ps
CPU time 25.68 seconds
Started Jun 22 04:53:45 PM PDT 24
Finished Jun 22 04:54:11 PM PDT 24
Peak memory 201592 kb
Host smart-e55f3220-675f-49f8-ae8a-9112d2e7896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679361859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.3679361859
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3480174756
Short name T536
Test name
Test status
Simulation time 80183976586 ps
CPU time 188.79 seconds
Started Jun 22 04:53:40 PM PDT 24
Finished Jun 22 04:56:49 PM PDT 24
Peak memory 201488 kb
Host smart-ab7515f2-3dd9-463a-abbf-91755a17fe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480174756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.3480174756
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2397951384
Short name T696
Test name
Test status
Simulation time 21336558968 ps
CPU time 28.35 seconds
Started Jun 22 04:53:43 PM PDT 24
Finished Jun 22 04:54:12 PM PDT 24
Peak memory 201572 kb
Host smart-920b7d92-be34-452e-883d-00d46e7fcc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397951384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.2397951384
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2721679904
Short name T260
Test name
Test status
Simulation time 82732937233 ps
CPU time 104.42 seconds
Started Jun 22 04:53:51 PM PDT 24
Finished Jun 22 04:55:36 PM PDT 24
Peak memory 201604 kb
Host smart-e58cddd8-2edf-4cea-9f23-f6b920bd7be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721679904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.2721679904
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.3225184590
Short name T194
Test name
Test status
Simulation time 2020354491 ps
CPU time 1.93 seconds
Started Jun 22 04:51:54 PM PDT 24
Finished Jun 22 04:51:57 PM PDT 24
Peak memory 201252 kb
Host smart-168dfda3-5c94-43d5-a2cf-a70ca67e7211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225184590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.3225184590
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.650541180
Short name T529
Test name
Test status
Simulation time 3999667714 ps
CPU time 10.88 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:57 PM PDT 24
Peak memory 201212 kb
Host smart-36a03f72-96f5-488a-a4ac-81b5c348f98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650541180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.650541180
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1022448993
Short name T49
Test name
Test status
Simulation time 27359876304 ps
CPU time 18.3 seconds
Started Jun 22 04:51:47 PM PDT 24
Finished Jun 22 04:52:06 PM PDT 24
Peak memory 201608 kb
Host smart-37c9dc94-86f8-415e-9747-f05c1b71e5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022448993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.1022448993
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3559843565
Short name T616
Test name
Test status
Simulation time 3066936689 ps
CPU time 8.18 seconds
Started Jun 22 04:51:42 PM PDT 24
Finished Jun 22 04:51:51 PM PDT 24
Peak memory 201228 kb
Host smart-49963651-f96b-479f-b1a2-37e5bbc43920
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559843565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.3559843565
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.1824350812
Short name T141
Test name
Test status
Simulation time 3693607779 ps
CPU time 8.53 seconds
Started Jun 22 04:51:57 PM PDT 24
Finished Jun 22 04:52:06 PM PDT 24
Peak memory 201204 kb
Host smart-b5fae47a-4935-40bd-b859-0178d565b29f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824350812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.1824350812
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1124329796
Short name T21
Test name
Test status
Simulation time 2609911959 ps
CPU time 6.75 seconds
Started Jun 22 04:52:09 PM PDT 24
Finished Jun 22 04:52:18 PM PDT 24
Peak memory 201240 kb
Host smart-bb5a3f12-677a-44d3-8567-e374d4202753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124329796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1124329796
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1474949330
Short name T689
Test name
Test status
Simulation time 2516675442 ps
CPU time 1.7 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201236 kb
Host smart-7f18289a-1dde-4a51-ae7a-12587980217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474949330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1474949330
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1786437064
Short name T570
Test name
Test status
Simulation time 2201542359 ps
CPU time 3.42 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201100 kb
Host smart-532dc6c1-19b0-4df1-81ba-eed47c344fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786437064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1786437064
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2279141645
Short name T612
Test name
Test status
Simulation time 2514294188 ps
CPU time 3.86 seconds
Started Jun 22 04:51:52 PM PDT 24
Finished Jun 22 04:51:57 PM PDT 24
Peak memory 201268 kb
Host smart-c5d1eed6-70a0-40ef-9b8b-0c0e6be68211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279141645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2279141645
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.1632815856
Short name T560
Test name
Test status
Simulation time 2133633352 ps
CPU time 1.97 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201132 kb
Host smart-a33abfed-1953-4378-a905-27d4f63c7e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632815856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1632815856
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.4227973592
Short name T132
Test name
Test status
Simulation time 15479600321 ps
CPU time 34.73 seconds
Started Jun 22 04:51:50 PM PDT 24
Finished Jun 22 04:52:26 PM PDT 24
Peak memory 201076 kb
Host smart-685e2baa-2888-4f30-ae2b-0f6fdd407587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227973592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.4227973592
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3633521014
Short name T766
Test name
Test status
Simulation time 42574192284 ps
CPU time 51.52 seconds
Started Jun 22 04:52:04 PM PDT 24
Finished Jun 22 04:52:56 PM PDT 24
Peak memory 218040 kb
Host smart-b4b88e45-9066-494e-9619-f07249910c71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633521014 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.3633521014
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2694355981
Short name T115
Test name
Test status
Simulation time 5534450877 ps
CPU time 7.2 seconds
Started Jun 22 04:51:54 PM PDT 24
Finished Jun 22 04:52:02 PM PDT 24
Peak memory 201264 kb
Host smart-749e7e54-ef61-4d6b-9681-1083d4c5cfea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694355981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.2694355981
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3545979720
Short name T358
Test name
Test status
Simulation time 127528949285 ps
CPU time 218.56 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:57:26 PM PDT 24
Peak memory 201604 kb
Host smart-6775b0bd-1169-4912-9859-45e0324d5281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545979720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.3545979720
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3734729130
Short name T91
Test name
Test status
Simulation time 30586046114 ps
CPU time 40.64 seconds
Started Jun 22 04:53:42 PM PDT 24
Finished Jun 22 04:54:24 PM PDT 24
Peak memory 201572 kb
Host smart-72e4b69b-2b2e-499f-a1e4-6ff3e0af9393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734729130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.3734729130
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3860725021
Short name T12
Test name
Test status
Simulation time 35702436962 ps
CPU time 94.89 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:55:25 PM PDT 24
Peak memory 201548 kb
Host smart-6e0eab43-9064-4f1c-a44b-6063ee8231d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860725021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.3860725021
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1683666623
Short name T481
Test name
Test status
Simulation time 47923577940 ps
CPU time 120.3 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:55:51 PM PDT 24
Peak memory 201504 kb
Host smart-74aed1f9-c8c5-4047-b8d1-62a38a953947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683666623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.1683666623
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.253940926
Short name T497
Test name
Test status
Simulation time 72357358795 ps
CPU time 48.42 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:54:36 PM PDT 24
Peak memory 201532 kb
Host smart-d5762e92-59c1-4dfb-925e-474a12dd2cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253940926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wi
th_pre_cond.253940926
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3123885012
Short name T551
Test name
Test status
Simulation time 36147163784 ps
CPU time 25.27 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:54:11 PM PDT 24
Peak memory 201592 kb
Host smart-9ac4bbcc-9f54-430f-ab2e-74a776ad920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123885012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.3123885012
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3614758768
Short name T439
Test name
Test status
Simulation time 36503887519 ps
CPU time 90.68 seconds
Started Jun 22 04:53:50 PM PDT 24
Finished Jun 22 04:55:22 PM PDT 24
Peak memory 201392 kb
Host smart-ff4b21f3-1aec-4c45-96f2-02ee79191e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614758768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.3614758768
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.559565699
Short name T154
Test name
Test status
Simulation time 27082836289 ps
CPU time 65.86 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:54:57 PM PDT 24
Peak memory 201420 kb
Host smart-0817d870-3b1e-4e94-9844-7c3cfb98cad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559565699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_wi
th_pre_cond.559565699
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.760400497
Short name T183
Test name
Test status
Simulation time 2032814469 ps
CPU time 1.8 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:09 PM PDT 24
Peak memory 201248 kb
Host smart-ea485359-61df-43a4-bfa8-df86ae709710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760400497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test
.760400497
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1447920813
Short name T508
Test name
Test status
Simulation time 3706831050 ps
CPU time 5.36 seconds
Started Jun 22 04:51:43 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201344 kb
Host smart-0fd0ef49-df7c-4cdc-8462-1d49cd63bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447920813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.1447920813
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.1469691959
Short name T794
Test name
Test status
Simulation time 142825339302 ps
CPU time 185.83 seconds
Started Jun 22 04:51:47 PM PDT 24
Finished Jun 22 04:54:54 PM PDT 24
Peak memory 201396 kb
Host smart-c5b151ff-9136-4c32-a11b-fbbe6e5c0361
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469691959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.1469691959
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1819532605
Short name T66
Test name
Test status
Simulation time 27330641145 ps
CPU time 70.36 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:52:58 PM PDT 24
Peak memory 201604 kb
Host smart-5daf10ec-fe20-4f7d-836b-b855f6a0a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819532605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.1819532605
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1233196729
Short name T134
Test name
Test status
Simulation time 3618346467 ps
CPU time 3.2 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:51 PM PDT 24
Peak memory 201208 kb
Host smart-0f1dd41d-27bd-4f67-bf99-6e77179e1832
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233196729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.1233196729
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3137066297
Short name T197
Test name
Test status
Simulation time 4100182773 ps
CPU time 4.69 seconds
Started Jun 22 04:51:54 PM PDT 24
Finished Jun 22 04:52:00 PM PDT 24
Peak memory 201156 kb
Host smart-6a5f8128-f66b-4749-86f6-65cae24af36a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137066297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3137066297
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.983720358
Short name T631
Test name
Test status
Simulation time 2614042995 ps
CPU time 7.38 seconds
Started Jun 22 04:51:45 PM PDT 24
Finished Jun 22 04:51:54 PM PDT 24
Peak memory 201232 kb
Host smart-fe5920f2-62a4-4cc5-80bb-dfdf97218e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983720358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.983720358
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1748175066
Short name T392
Test name
Test status
Simulation time 2473156297 ps
CPU time 7.31 seconds
Started Jun 22 04:52:06 PM PDT 24
Finished Jun 22 04:52:14 PM PDT 24
Peak memory 201256 kb
Host smart-6723214f-a227-43fa-8d86-233a755b869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748175066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1748175066
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2755008454
Short name T732
Test name
Test status
Simulation time 2062801576 ps
CPU time 1.9 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:49 PM PDT 24
Peak memory 201196 kb
Host smart-b9add71d-b58e-4b4e-a589-349cf5ab3d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755008454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.2755008454
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3577610701
Short name T274
Test name
Test status
Simulation time 2512094306 ps
CPU time 6.94 seconds
Started Jun 22 04:53:53 PM PDT 24
Finished Jun 22 04:54:00 PM PDT 24
Peak memory 201188 kb
Host smart-26cecda7-9bad-4c69-9f8f-e1ea67e5c30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577610701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3577610701
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.1245816614
Short name T276
Test name
Test status
Simulation time 2112411663 ps
CPU time 5.72 seconds
Started Jun 22 04:52:02 PM PDT 24
Finished Jun 22 04:52:09 PM PDT 24
Peak memory 201100 kb
Host smart-99b99674-7d21-4747-915c-10a5dec778d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245816614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.1245816614
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.804688453
Short name T593
Test name
Test status
Simulation time 162383391613 ps
CPU time 62.03 seconds
Started Jun 22 04:52:08 PM PDT 24
Finished Jun 22 04:53:12 PM PDT 24
Peak memory 201572 kb
Host smart-ce77f768-27f1-4b61-80a5-e5b20e66d850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804688453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_str
ess_all.804688453
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3341057613
Short name T769
Test name
Test status
Simulation time 34725173414 ps
CPU time 84.51 seconds
Started Jun 22 04:51:52 PM PDT 24
Finished Jun 22 04:53:17 PM PDT 24
Peak memory 209764 kb
Host smart-e2a7a397-d477-474e-8560-f0f5ea3af9ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341057613 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3341057613
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3769540226
Short name T230
Test name
Test status
Simulation time 8390122360 ps
CPU time 2.61 seconds
Started Jun 22 04:51:46 PM PDT 24
Finished Jun 22 04:51:50 PM PDT 24
Peak memory 201204 kb
Host smart-6b2bc295-ac63-42e3-8ddb-f4463ca1daec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769540226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.3769540226
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.627157659
Short name T349
Test name
Test status
Simulation time 98522240302 ps
CPU time 68.81 seconds
Started Jun 22 04:53:50 PM PDT 24
Finished Jun 22 04:55:00 PM PDT 24
Peak memory 201508 kb
Host smart-70c90dce-e2c4-40d5-9dc3-6b3dffdf918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627157659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_wi
th_pre_cond.627157659
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1807627558
Short name T259
Test name
Test status
Simulation time 216336042701 ps
CPU time 270.36 seconds
Started Jun 22 04:53:51 PM PDT 24
Finished Jun 22 04:58:22 PM PDT 24
Peak memory 201400 kb
Host smart-eec185a4-fe92-4481-b472-cce12cf4e247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807627558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.1807627558
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2237493889
Short name T659
Test name
Test status
Simulation time 101295579274 ps
CPU time 243.15 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:57:54 PM PDT 24
Peak memory 201524 kb
Host smart-f7a6bf25-9093-41f7-90bc-f04ccfa67d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237493889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.2237493889
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2361437852
Short name T241
Test name
Test status
Simulation time 38101328653 ps
CPU time 25.11 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 04:54:11 PM PDT 24
Peak memory 201596 kb
Host smart-6ea99117-d890-424f-a494-7b0d74d04772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361437852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.2361437852
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3607175367
Short name T517
Test name
Test status
Simulation time 26079437551 ps
CPU time 69.76 seconds
Started Jun 22 04:53:49 PM PDT 24
Finished Jun 22 04:55:00 PM PDT 24
Peak memory 201564 kb
Host smart-cf34333f-34cd-453d-b50b-7650ee61b5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607175367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3607175367
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2997473522
Short name T360
Test name
Test status
Simulation time 76671888809 ps
CPU time 89.63 seconds
Started Jun 22 04:53:47 PM PDT 24
Finished Jun 22 04:55:18 PM PDT 24
Peak memory 201412 kb
Host smart-ffd73e45-3494-477f-aef7-41f255c92985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997473522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.2997473522
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3577455339
Short name T103
Test name
Test status
Simulation time 60378343424 ps
CPU time 13.23 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:54:03 PM PDT 24
Peak memory 201604 kb
Host smart-e1b47654-f3de-439e-b717-f5376207f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577455339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.3577455339
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1190152921
Short name T354
Test name
Test status
Simulation time 192306048711 ps
CPU time 467.69 seconds
Started Jun 22 04:53:46 PM PDT 24
Finished Jun 22 05:01:35 PM PDT 24
Peak memory 201484 kb
Host smart-81679a93-0da9-417f-8fc3-82d169d9a391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190152921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.1190152921
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2734025967
Short name T498
Test name
Test status
Simulation time 54403258118 ps
CPU time 37.02 seconds
Started Jun 22 04:53:48 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 201592 kb
Host smart-ce317e27-c565-449d-924a-649748324762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734025967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.2734025967
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest
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