Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1358

1

T4

11

T2

10

T6

6

auto[1]

1919

1

T4

9

T2

12

T6

13

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2721

1

T4

20

T2

20

T6

17

auto[1]

556

1

T2

2

T6

2

T10

1

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3076

1

T4

20

T2

22

T6

19

auto[1]

201

1

T10

2

T34

2

T35

5

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3093

1

T4

20

T2

22

T6

18

auto[1]

184

1

T6

1

T9

1

T12

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3152

1

T4

20

T2

20

T6

18

auto[1]

125

1

T2

2

T6

1

T36

4

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2089

1

T4

20

T2

22

T6

9

auto[1]

1188

1

T6

10

T9

9

T10

10

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1321

1

T4

13

T2

8

T6

11

auto[1]

1956

1

T4

7

T2

14

T6

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1322

1

T4

10

T2

11

T6

5

auto[1]

1955

1

T4

10

T2

11

T6

14

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1396

1

T4

9

T2

12

T6

12

auto[1]

1881

1

T4

11

T2

10

T6

7

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1271

1

T4

9

T2

11

T6

9

auto[1]

2006

1

T4

11

T2

11

T6

10

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

64

1

T2

1

T34

1

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T33

1

T51

1

T116

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T2

1

T6

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T32

1

T35

1

T101

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T4

2

T2

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T51

2

T115

1

T354

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T4

2

T2

1

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T32

1

T33

1

T116

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T4

2

T72

1

T73

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T51

1

T72

1

T354

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T2

1

T33

1

T72

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T72

2

T101

1

T102

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T2

1

T12

2

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T51

1

T116

1

T252

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

39

1

T34

1

T115

3

T260

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

29

1

T33

1

T51

1

T115

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T4

2

T2

1

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T10

1

T33

1

T191

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T34

1

T51

1

T73

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T33

1

T101

3

T355

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T6

1

T36

3

T72

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T10

1

T36

4

T33

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

38

1

T4

1

T6

2

T65

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T6

6

T33

2

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

33

1

T12

1

T94

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T10

1

T102

3

T278

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

56

1

T4

1

T2

1

T94

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T35

1

T116

1

T254

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T4

1

T12

9

T34

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

33

1

T32

1

T33

1

T252

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

56

1

T4

2

T34

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

49

1

T10

1

T33

1

T35

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T4

1

T2

1

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T10

1

T354

1

T102

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T2

1

T35

1

T72

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T101

1

T356

1

T258

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

31

1

T34

1

T71

1

T241

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

25

1

T35

1

T51

2

T116

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57

1

T2

2

T199

1

T97

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T33

1

T101

1

T102

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

34

1

T4

1

T6

1

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T10

1

T33

1

T354

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T4

1

T6

1

T34

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T72

1

T116

2

T163

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T4

1

T34

1

T71

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

33

1

T71

4

T72

1

T101

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

88

1

T2

1

T65

1

T260

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

38

1

T10

1

T35

1

T116

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T2

2

T34

1

T261

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T51

1

T116

1

T354

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T4

1

T71

1

T73

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T33

1

T35

1

T51

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T34

1

T45

1

T71

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T33

1

T35

1

T115

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

70

1

T2

1

T9

1

T251

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

84

1

T9

9

T10

2

T45

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T2

1

T72

2

T94

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T6

1

T35

2

T357

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

83

1

T6

1

T10

1

T44

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T6

1

T44

9

T278

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T4

1

T36

1

T71

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

92

1

T36

1

T33

1

T35

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

317

1

T4

1

T2

3

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T51

1

T102

1

T220

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T116

1

T358

1

T359

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T360

1

T361

1

T355

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T35

1

T115

1

T116

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T51

1

T115

2

T360

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T72

2

T254

1

T191

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T116

1

T360

1

T355

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T35

1

T356

1

T220

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T51

1

T360

1

T220

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T35

1

T51

1

T354

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T354

1

T278

1

T358

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T36

3

T35

1

T191

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T35

1

T360

2

T354

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T33

1

T362

1

T363

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T116

1

T364

1

T254

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T100

1

T278

1

T361

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T278

1

T191

1

T365

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T35

1

T358

1

T359

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T360

1

T220

1

T359

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T360

1

T361

1

T366

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T32

1

T51

1

T120

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T360

1

T354

2

T102

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T354

1

T355

1

T259

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T33

1

T51

1

T71

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T116

1

T367

1

T259

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T35

1

T186

3

T191

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T35

1

T51

1

T354

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T115

2

T116

1

T191

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T51

1

T115

2

T360

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T6

2

T116

1

T100

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T116

1

T360

1

T100

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T10

1

T33

1

T250

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

117

1

T32

1

T33

2

T35

2

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

74

1

T2

1

T34

1

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T33

1

T51

1

T116

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T2

1

T6

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T32

1

T35

1

T360

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T4

2

T2

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T35

1

T51

2

T115

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T4

2

T2

1

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T32

1

T33

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T4

2

T34

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T51

1

T72

3

T254

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T2

1

T33

1

T72

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T72

2

T116

1

T360

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T2

1

T12

2

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T35

1

T51

1

T116

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

45

1

T34

1

T115

3

T260

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T33

1

T51

2

T115

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T4

2

T2

1

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T10

1

T33

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T34

1

T51

1

T73

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T33

1

T354

1

T101

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T6

1

T36

3

T72

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T10

1

T36

7

T33

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T4

1

T6

2

T65

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T6

6

T33

2

T35

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T12

1

T94

1

T261

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T10

1

T33

1

T102

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T4

1

T2

1

T94

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

34

1

T35

1

T116

2

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T4

1

T12

9

T34

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T32

1

T33

1

T252

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T4

2

T34

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

58

1

T10

1

T33

1

T35

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T4

1

T2

1

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T10

1

T35

1

T354

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T2

1

T35

1

T72

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T360

1

T101

1

T356

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T34

1

T71

1

T241

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T35

1

T51

2

T116

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T2

2

T199

2

T97

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T32

1

T33

1

T51

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T4

1

T6

1

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T10

1

T33

1

T360

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T4

1

T6

1

T34

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T72

1

T116

2

T354

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T4

1

T34

1

T71

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

42

1

T33

1

T51

1

T71

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

93

1

T2

1

T65

1

T260

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

42

1

T10

1

T35

1

T116

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

67

1

T2

2

T34

1

T261

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T35

1

T51

1

T116

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T4

1

T71

1

T73

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

38

1

T33

1

T35

2

T51

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T34

1

T45

1

T71

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T33

1

T35

1

T115

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

77

1

T2

1

T9

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

95

1

T9

9

T10

2

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T2

2

T72

2

T94

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T6

3

T35

2

T116

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

87

1

T6

1

T10

1

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T6

1

T44

9

T116

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T4

1

T2

1

T36

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

110

1

T10

1

T36

1

T33

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

185

1

T4

1

T2

3

T34

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

115

1

T32

1

T33

2

T35

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T368

4

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T369

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T35

1

T51

1

T361

4

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	27	69	71.88	27
Automatically Generated Cross Bins	96	27	69	71.88	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

74

1

T2

1

T34

1

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T33

1

T51

1

T116

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T2

1

T6

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T32

1

T35

1

T360

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T4

2

T2

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T35

1

T51

2

T115

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T4

2

T2

1

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T32

1

T33

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T4

2

T34

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T51

1

T72

1

T354

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T2

1

T33

1

T115

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T72

2

T116

1

T360

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T2

1

T12

2

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T35

1

T51

1

T116

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44

1

T34

1

T115

1

T260

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T33

1

T51

2

T115

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T4

2

T2

1

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T10

1

T33

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T34

1

T51

1

T73

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T33

1

T354

1

T101

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T6

1

T36

3

T72

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T10

1

T36

7

T33

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T4

1

T6

2

T65

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T6

6

T33

2

T35

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T12

1

T94

1

T261

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T10

1

T33

1

T102

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T4

1

T2

1

T94

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T35

1

T116

2

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T4

1

T12

7

T34

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T32

1

T33

1

T252

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T4

2

T34

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

58

1

T10

1

T33

1

T35

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T4

1

T2

1

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T10

1

T35

1

T354

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T2

1

T35

1

T72

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T360

1

T101

1

T356

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T34

1

T71

1

T241

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T35

1

T51

2

T116

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

58

1

T2

2

T199

2

T97

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T32

1

T33

1

T51

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

33

1

T4

1

T6

1

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T10

1

T33

1

T360

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T4

1

T6

1

T34

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T72

1

T116

2

T354

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T4

1

T34

1

T72

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T33

1

T51

1

T71

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

90

1

T2

1

T65

1

T260

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

42

1

T10

1

T35

1

T116

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

67

1

T2

2

T34

1

T261

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T35

1

T51

1

T116

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T4

1

T71

1

T73

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

38

1

T33

1

T35

2

T51

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T34

1

T45

1

T71

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T33

1

T35

1

T115

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

78

1

T2

1

T34

1

T261

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

95

1

T9

9

T10

2

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T2

2

T72

2

T94

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T6

3

T35

2

T116

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

85

1

T10

1

T34

1

T44

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T6

1

T44

9

T116

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T4

1

T2

1

T36

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

110

1

T10

1

T36

1

T33

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

213

1

T4

1

T2

3

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

112

1

T32

1

T33

2

T35

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T115

2

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T72

2

T254

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T71

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T370

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T35

1

T354

5

T358

1

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

74

1

T2

1

T34

1

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T33

1

T51

1

T116

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T2

1

T6

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T32

1

T35

1

T360

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T4

2

T2

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T35

1

T51

2

T115

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T4

2

T2

1

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T32

1

T33

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T4

2

T34

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T51

1

T72

3

T254

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T2

1

T33

1

T72

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T72

2

T116

1

T360

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T2

1

T12

2

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T35

1

T51

1

T116

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

46

1

T34

1

T115

3

T260

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T33

1

T51

2

T115

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T4

2

T2

1

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T10

1

T33

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T34

1

T51

1

T73

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T33

1

T354

1

T101

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T6

1

T72

1

T115

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T10

1

T36

7

T33

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T4

1

T6

1

T65

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T6

6

T33

2

T35

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T12

1

T94

1

T261

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T10

1

T33

1

T102

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T4

1

T2

1

T94

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T35

1

T116

2

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T4

1

T12

9

T34

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T32

1

T33

1

T252

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

64

1

T4

2

T34

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

58

1

T10

1

T33

1

T35

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T4

1

T2

1

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T10

1

T35

1

T354

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T2

1

T35

1

T72

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T360

1

T101

1

T356

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T34

1

T71

1

T241

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T35

1

T51

2

T116

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

64

1

T2

2

T199

2

T97

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T32

1

T33

1

T51

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T4

1

T6

1

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T10

1

T33

1

T360

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T4

1

T6

1

T34

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T72

1

T116

2

T354

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T4

1

T34

1

T71

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

42

1

T33

1

T51

1

T71

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

91

1

T2

1

T65

1

T260

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

42

1

T10

1

T35

1

T116

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

67

1

T2

2

T34

1

T261

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T35

1

T51

1

T116

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T4

1

T71

1

T73

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

38

1

T33

1

T35

2

T51

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T34

1

T45

1

T71

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T33

1

T35

1

T115

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

81

1

T2

1

T9

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

95

1

T9

9

T10

2

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T2

2

T72

2

T94

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T6

3

T35

2

T116

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

88

1

T6

1

T10

1

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T6

1

T44

9

T116

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T4

1

T2

1

T71

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

107

1

T10

1

T36

1

T33

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

241

1

T4

1

T2

1

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

118

1

T32

1

T33

1

T35

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T371

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T250

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T33

1

T360

1

T134

3

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded