Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T10 |
8 |
|
T24 |
14 |
|
T25 |
10 |
| auto[1] |
918 |
1 |
|
|
T10 |
12 |
|
T24 |
6 |
|
T25 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
924 |
1 |
|
|
T10 |
10 |
|
T24 |
7 |
|
T25 |
10 |
| auto[1] |
896 |
1 |
|
|
T10 |
10 |
|
T24 |
13 |
|
T25 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
884 |
1 |
|
|
T10 |
9 |
|
T24 |
12 |
|
T25 |
12 |
| auto[1] |
936 |
1 |
|
|
T10 |
11 |
|
T24 |
8 |
|
T25 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
925 |
1 |
|
|
T10 |
7 |
|
T24 |
9 |
|
T25 |
7 |
| auto[1] |
895 |
1 |
|
|
T10 |
13 |
|
T24 |
11 |
|
T25 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
910 |
1 |
|
|
T10 |
13 |
|
T24 |
9 |
|
T25 |
12 |
| auto[1] |
910 |
1 |
|
|
T10 |
7 |
|
T24 |
11 |
|
T25 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
941 |
1 |
|
|
T10 |
10 |
|
T24 |
11 |
|
T25 |
8 |
| auto[1] |
879 |
1 |
|
|
T10 |
10 |
|
T24 |
9 |
|
T25 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
935 |
1 |
|
|
T10 |
11 |
|
T24 |
11 |
|
T25 |
10 |
| auto[1] |
885 |
1 |
|
|
T10 |
9 |
|
T24 |
9 |
|
T25 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
889 |
1 |
|
|
T10 |
10 |
|
T24 |
8 |
|
T25 |
8 |
| auto[1] |
931 |
1 |
|
|
T10 |
10 |
|
T24 |
12 |
|
T25 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T10 |
10 |
|
T24 |
11 |
|
T25 |
10 |
| auto[1] |
906 |
1 |
|
|
T10 |
10 |
|
T24 |
9 |
|
T25 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
915 |
1 |
|
|
T10 |
9 |
|
T24 |
10 |
|
T25 |
13 |
| auto[1] |
905 |
1 |
|
|
T10 |
11 |
|
T24 |
10 |
|
T25 |
7 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
932 |
1 |
|
|
T10 |
12 |
|
T24 |
12 |
|
T25 |
11 |
| auto[1] |
888 |
1 |
|
|
T10 |
8 |
|
T24 |
8 |
|
T25 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T10 |
10 |
|
T24 |
10 |
|
T25 |
10 |
| auto[1] |
914 |
1 |
|
|
T10 |
10 |
|
T24 |
10 |
|
T25 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
930 |
1 |
|
|
T10 |
10 |
|
T24 |
7 |
|
T25 |
11 |
| auto[1] |
890 |
1 |
|
|
T10 |
10 |
|
T24 |
13 |
|
T25 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
924 |
1 |
|
|
T10 |
10 |
|
T24 |
7 |
|
T25 |
10 |
| auto[1] |
896 |
1 |
|
|
T10 |
10 |
|
T24 |
13 |
|
T25 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
934 |
1 |
|
|
T10 |
7 |
|
T24 |
9 |
|
T25 |
7 |
| auto[1] |
886 |
1 |
|
|
T10 |
13 |
|
T24 |
11 |
|
T25 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T10 |
9 |
|
T24 |
10 |
|
T25 |
10 |
| auto[1] |
949 |
1 |
|
|
T10 |
11 |
|
T24 |
10 |
|
T25 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T10 |
11 |
|
T24 |
11 |
|
T25 |
12 |
| auto[1] |
916 |
1 |
|
|
T10 |
9 |
|
T24 |
9 |
|
T25 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T10 |
12 |
|
T24 |
11 |
|
T25 |
10 |
| auto[1] |
927 |
1 |
|
|
T10 |
8 |
|
T24 |
9 |
|
T25 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
921 |
1 |
|
|
T10 |
10 |
|
T24 |
6 |
|
T25 |
9 |
| auto[1] |
899 |
1 |
|
|
T10 |
10 |
|
T24 |
14 |
|
T25 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
939 |
1 |
|
|
T10 |
5 |
|
T24 |
9 |
|
T25 |
11 |
| auto[1] |
881 |
1 |
|
|
T10 |
15 |
|
T24 |
11 |
|
T25 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
923 |
1 |
|
|
T10 |
11 |
|
T24 |
7 |
|
T25 |
15 |
| auto[1] |
897 |
1 |
|
|
T10 |
9 |
|
T24 |
13 |
|
T25 |
5 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T10 |
7 |
|
T24 |
11 |
|
T25 |
10 |
| auto[1] |
916 |
1 |
|
|
T10 |
13 |
|
T24 |
9 |
|
T25 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
923 |
1 |
|
|
T10 |
10 |
|
T24 |
13 |
|
T25 |
10 |
| auto[1] |
897 |
1 |
|
|
T10 |
10 |
|
T24 |
7 |
|
T25 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T10 |
10 |
|
T24 |
10 |
|
T25 |
10 |
| auto[1] |
914 |
1 |
|
|
T10 |
10 |
|
T24 |
10 |
|
T25 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
449 |
1 |
|
|
T10 |
3 |
|
T24 |
6 |
|
T25 |
4 |
| auto[0] |
auto[1] |
485 |
1 |
|
|
T10 |
4 |
|
T24 |
3 |
|
T25 |
3 |
| auto[1] |
auto[0] |
435 |
1 |
|
|
T10 |
6 |
|
T24 |
6 |
|
T25 |
8 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T10 |
7 |
|
T24 |
5 |
|
T25 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
438 |
1 |
|
|
T10 |
3 |
|
T24 |
5 |
|
T25 |
3 |
| auto[0] |
auto[1] |
433 |
1 |
|
|
T10 |
6 |
|
T24 |
5 |
|
T25 |
7 |
| auto[1] |
auto[0] |
487 |
1 |
|
|
T10 |
4 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
462 |
1 |
|
|
T10 |
7 |
|
T24 |
6 |
|
T25 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
464 |
1 |
|
|
T10 |
8 |
|
T24 |
5 |
|
T25 |
7 |
| auto[0] |
auto[1] |
440 |
1 |
|
|
T10 |
3 |
|
T24 |
6 |
|
T25 |
5 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T10 |
5 |
|
T24 |
4 |
|
T25 |
5 |
| auto[1] |
auto[1] |
470 |
1 |
|
|
T10 |
4 |
|
T24 |
5 |
|
T25 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
474 |
1 |
|
|
T10 |
7 |
|
T24 |
6 |
|
T25 |
4 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T10 |
5 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[0] |
467 |
1 |
|
|
T10 |
3 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
auto[1] |
460 |
1 |
|
|
T10 |
5 |
|
T24 |
4 |
|
T25 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
480 |
1 |
|
|
T10 |
5 |
|
T24 |
5 |
|
T25 |
5 |
| auto[0] |
auto[1] |
441 |
1 |
|
|
T10 |
5 |
|
T24 |
1 |
|
T25 |
4 |
| auto[1] |
auto[0] |
455 |
1 |
|
|
T10 |
6 |
|
T24 |
6 |
|
T25 |
5 |
| auto[1] |
auto[1] |
444 |
1 |
|
|
T10 |
4 |
|
T24 |
8 |
|
T25 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
466 |
1 |
|
|
T10 |
2 |
|
T24 |
5 |
|
T25 |
5 |
| auto[0] |
auto[1] |
473 |
1 |
|
|
T10 |
3 |
|
T24 |
4 |
|
T25 |
6 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T10 |
8 |
|
T24 |
3 |
|
T25 |
3 |
| auto[1] |
auto[1] |
458 |
1 |
|
|
T10 |
7 |
|
T24 |
8 |
|
T25 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
461 |
1 |
|
|
T10 |
3 |
|
T24 |
8 |
|
T25 |
7 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T10 |
4 |
|
T24 |
3 |
|
T25 |
3 |
| auto[1] |
auto[0] |
454 |
1 |
|
|
T10 |
6 |
|
T24 |
2 |
|
T25 |
6 |
| auto[1] |
auto[1] |
462 |
1 |
|
|
T10 |
7 |
|
T24 |
7 |
|
T25 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
479 |
1 |
|
|
T10 |
6 |
|
T24 |
10 |
|
T25 |
6 |
| auto[0] |
auto[1] |
444 |
1 |
|
|
T10 |
4 |
|
T24 |
3 |
|
T25 |
4 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T10 |
6 |
|
T24 |
2 |
|
T25 |
5 |
| auto[1] |
auto[1] |
444 |
1 |
|
|
T10 |
4 |
|
T24 |
5 |
|
T25 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T10 |
5 |
|
T24 |
5 |
|
T25 |
7 |
| auto[0] |
auto[1] |
480 |
1 |
|
|
T10 |
5 |
|
T24 |
2 |
|
T25 |
4 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T10 |
3 |
|
T24 |
9 |
|
T25 |
3 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T10 |
7 |
|
T24 |
4 |
|
T25 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
924 |
1 |
|
|
T10 |
10 |
|
T24 |
7 |
|
T25 |
10 |
| auto[1] |
auto[1] |
896 |
1 |
|
|
T10 |
10 |
|
T24 |
13 |
|
T25 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
471 |
1 |
|
|
T10 |
7 |
|
T24 |
5 |
|
T25 |
6 |
| auto[0] |
auto[1] |
452 |
1 |
|
|
T10 |
4 |
|
T24 |
2 |
|
T25 |
9 |
| auto[1] |
auto[0] |
443 |
1 |
|
|
T10 |
3 |
|
T24 |
6 |
|
T25 |
4 |
| auto[1] |
auto[1] |
454 |
1 |
|
|
T10 |
6 |
|
T24 |
7 |
|
T25 |
1 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
906 |
1 |
|
|
T10 |
10 |
|
T24 |
10 |
|
T25 |
10 |
| auto[1] |
auto[1] |
914 |
1 |
|
|
T10 |
10 |
|
T24 |
10 |
|
T25 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T42 |
11 |
|
T65 |
13 |
|
T88 |
7 |
| auto[1] |
145 |
1 |
|
|
T42 |
9 |
|
T65 |
7 |
|
T88 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T42 |
6 |
|
T65 |
10 |
|
T88 |
9 |
| auto[1] |
146 |
1 |
|
|
T42 |
14 |
|
T65 |
10 |
|
T88 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T42 |
12 |
|
T65 |
8 |
|
T88 |
7 |
| auto[1] |
152 |
1 |
|
|
T42 |
8 |
|
T65 |
12 |
|
T88 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T42 |
8 |
|
T65 |
10 |
|
T88 |
10 |
| auto[1] |
141 |
1 |
|
|
T42 |
12 |
|
T65 |
10 |
|
T88 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T42 |
6 |
|
T65 |
7 |
|
T88 |
10 |
| auto[1] |
154 |
1 |
|
|
T42 |
14 |
|
T65 |
13 |
|
T88 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T42 |
13 |
|
T65 |
10 |
|
T88 |
7 |
| auto[1] |
147 |
1 |
|
|
T42 |
7 |
|
T65 |
10 |
|
T88 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T42 |
12 |
|
T65 |
8 |
|
T88 |
8 |
| auto[1] |
142 |
1 |
|
|
T42 |
8 |
|
T65 |
12 |
|
T88 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T42 |
10 |
|
T65 |
13 |
|
T88 |
10 |
| auto[1] |
140 |
1 |
|
|
T42 |
10 |
|
T65 |
7 |
|
T88 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T42 |
7 |
|
T65 |
9 |
|
T88 |
14 |
| auto[1] |
147 |
1 |
|
|
T42 |
13 |
|
T65 |
11 |
|
T88 |
6 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T42 |
12 |
|
T65 |
14 |
|
T88 |
9 |
| auto[1] |
125 |
1 |
|
|
T42 |
8 |
|
T65 |
6 |
|
T88 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T42 |
9 |
|
T65 |
15 |
|
T88 |
11 |
| auto[1] |
134 |
1 |
|
|
T42 |
11 |
|
T65 |
5 |
|
T88 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T42 |
9 |
|
T65 |
6 |
|
T88 |
5 |
| auto[1] |
161 |
1 |
|
|
T42 |
11 |
|
T65 |
14 |
|
T88 |
15 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T42 |
9 |
|
T65 |
7 |
|
T88 |
15 |
| auto[1] |
161 |
1 |
|
|
T42 |
11 |
|
T65 |
13 |
|
T88 |
5 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T42 |
6 |
|
T65 |
10 |
|
T88 |
9 |
| auto[1] |
146 |
1 |
|
|
T42 |
14 |
|
T65 |
10 |
|
T88 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T42 |
6 |
|
T65 |
11 |
|
T88 |
13 |
| auto[1] |
138 |
1 |
|
|
T42 |
14 |
|
T65 |
9 |
|
T88 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T42 |
12 |
|
T65 |
11 |
|
T88 |
8 |
| auto[1] |
153 |
1 |
|
|
T42 |
8 |
|
T65 |
9 |
|
T88 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T42 |
6 |
|
T65 |
8 |
|
T88 |
8 |
| auto[1] |
145 |
1 |
|
|
T42 |
14 |
|
T65 |
12 |
|
T88 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T42 |
7 |
|
T65 |
7 |
|
T88 |
7 |
| auto[1] |
156 |
1 |
|
|
T42 |
13 |
|
T65 |
13 |
|
T88 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T42 |
10 |
|
T65 |
7 |
|
T88 |
9 |
| auto[1] |
154 |
1 |
|
|
T42 |
10 |
|
T65 |
13 |
|
T88 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T42 |
10 |
|
T65 |
8 |
|
T88 |
9 |
| auto[1] |
154 |
1 |
|
|
T42 |
10 |
|
T65 |
12 |
|
T88 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T42 |
10 |
|
T65 |
9 |
|
T88 |
11 |
| auto[1] |
147 |
1 |
|
|
T42 |
10 |
|
T65 |
11 |
|
T88 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T42 |
14 |
|
T65 |
13 |
|
T88 |
12 |
| auto[1] |
126 |
1 |
|
|
T42 |
6 |
|
T65 |
7 |
|
T88 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T42 |
7 |
|
T65 |
10 |
|
T88 |
4 |
| auto[1] |
147 |
1 |
|
|
T42 |
13 |
|
T65 |
10 |
|
T88 |
16 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T42 |
9 |
|
T65 |
6 |
|
T88 |
5 |
| auto[1] |
161 |
1 |
|
|
T42 |
11 |
|
T65 |
14 |
|
T88 |
15 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T42 |
3 |
|
T65 |
3 |
|
T88 |
4 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T42 |
3 |
|
T65 |
8 |
|
T88 |
9 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T42 |
9 |
|
T65 |
5 |
|
T88 |
3 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T42 |
5 |
|
T65 |
4 |
|
T88 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T42 |
4 |
|
T65 |
4 |
|
T88 |
3 |
| auto[0] |
auto[1] |
64 |
1 |
|
|
T42 |
8 |
|
T65 |
7 |
|
T88 |
5 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T42 |
4 |
|
T65 |
6 |
|
T88 |
7 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T42 |
4 |
|
T65 |
3 |
|
T88 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T42 |
1 |
|
T65 |
2 |
|
T88 |
5 |
| auto[0] |
auto[1] |
75 |
1 |
|
|
T42 |
5 |
|
T65 |
6 |
|
T88 |
3 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T42 |
5 |
|
T65 |
5 |
|
T88 |
5 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T42 |
9 |
|
T65 |
7 |
|
T88 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T42 |
5 |
|
T65 |
3 |
|
T88 |
3 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T42 |
2 |
|
T65 |
4 |
|
T88 |
4 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T42 |
8 |
|
T65 |
7 |
|
T88 |
4 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T42 |
5 |
|
T65 |
6 |
|
T88 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T42 |
5 |
|
T65 |
1 |
|
T88 |
1 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T42 |
5 |
|
T65 |
6 |
|
T88 |
8 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T42 |
7 |
|
T65 |
7 |
|
T88 |
7 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T42 |
3 |
|
T65 |
6 |
|
T88 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T42 |
4 |
|
T65 |
4 |
|
T88 |
2 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T42 |
6 |
|
T65 |
4 |
|
T88 |
7 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T42 |
6 |
|
T65 |
9 |
|
T88 |
8 |
| auto[1] |
auto[1] |
78 |
1 |
|
|
T42 |
4 |
|
T65 |
3 |
|
T88 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T42 |
7 |
|
T65 |
8 |
|
T88 |
3 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T42 |
7 |
|
T65 |
5 |
|
T88 |
9 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T42 |
5 |
|
T65 |
6 |
|
T88 |
6 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T42 |
1 |
|
T65 |
1 |
|
T88 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
68 |
1 |
|
|
T42 |
2 |
|
T65 |
7 |
|
T402 |
4 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T42 |
5 |
|
T65 |
3 |
|
T88 |
4 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T42 |
7 |
|
T65 |
8 |
|
T88 |
11 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T42 |
6 |
|
T65 |
2 |
|
T88 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T42 |
5 |
|
T65 |
4 |
|
T88 |
4 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T42 |
4 |
|
T65 |
3 |
|
T88 |
11 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T42 |
6 |
|
T65 |
9 |
|
T88 |
3 |
| auto[1] |
auto[1] |
83 |
1 |
|
|
T42 |
5 |
|
T65 |
4 |
|
T88 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
134 |
1 |
|
|
T42 |
6 |
|
T65 |
10 |
|
T88 |
9 |
| auto[1] |
auto[1] |
146 |
1 |
|
|
T42 |
14 |
|
T65 |
10 |
|
T88 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T42 |
3 |
|
T65 |
4 |
|
T88 |
8 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T42 |
7 |
|
T65 |
5 |
|
T88 |
3 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T42 |
4 |
|
T65 |
5 |
|
T88 |
6 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T42 |
6 |
|
T65 |
6 |
|
T88 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
119 |
1 |
|
|
T42 |
9 |
|
T65 |
6 |
|
T88 |
5 |
| auto[1] |
auto[1] |
161 |
1 |
|
|
T42 |
11 |
|
T65 |
14 |
|
T88 |
15 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T88 |
4 |
|
T402 |
10 |
|
T264 |
10 |
| auto[1] |
70 |
1 |
|
|
T88 |
16 |
|
T402 |
10 |
|
T264 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T88 |
13 |
|
T402 |
13 |
|
T264 |
10 |
| auto[1] |
54 |
1 |
|
|
T88 |
7 |
|
T402 |
7 |
|
T264 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
63 |
1 |
|
|
T88 |
9 |
|
T402 |
12 |
|
T264 |
10 |
| auto[1] |
57 |
1 |
|
|
T88 |
11 |
|
T402 |
8 |
|
T264 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T88 |
10 |
|
T402 |
10 |
|
T264 |
9 |
| auto[1] |
58 |
1 |
|
|
T88 |
10 |
|
T402 |
10 |
|
T264 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T88 |
9 |
|
T402 |
8 |
|
T264 |
12 |
| auto[1] |
58 |
1 |
|
|
T88 |
11 |
|
T402 |
12 |
|
T264 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T88 |
13 |
|
T402 |
9 |
|
T264 |
10 |
| auto[1] |
58 |
1 |
|
|
T88 |
7 |
|
T402 |
11 |
|
T264 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T88 |
7 |
|
T402 |
15 |
|
T264 |
9 |
| auto[1] |
58 |
1 |
|
|
T88 |
13 |
|
T402 |
5 |
|
T264 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
61 |
1 |
|
|
T88 |
12 |
|
T402 |
6 |
|
T264 |
10 |
| auto[1] |
59 |
1 |
|
|
T88 |
8 |
|
T402 |
14 |
|
T264 |
10 |