Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1241

1

T1

4

T2

5

T3

13

auto[1]

1772

1

T1

13

T2

23

T3

16

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2491

1

T1

16

T2

12

T3

15

auto[1]

522

1

T1

1

T2

16

T3

14

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2829

1

T1

17

T2

28

T3

29

auto[1]

184

1

T10

1

T11

3

T32

6

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2814

1

T1

17

T2

28

T3

29

auto[1]

199

1

T9

1

T11

3

T33

6

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2862

1

T1

17

T2

28

T3

22

auto[1]

151

1

T3

7

T9

3

T34

2

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1812

1

T1

7

T2

1

T3

5

auto[1]

1201

1

T1

10

T2

27

T3

24

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1340

1

T1

17

T2

12

T3

11

auto[1]

1673

1

T2

16

T3

18

T9

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1315

1

T1

2

T2

14

T3

13

auto[1]

1698

1

T1

15

T2

14

T3

16

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1273

1

T1

7

T2

10

T3

11

auto[1]

1740

1

T1

10

T2

18

T3

18

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1262

1

T1

5

T2

11

T3

12

auto[1]

1751

1

T1

12

T2

17

T3

17

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

65

1

T1

1

T45

2

T115

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T49

1

T32

2

T96

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T9

1

T33

2

T286

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T2

2

T374

1

T97

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T9

1

T115

1

T34

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T3

1

T49

3

T298

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T2

1

T115

1

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

31

1

T49

1

T90

4

T173

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

59

1

T1

1

T9

2

T115

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T2

1

T49

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T10

1

T46

1

T144

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T2

1

T3

1

T32

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T115

2

T144

1

T172

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T3

1

T13

1

T93

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T115

1

T144

2

T81

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

23

1

T2

1

T49

2

T375

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T9

1

T115

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T2

1

T13

1

T194

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T1

2

T11

2

T115

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T2

1

T3

1

T49

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T3

1

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T1

1

T302

5

T306

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

68

1

T1

2

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T33

3

T374

1

T376

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T13

1

T46

1

T47

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T2

1

T32

1

T377

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T1

1

T9

1

T287

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T287

1

T377

3

T378

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T9

1

T115

1

T287

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T49

1

T173

1

T377

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

53

1

T115

1

T77

1

T291

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

70

1

T1

8

T49

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T11

1

T144

1

T33

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T3

1

T49

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

39

1

T46

1

T47

1

T34

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T2

1

T194

1

T93

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T11

5

T115

1

T286

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T3

1

T93

1

T305

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T9

1

T34

1

T286

15

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T13

1

T374

1

T305

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T11

2

T45

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T3

1

T45

2

T49

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T9

1

T49

1

T115

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

31

1

T49

1

T46

2

T194

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T9

1

T11

1

T80

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T32

1

T93

1

T305

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T80

4

T77

1

T304

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

52

1

T2

1

T49

1

T32

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

31

1

T144

1

T287

1

T291

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T3

1

T194

1

T93

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31

1

T47

2

T75

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T3

1

T33

6

T93

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T9

2

T115

1

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T49

1

T32

1

T302

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T11

6

T75

11

T34

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

46

1

T32

1

T287

3

T194

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T9

1

T115

1

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

45

1

T3

1

T46

7

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T9

1

T34

1

T144

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T32

1

T47

6

T379

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T115

1

T47

1

T80

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

52

1

T13

1

T32

2

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

298

1

T3

4

T9

4

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T2

1

T49

2

T93

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T3

2

T298

1

T306

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T306

1

T380

1

T100

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T32

1

T374

1

T306

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T2

2

T93

1

T233

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T381

3

T382

1

T383

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T298

1

T382

1

T384

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T3

1

T194

1

T294

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T3

1

T32

1

T194

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T33

1

T93

1

T385

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T33

1

T93

1

T374

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T1

1

T298

1

T374

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T287

2

T194

1

T386

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T2

1

T3

1

T47

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T298

2

T381

2

T376

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T194

1

T377

1

T387

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T3

1

T378

3

T306

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T298

1

T376

2

T380

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T3

1

T298

1

T374

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T3

1

T32

1

T385

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T2

2

T381

1

T219

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T2

1

T45

2

T377

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T3

1

T32

1

T298

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T381

1

T388

1

T100

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T2

1

T298

1

T112

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3

1

T298

1

T388

1

T389

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T194

1

T381

1

T108

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T376

1

T233

1

T300

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T298

1

T381

1

T306

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T47

1

T374

1

T389

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T2

1

T47

1

T97

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T32

1

T381

1

T388

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

113

1

T2

8

T3

5

T32

3

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

72

1

T1

1

T45

2

T115

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T3

2

T49

1

T32

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T9

2

T33

2

T286

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T2

2

T374

1

T306

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T9

1

T115

1

T34

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T3

1

T49

3

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T2

1

T115

1

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

39

1

T2

2

T49

1

T90

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T1

1

T9

2

T115

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T2

1

T49

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T9

1

T10

1

T46

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T2

1

T3

1

T32

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T115

2

T144

1

T172

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T3

2

T13

1

T194

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T115

1

T144

2

T291

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T2

1

T3

1

T49

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T9

1

T115

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T2

1

T13

1

T33

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T1

2

T11

2

T115

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T2

1

T3

1

T49

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T3

1

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T1

2

T302

5

T298

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

70

1

T1

2

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T33

3

T287

2

T194

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T9

1

T13

1

T46

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

38

1

T2

2

T3

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

59

1

T1

1

T9

1

T34

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T287

1

T377

3

T298

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T9

1

T115

1

T287

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T49

1

T173

1

T194

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T115

1

T77

2

T291

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

84

1

T1

8

T3

1

T49

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T11

1

T144

1

T33

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T3

1

T49

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T9

1

T46

1

T47

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T2

1

T3

1

T194

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T11

7

T115

1

T286

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T3

2

T32

1

T93

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53

1

T9

1

T34

1

T286

15

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T2

2

T13

1

T374

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T11

2

T45

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T2

1

T3

1

T45

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T9

1

T49

1

T115

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T3

1

T49

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T9

1

T11

1

T80

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T32

1

T93

1

T381

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T80

4

T77

1

T304

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

64

1

T2

2

T49

1

T32

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

36

1

T144

1

T287

1

T291

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T3

1

T194

1

T93

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T47

2

T75

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T3

1

T33

6

T194

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T9

2

T115

1

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T49

1

T32

1

T302

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T11

3

T75

9

T34

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

51

1

T32

1

T287

3

T194

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

35

1

T9

1

T115

1

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

52

1

T3

1

T46

7

T47

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T9

1

T34

1

T144

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T2

1

T32

1

T47

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T115

1

T47

1

T80

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

63

1

T13

1

T32

3

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

178

1

T3

4

T9

4

T115

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

108

1

T2

9

T3

5

T49

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T294

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T377

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T32

3

T381

4

T233

2

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	25	71	73.96	25
Automatically Generated Cross Bins	96	25	71	73.96	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

72

1

T1

1

T45

2

T115

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T3

2

T49

1

T32

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T9

2

T33

2

T286

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T2

2

T374

1

T306

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T9

1

T115

1

T34

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T3

1

T49

3

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T2

1

T115

1

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T2

2

T49

1

T90

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T1

1

T9

2

T115

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T2

1

T49

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T9

1

T10

1

T46

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T2

1

T3

1

T32

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T115

2

T144

1

T172

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T3

2

T13

1

T194

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26

1

T115

1

T144

2

T291

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T2

1

T3

1

T49

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T9

1

T115

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T2

1

T13

1

T33

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T1

2

T11

2

T115

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T2

1

T3

1

T49

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T3

1

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T1

2

T302

5

T298

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

61

1

T1

2

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T33

3

T287

2

T194

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T9

1

T13

1

T46

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T2

2

T3

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T1

1

T9

1

T34

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T287

1

T377

3

T298

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T9

1

T115

1

T287

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T49

1

T173

1

T194

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T115

1

T77

2

T291

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

84

1

T1

8

T3

1

T49

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T11

1

T144

1

T33

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T3

1

T49

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T9

1

T46

1

T47

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T2

1

T3

1

T194

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T11

5

T115

1

T286

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T3

2

T32

1

T93

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T9

1

T34

1

T286

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T2

2

T13

1

T374

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T11

2

T45

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T2

1

T3

1

T45

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T9

1

T49

1

T115

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T3

1

T49

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

35

1

T9

1

T80

1

T291

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T32

1

T93

1

T381

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

54

1

T80

3

T77

1

T304

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

64

1

T2

2

T49

1

T32

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T144

1

T287

1

T291

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T3

1

T194

1

T93

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T47

2

T75

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T3

1

T33

6

T194

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T9

2

T115

1

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T49

1

T32

1

T302

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

63

1

T11

6

T75

11

T34

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

51

1

T32

1

T287

3

T194

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T9

1

T115

1

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

52

1

T3

1

T46

7

T47

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

37

1

T9

1

T34

1

T144

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T2

1

T32

1

T47

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T115

1

T47

1

T80

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

62

1

T13

1

T32

3

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

182

1

T3

4

T9

3

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

108

1

T2

9

T3

5

T49

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T390

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T382

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T382

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T33

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T390

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T391

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T306

7

T219

1

T392

5

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	26	70	72.92	26
Automatically Generated Cross Bins	96	26	70	72.92	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

72

1

T1

1

T45

2

T115

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T3

2

T49

1

T32

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T9

2

T33

2

T286

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T2

2

T374

1

T306

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T9

1

T115

1

T34

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T3

1

T49

3

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

48

1

T2

1

T115

1

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

39

1

T2

2

T49

1

T90

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T1

1

T9

2

T115

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T2

1

T49

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T9

1

T10

1

T46

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T2

1

T3

1

T32

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T115

2

T144

1

T172

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T3

2

T13

1

T194

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T115

1

T144

2

T291

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T2

1

T3

1

T49

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T9

1

T115

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T2

1

T13

1

T194

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T1

2

T11

2

T115

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T2

1

T3

1

T49

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T3

1

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T1

2

T302

5

T298

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

72

1

T1

2

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T33

3

T287

2

T194

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T9

1

T13

1

T46

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T2

2

T3

1

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T1

1

T9

1

T34

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T287

1

T377

3

T298

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T9

1

T115

1

T287

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T49

1

T173

1

T194

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T115

1

T77

2

T291

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

84

1

T1

8

T3

1

T49

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T11

1

T144

1

T33

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T3

1

T49

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T9

1

T46

1

T47

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T2

1

T3

1

T194

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T11

7

T115

1

T286

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T3

2

T32

1

T93

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T9

1

T34

1

T286

15

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T2

2

T13

1

T374

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T11

2

T45

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T2

1

T3

1

T45

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T9

1

T49

1

T115

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T3

1

T49

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T9

1

T11

1

T80

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T32

1

T93

1

T381

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T80

4

T77

1

T304

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

64

1

T2

2

T49

1

T32

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T144

1

T287

1

T291

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T3

1

T194

1

T93

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T47

2

T75

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T3

1

T33

6

T194

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T9

2

T115

1

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T49

1

T32

1

T302

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T11

6

T75

11

T34

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

51

1

T32

1

T287

3

T194

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T9

1

T115

1

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

51

1

T3

1

T46

7

T47

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T9

1

T34

1

T144

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T2

1

T32

1

T47

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T115

1

T47

1

T80

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

63

1

T13

1

T32

3

T47

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

210

1

T9

1

T10

1

T32

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

117

1

T2

9

T3

2

T49

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T391

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T33

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T393

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T389

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T389

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T3

3

T394

2

T383

1

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded