Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
799 |
1 |
|
|
T22 |
14 |
|
T23 |
11 |
|
T24 |
7 |
| auto[1] |
721 |
1 |
|
|
T22 |
6 |
|
T23 |
9 |
|
T24 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
765 |
1 |
|
|
T22 |
6 |
|
T23 |
10 |
|
T24 |
11 |
| auto[1] |
755 |
1 |
|
|
T22 |
14 |
|
T23 |
10 |
|
T24 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
760 |
1 |
|
|
T22 |
9 |
|
T23 |
9 |
|
T24 |
12 |
| auto[1] |
760 |
1 |
|
|
T22 |
11 |
|
T23 |
11 |
|
T24 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
762 |
1 |
|
|
T22 |
11 |
|
T23 |
7 |
|
T24 |
11 |
| auto[1] |
758 |
1 |
|
|
T22 |
9 |
|
T23 |
13 |
|
T24 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
758 |
1 |
|
|
T22 |
11 |
|
T23 |
8 |
|
T24 |
9 |
| auto[1] |
762 |
1 |
|
|
T22 |
9 |
|
T23 |
12 |
|
T24 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
768 |
1 |
|
|
T22 |
8 |
|
T23 |
12 |
|
T24 |
9 |
| auto[1] |
752 |
1 |
|
|
T22 |
12 |
|
T23 |
8 |
|
T24 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
765 |
1 |
|
|
T22 |
12 |
|
T23 |
11 |
|
T24 |
8 |
| auto[1] |
755 |
1 |
|
|
T22 |
8 |
|
T23 |
9 |
|
T24 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
743 |
1 |
|
|
T22 |
9 |
|
T23 |
8 |
|
T24 |
10 |
| auto[1] |
777 |
1 |
|
|
T22 |
11 |
|
T23 |
12 |
|
T24 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T22 |
9 |
|
T23 |
11 |
|
T24 |
11 |
| auto[1] |
725 |
1 |
|
|
T22 |
11 |
|
T23 |
9 |
|
T24 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
764 |
1 |
|
|
T22 |
7 |
|
T23 |
8 |
|
T24 |
10 |
| auto[1] |
756 |
1 |
|
|
T22 |
13 |
|
T23 |
12 |
|
T24 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
758 |
1 |
|
|
T22 |
6 |
|
T23 |
14 |
|
T24 |
12 |
| auto[1] |
762 |
1 |
|
|
T22 |
14 |
|
T23 |
6 |
|
T24 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
774 |
1 |
|
|
T22 |
12 |
|
T23 |
6 |
|
T24 |
9 |
| auto[1] |
746 |
1 |
|
|
T22 |
8 |
|
T23 |
14 |
|
T24 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
763 |
1 |
|
|
T22 |
12 |
|
T23 |
8 |
|
T24 |
6 |
| auto[1] |
757 |
1 |
|
|
T22 |
8 |
|
T23 |
12 |
|
T24 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
765 |
1 |
|
|
T22 |
6 |
|
T23 |
10 |
|
T24 |
11 |
| auto[1] |
755 |
1 |
|
|
T22 |
14 |
|
T23 |
10 |
|
T24 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
730 |
1 |
|
|
T22 |
12 |
|
T23 |
11 |
|
T24 |
13 |
| auto[1] |
790 |
1 |
|
|
T22 |
8 |
|
T23 |
9 |
|
T24 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
756 |
1 |
|
|
T22 |
10 |
|
T23 |
9 |
|
T24 |
6 |
| auto[1] |
764 |
1 |
|
|
T22 |
10 |
|
T23 |
11 |
|
T24 |
14 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
723 |
1 |
|
|
T22 |
10 |
|
T23 |
8 |
|
T24 |
11 |
| auto[1] |
797 |
1 |
|
|
T22 |
10 |
|
T23 |
12 |
|
T24 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
771 |
1 |
|
|
T22 |
11 |
|
T23 |
4 |
|
T24 |
13 |
| auto[1] |
749 |
1 |
|
|
T22 |
9 |
|
T23 |
16 |
|
T24 |
7 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
758 |
1 |
|
|
T22 |
12 |
|
T23 |
7 |
|
T24 |
10 |
| auto[1] |
762 |
1 |
|
|
T22 |
8 |
|
T23 |
13 |
|
T24 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
736 |
1 |
|
|
T22 |
11 |
|
T23 |
10 |
|
T24 |
14 |
| auto[1] |
784 |
1 |
|
|
T22 |
9 |
|
T23 |
10 |
|
T24 |
6 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
769 |
1 |
|
|
T22 |
11 |
|
T23 |
11 |
|
T24 |
11 |
| auto[1] |
751 |
1 |
|
|
T22 |
9 |
|
T23 |
9 |
|
T24 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
774 |
1 |
|
|
T22 |
10 |
|
T23 |
9 |
|
T24 |
9 |
| auto[1] |
746 |
1 |
|
|
T22 |
10 |
|
T23 |
11 |
|
T24 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
764 |
1 |
|
|
T22 |
11 |
|
T23 |
13 |
|
T24 |
15 |
| auto[1] |
756 |
1 |
|
|
T22 |
9 |
|
T23 |
7 |
|
T24 |
5 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
774 |
1 |
|
|
T22 |
12 |
|
T23 |
6 |
|
T24 |
9 |
| auto[1] |
746 |
1 |
|
|
T22 |
8 |
|
T23 |
14 |
|
T24 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
381 |
1 |
|
|
T22 |
5 |
|
T23 |
5 |
|
T24 |
8 |
| auto[0] |
auto[1] |
349 |
1 |
|
|
T22 |
7 |
|
T23 |
6 |
|
T24 |
5 |
| auto[1] |
auto[0] |
379 |
1 |
|
|
T22 |
4 |
|
T23 |
4 |
|
T24 |
4 |
| auto[1] |
auto[1] |
411 |
1 |
|
|
T22 |
4 |
|
T23 |
5 |
|
T24 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
395 |
1 |
|
|
T22 |
5 |
|
T23 |
3 |
|
T24 |
4 |
| auto[0] |
auto[1] |
361 |
1 |
|
|
T22 |
5 |
|
T23 |
6 |
|
T24 |
2 |
| auto[1] |
auto[0] |
367 |
1 |
|
|
T22 |
6 |
|
T23 |
4 |
|
T24 |
7 |
| auto[1] |
auto[1] |
397 |
1 |
|
|
T22 |
4 |
|
T23 |
7 |
|
T24 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
356 |
1 |
|
|
T22 |
6 |
|
T23 |
3 |
|
T24 |
5 |
| auto[0] |
auto[1] |
367 |
1 |
|
|
T22 |
4 |
|
T23 |
5 |
|
T24 |
6 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T22 |
5 |
|
T23 |
5 |
|
T24 |
4 |
| auto[1] |
auto[1] |
395 |
1 |
|
|
T22 |
5 |
|
T23 |
7 |
|
T24 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
385 |
1 |
|
|
T22 |
5 |
|
T23 |
3 |
|
T24 |
6 |
| auto[0] |
auto[1] |
386 |
1 |
|
|
T22 |
6 |
|
T23 |
1 |
|
T24 |
7 |
| auto[1] |
auto[0] |
383 |
1 |
|
|
T22 |
3 |
|
T23 |
9 |
|
T24 |
3 |
| auto[1] |
auto[1] |
366 |
1 |
|
|
T22 |
6 |
|
T23 |
7 |
|
T24 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
360 |
1 |
|
|
T22 |
9 |
|
T23 |
4 |
|
T24 |
4 |
| auto[0] |
auto[1] |
398 |
1 |
|
|
T22 |
3 |
|
T23 |
3 |
|
T24 |
6 |
| auto[1] |
auto[0] |
405 |
1 |
|
|
T22 |
3 |
|
T23 |
7 |
|
T24 |
4 |
| auto[1] |
auto[1] |
357 |
1 |
|
|
T22 |
5 |
|
T23 |
6 |
|
T24 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
338 |
1 |
|
|
T22 |
7 |
|
T23 |
4 |
|
T24 |
7 |
| auto[0] |
auto[1] |
398 |
1 |
|
|
T22 |
4 |
|
T23 |
6 |
|
T24 |
7 |
| auto[1] |
auto[0] |
405 |
1 |
|
|
T22 |
2 |
|
T23 |
4 |
|
T24 |
3 |
| auto[1] |
auto[1] |
379 |
1 |
|
|
T22 |
7 |
|
T23 |
6 |
|
T24 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
373 |
1 |
|
|
T22 |
5 |
|
T23 |
4 |
|
T24 |
4 |
| auto[0] |
auto[1] |
401 |
1 |
|
|
T22 |
5 |
|
T23 |
5 |
|
T24 |
5 |
| auto[1] |
auto[0] |
391 |
1 |
|
|
T22 |
2 |
|
T23 |
4 |
|
T24 |
6 |
| auto[1] |
auto[1] |
355 |
1 |
|
|
T22 |
8 |
|
T23 |
7 |
|
T24 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
365 |
1 |
|
|
T22 |
5 |
|
T23 |
9 |
|
T24 |
8 |
| auto[0] |
auto[1] |
399 |
1 |
|
|
T22 |
6 |
|
T23 |
4 |
|
T24 |
7 |
| auto[1] |
auto[0] |
393 |
1 |
|
|
T22 |
1 |
|
T23 |
5 |
|
T24 |
4 |
| auto[1] |
auto[1] |
363 |
1 |
|
|
T22 |
8 |
|
T23 |
2 |
|
T24 |
1 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
397 |
1 |
|
|
T22 |
8 |
|
T23 |
3 |
|
T24 |
2 |
| auto[0] |
auto[1] |
366 |
1 |
|
|
T22 |
4 |
|
T23 |
5 |
|
T24 |
4 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T22 |
6 |
|
T23 |
8 |
|
T24 |
5 |
| auto[1] |
auto[1] |
355 |
1 |
|
|
T22 |
2 |
|
T23 |
4 |
|
T24 |
9 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
765 |
1 |
|
|
T22 |
6 |
|
T23 |
10 |
|
T24 |
11 |
| auto[1] |
auto[1] |
755 |
1 |
|
|
T22 |
14 |
|
T23 |
10 |
|
T24 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
403 |
1 |
|
|
T22 |
5 |
|
T23 |
5 |
|
T24 |
7 |
| auto[0] |
auto[1] |
366 |
1 |
|
|
T22 |
6 |
|
T23 |
6 |
|
T24 |
4 |
| auto[1] |
auto[0] |
392 |
1 |
|
|
T22 |
4 |
|
T23 |
6 |
|
T24 |
4 |
| auto[1] |
auto[1] |
359 |
1 |
|
|
T22 |
5 |
|
T23 |
3 |
|
T24 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
774 |
1 |
|
|
T22 |
12 |
|
T23 |
6 |
|
T24 |
9 |
| auto[1] |
auto[1] |
746 |
1 |
|
|
T22 |
8 |
|
T23 |
14 |
|
T24 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T184 |
13 |
|
T228 |
10 |
|
T216 |
9 |
| auto[1] |
78 |
1 |
|
|
T184 |
7 |
|
T228 |
10 |
|
T216 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
63 |
1 |
|
|
T184 |
10 |
|
T228 |
11 |
|
T216 |
9 |
| auto[1] |
77 |
1 |
|
|
T184 |
10 |
|
T228 |
9 |
|
T216 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73 |
1 |
|
|
T184 |
12 |
|
T228 |
9 |
|
T216 |
10 |
| auto[1] |
67 |
1 |
|
|
T184 |
8 |
|
T228 |
11 |
|
T216 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T184 |
12 |
|
T228 |
9 |
|
T216 |
11 |
| auto[1] |
72 |
1 |
|
|
T184 |
8 |
|
T228 |
11 |
|
T216 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T184 |
8 |
|
T228 |
13 |
|
T216 |
10 |
| auto[1] |
70 |
1 |
|
|
T184 |
12 |
|
T228 |
7 |
|
T216 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T184 |
7 |
|
T228 |
11 |
|
T216 |
14 |
| auto[1] |
65 |
1 |
|
|
T184 |
13 |
|
T228 |
9 |
|
T216 |
6 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T184 |
15 |
|
T228 |
11 |
|
T216 |
15 |
| auto[1] |
52 |
1 |
|
|
T184 |
5 |
|
T228 |
9 |
|
T216 |
5 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T184 |
11 |
|
T228 |
10 |
|
T216 |
8 |
| auto[1] |
66 |
1 |
|
|
T184 |
9 |
|
T228 |
10 |
|
T216 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T184 |
13 |
|
T228 |
10 |
|
T216 |
11 |
| auto[1] |
66 |
1 |
|
|
T184 |
7 |
|
T228 |
10 |
|
T216 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T184 |
9 |
|
T228 |
9 |
|
T216 |
10 |
| auto[1] |
72 |
1 |
|
|
T184 |
11 |
|
T228 |
11 |
|
T216 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73 |
1 |
|
|
T184 |
12 |
|
T228 |
11 |
|
T216 |
10 |
| auto[1] |
67 |
1 |
|
|
T184 |
8 |
|
T228 |
9 |
|
T216 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69 |
1 |
|
|
T184 |
9 |
|
T228 |
15 |
|
T216 |
5 |
| auto[1] |
71 |
1 |
|
|
T184 |
11 |
|
T228 |
5 |
|
T216 |
15 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T184 |
12 |
|
T228 |
13 |
|
T216 |
9 |
| auto[1] |
64 |
1 |
|
|
T184 |
8 |
|
T228 |
7 |
|
T216 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
63 |
1 |
|
|
T184 |
10 |
|
T228 |
11 |
|
T216 |
9 |
| auto[1] |
77 |
1 |
|
|
T184 |
10 |
|
T228 |
9 |
|
T216 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
65 |
1 |
|
|
T184 |
8 |
|
T228 |
9 |
|
T216 |
8 |
| auto[1] |
75 |
1 |
|
|
T184 |
12 |
|
T228 |
11 |
|
T216 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T184 |
8 |
|
T228 |
11 |
|
T216 |
13 |
| auto[1] |
80 |
1 |
|
|
T184 |
12 |
|
T228 |
9 |
|
T216 |
7 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T184 |
10 |
|
T228 |
10 |
|
T216 |
11 |
| auto[1] |
70 |
1 |
|
|
T184 |
10 |
|
T228 |
10 |
|
T216 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T184 |
9 |
|
T228 |
10 |
|
T216 |
9 |
| auto[1] |
81 |
1 |
|
|
T184 |
11 |
|
T228 |
10 |
|
T216 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T184 |
11 |
|
T228 |
9 |
|
T216 |
13 |
| auto[1] |
66 |
1 |
|
|
T184 |
9 |
|
T228 |
11 |
|
T216 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T184 |
9 |
|
T228 |
10 |
|
T216 |
6 |
| auto[1] |
76 |
1 |
|
|
T184 |
11 |
|
T228 |
10 |
|
T216 |
14 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T184 |
14 |
|
T228 |
12 |
|
T216 |
11 |
| auto[1] |
63 |
1 |
|
|
T184 |
6 |
|
T228 |
8 |
|
T216 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T184 |
9 |
|
T228 |
11 |
|
T216 |
7 |
| auto[1] |
76 |
1 |
|
|
T184 |
11 |
|
T228 |
9 |
|
T216 |
13 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
65 |
1 |
|
|
T184 |
10 |
|
T228 |
7 |
|
T216 |
9 |
| auto[1] |
75 |
1 |
|
|
T184 |
10 |
|
T228 |
13 |
|
T216 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69 |
1 |
|
|
T184 |
9 |
|
T228 |
15 |
|
T216 |
5 |
| auto[1] |
71 |
1 |
|
|
T184 |
11 |
|
T228 |
5 |
|
T216 |
15 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T184 |
6 |
|
T228 |
3 |
|
T216 |
5 |
| auto[0] |
auto[1] |
26 |
1 |
|
|
T184 |
2 |
|
T228 |
6 |
|
T216 |
3 |
| auto[1] |
auto[0] |
34 |
1 |
|
|
T184 |
6 |
|
T228 |
6 |
|
T216 |
5 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T184 |
6 |
|
T228 |
5 |
|
T216 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
34 |
1 |
|
|
T184 |
6 |
|
T228 |
4 |
|
T216 |
8 |
| auto[0] |
auto[1] |
26 |
1 |
|
|
T184 |
2 |
|
T228 |
7 |
|
T216 |
5 |
| auto[1] |
auto[0] |
34 |
1 |
|
|
T184 |
6 |
|
T228 |
5 |
|
T216 |
3 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T184 |
6 |
|
T228 |
4 |
|
T216 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
35 |
1 |
|
|
T184 |
3 |
|
T228 |
5 |
|
T216 |
6 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T184 |
7 |
|
T228 |
5 |
|
T216 |
5 |
| auto[1] |
auto[0] |
35 |
1 |
|
|
T184 |
5 |
|
T228 |
8 |
|
T216 |
4 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T184 |
5 |
|
T228 |
2 |
|
T216 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
32 |
1 |
|
|
T184 |
2 |
|
T228 |
4 |
|
T216 |
7 |
| auto[0] |
auto[1] |
27 |
1 |
|
|
T184 |
7 |
|
T228 |
6 |
|
T216 |
2 |
| auto[1] |
auto[0] |
43 |
1 |
|
|
T184 |
5 |
|
T228 |
7 |
|
T216 |
7 |
| auto[1] |
auto[1] |
38 |
1 |
|
|
T184 |
6 |
|
T228 |
3 |
|
T216 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T184 |
8 |
|
T228 |
4 |
|
T216 |
9 |
| auto[0] |
auto[1] |
29 |
1 |
|
|
T184 |
3 |
|
T228 |
5 |
|
T216 |
4 |
| auto[1] |
auto[0] |
43 |
1 |
|
|
T184 |
7 |
|
T228 |
7 |
|
T216 |
6 |
| auto[1] |
auto[1] |
23 |
1 |
|
|
T184 |
2 |
|
T228 |
4 |
|
T216 |
1 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
33 |
1 |
|
|
T184 |
5 |
|
T228 |
4 |
|
T216 |
2 |
| auto[0] |
auto[1] |
31 |
1 |
|
|
T184 |
4 |
|
T228 |
6 |
|
T216 |
4 |
| auto[1] |
auto[0] |
41 |
1 |
|
|
T184 |
6 |
|
T228 |
6 |
|
T216 |
6 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T184 |
5 |
|
T228 |
4 |
|
T216 |
8 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
30 |
1 |
|
|
T184 |
4 |
|
T228 |
5 |
|
T216 |
4 |
| auto[0] |
auto[1] |
34 |
1 |
|
|
T184 |
5 |
|
T228 |
6 |
|
T216 |
3 |
| auto[1] |
auto[0] |
38 |
1 |
|
|
T184 |
5 |
|
T228 |
4 |
|
T216 |
6 |
| auto[1] |
auto[1] |
38 |
1 |
|
|
T184 |
6 |
|
T228 |
5 |
|
T216 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
33 |
1 |
|
|
T184 |
6 |
|
T228 |
4 |
|
T216 |
5 |
| auto[0] |
auto[1] |
32 |
1 |
|
|
T184 |
4 |
|
T228 |
3 |
|
T216 |
4 |
| auto[1] |
auto[0] |
40 |
1 |
|
|
T184 |
6 |
|
T228 |
7 |
|
T216 |
5 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T184 |
4 |
|
T228 |
6 |
|
T216 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
34 |
1 |
|
|
T184 |
7 |
|
T228 |
4 |
|
T216 |
8 |
| auto[0] |
auto[1] |
42 |
1 |
|
|
T184 |
5 |
|
T228 |
9 |
|
T216 |
1 |
| auto[1] |
auto[0] |
28 |
1 |
|
|
T184 |
6 |
|
T228 |
6 |
|
T216 |
1 |
| auto[1] |
auto[1] |
36 |
1 |
|
|
T184 |
2 |
|
T228 |
1 |
|
T216 |
10 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T184 |
10 |
|
T228 |
11 |
|
T216 |
9 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T184 |
10 |
|
T228 |
9 |
|
T216 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
40 |
1 |
|
|
T184 |
10 |
|
T228 |
7 |
|
T216 |
4 |
| auto[0] |
auto[1] |
37 |
1 |
|
|
T184 |
4 |
|
T228 |
5 |
|
T216 |
7 |
| auto[1] |
auto[0] |
34 |
1 |
|
|
T184 |
3 |
|
T228 |
3 |
|
T216 |
7 |
| auto[1] |
auto[1] |
29 |
1 |
|
|
T184 |
3 |
|
T228 |
5 |
|
T216 |
2 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T184 |
9 |
|
T228 |
15 |
|
T216 |
5 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T184 |
11 |
|
T228 |
5 |
|
T216 |
15 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T167 |
11 |
|
T216 |
11 |
|
T258 |
11 |
| auto[1] |
38 |
1 |
|
|
T167 |
9 |
|
T216 |
9 |
|
T258 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T167 |
9 |
|
T216 |
8 |
|
T258 |
13 |
| auto[1] |
38 |
1 |
|
|
T167 |
11 |
|
T216 |
12 |
|
T258 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T167 |
10 |
|
T216 |
13 |
|
T258 |
10 |
| auto[1] |
34 |
1 |
|
|
T167 |
10 |
|
T216 |
7 |
|
T258 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
38 |
1 |
|
|
T167 |
12 |
|
T216 |
8 |
|
T258 |
10 |
| auto[1] |
42 |
1 |
|
|
T167 |
8 |
|
T216 |
12 |
|
T258 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
35 |
1 |
|
|
T167 |
9 |
|
T216 |
8 |
|
T258 |
8 |
| auto[1] |
45 |
1 |
|
|
T167 |
11 |
|
T216 |
12 |
|
T258 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
37 |
1 |
|
|
T167 |
9 |
|
T216 |
11 |
|
T258 |
11 |
| auto[1] |
43 |
1 |
|
|
T167 |
11 |
|
T216 |
9 |
|
T258 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T167 |
11 |
|
T216 |
10 |
|
T258 |
10 |
| auto[1] |
38 |
1 |
|
|
T167 |
9 |
|
T216 |
10 |
|
T258 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T167 |
8 |
|
T216 |
12 |
|
T258 |
9 |
| auto[1] |
38 |
1 |
|
|
T167 |
12 |
|
T216 |
8 |
|
T258 |
11 |