Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T1 |
11 |
|
T2 |
7 |
|
T9 |
11 |
| auto[1] |
813 |
1 |
|
|
T1 |
9 |
|
T2 |
13 |
|
T9 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T9 |
10 |
| auto[1] |
834 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T9 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
863 |
1 |
|
|
T1 |
11 |
|
T2 |
10 |
|
T9 |
13 |
| auto[1] |
797 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T9 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
850 |
1 |
|
|
T1 |
12 |
|
T2 |
12 |
|
T9 |
10 |
| auto[1] |
810 |
1 |
|
|
T1 |
8 |
|
T2 |
8 |
|
T9 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
825 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T9 |
11 |
| auto[1] |
835 |
1 |
|
|
T1 |
11 |
|
T2 |
9 |
|
T9 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T9 |
13 |
| auto[1] |
829 |
1 |
|
|
T1 |
13 |
|
T2 |
12 |
|
T9 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T9 |
11 |
| auto[1] |
854 |
1 |
|
|
T1 |
13 |
|
T2 |
12 |
|
T9 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
837 |
1 |
|
|
T1 |
11 |
|
T2 |
14 |
|
T9 |
8 |
| auto[1] |
823 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T9 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
819 |
1 |
|
|
T1 |
11 |
|
T2 |
10 |
|
T9 |
9 |
| auto[1] |
841 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T9 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T9 |
9 |
| auto[1] |
807 |
1 |
|
|
T1 |
8 |
|
T2 |
7 |
|
T9 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T1 |
8 |
|
T2 |
10 |
|
T9 |
6 |
| auto[1] |
834 |
1 |
|
|
T1 |
12 |
|
T2 |
10 |
|
T9 |
14 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T1 |
14 |
|
T2 |
11 |
|
T9 |
8 |
| auto[1] |
811 |
1 |
|
|
T1 |
6 |
|
T2 |
9 |
|
T9 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T1 |
13 |
|
T2 |
9 |
|
T9 |
12 |
| auto[1] |
826 |
1 |
|
|
T1 |
7 |
|
T2 |
11 |
|
T9 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T9 |
10 |
| auto[1] |
834 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T9 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T1 |
9 |
|
T2 |
13 |
|
T9 |
8 |
| auto[1] |
806 |
1 |
|
|
T1 |
11 |
|
T2 |
7 |
|
T9 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
819 |
1 |
|
|
T1 |
6 |
|
T2 |
7 |
|
T9 |
9 |
| auto[1] |
841 |
1 |
|
|
T1 |
14 |
|
T2 |
13 |
|
T9 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
797 |
1 |
|
|
T1 |
11 |
|
T2 |
8 |
|
T9 |
9 |
| auto[1] |
863 |
1 |
|
|
T1 |
9 |
|
T2 |
12 |
|
T9 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T1 |
7 |
|
T2 |
9 |
|
T9 |
7 |
| auto[1] |
817 |
1 |
|
|
T1 |
13 |
|
T2 |
11 |
|
T9 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T1 |
7 |
|
T2 |
13 |
|
T9 |
7 |
| auto[1] |
852 |
1 |
|
|
T1 |
13 |
|
T2 |
7 |
|
T9 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
859 |
1 |
|
|
T1 |
13 |
|
T2 |
15 |
|
T9 |
10 |
| auto[1] |
801 |
1 |
|
|
T1 |
7 |
|
T2 |
5 |
|
T9 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
837 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T9 |
10 |
| auto[1] |
823 |
1 |
|
|
T1 |
10 |
|
T2 |
9 |
|
T9 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T1 |
13 |
|
T2 |
9 |
|
T9 |
6 |
| auto[1] |
815 |
1 |
|
|
T1 |
7 |
|
T2 |
11 |
|
T9 |
14 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T9 |
11 |
| auto[1] |
820 |
1 |
|
|
T1 |
11 |
|
T2 |
10 |
|
T9 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T1 |
14 |
|
T2 |
11 |
|
T9 |
8 |
| auto[1] |
811 |
1 |
|
|
T1 |
6 |
|
T2 |
9 |
|
T9 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
440 |
1 |
|
|
T1 |
6 |
|
T2 |
7 |
|
T9 |
6 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T1 |
3 |
|
T2 |
6 |
|
T9 |
2 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T9 |
7 |
| auto[1] |
auto[1] |
383 |
1 |
|
|
T1 |
6 |
|
T2 |
4 |
|
T9 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T9 |
5 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T9 |
4 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T1 |
7 |
|
T2 |
7 |
|
T9 |
5 |
| auto[1] |
auto[1] |
407 |
1 |
|
|
T1 |
7 |
|
T2 |
6 |
|
T9 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
380 |
1 |
|
|
T1 |
6 |
|
T2 |
5 |
|
T9 |
5 |
| auto[0] |
auto[1] |
417 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T9 |
4 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T1 |
3 |
|
T2 |
6 |
|
T9 |
6 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T1 |
6 |
|
T2 |
6 |
|
T9 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
406 |
1 |
|
|
T1 |
3 |
|
T2 |
4 |
|
T9 |
5 |
| auto[0] |
auto[1] |
437 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T9 |
2 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T9 |
8 |
| auto[1] |
auto[1] |
392 |
1 |
|
|
T1 |
9 |
|
T2 |
7 |
|
T9 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
404 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T9 |
4 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T1 |
3 |
|
T2 |
7 |
|
T9 |
3 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T9 |
7 |
| auto[1] |
auto[1] |
450 |
1 |
|
|
T1 |
10 |
|
T2 |
5 |
|
T9 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
445 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T9 |
4 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T9 |
6 |
| auto[1] |
auto[0] |
392 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T9 |
4 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T9 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T1 |
8 |
|
T2 |
8 |
|
T9 |
1 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T9 |
5 |
| auto[1] |
auto[0] |
431 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T9 |
8 |
| auto[1] |
auto[1] |
384 |
1 |
|
|
T1 |
3 |
|
T2 |
6 |
|
T9 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
406 |
1 |
|
|
T1 |
4 |
|
T2 |
7 |
|
T9 |
2 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T9 |
9 |
| auto[1] |
auto[0] |
420 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T9 |
4 |
| auto[1] |
auto[1] |
400 |
1 |
|
|
T1 |
7 |
|
T2 |
7 |
|
T9 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T9 |
9 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T9 |
3 |
| auto[1] |
auto[0] |
416 |
1 |
|
|
T1 |
3 |
|
T2 |
4 |
|
T9 |
2 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T1 |
4 |
|
T2 |
7 |
|
T9 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
826 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T9 |
10 |
| auto[1] |
auto[1] |
834 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T9 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T9 |
6 |
| auto[0] |
auto[1] |
411 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T9 |
4 |
| auto[1] |
auto[0] |
393 |
1 |
|
|
T1 |
6 |
|
T2 |
4 |
|
T9 |
3 |
| auto[1] |
auto[1] |
430 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T9 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
849 |
1 |
|
|
T1 |
14 |
|
T2 |
11 |
|
T9 |
8 |
| auto[1] |
auto[1] |
811 |
1 |
|
|
T1 |
6 |
|
T2 |
9 |
|
T9 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T1 |
14 |
|
T27 |
9 |
|
T32 |
12 |
| auto[1] |
125 |
1 |
|
|
T1 |
6 |
|
T27 |
11 |
|
T32 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T1 |
10 |
|
T27 |
9 |
|
T32 |
11 |
| auto[1] |
133 |
1 |
|
|
T1 |
10 |
|
T27 |
11 |
|
T32 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T1 |
10 |
|
T27 |
7 |
|
T32 |
12 |
| auto[1] |
137 |
1 |
|
|
T1 |
10 |
|
T27 |
13 |
|
T32 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T1 |
11 |
|
T27 |
8 |
|
T32 |
9 |
| auto[1] |
131 |
1 |
|
|
T1 |
9 |
|
T27 |
12 |
|
T32 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T1 |
10 |
|
T27 |
8 |
|
T32 |
10 |
| auto[1] |
131 |
1 |
|
|
T1 |
10 |
|
T27 |
12 |
|
T32 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T1 |
10 |
|
T27 |
12 |
|
T32 |
10 |
| auto[1] |
114 |
1 |
|
|
T1 |
10 |
|
T27 |
8 |
|
T32 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T1 |
7 |
|
T27 |
11 |
|
T32 |
7 |
| auto[1] |
131 |
1 |
|
|
T1 |
13 |
|
T27 |
9 |
|
T32 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T1 |
10 |
|
T27 |
12 |
|
T32 |
11 |
| auto[1] |
125 |
1 |
|
|
T1 |
10 |
|
T27 |
8 |
|
T32 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T1 |
10 |
|
T27 |
12 |
|
T32 |
10 |
| auto[1] |
136 |
1 |
|
|
T1 |
10 |
|
T27 |
8 |
|
T32 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T1 |
7 |
|
T27 |
7 |
|
T32 |
8 |
| auto[1] |
137 |
1 |
|
|
T1 |
13 |
|
T27 |
13 |
|
T32 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T1 |
9 |
|
T27 |
11 |
|
T32 |
12 |
| auto[1] |
126 |
1 |
|
|
T1 |
11 |
|
T27 |
9 |
|
T32 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T1 |
6 |
|
T27 |
9 |
|
T32 |
10 |
| auto[1] |
133 |
1 |
|
|
T1 |
14 |
|
T27 |
11 |
|
T32 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T1 |
10 |
|
T27 |
9 |
|
T32 |
8 |
| auto[1] |
130 |
1 |
|
|
T1 |
10 |
|
T27 |
11 |
|
T32 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T1 |
10 |
|
T27 |
9 |
|
T32 |
11 |
| auto[1] |
133 |
1 |
|
|
T1 |
10 |
|
T27 |
11 |
|
T32 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T1 |
12 |
|
T27 |
12 |
|
T32 |
11 |
| auto[1] |
142 |
1 |
|
|
T1 |
8 |
|
T27 |
8 |
|
T32 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T1 |
13 |
|
T27 |
11 |
|
T32 |
8 |
| auto[1] |
130 |
1 |
|
|
T1 |
7 |
|
T27 |
9 |
|
T32 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T1 |
7 |
|
T27 |
11 |
|
T32 |
7 |
| auto[1] |
132 |
1 |
|
|
T1 |
13 |
|
T27 |
9 |
|
T32 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T1 |
9 |
|
T27 |
11 |
|
T32 |
11 |
| auto[1] |
127 |
1 |
|
|
T1 |
11 |
|
T27 |
9 |
|
T32 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T1 |
3 |
|
T27 |
9 |
|
T32 |
12 |
| auto[1] |
136 |
1 |
|
|
T1 |
17 |
|
T27 |
11 |
|
T32 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T1 |
6 |
|
T27 |
16 |
|
T32 |
10 |
| auto[1] |
134 |
1 |
|
|
T1 |
14 |
|
T27 |
4 |
|
T32 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T1 |
11 |
|
T27 |
11 |
|
T32 |
8 |
| auto[1] |
134 |
1 |
|
|
T1 |
9 |
|
T27 |
9 |
|
T32 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T1 |
10 |
|
T27 |
8 |
|
T32 |
8 |
| auto[1] |
131 |
1 |
|
|
T1 |
10 |
|
T27 |
12 |
|
T32 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T1 |
8 |
|
T27 |
10 |
|
T32 |
12 |
| auto[1] |
114 |
1 |
|
|
T1 |
12 |
|
T27 |
10 |
|
T32 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T1 |
6 |
|
T27 |
9 |
|
T32 |
10 |
| auto[1] |
133 |
1 |
|
|
T1 |
14 |
|
T27 |
11 |
|
T32 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T1 |
6 |
|
T27 |
3 |
|
T32 |
6 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T1 |
6 |
|
T27 |
9 |
|
T32 |
5 |
| auto[1] |
auto[0] |
70 |
1 |
|
|
T1 |
4 |
|
T27 |
4 |
|
T32 |
6 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T1 |
4 |
|
T27 |
4 |
|
T32 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T1 |
7 |
|
T27 |
3 |
|
T32 |
3 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T1 |
6 |
|
T27 |
8 |
|
T32 |
5 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T1 |
4 |
|
T27 |
5 |
|
T32 |
6 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T1 |
3 |
|
T27 |
4 |
|
T32 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T1 |
6 |
|
T27 |
6 |
|
T32 |
3 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T1 |
1 |
|
T27 |
5 |
|
T32 |
4 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T1 |
4 |
|
T27 |
2 |
|
T32 |
7 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T1 |
9 |
|
T27 |
7 |
|
T32 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T1 |
7 |
|
T27 |
8 |
|
T32 |
5 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T1 |
2 |
|
T27 |
3 |
|
T32 |
6 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T1 |
3 |
|
T27 |
4 |
|
T32 |
5 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T1 |
8 |
|
T27 |
5 |
|
T32 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T27 |
5 |
|
T32 |
6 |
|
T277 |
4 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T1 |
3 |
|
T27 |
4 |
|
T32 |
6 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T1 |
7 |
|
T27 |
6 |
|
T32 |
1 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T1 |
10 |
|
T27 |
5 |
|
T32 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T1 |
3 |
|
T27 |
9 |
|
T32 |
7 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T1 |
3 |
|
T27 |
7 |
|
T32 |
3 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T1 |
7 |
|
T27 |
3 |
|
T32 |
4 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T1 |
7 |
|
T27 |
1 |
|
T32 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T1 |
2 |
|
T27 |
2 |
|
T32 |
2 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T1 |
8 |
|
T27 |
6 |
|
T32 |
6 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T1 |
5 |
|
T27 |
5 |
|
T32 |
6 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T1 |
5 |
|
T27 |
7 |
|
T32 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
78 |
1 |
|
|
T1 |
2 |
|
T27 |
5 |
|
T32 |
6 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T1 |
6 |
|
T27 |
5 |
|
T32 |
6 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T1 |
7 |
|
T27 |
6 |
|
T32 |
6 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T1 |
5 |
|
T27 |
4 |
|
T32 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T1 |
5 |
|
T27 |
3 |
|
T32 |
5 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T1 |
5 |
|
T27 |
6 |
|
T32 |
3 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T1 |
9 |
|
T27 |
6 |
|
T32 |
7 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T1 |
1 |
|
T27 |
5 |
|
T32 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
127 |
1 |
|
|
T1 |
10 |
|
T27 |
9 |
|
T32 |
11 |
| auto[1] |
auto[1] |
133 |
1 |
|
|
T1 |
10 |
|
T27 |
11 |
|
T32 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T1 |
7 |
|
T27 |
6 |
|
T32 |
4 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T1 |
4 |
|
T27 |
5 |
|
T32 |
4 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T1 |
3 |
|
T27 |
6 |
|
T32 |
6 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T1 |
6 |
|
T27 |
3 |
|
T32 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
127 |
1 |
|
|
T1 |
6 |
|
T27 |
9 |
|
T32 |
10 |
| auto[1] |
auto[1] |
133 |
1 |
|
|
T1 |
14 |
|
T27 |
11 |
|
T32 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T113 |
12 |
|
T134 |
8 |
|
T161 |
10 |
| auto[1] |
52 |
1 |
|
|
T113 |
8 |
|
T134 |
12 |
|
T161 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T113 |
9 |
|
T134 |
13 |
|
T161 |
10 |
| auto[1] |
49 |
1 |
|
|
T113 |
11 |
|
T134 |
7 |
|
T161 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T113 |
8 |
|
T134 |
8 |
|
T161 |
8 |
| auto[1] |
55 |
1 |
|
|
T113 |
12 |
|
T134 |
12 |
|
T161 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T113 |
12 |
|
T134 |
8 |
|
T161 |
9 |
| auto[1] |
50 |
1 |
|
|
T113 |
8 |
|
T134 |
12 |
|
T161 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T113 |
7 |
|
T134 |
10 |
|
T161 |
11 |
| auto[1] |
53 |
1 |
|
|
T113 |
13 |
|
T134 |
10 |
|
T161 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T113 |
9 |
|
T134 |
9 |
|
T161 |
9 |
| auto[1] |
47 |
1 |
|
|
T113 |
11 |
|
T134 |
11 |
|
T161 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T113 |
7 |
|
T134 |
8 |
|
T161 |
10 |
| auto[1] |
55 |
1 |
|
|
T113 |
13 |
|
T134 |
12 |
|
T161 |
10 |