Unified Coverage Report :: Cond split page

Go back

 LINE       6673
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T1,T2,T8

 LINE       6675
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T19,T258,T263
1	1	1	Covered	T1,T2,T8

 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T258,T263,T265
1	1	1	Covered	T1,T2,T8

 LINE       6680
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T258,T262,T265
1	1	1	Covered	T1,T2,T6

 LINE       6682
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T1,T2,T9

 LINE       6695
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T5,T2
1	1	0	Covered	T19,T263,T267
1	1	1	Covered	T1,T5,T2

 LINE       6712
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T258,T263,T265
1	1	1	Covered	T1,T5,T2

 LINE       6721
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T134,T105,T258
1	1	1	Covered	T1,T5,T2

 LINE       6730
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T1,T3,T11

 LINE       6745
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T262,T263,T265
1	1	1	Covered	T1,T3,T6

 LINE       6747
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T258,T263,T268
1	1	1	Covered	T1,T8,T18

 LINE       6750
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T1,T8,T18

 LINE       6757
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T269,T262,T265
1	1	1	Covered	T6,T7,T14

 LINE       6763
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T6,T7,T14

 LINE       6769
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T6,T7,T14

 LINE       6775
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T19,T258,T262
1	1	1	Covered	T6,T7,T14

 LINE       6781
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T262,T263,T270
1	1	1	Covered	T6,T7,T14

 LINE       6783
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T257,T258,T262
1	1	1	Covered	T6,T7,T14

 LINE       6785
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T262,T263,T265
1	1	1	Covered	T6,T7,T14

 LINE       6787
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T260,T262
1	1	1	Covered	T6,T7,T14

 LINE       6789
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T266,T262
1	1	1	Covered	T1,T6,T7

 LINE       6795
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T257,T258,T264
1	1	1	Covered	T1,T6,T7

 LINE       6801
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T263,T265
1	1	1	Covered	T1,T6,T7

 LINE       6807
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T263,T265,T268
1	1	1	Covered	T1,T6,T7

 LINE       6813
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T1,T6,T7

 LINE       6815
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T262,T263,T265
1	1	1	Covered	T1,T6,T7

 LINE       6817
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T116,T258,T262
1	1	1	Covered	T1,T6,T7

 LINE       6819
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T1,T6,T7

 LINE       6821
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T261,T258,T262
1	1	1	Covered	T1,T6,T7

 LINE       6826
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T266,T263,T271
1	1	1	Covered	T1,T6,T7

 LINE       6831
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T262,T263
1	1	1	Covered	T1,T6,T7

 LINE       6836
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T272,T263
1	1	1	Covered	T1,T6,T7

 LINE       6841
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T258,T263,T265
1	1	1	Covered	T1,T6,T7

 LINE       6850
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T19,T257,T258
1	1	1	Covered	T1,T3,T11

 LINE       7105
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2