Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
911 |
1 |
|
|
T1 |
10 |
|
T25 |
10 |
|
T41 |
9 |
| auto[1] |
889 |
1 |
|
|
T1 |
10 |
|
T25 |
10 |
|
T41 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T1 |
9 |
|
T25 |
12 |
|
T41 |
11 |
| auto[1] |
883 |
1 |
|
|
T1 |
11 |
|
T25 |
8 |
|
T41 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T1 |
9 |
|
T25 |
10 |
|
T41 |
7 |
| auto[1] |
903 |
1 |
|
|
T1 |
11 |
|
T25 |
10 |
|
T41 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
916 |
1 |
|
|
T1 |
13 |
|
T25 |
12 |
|
T41 |
7 |
| auto[1] |
884 |
1 |
|
|
T1 |
7 |
|
T25 |
8 |
|
T41 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
888 |
1 |
|
|
T1 |
13 |
|
T25 |
11 |
|
T41 |
12 |
| auto[1] |
912 |
1 |
|
|
T1 |
7 |
|
T25 |
9 |
|
T41 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T1 |
8 |
|
T25 |
8 |
|
T41 |
7 |
| auto[1] |
899 |
1 |
|
|
T1 |
12 |
|
T25 |
12 |
|
T41 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T1 |
12 |
|
T25 |
7 |
|
T41 |
9 |
| auto[1] |
952 |
1 |
|
|
T1 |
8 |
|
T25 |
13 |
|
T41 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
932 |
1 |
|
|
T1 |
12 |
|
T25 |
11 |
|
T41 |
12 |
| auto[1] |
868 |
1 |
|
|
T1 |
8 |
|
T25 |
9 |
|
T41 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
869 |
1 |
|
|
T1 |
13 |
|
T25 |
7 |
|
T41 |
6 |
| auto[1] |
931 |
1 |
|
|
T1 |
7 |
|
T25 |
13 |
|
T41 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
933 |
1 |
|
|
T1 |
9 |
|
T25 |
12 |
|
T41 |
12 |
| auto[1] |
867 |
1 |
|
|
T1 |
11 |
|
T25 |
8 |
|
T41 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
910 |
1 |
|
|
T1 |
7 |
|
T25 |
10 |
|
T41 |
6 |
| auto[1] |
890 |
1 |
|
|
T1 |
13 |
|
T25 |
10 |
|
T41 |
14 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T1 |
8 |
|
T25 |
9 |
|
T41 |
7 |
| auto[1] |
938 |
1 |
|
|
T1 |
12 |
|
T25 |
11 |
|
T41 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
944 |
1 |
|
|
T1 |
11 |
|
T25 |
11 |
|
T41 |
13 |
| auto[1] |
856 |
1 |
|
|
T1 |
9 |
|
T25 |
9 |
|
T41 |
7 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T1 |
9 |
|
T25 |
12 |
|
T41 |
11 |
| auto[1] |
883 |
1 |
|
|
T1 |
11 |
|
T25 |
8 |
|
T41 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T1 |
10 |
|
T25 |
9 |
|
T41 |
10 |
| auto[1] |
887 |
1 |
|
|
T1 |
10 |
|
T25 |
11 |
|
T41 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
896 |
1 |
|
|
T1 |
12 |
|
T25 |
13 |
|
T41 |
8 |
| auto[1] |
904 |
1 |
|
|
T1 |
8 |
|
T25 |
7 |
|
T41 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T1 |
14 |
|
T25 |
8 |
|
T41 |
10 |
| auto[1] |
906 |
1 |
|
|
T1 |
6 |
|
T25 |
12 |
|
T41 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T1 |
9 |
|
T25 |
9 |
|
T41 |
7 |
| auto[1] |
913 |
1 |
|
|
T1 |
11 |
|
T25 |
11 |
|
T41 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T1 |
13 |
|
T25 |
11 |
|
T41 |
12 |
| auto[1] |
886 |
1 |
|
|
T1 |
7 |
|
T25 |
9 |
|
T41 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T1 |
7 |
|
T25 |
7 |
|
T41 |
11 |
| auto[1] |
910 |
1 |
|
|
T1 |
13 |
|
T25 |
13 |
|
T41 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T1 |
12 |
|
T25 |
8 |
|
T41 |
8 |
| auto[1] |
906 |
1 |
|
|
T1 |
8 |
|
T25 |
12 |
|
T41 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T1 |
10 |
|
T25 |
11 |
|
T41 |
7 |
| auto[1] |
903 |
1 |
|
|
T1 |
10 |
|
T25 |
9 |
|
T41 |
13 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
934 |
1 |
|
|
T1 |
14 |
|
T25 |
9 |
|
T41 |
15 |
| auto[1] |
866 |
1 |
|
|
T1 |
6 |
|
T25 |
11 |
|
T41 |
5 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T1 |
8 |
|
T25 |
9 |
|
T41 |
7 |
| auto[1] |
938 |
1 |
|
|
T1 |
12 |
|
T25 |
11 |
|
T41 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
468 |
1 |
|
|
T1 |
7 |
|
T25 |
5 |
|
T41 |
6 |
| auto[0] |
auto[1] |
445 |
1 |
|
|
T1 |
3 |
|
T25 |
4 |
|
T41 |
4 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T1 |
2 |
|
T25 |
5 |
|
T41 |
1 |
| auto[1] |
auto[1] |
458 |
1 |
|
|
T1 |
8 |
|
T25 |
6 |
|
T41 |
9 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
469 |
1 |
|
|
T1 |
10 |
|
T25 |
8 |
|
T41 |
5 |
| auto[0] |
auto[1] |
427 |
1 |
|
|
T1 |
2 |
|
T25 |
5 |
|
T41 |
3 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T1 |
3 |
|
T25 |
4 |
|
T41 |
2 |
| auto[1] |
auto[1] |
457 |
1 |
|
|
T1 |
5 |
|
T25 |
3 |
|
T41 |
10 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T1 |
8 |
|
T25 |
7 |
|
T41 |
7 |
| auto[0] |
auto[1] |
452 |
1 |
|
|
T1 |
6 |
|
T25 |
1 |
|
T41 |
3 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T1 |
5 |
|
T25 |
4 |
|
T41 |
5 |
| auto[1] |
auto[1] |
460 |
1 |
|
|
T1 |
1 |
|
T25 |
8 |
|
T41 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
445 |
1 |
|
|
T1 |
3 |
|
T25 |
6 |
|
T41 |
3 |
| auto[0] |
auto[1] |
442 |
1 |
|
|
T1 |
6 |
|
T25 |
3 |
|
T41 |
4 |
| auto[1] |
auto[0] |
456 |
1 |
|
|
T1 |
5 |
|
T25 |
2 |
|
T41 |
4 |
| auto[1] |
auto[1] |
457 |
1 |
|
|
T1 |
6 |
|
T25 |
9 |
|
T41 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
421 |
1 |
|
|
T1 |
8 |
|
T25 |
4 |
|
T41 |
5 |
| auto[0] |
auto[1] |
493 |
1 |
|
|
T1 |
5 |
|
T25 |
7 |
|
T41 |
7 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T1 |
4 |
|
T25 |
3 |
|
T41 |
4 |
| auto[1] |
auto[1] |
459 |
1 |
|
|
T1 |
3 |
|
T25 |
6 |
|
T41 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
451 |
1 |
|
|
T1 |
5 |
|
T25 |
4 |
|
T41 |
6 |
| auto[0] |
auto[1] |
439 |
1 |
|
|
T1 |
2 |
|
T25 |
3 |
|
T41 |
5 |
| auto[1] |
auto[0] |
481 |
1 |
|
|
T1 |
7 |
|
T25 |
7 |
|
T41 |
6 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T1 |
6 |
|
T25 |
6 |
|
T41 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T1 |
5 |
|
T25 |
6 |
|
T41 |
3 |
| auto[0] |
auto[1] |
447 |
1 |
|
|
T1 |
5 |
|
T25 |
5 |
|
T41 |
4 |
| auto[1] |
auto[0] |
483 |
1 |
|
|
T1 |
4 |
|
T25 |
6 |
|
T41 |
9 |
| auto[1] |
auto[1] |
420 |
1 |
|
|
T1 |
6 |
|
T25 |
3 |
|
T41 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
457 |
1 |
|
|
T1 |
6 |
|
T25 |
4 |
|
T41 |
4 |
| auto[0] |
auto[1] |
477 |
1 |
|
|
T1 |
8 |
|
T25 |
5 |
|
T41 |
11 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T1 |
1 |
|
T25 |
6 |
|
T41 |
2 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T1 |
5 |
|
T25 |
5 |
|
T41 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
461 |
1 |
|
|
T1 |
6 |
|
T25 |
5 |
|
T41 |
5 |
| auto[0] |
auto[1] |
483 |
1 |
|
|
T1 |
5 |
|
T25 |
6 |
|
T41 |
8 |
| auto[1] |
auto[0] |
450 |
1 |
|
|
T1 |
4 |
|
T25 |
5 |
|
T41 |
4 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T1 |
5 |
|
T25 |
4 |
|
T41 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
917 |
1 |
|
|
T1 |
9 |
|
T25 |
12 |
|
T41 |
11 |
| auto[1] |
auto[1] |
883 |
1 |
|
|
T1 |
11 |
|
T25 |
8 |
|
T41 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T1 |
8 |
|
T25 |
5 |
|
T41 |
2 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T1 |
4 |
|
T25 |
3 |
|
T41 |
6 |
| auto[1] |
auto[0] |
436 |
1 |
|
|
T1 |
5 |
|
T25 |
2 |
|
T41 |
4 |
| auto[1] |
auto[1] |
470 |
1 |
|
|
T1 |
3 |
|
T25 |
10 |
|
T41 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
862 |
1 |
|
|
T1 |
8 |
|
T25 |
9 |
|
T41 |
7 |
| auto[1] |
auto[1] |
938 |
1 |
|
|
T1 |
12 |
|
T25 |
11 |
|
T41 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T1 |
13 |
|
T2 |
10 |
|
T112 |
13 |
| auto[1] |
183 |
1 |
|
|
T1 |
7 |
|
T2 |
10 |
|
T112 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
194 |
1 |
|
|
T1 |
11 |
|
T2 |
14 |
|
T112 |
13 |
| auto[1] |
166 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T112 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
185 |
1 |
|
|
T1 |
8 |
|
T2 |
9 |
|
T112 |
6 |
| auto[1] |
175 |
1 |
|
|
T1 |
12 |
|
T2 |
11 |
|
T112 |
14 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T112 |
10 |
| auto[1] |
193 |
1 |
|
|
T1 |
9 |
|
T2 |
8 |
|
T112 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
192 |
1 |
|
|
T1 |
15 |
|
T2 |
8 |
|
T112 |
11 |
| auto[1] |
168 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T112 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T1 |
9 |
|
T2 |
12 |
|
T112 |
11 |
| auto[1] |
183 |
1 |
|
|
T1 |
11 |
|
T2 |
8 |
|
T112 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T112 |
7 |
| auto[1] |
189 |
1 |
|
|
T1 |
15 |
|
T2 |
8 |
|
T112 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
160 |
1 |
|
|
T1 |
11 |
|
T2 |
5 |
|
T112 |
8 |
| auto[1] |
200 |
1 |
|
|
T1 |
9 |
|
T2 |
15 |
|
T112 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
176 |
1 |
|
|
T1 |
11 |
|
T2 |
9 |
|
T112 |
9 |
| auto[1] |
184 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T112 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T1 |
12 |
|
T2 |
9 |
|
T112 |
9 |
| auto[1] |
177 |
1 |
|
|
T1 |
8 |
|
T2 |
11 |
|
T112 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T1 |
8 |
|
T2 |
11 |
|
T112 |
12 |
| auto[1] |
193 |
1 |
|
|
T1 |
12 |
|
T2 |
9 |
|
T112 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
180 |
1 |
|
|
T1 |
9 |
|
T2 |
8 |
|
T112 |
6 |
| auto[1] |
180 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T112 |
14 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
188 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T112 |
11 |
| auto[1] |
172 |
1 |
|
|
T1 |
11 |
|
T2 |
10 |
|
T112 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
194 |
1 |
|
|
T1 |
11 |
|
T2 |
14 |
|
T112 |
13 |
| auto[1] |
166 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T112 |
7 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T1 |
8 |
|
T2 |
9 |
|
T112 |
10 |
| auto[1] |
196 |
1 |
|
|
T1 |
12 |
|
T2 |
11 |
|
T112 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
192 |
1 |
|
|
T1 |
11 |
|
T2 |
10 |
|
T112 |
8 |
| auto[1] |
168 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T112 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T1 |
5 |
|
T2 |
4 |
|
T112 |
7 |
| auto[1] |
187 |
1 |
|
|
T1 |
15 |
|
T2 |
16 |
|
T112 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T1 |
5 |
|
T2 |
8 |
|
T112 |
7 |
| auto[1] |
198 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T112 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T1 |
10 |
|
T2 |
7 |
|
T112 |
15 |
| auto[1] |
177 |
1 |
|
|
T1 |
10 |
|
T2 |
13 |
|
T112 |
5 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
170 |
1 |
|
|
T1 |
10 |
|
T2 |
12 |
|
T112 |
12 |
| auto[1] |
190 |
1 |
|
|
T1 |
10 |
|
T2 |
8 |
|
T112 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T112 |
12 |
| auto[1] |
181 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T112 |
8 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T1 |
11 |
|
T2 |
9 |
|
T112 |
10 |
| auto[1] |
177 |
1 |
|
|
T1 |
9 |
|
T2 |
11 |
|
T112 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
187 |
1 |
|
|
T1 |
11 |
|
T2 |
11 |
|
T112 |
11 |
| auto[1] |
173 |
1 |
|
|
T1 |
9 |
|
T2 |
9 |
|
T112 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
180 |
1 |
|
|
T1 |
9 |
|
T2 |
8 |
|
T112 |
6 |
| auto[1] |
180 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T112 |
14 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
85 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T112 |
3 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T112 |
7 |
| auto[1] |
auto[0] |
100 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T112 |
3 |
| auto[1] |
auto[1] |
96 |
1 |
|
|
T1 |
8 |
|
T2 |
8 |
|
T112 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T112 |
4 |
| auto[0] |
auto[1] |
102 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T112 |
4 |
| auto[1] |
auto[0] |
77 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T112 |
6 |
| auto[1] |
auto[1] |
91 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T112 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T112 |
5 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T112 |
2 |
| auto[1] |
auto[0] |
102 |
1 |
|
|
T1 |
12 |
|
T2 |
6 |
|
T112 |
6 |
| auto[1] |
auto[1] |
85 |
1 |
|
|
T1 |
3 |
|
T2 |
10 |
|
T112 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
77 |
1 |
|
|
T2 |
6 |
|
T112 |
5 |
|
T114 |
3 |
| auto[0] |
auto[1] |
85 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T112 |
2 |
| auto[1] |
auto[0] |
100 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T112 |
6 |
| auto[1] |
auto[1] |
98 |
1 |
|
|
T1 |
6 |
|
T2 |
6 |
|
T112 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
88 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T112 |
5 |
| auto[0] |
auto[1] |
95 |
1 |
|
|
T1 |
8 |
|
T2 |
4 |
|
T112 |
10 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T1 |
3 |
|
T2 |
9 |
|
T112 |
2 |
| auto[1] |
auto[1] |
94 |
1 |
|
|
T1 |
7 |
|
T2 |
4 |
|
T112 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T112 |
4 |
| auto[0] |
auto[1] |
94 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T112 |
8 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T1 |
6 |
|
T2 |
3 |
|
T112 |
4 |
| auto[1] |
auto[1] |
106 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T112 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
95 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T112 |
5 |
| auto[0] |
auto[1] |
88 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T112 |
5 |
| auto[1] |
auto[0] |
88 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T112 |
4 |
| auto[1] |
auto[1] |
89 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T112 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
89 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T112 |
7 |
| auto[0] |
auto[1] |
98 |
1 |
|
|
T1 |
6 |
|
T2 |
6 |
|
T112 |
4 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T1 |
3 |
|
T2 |
6 |
|
T112 |
5 |
| auto[1] |
auto[1] |
95 |
1 |
|
|
T1 |
6 |
|
T2 |
3 |
|
T112 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
94 |
1 |
|
|
T1 |
6 |
|
T2 |
5 |
|
T112 |
7 |
| auto[0] |
auto[1] |
94 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T112 |
4 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T1 |
7 |
|
T2 |
5 |
|
T112 |
6 |
| auto[1] |
auto[1] |
89 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T112 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
194 |
1 |
|
|
T1 |
11 |
|
T2 |
14 |
|
T112 |
13 |
| auto[1] |
auto[1] |
166 |
1 |
|
|
T1 |
9 |
|
T2 |
6 |
|
T112 |
7 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
95 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T112 |
7 |
| auto[0] |
auto[1] |
84 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T112 |
5 |
| auto[1] |
auto[0] |
81 |
1 |
|
|
T1 |
6 |
|
T2 |
4 |
|
T112 |
2 |
| auto[1] |
auto[1] |
100 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T112 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
180 |
1 |
|
|
T1 |
9 |
|
T2 |
8 |
|
T112 |
6 |
| auto[1] |
auto[1] |
180 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T112 |
14 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T86 |
11 |
|
T116 |
9 |
|
T338 |
8 |
| auto[1] |
64 |
1 |
|
|
T86 |
9 |
|
T116 |
11 |
|
T338 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T86 |
9 |
|
T116 |
9 |
|
T338 |
12 |
| auto[1] |
61 |
1 |
|
|
T86 |
11 |
|
T116 |
11 |
|
T338 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T86 |
9 |
|
T116 |
9 |
|
T338 |
9 |
| auto[1] |
68 |
1 |
|
|
T86 |
11 |
|
T116 |
11 |
|
T338 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T86 |
9 |
|
T116 |
12 |
|
T338 |
12 |
| auto[1] |
61 |
1 |
|
|
T86 |
11 |
|
T116 |
8 |
|
T338 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
58 |
1 |
|
|
T86 |
9 |
|
T116 |
9 |
|
T338 |
10 |
| auto[1] |
62 |
1 |
|
|
T86 |
11 |
|
T116 |
11 |
|
T338 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T86 |
10 |
|
T116 |
11 |
|
T338 |
4 |
| auto[1] |
63 |
1 |
|
|
T86 |
10 |
|
T116 |
9 |
|
T338 |
16 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T86 |
5 |
|
T116 |
8 |
|
T338 |
8 |
| auto[1] |
73 |
1 |
|
|
T86 |
15 |
|
T116 |
12 |
|
T338 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T86 |
7 |
|
T116 |
10 |
|
T338 |
10 |
| auto[1] |
69 |
1 |
|
|
T86 |
13 |
|
T116 |
10 |
|
T338 |
10 |