Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_inXval
Uncovered bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_outXval
Uncovered bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_inXval
Uncovered bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_outXval
Uncovered bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_inXval
Uncovered bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_outXval
Uncovered bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_inXval
Uncovered bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_outXval
Uncovered bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for ac_presentXval
Uncovered bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Uncovered bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for lid_openXval
Uncovered bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Uncovered bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
746 |
1 |
|
|
T20 |
13 |
|
T21 |
13 |
|
T22 |
11 |
| auto[1] |
794 |
1 |
|
|
T20 |
7 |
|
T21 |
7 |
|
T22 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
758 |
1 |
|
|
T20 |
8 |
|
T21 |
9 |
|
T22 |
7 |
| auto[1] |
782 |
1 |
|
|
T20 |
12 |
|
T21 |
11 |
|
T22 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
734 |
1 |
|
|
T20 |
5 |
|
T21 |
8 |
|
T22 |
7 |
| auto[1] |
806 |
1 |
|
|
T20 |
15 |
|
T21 |
12 |
|
T22 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
777 |
1 |
|
|
T20 |
10 |
|
T21 |
11 |
|
T22 |
12 |
| auto[1] |
763 |
1 |
|
|
T20 |
10 |
|
T21 |
9 |
|
T22 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
758 |
1 |
|
|
T20 |
12 |
|
T21 |
11 |
|
T22 |
14 |
| auto[1] |
782 |
1 |
|
|
T20 |
8 |
|
T21 |
9 |
|
T22 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
753 |
1 |
|
|
T20 |
12 |
|
T21 |
11 |
|
T22 |
7 |
| auto[1] |
787 |
1 |
|
|
T20 |
8 |
|
T21 |
9 |
|
T22 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
794 |
1 |
|
|
T20 |
11 |
|
T21 |
8 |
|
T22 |
7 |
| auto[1] |
746 |
1 |
|
|
T20 |
9 |
|
T21 |
12 |
|
T22 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
775 |
1 |
|
|
T20 |
7 |
|
T21 |
10 |
|
T22 |
11 |
| auto[1] |
765 |
1 |
|
|
T20 |
13 |
|
T21 |
10 |
|
T22 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
785 |
1 |
|
|
T20 |
7 |
|
T21 |
8 |
|
T22 |
12 |
| auto[1] |
755 |
1 |
|
|
T20 |
13 |
|
T21 |
12 |
|
T22 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
740 |
1 |
|
|
T20 |
15 |
|
T21 |
10 |
|
T22 |
14 |
| auto[1] |
800 |
1 |
|
|
T20 |
5 |
|
T21 |
10 |
|
T22 |
6 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
804 |
1 |
|
|
T20 |
9 |
|
T21 |
8 |
|
T22 |
11 |
| auto[1] |
736 |
1 |
|
|
T20 |
11 |
|
T21 |
12 |
|
T22 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
755 |
1 |
|
|
T20 |
8 |
|
T21 |
9 |
|
T22 |
10 |
| auto[1] |
785 |
1 |
|
|
T20 |
12 |
|
T21 |
11 |
|
T22 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
781 |
1 |
|
|
T20 |
13 |
|
T21 |
14 |
|
T22 |
9 |
| auto[1] |
759 |
1 |
|
|
T20 |
7 |
|
T21 |
6 |
|
T22 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
758 |
1 |
|
|
T20 |
8 |
|
T21 |
9 |
|
T22 |
7 |
| auto[1] |
782 |
1 |
|
|
T20 |
12 |
|
T21 |
11 |
|
T22 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
739 |
1 |
|
|
T20 |
6 |
|
T21 |
9 |
|
T22 |
9 |
| auto[1] |
801 |
1 |
|
|
T20 |
14 |
|
T21 |
11 |
|
T22 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T20 |
15 |
|
T21 |
10 |
|
T22 |
8 |
| auto[1] |
768 |
1 |
|
|
T20 |
5 |
|
T21 |
10 |
|
T22 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
746 |
1 |
|
|
T20 |
9 |
|
T21 |
11 |
|
T22 |
6 |
| auto[1] |
794 |
1 |
|
|
T20 |
11 |
|
T21 |
9 |
|
T22 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
777 |
1 |
|
|
T20 |
11 |
|
T21 |
11 |
|
T22 |
7 |
| auto[1] |
763 |
1 |
|
|
T20 |
9 |
|
T21 |
9 |
|
T22 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T20 |
5 |
|
T21 |
14 |
|
T22 |
10 |
| auto[1] |
720 |
1 |
|
|
T20 |
15 |
|
T21 |
6 |
|
T22 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
753 |
1 |
|
|
T20 |
7 |
|
T21 |
12 |
|
T22 |
14 |
| auto[1] |
787 |
1 |
|
|
T20 |
13 |
|
T21 |
8 |
|
T22 |
6 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
778 |
1 |
|
|
T20 |
7 |
|
T21 |
9 |
|
T22 |
8 |
| auto[1] |
762 |
1 |
|
|
T20 |
13 |
|
T21 |
11 |
|
T22 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
797 |
1 |
|
|
T20 |
9 |
|
T21 |
12 |
|
T22 |
9 |
| auto[1] |
743 |
1 |
|
|
T20 |
11 |
|
T21 |
8 |
|
T22 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T20 |
11 |
|
T21 |
10 |
|
T22 |
8 |
| auto[1] |
753 |
1 |
|
|
T20 |
9 |
|
T21 |
10 |
|
T22 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
755 |
1 |
|
|
T20 |
8 |
|
T21 |
9 |
|
T22 |
10 |
| auto[1] |
785 |
1 |
|
|
T20 |
12 |
|
T21 |
11 |
|
T22 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
346 |
1 |
|
|
T20 |
3 |
|
T21 |
5 |
|
T22 |
2 |
| auto[0] |
auto[1] |
393 |
1 |
|
|
T20 |
3 |
|
T21 |
4 |
|
T22 |
7 |
| auto[1] |
auto[0] |
388 |
1 |
|
|
T20 |
2 |
|
T21 |
3 |
|
T22 |
5 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T20 |
12 |
|
T21 |
8 |
|
T22 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
384 |
1 |
|
|
T20 |
10 |
|
T21 |
7 |
|
T22 |
4 |
| auto[0] |
auto[1] |
388 |
1 |
|
|
T20 |
5 |
|
T21 |
3 |
|
T22 |
4 |
| auto[1] |
auto[0] |
393 |
1 |
|
|
T21 |
4 |
|
T22 |
8 |
|
T11 |
3 |
| auto[1] |
auto[1] |
375 |
1 |
|
|
T20 |
5 |
|
T21 |
6 |
|
T22 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
376 |
1 |
|
|
T20 |
7 |
|
T21 |
6 |
|
T22 |
6 |
| auto[0] |
auto[1] |
370 |
1 |
|
|
T20 |
2 |
|
T21 |
5 |
|
T11 |
1 |
| auto[1] |
auto[0] |
382 |
1 |
|
|
T20 |
5 |
|
T21 |
5 |
|
T22 |
8 |
| auto[1] |
auto[1] |
412 |
1 |
|
|
T20 |
6 |
|
T21 |
4 |
|
T22 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
389 |
1 |
|
|
T20 |
8 |
|
T21 |
6 |
|
T22 |
3 |
| auto[0] |
auto[1] |
388 |
1 |
|
|
T20 |
3 |
|
T21 |
5 |
|
T22 |
4 |
| auto[1] |
auto[0] |
364 |
1 |
|
|
T20 |
4 |
|
T21 |
5 |
|
T22 |
4 |
| auto[1] |
auto[1] |
399 |
1 |
|
|
T20 |
5 |
|
T21 |
4 |
|
T22 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T20 |
3 |
|
T21 |
5 |
|
T22 |
3 |
| auto[0] |
auto[1] |
387 |
1 |
|
|
T20 |
2 |
|
T21 |
9 |
|
T22 |
7 |
| auto[1] |
auto[0] |
361 |
1 |
|
|
T20 |
8 |
|
T21 |
3 |
|
T22 |
4 |
| auto[1] |
auto[1] |
359 |
1 |
|
|
T20 |
7 |
|
T21 |
3 |
|
T22 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
390 |
1 |
|
|
T20 |
2 |
|
T21 |
5 |
|
T22 |
7 |
| auto[0] |
auto[1] |
363 |
1 |
|
|
T20 |
5 |
|
T21 |
7 |
|
T22 |
7 |
| auto[1] |
auto[0] |
385 |
1 |
|
|
T20 |
5 |
|
T21 |
5 |
|
T22 |
4 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T20 |
8 |
|
T21 |
3 |
|
T22 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
368 |
1 |
|
|
T20 |
5 |
|
T21 |
7 |
|
T22 |
7 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T20 |
4 |
|
T21 |
5 |
|
T22 |
2 |
| auto[1] |
auto[0] |
372 |
1 |
|
|
T20 |
10 |
|
T21 |
3 |
|
T22 |
7 |
| auto[1] |
auto[1] |
371 |
1 |
|
|
T20 |
1 |
|
T21 |
5 |
|
T22 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
395 |
1 |
|
|
T20 |
3 |
|
T21 |
5 |
|
T22 |
5 |
| auto[0] |
auto[1] |
392 |
1 |
|
|
T20 |
8 |
|
T21 |
5 |
|
T22 |
3 |
| auto[1] |
auto[0] |
409 |
1 |
|
|
T20 |
6 |
|
T21 |
3 |
|
T22 |
6 |
| auto[1] |
auto[1] |
344 |
1 |
|
|
T20 |
3 |
|
T21 |
7 |
|
T22 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
363 |
1 |
|
|
T20 |
10 |
|
T21 |
8 |
|
T22 |
3 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T20 |
3 |
|
T21 |
6 |
|
T22 |
6 |
| auto[1] |
auto[0] |
383 |
1 |
|
|
T20 |
3 |
|
T21 |
5 |
|
T22 |
8 |
| auto[1] |
auto[1] |
376 |
1 |
|
|
T20 |
4 |
|
T21 |
1 |
|
T22 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
758 |
1 |
|
|
T20 |
8 |
|
T21 |
9 |
|
T22 |
7 |
| auto[1] |
auto[1] |
782 |
1 |
|
|
T20 |
12 |
|
T21 |
11 |
|
T22 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
374 |
1 |
|
|
T20 |
1 |
|
T21 |
3 |
|
T22 |
7 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T20 |
6 |
|
T21 |
6 |
|
T22 |
1 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T20 |
6 |
|
T21 |
5 |
|
T22 |
5 |
| auto[1] |
auto[1] |
351 |
1 |
|
|
T20 |
7 |
|
T21 |
6 |
|
T22 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
755 |
1 |
|
|
T20 |
8 |
|
T21 |
9 |
|
T22 |
10 |
| auto[1] |
auto[1] |
785 |
1 |
|
|
T20 |
12 |
|
T21 |
11 |
|
T22 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T11 |
11 |
|
T40 |
8 |
|
T42 |
6 |
| auto[1] |
115 |
1 |
|
|
T11 |
9 |
|
T40 |
12 |
|
T42 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T11 |
13 |
|
T40 |
8 |
|
T42 |
11 |
| auto[1] |
120 |
1 |
|
|
T11 |
7 |
|
T40 |
12 |
|
T42 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T11 |
10 |
|
T40 |
7 |
|
T42 |
12 |
| auto[1] |
126 |
1 |
|
|
T11 |
10 |
|
T40 |
13 |
|
T42 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T11 |
10 |
|
T40 |
7 |
|
T42 |
8 |
| auto[1] |
124 |
1 |
|
|
T11 |
10 |
|
T40 |
13 |
|
T42 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T11 |
9 |
|
T40 |
9 |
|
T42 |
14 |
| auto[1] |
117 |
1 |
|
|
T11 |
11 |
|
T40 |
11 |
|
T42 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T11 |
9 |
|
T40 |
5 |
|
T42 |
11 |
| auto[1] |
116 |
1 |
|
|
T11 |
11 |
|
T40 |
15 |
|
T42 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T11 |
8 |
|
T40 |
4 |
|
T42 |
11 |
| auto[1] |
120 |
1 |
|
|
T11 |
12 |
|
T40 |
16 |
|
T42 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T11 |
10 |
|
T40 |
12 |
|
T42 |
10 |
| auto[1] |
105 |
1 |
|
|
T11 |
10 |
|
T40 |
8 |
|
T42 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T11 |
10 |
|
T40 |
8 |
|
T42 |
6 |
| auto[1] |
119 |
1 |
|
|
T11 |
10 |
|
T40 |
12 |
|
T42 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T11 |
10 |
|
T40 |
10 |
|
T42 |
11 |
| auto[1] |
121 |
1 |
|
|
T11 |
10 |
|
T40 |
10 |
|
T42 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
105 |
1 |
|
|
T11 |
10 |
|
T40 |
10 |
|
T42 |
13 |
| auto[1] |
135 |
1 |
|
|
T11 |
10 |
|
T40 |
10 |
|
T42 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T11 |
7 |
|
T40 |
9 |
|
T42 |
11 |
| auto[1] |
124 |
1 |
|
|
T11 |
13 |
|
T40 |
11 |
|
T42 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T11 |
10 |
|
T40 |
14 |
|
T42 |
8 |
| auto[1] |
114 |
1 |
|
|
T11 |
10 |
|
T40 |
6 |
|
T42 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T11 |
13 |
|
T40 |
8 |
|
T42 |
11 |
| auto[1] |
120 |
1 |
|
|
T11 |
7 |
|
T40 |
12 |
|
T42 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T11 |
11 |
|
T40 |
12 |
|
T42 |
10 |
| auto[1] |
115 |
1 |
|
|
T11 |
9 |
|
T40 |
8 |
|
T42 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T11 |
11 |
|
T40 |
12 |
|
T42 |
10 |
| auto[1] |
105 |
1 |
|
|
T11 |
9 |
|
T40 |
8 |
|
T42 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T11 |
12 |
|
T40 |
10 |
|
T42 |
10 |
| auto[1] |
120 |
1 |
|
|
T11 |
8 |
|
T40 |
10 |
|
T42 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
105 |
1 |
|
|
T11 |
10 |
|
T40 |
6 |
|
T42 |
7 |
| auto[1] |
135 |
1 |
|
|
T11 |
10 |
|
T40 |
14 |
|
T42 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T11 |
10 |
|
T40 |
9 |
|
T42 |
11 |
| auto[1] |
108 |
1 |
|
|
T11 |
10 |
|
T40 |
11 |
|
T42 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T11 |
12 |
|
T40 |
11 |
|
T42 |
8 |
| auto[1] |
127 |
1 |
|
|
T11 |
8 |
|
T40 |
9 |
|
T42 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T11 |
8 |
|
T40 |
12 |
|
T42 |
8 |
| auto[1] |
113 |
1 |
|
|
T11 |
12 |
|
T40 |
8 |
|
T42 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T11 |
9 |
|
T40 |
8 |
|
T42 |
12 |
| auto[1] |
118 |
1 |
|
|
T11 |
11 |
|
T40 |
12 |
|
T42 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T11 |
7 |
|
T40 |
8 |
|
T42 |
8 |
| auto[1] |
128 |
1 |
|
|
T11 |
13 |
|
T40 |
12 |
|
T42 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T11 |
7 |
|
T40 |
9 |
|
T42 |
11 |
| auto[1] |
124 |
1 |
|
|
T11 |
13 |
|
T40 |
11 |
|
T42 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T11 |
5 |
|
T40 |
5 |
|
T42 |
7 |
| auto[0] |
auto[1] |
67 |
1 |
|
|
T11 |
6 |
|
T40 |
7 |
|
T42 |
3 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T11 |
5 |
|
T40 |
2 |
|
T42 |
5 |
| auto[1] |
auto[1] |
59 |
1 |
|
|
T11 |
4 |
|
T40 |
6 |
|
T42 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T11 |
5 |
|
T40 |
5 |
|
T42 |
5 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T11 |
6 |
|
T40 |
7 |
|
T42 |
5 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T11 |
5 |
|
T40 |
2 |
|
T42 |
3 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T11 |
4 |
|
T40 |
6 |
|
T42 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T11 |
5 |
|
T40 |
7 |
|
T42 |
7 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T11 |
7 |
|
T40 |
3 |
|
T42 |
3 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T11 |
4 |
|
T40 |
2 |
|
T42 |
7 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T11 |
4 |
|
T40 |
8 |
|
T42 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T11 |
4 |
|
T40 |
3 |
|
T42 |
4 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T11 |
6 |
|
T40 |
3 |
|
T42 |
3 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T11 |
5 |
|
T40 |
2 |
|
T42 |
7 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T11 |
5 |
|
T40 |
12 |
|
T42 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T11 |
5 |
|
T40 |
2 |
|
T42 |
5 |
| auto[0] |
auto[1] |
74 |
1 |
|
|
T11 |
5 |
|
T40 |
7 |
|
T42 |
6 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T11 |
3 |
|
T40 |
2 |
|
T42 |
6 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T11 |
7 |
|
T40 |
9 |
|
T42 |
3 |