Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T9 |
9 |
|
T20 |
9 |
|
T21 |
10 |
| auto[1] |
828 |
1 |
|
|
T9 |
11 |
|
T20 |
11 |
|
T21 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
797 |
1 |
|
|
T9 |
9 |
|
T20 |
9 |
|
T21 |
10 |
| auto[1] |
863 |
1 |
|
|
T9 |
11 |
|
T20 |
11 |
|
T21 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
767 |
1 |
|
|
T9 |
3 |
|
T20 |
9 |
|
T21 |
10 |
| auto[1] |
893 |
1 |
|
|
T9 |
17 |
|
T20 |
11 |
|
T21 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T9 |
11 |
|
T20 |
7 |
|
T21 |
6 |
| auto[1] |
811 |
1 |
|
|
T9 |
9 |
|
T20 |
13 |
|
T21 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T9 |
11 |
|
T20 |
13 |
|
T21 |
7 |
| auto[1] |
834 |
1 |
|
|
T9 |
9 |
|
T20 |
7 |
|
T21 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T9 |
14 |
|
T20 |
13 |
|
T21 |
7 |
| auto[1] |
837 |
1 |
|
|
T9 |
6 |
|
T20 |
7 |
|
T21 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T9 |
10 |
|
T20 |
4 |
|
T21 |
5 |
| auto[1] |
859 |
1 |
|
|
T9 |
10 |
|
T20 |
16 |
|
T21 |
15 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
822 |
1 |
|
|
T9 |
7 |
|
T20 |
11 |
|
T21 |
12 |
| auto[1] |
838 |
1 |
|
|
T9 |
13 |
|
T20 |
9 |
|
T21 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
838 |
1 |
|
|
T9 |
9 |
|
T20 |
7 |
|
T21 |
7 |
| auto[1] |
822 |
1 |
|
|
T9 |
11 |
|
T20 |
13 |
|
T21 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
797 |
1 |
|
|
T9 |
10 |
|
T20 |
8 |
|
T21 |
8 |
| auto[1] |
863 |
1 |
|
|
T9 |
10 |
|
T20 |
12 |
|
T21 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
852 |
1 |
|
|
T9 |
6 |
|
T20 |
10 |
|
T21 |
10 |
| auto[1] |
808 |
1 |
|
|
T9 |
14 |
|
T20 |
10 |
|
T21 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T9 |
11 |
|
T20 |
9 |
|
T21 |
10 |
| auto[1] |
798 |
1 |
|
|
T9 |
9 |
|
T20 |
11 |
|
T21 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
796 |
1 |
|
|
T9 |
10 |
|
T20 |
10 |
|
T21 |
11 |
| auto[1] |
864 |
1 |
|
|
T9 |
10 |
|
T20 |
10 |
|
T21 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
797 |
1 |
|
|
T9 |
9 |
|
T20 |
9 |
|
T21 |
10 |
| auto[1] |
863 |
1 |
|
|
T9 |
11 |
|
T20 |
11 |
|
T21 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
846 |
1 |
|
|
T9 |
6 |
|
T20 |
14 |
|
T21 |
9 |
| auto[1] |
814 |
1 |
|
|
T9 |
14 |
|
T20 |
6 |
|
T21 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T9 |
12 |
|
T20 |
10 |
|
T21 |
9 |
| auto[1] |
828 |
1 |
|
|
T9 |
8 |
|
T20 |
10 |
|
T21 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T9 |
13 |
|
T20 |
15 |
|
T21 |
10 |
| auto[1] |
829 |
1 |
|
|
T9 |
7 |
|
T20 |
5 |
|
T21 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
864 |
1 |
|
|
T9 |
8 |
|
T20 |
11 |
|
T21 |
8 |
| auto[1] |
796 |
1 |
|
|
T9 |
12 |
|
T20 |
9 |
|
T21 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T9 |
8 |
|
T20 |
10 |
|
T21 |
9 |
| auto[1] |
794 |
1 |
|
|
T9 |
12 |
|
T20 |
10 |
|
T21 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T9 |
9 |
|
T20 |
11 |
|
T21 |
10 |
| auto[1] |
831 |
1 |
|
|
T9 |
11 |
|
T20 |
9 |
|
T21 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
850 |
1 |
|
|
T9 |
13 |
|
T20 |
12 |
|
T21 |
9 |
| auto[1] |
810 |
1 |
|
|
T9 |
7 |
|
T20 |
8 |
|
T21 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T9 |
12 |
|
T20 |
13 |
|
T21 |
5 |
| auto[1] |
815 |
1 |
|
|
T9 |
8 |
|
T20 |
7 |
|
T21 |
15 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T9 |
10 |
|
T20 |
13 |
|
T21 |
7 |
| auto[1] |
834 |
1 |
|
|
T9 |
10 |
|
T20 |
7 |
|
T21 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T9 |
11 |
|
T20 |
9 |
|
T21 |
10 |
| auto[1] |
798 |
1 |
|
|
T9 |
9 |
|
T20 |
11 |
|
T21 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
385 |
1 |
|
|
T20 |
8 |
|
T21 |
4 |
|
T58 |
9 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T9 |
6 |
|
T20 |
6 |
|
T21 |
5 |
| auto[1] |
auto[0] |
382 |
1 |
|
|
T9 |
3 |
|
T20 |
1 |
|
T21 |
6 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T9 |
11 |
|
T20 |
5 |
|
T21 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T9 |
7 |
|
T20 |
5 |
|
T21 |
2 |
| auto[0] |
auto[1] |
413 |
1 |
|
|
T9 |
5 |
|
T20 |
5 |
|
T21 |
7 |
| auto[1] |
auto[0] |
430 |
1 |
|
|
T9 |
4 |
|
T20 |
2 |
|
T21 |
4 |
| auto[1] |
auto[1] |
398 |
1 |
|
|
T9 |
4 |
|
T20 |
8 |
|
T21 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
420 |
1 |
|
|
T9 |
6 |
|
T20 |
10 |
|
T21 |
5 |
| auto[0] |
auto[1] |
411 |
1 |
|
|
T9 |
7 |
|
T20 |
5 |
|
T21 |
5 |
| auto[1] |
auto[0] |
406 |
1 |
|
|
T9 |
5 |
|
T20 |
3 |
|
T21 |
2 |
| auto[1] |
auto[1] |
423 |
1 |
|
|
T9 |
2 |
|
T20 |
2 |
|
T21 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
435 |
1 |
|
|
T9 |
5 |
|
T20 |
8 |
|
T21 |
4 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T9 |
3 |
|
T20 |
3 |
|
T21 |
4 |
| auto[1] |
auto[0] |
388 |
1 |
|
|
T9 |
9 |
|
T20 |
5 |
|
T21 |
3 |
| auto[1] |
auto[1] |
408 |
1 |
|
|
T9 |
3 |
|
T20 |
4 |
|
T21 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
405 |
1 |
|
|
T9 |
5 |
|
T21 |
2 |
|
T58 |
6 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T9 |
3 |
|
T20 |
10 |
|
T21 |
7 |
| auto[1] |
auto[0] |
396 |
1 |
|
|
T9 |
5 |
|
T20 |
4 |
|
T21 |
3 |
| auto[1] |
auto[1] |
398 |
1 |
|
|
T9 |
7 |
|
T20 |
6 |
|
T21 |
8 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
397 |
1 |
|
|
T9 |
4 |
|
T20 |
4 |
|
T21 |
6 |
| auto[0] |
auto[1] |
432 |
1 |
|
|
T9 |
5 |
|
T20 |
7 |
|
T21 |
4 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T9 |
3 |
|
T20 |
7 |
|
T21 |
6 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T9 |
8 |
|
T20 |
2 |
|
T21 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
394 |
1 |
|
|
T9 |
6 |
|
T20 |
6 |
|
T21 |
1 |
| auto[0] |
auto[1] |
451 |
1 |
|
|
T9 |
6 |
|
T20 |
7 |
|
T21 |
4 |
| auto[1] |
auto[0] |
403 |
1 |
|
|
T9 |
4 |
|
T20 |
2 |
|
T21 |
7 |
| auto[1] |
auto[1] |
412 |
1 |
|
|
T9 |
4 |
|
T20 |
5 |
|
T21 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
412 |
1 |
|
|
T9 |
3 |
|
T20 |
7 |
|
T21 |
3 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T9 |
7 |
|
T20 |
6 |
|
T21 |
4 |
| auto[1] |
auto[0] |
440 |
1 |
|
|
T9 |
3 |
|
T20 |
3 |
|
T21 |
7 |
| auto[1] |
auto[1] |
394 |
1 |
|
|
T9 |
7 |
|
T20 |
4 |
|
T21 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
393 |
1 |
|
|
T9 |
4 |
|
T20 |
4 |
|
T21 |
3 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T9 |
6 |
|
T20 |
6 |
|
T21 |
8 |
| auto[1] |
auto[0] |
439 |
1 |
|
|
T9 |
5 |
|
T20 |
5 |
|
T21 |
7 |
| auto[1] |
auto[1] |
425 |
1 |
|
|
T9 |
5 |
|
T20 |
5 |
|
T21 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
797 |
1 |
|
|
T9 |
9 |
|
T20 |
9 |
|
T21 |
10 |
| auto[1] |
auto[1] |
863 |
1 |
|
|
T9 |
11 |
|
T20 |
11 |
|
T21 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T9 |
6 |
|
T20 |
3 |
|
T21 |
4 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T9 |
7 |
|
T20 |
9 |
|
T21 |
5 |
| auto[1] |
auto[0] |
422 |
1 |
|
|
T9 |
3 |
|
T20 |
4 |
|
T21 |
3 |
| auto[1] |
auto[1] |
388 |
1 |
|
|
T9 |
4 |
|
T20 |
4 |
|
T21 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
862 |
1 |
|
|
T9 |
11 |
|
T20 |
9 |
|
T21 |
10 |
| auto[1] |
auto[1] |
798 |
1 |
|
|
T9 |
9 |
|
T20 |
11 |
|
T21 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
98 |
1 |
|
|
T9 |
9 |
|
T37 |
9 |
|
T296 |
10 |
| auto[1] |
102 |
1 |
|
|
T9 |
11 |
|
T37 |
11 |
|
T296 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T9 |
13 |
|
T37 |
11 |
|
T296 |
14 |
| auto[1] |
87 |
1 |
|
|
T9 |
7 |
|
T37 |
9 |
|
T296 |
6 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T9 |
13 |
|
T37 |
14 |
|
T296 |
10 |
| auto[1] |
101 |
1 |
|
|
T9 |
7 |
|
T37 |
6 |
|
T296 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T9 |
15 |
|
T37 |
12 |
|
T296 |
5 |
| auto[1] |
97 |
1 |
|
|
T9 |
5 |
|
T37 |
8 |
|
T296 |
15 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
96 |
1 |
|
|
T9 |
6 |
|
T37 |
11 |
|
T296 |
9 |
| auto[1] |
104 |
1 |
|
|
T9 |
14 |
|
T37 |
9 |
|
T296 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T9 |
12 |
|
T37 |
12 |
|
T296 |
14 |
| auto[1] |
90 |
1 |
|
|
T9 |
8 |
|
T37 |
8 |
|
T296 |
6 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
87 |
1 |
|
|
T9 |
9 |
|
T37 |
10 |
|
T296 |
9 |
| auto[1] |
113 |
1 |
|
|
T9 |
11 |
|
T37 |
10 |
|
T296 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T9 |
8 |
|
T37 |
10 |
|
T296 |
10 |
| auto[1] |
96 |
1 |
|
|
T9 |
12 |
|
T37 |
10 |
|
T296 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T9 |
11 |
|
T37 |
13 |
|
T296 |
15 |
| auto[1] |
86 |
1 |
|
|
T9 |
9 |
|
T37 |
7 |
|
T296 |
5 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T9 |
10 |
|
T37 |
10 |
|
T296 |
10 |
| auto[1] |
99 |
1 |
|
|
T9 |
10 |
|
T37 |
10 |
|
T296 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T9 |
10 |
|
T37 |
6 |
|
T296 |
17 |
| auto[1] |
101 |
1 |
|
|
T9 |
10 |
|
T37 |
14 |
|
T296 |
3 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T9 |
10 |
|
T37 |
8 |
|
T296 |
11 |
| auto[1] |
97 |
1 |
|
|
T9 |
10 |
|
T37 |
12 |
|
T296 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T9 |
13 |
|
T37 |
16 |
|
T296 |
13 |
| auto[1] |
82 |
1 |
|
|
T9 |
7 |
|
T37 |
4 |
|
T296 |
7 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T9 |
13 |
|
T37 |
11 |
|
T296 |
14 |
| auto[1] |
87 |
1 |
|
|
T9 |
7 |
|
T37 |
9 |
|
T296 |
6 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
93 |
1 |
|
|
T9 |
10 |
|
T37 |
10 |
|
T296 |
10 |
| auto[1] |
107 |
1 |
|
|
T9 |
10 |
|
T37 |
10 |
|
T296 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T9 |
10 |
|
T37 |
10 |
|
T296 |
9 |
| auto[1] |
109 |
1 |
|
|
T9 |
10 |
|
T37 |
10 |
|
T296 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T9 |
7 |
|
T37 |
13 |
|
T296 |
13 |
| auto[1] |
92 |
1 |
|
|
T9 |
13 |
|
T37 |
7 |
|
T296 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
102 |
1 |
|
|
T9 |
9 |
|
T37 |
12 |
|
T296 |
10 |
| auto[1] |
98 |
1 |
|
|
T9 |
11 |
|
T37 |
8 |
|
T296 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T9 |
12 |
|
T37 |
6 |
|
T296 |
7 |
| auto[1] |
96 |
1 |
|
|
T9 |
8 |
|
T37 |
14 |
|
T296 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T9 |
7 |
|
T37 |
10 |
|
T296 |
12 |
| auto[1] |
109 |
1 |
|
|
T9 |
13 |
|
T37 |
10 |
|
T296 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T9 |
8 |
|
T37 |
10 |
|
T296 |
6 |
| auto[1] |
100 |
1 |
|
|
T9 |
12 |
|
T37 |
10 |
|
T296 |
14 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
106 |
1 |
|
|
T9 |
8 |
|
T37 |
11 |
|
T296 |
11 |
| auto[1] |
94 |
1 |
|
|
T9 |
12 |
|
T37 |
9 |
|
T296 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
96 |
1 |
|
|
T9 |
8 |
|
T37 |
11 |
|
T296 |
10 |
| auto[1] |
104 |
1 |
|
|
T9 |
12 |
|
T37 |
9 |
|
T296 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T9 |
10 |
|
T37 |
8 |
|
T296 |
11 |
| auto[1] |
97 |
1 |
|
|
T9 |
10 |
|
T37 |
12 |
|
T296 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T9 |
7 |
|
T37 |
8 |
|
T296 |
5 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T9 |
3 |
|
T37 |
2 |
|
T296 |
5 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T9 |
6 |
|
T37 |
6 |
|
T296 |
5 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T9 |
4 |
|
T37 |
4 |
|
T296 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
47 |
1 |
|
|
T9 |
8 |
|
T37 |
7 |
|
T296 |
2 |
| auto[0] |
auto[1] |
44 |
1 |
|
|
T9 |
2 |
|
T37 |
3 |
|
T296 |
7 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T9 |
7 |
|
T37 |
5 |
|
T296 |
3 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T9 |
3 |
|
T37 |
5 |
|
T296 |
8 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
49 |
1 |
|
|
T9 |
4 |
|
T37 |
7 |
|
T296 |
7 |
| auto[0] |
auto[1] |
59 |
1 |
|
|
T9 |
3 |
|
T37 |
6 |
|
T296 |
6 |
| auto[1] |
auto[0] |
47 |
1 |
|
|
T9 |
2 |
|
T37 |
4 |
|
T296 |
2 |
| auto[1] |
auto[1] |
45 |
1 |
|
|
T9 |
11 |
|
T37 |
3 |
|
T296 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T9 |
8 |
|
T37 |
7 |
|
T296 |
8 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T9 |
1 |
|
T37 |
5 |
|
T296 |
2 |
| auto[1] |
auto[0] |
57 |
1 |
|
|
T9 |
4 |
|
T37 |
5 |
|
T296 |
6 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T9 |
7 |
|
T37 |
3 |
|
T296 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T9 |
6 |
|
T37 |
2 |
|
T296 |
2 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T9 |
6 |
|
T37 |
4 |
|
T296 |
5 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T9 |
3 |
|
T37 |
8 |
|
T296 |
7 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T9 |
5 |
|
T37 |
6 |
|
T296 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
41 |
1 |
|
|
T9 |
3 |
|
T37 |
4 |
|
T296 |
5 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T9 |
4 |
|
T37 |
6 |
|
T296 |
7 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T9 |
5 |
|
T37 |
6 |
|
T296 |
5 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T9 |
8 |
|
T37 |
4 |
|
T296 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
55 |
1 |
|
|
T9 |
5 |
|
T37 |
5 |
|
T296 |
5 |
| auto[0] |
auto[1] |
51 |
1 |
|
|
T9 |
3 |
|
T37 |
6 |
|
T296 |
6 |
| auto[1] |
auto[0] |
46 |
1 |
|
|
T9 |
5 |
|
T37 |
5 |
|
T296 |
5 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T9 |
7 |
|
T37 |
4 |
|
T296 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
49 |
1 |
|
|
T9 |
5 |
|
T37 |
3 |
|
T296 |
8 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T9 |
3 |
|
T37 |
8 |
|
T296 |
2 |
| auto[1] |
auto[0] |
50 |
1 |
|
|
T9 |
5 |
|
T37 |
3 |
|
T296 |
9 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T9 |
7 |
|
T37 |
6 |
|
T296 |
1 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T9 |
6 |
|
T37 |
7 |
|
T296 |
6 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T9 |
7 |
|
T37 |
9 |
|
T296 |
7 |
| auto[1] |
auto[0] |
35 |
1 |
|
|
T9 |
3 |
|
T37 |
2 |
|
T296 |
4 |
| auto[1] |
auto[1] |
47 |
1 |
|
|
T9 |
4 |
|
T37 |
2 |
|
T296 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
113 |
1 |
|
|
T9 |
13 |
|
T37 |
11 |
|
T296 |
14 |
| auto[1] |
auto[1] |
87 |
1 |
|
|
T9 |
7 |
|
T37 |
9 |
|
T296 |
6 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T9 |
5 |
|
T37 |
8 |
|
T296 |
4 |
| auto[0] |
auto[1] |
38 |
1 |
|
|
T9 |
3 |
|
T37 |
2 |
|
T296 |
2 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T9 |
6 |
|
T37 |
5 |
|
T296 |
11 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T9 |
6 |
|
T37 |
5 |
|
T296 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T9 |
10 |
|
T37 |
8 |
|
T296 |
11 |
| auto[1] |
auto[1] |
97 |
1 |
|
|
T9 |
10 |
|
T37 |
12 |
|
T296 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T9 |
13 |
|
T37 |
15 |
|
T95 |
9 |
| auto[1] |
64 |
1 |
|
|
T9 |
7 |
|
T37 |
5 |
|
T95 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T9 |
11 |
|
T37 |
7 |
|
T95 |
11 |
| auto[1] |
69 |
1 |
|
|
T9 |
9 |
|
T37 |
13 |
|
T95 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
67 |
1 |
|
|
T9 |
10 |
|
T37 |
10 |
|
T95 |
9 |
| auto[1] |
73 |
1 |
|
|
T9 |
10 |
|
T37 |
10 |
|
T95 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T9 |
10 |
|
T37 |
11 |
|
T95 |
7 |
| auto[1] |
74 |
1 |
|
|
T9 |
10 |
|
T37 |
9 |
|
T95 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T9 |
9 |
|
T37 |
11 |
|
T95 |
10 |
| auto[1] |
69 |
1 |
|
|
T9 |
11 |
|
T37 |
9 |
|
T95 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T9 |
12 |
|
T37 |
11 |
|
T95 |
9 |
| auto[1] |
69 |
1 |
|
|
T9 |
8 |
|
T37 |
9 |
|
T95 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69 |
1 |
|
|
T9 |
11 |
|
T37 |
11 |
|
T95 |
10 |
| auto[1] |
71 |
1 |
|
|
T9 |
9 |
|
T37 |
9 |
|
T95 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
72 |
1 |
|
|
T9 |
10 |
|
T37 |
11 |
|
T95 |
10 |
| auto[1] |
68 |
1 |
|
|
T9 |
10 |
|
T37 |
9 |
|
T95 |
10 |