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Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_outcfg.vif.key2_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 45 1 T131 6 T105 7 T397 4
auto[0] auto[1] 38 1 T131 7 T105 6 T397 5
auto[1] auto[0] 36 1 T131 5 T105 4 T397 5
auto[1] auto[1] 41 1 T131 2 T105 3 T397 6


Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_incfg.vif.pwrb_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 33 1 T131 3 T105 5 T397 6
auto[0] auto[1] 37 1 T131 4 T105 6 T397 5
auto[1] auto[0] 43 1 T131 4 T105 5 T397 4
auto[1] auto[1] 47 1 T131 9 T105 4 T397 5


Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_outcfg.vif.pwrb_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 40 1 T131 5 T105 5 T397 8
auto[0] auto[1] 41 1 T131 4 T105 2 T397 5
auto[1] auto[0] 39 1 T131 4 T105 9 T397 4
auto[1] auto[1] 40 1 T131 7 T105 4 T397 3


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_presentcfg.vif.ac_presentCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 35 1 T131 7 T105 4 T397 2
auto[0] auto[1] 51 1 T131 7 T105 6 T397 4
auto[1] auto[0] 40 1 T131 6 T105 3 T397 9
auto[1] auto[1] 34 1 T105 7 T397 5 T141 5


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disablecfg.vif.bat_disableCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 75 1 T131 8 T105 10 T397 10
auto[1] auto[1] 85 1 T131 12 T105 10 T397 10


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_opencfg.vif.lid_openCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 39 1 T131 3 T105 6 T397 7
auto[0] auto[1] 45 1 T131 6 T105 6 T397 6
auto[1] auto[0] 44 1 T131 7 T105 4 T397 5
auto[1] auto[1] 32 1 T131 4 T105 4 T397 2


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeupcfg.vif.z3_wakeupCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 70 1 T131 11 T105 9 T397 11
auto[1] auto[1] 90 1 T131 9 T105 11 T397 9


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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