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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 99.40 96.83 100.00 97.44 98.89 99.61 88.52


Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T37 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1507523726 Jul 20 04:55:09 PM PDT 24 Jul 20 04:55:16 PM PDT 24 2131805063 ps
T38 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1773779323 Jul 20 04:54:24 PM PDT 24 Jul 20 04:54:27 PM PDT 24 2088775748 ps
T795 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2790017359 Jul 20 04:55:33 PM PDT 24 Jul 20 04:55:39 PM PDT 24 2012915271 ps
T39 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1144157412 Jul 20 04:54:21 PM PDT 24 Jul 20 04:54:27 PM PDT 24 2065863495 ps
T281 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1353040034 Jul 20 04:54:29 PM PDT 24 Jul 20 04:54:53 PM PDT 24 22272294307 ps
T796 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1415360612 Jul 20 04:54:21 PM PDT 24 Jul 20 04:54:24 PM PDT 24 2036435488 ps
T286 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3665940696 Jul 20 04:54:39 PM PDT 24 Jul 20 04:54:41 PM PDT 24 2151525087 ps
T287 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3586820223 Jul 20 04:55:00 PM PDT 24 Jul 20 04:55:04 PM PDT 24 2083120803 ps
T283 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3400439252 Jul 20 04:55:00 PM PDT 24 Jul 20 04:55:57 PM PDT 24 22195127185 ps
T26 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1960163809 Jul 20 04:55:17 PM PDT 24 Jul 20 04:55:29 PM PDT 24 4821136618 ps
T797 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1538128671 Jul 20 04:55:08 PM PDT 24 Jul 20 04:55:14 PM PDT 24 2011211553 ps
T345 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2227919433 Jul 20 04:55:01 PM PDT 24 Jul 20 04:55:04 PM PDT 24 2056870809 ps
T798 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1249880945 Jul 20 04:54:14 PM PDT 24 Jul 20 04:54:20 PM PDT 24 2013969811 ps
T285 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098115413 Jul 20 04:54:55 PM PDT 24 Jul 20 04:54:57 PM PDT 24 2144851792 ps
T334 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3652116475 Jul 20 04:55:06 PM PDT 24 Jul 20 04:55:13 PM PDT 24 2028095629 ps
T799 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.598347628 Jul 20 04:54:14 PM PDT 24 Jul 20 04:54:17 PM PDT 24 2026865109 ps
T282 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.4049409565 Jul 20 04:53:57 PM PDT 24 Jul 20 04:54:03 PM PDT 24 2177283892 ps
T27 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3302823208 Jul 20 04:54:47 PM PDT 24 Jul 20 04:54:53 PM PDT 24 4850970273 ps
T335 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2611258272 Jul 20 04:54:15 PM PDT 24 Jul 20 04:54:21 PM PDT 24 2047153372 ps
T336 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2516029218 Jul 20 04:54:13 PM PDT 24 Jul 20 04:54:16 PM PDT 24 4065365694 ps
T288 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3343925235 Jul 20 04:55:08 PM PDT 24 Jul 20 04:55:16 PM PDT 24 2043221272 ps
T800 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.648824206 Jul 20 04:55:33 PM PDT 24 Jul 20 04:55:35 PM PDT 24 2031949453 ps
T801 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4279604161 Jul 20 04:55:01 PM PDT 24 Jul 20 04:55:07 PM PDT 24 2014938296 ps
T346 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2690661804 Jul 20 04:55:01 PM PDT 24 Jul 20 04:55:08 PM PDT 24 2025381483 ps
T348 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.4279367059 Jul 20 04:53:59 PM PDT 24 Jul 20 04:54:05 PM PDT 24 3162145406 ps
T393 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.946416568 Jul 20 04:54:46 PM PDT 24 Jul 20 04:54:53 PM PDT 24 2111458960 ps
T347 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1185030126 Jul 20 04:53:58 PM PDT 24 Jul 20 04:54:01 PM PDT 24 2101417142 ps
T337 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1699111756 Jul 20 04:54:05 PM PDT 24 Jul 20 04:54:59 PM PDT 24 37465567970 ps
T295 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098199031 Jul 20 04:54:54 PM PDT 24 Jul 20 04:55:01 PM PDT 24 2145723671 ps
T802 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3444482151 Jul 20 04:55:34 PM PDT 24 Jul 20 04:55:36 PM PDT 24 2044582743 ps
T803 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2661182923 Jul 20 04:55:34 PM PDT 24 Jul 20 04:55:35 PM PDT 24 2069666102 ps
T804 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1311788930 Jul 20 04:55:07 PM PDT 24 Jul 20 04:55:09 PM PDT 24 2032040618 ps
T392 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1275190718 Jul 20 04:54:12 PM PDT 24 Jul 20 04:55:28 PM PDT 24 39188821948 ps
T292 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.282076070 Jul 20 04:54:54 PM PDT 24 Jul 20 04:55:02 PM PDT 24 2043447363 ps
T338 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.903975198 Jul 20 04:54:52 PM PDT 24 Jul 20 04:54:55 PM PDT 24 2030285039 ps
T28 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2742541170 Jul 20 04:55:01 PM PDT 24 Jul 20 04:55:07 PM PDT 24 4601453752 ps
T289 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.737092505 Jul 20 04:54:45 PM PDT 24 Jul 20 04:54:50 PM PDT 24 2474104923 ps
T805 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.735014024 Jul 20 04:55:09 PM PDT 24 Jul 20 04:55:17 PM PDT 24 2027907994 ps
T284 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.804072042 Jul 20 04:53:58 PM PDT 24 Jul 20 04:54:44 PM PDT 24 22207313745 ps
T806 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2307175653 Jul 20 04:54:39 PM PDT 24 Jul 20 04:54:43 PM PDT 24 2021332997 ps
T807 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.708036971 Jul 20 04:54:46 PM PDT 24 Jul 20 04:54:53 PM PDT 24 2014271240 ps
T808 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.423375643 Jul 20 04:55:16 PM PDT 24 Jul 20 04:55:22 PM PDT 24 2018405174 ps
T290 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3172048938 Jul 20 04:54:44 PM PDT 24 Jul 20 04:54:48 PM PDT 24 2399222036 ps
T296 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.406452608 Jul 20 04:53:56 PM PDT 24 Jul 20 04:54:56 PM PDT 24 42538206564 ps
T809 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2323554361 Jul 20 04:54:54 PM PDT 24 Jul 20 04:54:56 PM PDT 24 2047120641 ps
T810 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.121767554 Jul 20 04:55:21 PM PDT 24 Jul 20 04:55:23 PM PDT 24 2047802539 ps
T811 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3281245062 Jul 20 04:54:27 PM PDT 24 Jul 20 04:54:30 PM PDT 24 2019404788 ps
T812 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3701472626 Jul 20 04:55:25 PM PDT 24 Jul 20 04:55:27 PM PDT 24 2032947527 ps
T813 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3895236739 Jul 20 04:55:06 PM PDT 24 Jul 20 04:55:12 PM PDT 24 2061543279 ps
T291 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2665899131 Jul 20 04:55:10 PM PDT 24 Jul 20 04:55:17 PM PDT 24 2024645001 ps
T339 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1157686923 Jul 20 04:53:52 PM PDT 24 Jul 20 04:56:59 PM PDT 24 75548820531 ps
T814 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3269058016 Jul 20 04:55:10 PM PDT 24 Jul 20 04:55:13 PM PDT 24 2032012319 ps
T815 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.837450022 Jul 20 04:55:23 PM PDT 24 Jul 20 04:55:29 PM PDT 24 2013009875 ps
T816 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.388300324 Jul 20 04:55:08 PM PDT 24 Jul 20 04:55:11 PM PDT 24 2136373698 ps
T817 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3750654280 Jul 20 04:54:39 PM PDT 24 Jul 20 04:54:46 PM PDT 24 2072896809 ps
T818 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3994920891 Jul 20 04:55:34 PM PDT 24 Jul 20 04:55:40 PM PDT 24 2014592497 ps
T819 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3281203432 Jul 20 04:55:00 PM PDT 24 Jul 20 04:55:18 PM PDT 24 4711771523 ps
T820 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3007424670 Jul 20 04:55:16 PM PDT 24 Jul 20 04:55:17 PM PDT 24 2092219330 ps
T821 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4035027132 Jul 20 04:53:57 PM PDT 24 Jul 20 04:54:03 PM PDT 24 2077586025 ps
T822 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2434554758 Jul 20 04:54:39 PM PDT 24 Jul 20 04:54:46 PM PDT 24 2148830829 ps
T391 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3690570532 Jul 20 04:55:10 PM PDT 24 Jul 20 04:57:04 PM PDT 24 42380860042 ps
T823 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3408680166 Jul 20 04:55:01 PM PDT 24 Jul 20 04:55:07 PM PDT 24 2014267636 ps
T297 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2576226806 Jul 20 04:54:46 PM PDT 24 Jul 20 04:55:45 PM PDT 24 42522560194 ps
T824 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.243295643 Jul 20 04:54:20 PM PDT 24 Jul 20 04:54:23 PM PDT 24 3082459457 ps
T825 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3486715786 Jul 20 04:55:35 PM PDT 24 Jul 20 04:55:37 PM PDT 24 2058909828 ps
T298 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1198879700 Jul 20 04:54:52 PM PDT 24 Jul 20 04:55:08 PM PDT 24 22300728762 ps
T826 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1842909188 Jul 20 04:54:53 PM PDT 24 Jul 20 04:55:05 PM PDT 24 4805319397 ps
T827 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.789828226 Jul 20 04:54:39 PM PDT 24 Jul 20 04:54:50 PM PDT 24 9989421352 ps
T293 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3866097177 Jul 20 04:54:44 PM PDT 24 Jul 20 04:54:47 PM PDT 24 2873897639 ps
T828 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3007637654 Jul 20 04:54:48 PM PDT 24 Jul 20 04:55:08 PM PDT 24 9289118331 ps
T340 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.4230490850 Jul 20 04:54:14 PM PDT 24 Jul 20 04:54:22 PM PDT 24 2118640199 ps
T341 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2103247326 Jul 20 04:53:52 PM PDT 24 Jul 20 04:54:02 PM PDT 24 4008617245 ps
T342 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3183457003 Jul 20 04:54:03 PM PDT 24 Jul 20 04:54:06 PM PDT 24 2057743553 ps
T829 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3832485269 Jul 20 04:54:22 PM PDT 24 Jul 20 04:54:29 PM PDT 24 4191276114 ps
T389 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.63697482 Jul 20 04:54:54 PM PDT 24 Jul 20 04:56:36 PM PDT 24 42406764111 ps
T830 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1501364409 Jul 20 04:55:00 PM PDT 24 Jul 20 04:55:07 PM PDT 24 2061028819 ps
T831 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3862778763 Jul 20 04:54:46 PM PDT 24 Jul 20 04:54:53 PM PDT 24 23805914971 ps
T832 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1932724745 Jul 20 04:54:39 PM PDT 24 Jul 20 04:55:35 PM PDT 24 42578847487 ps
T833 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2525357844 Jul 20 04:55:17 PM PDT 24 Jul 20 04:55:19 PM PDT 24 2039059701 ps
T834 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1411651689 Jul 20 04:55:35 PM PDT 24 Jul 20 04:55:38 PM PDT 24 2049431315 ps
T835 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4064598940 Jul 20 04:54:52 PM PDT 24 Jul 20 04:55:05 PM PDT 24 4977101872 ps
T836 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.519900138 Jul 20 04:53:58 PM PDT 24 Jul 20 04:54:05 PM PDT 24 2075954656 ps
T837 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1796296219 Jul 20 04:55:23 PM PDT 24 Jul 20 04:55:27 PM PDT 24 2023201511 ps
T343 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2964446122 Jul 20 04:53:51 PM PDT 24 Jul 20 04:53:53 PM PDT 24 2087228928 ps
T838 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2430696799 Jul 20 04:54:23 PM PDT 24 Jul 20 04:54:26 PM PDT 24 2149728519 ps
T839 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.4098535812 Jul 20 04:53:49 PM PDT 24 Jul 20 04:53:51 PM PDT 24 2088865823 ps
T840 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1819727400 Jul 20 04:53:59 PM PDT 24 Jul 20 04:54:06 PM PDT 24 2014022275 ps
T841 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2771657164 Jul 20 04:55:34 PM PDT 24 Jul 20 04:55:40 PM PDT 24 2012925503 ps
T842 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.697396406 Jul 20 04:54:43 PM PDT 24 Jul 20 04:54:47 PM PDT 24 2020746575 ps
T843 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3062259297 Jul 20 04:54:14 PM PDT 24 Jul 20 04:55:09 PM PDT 24 22182476397 ps
T844 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.864166218 Jul 20 04:55:09 PM PDT 24 Jul 20 04:55:13 PM PDT 24 2052852405 ps
T845 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1501289314 Jul 20 04:55:34 PM PDT 24 Jul 20 04:55:40 PM PDT 24 2014615459 ps
T846 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1448287359 Jul 20 04:54:13 PM PDT 24 Jul 20 04:54:15 PM PDT 24 2404810479 ps
T344 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.707646253 Jul 20 04:54:53 PM PDT 24 Jul 20 04:54:54 PM PDT 24 2146135498 ps
T847 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1459706532 Jul 20 04:54:47 PM PDT 24 Jul 20 04:56:34 PM PDT 24 42372432360 ps
T848 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2126168106 Jul 20 04:54:44 PM PDT 24 Jul 20 04:54:51 PM PDT 24 2047003866 ps
T849 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3461250895 Jul 20 04:54:38 PM PDT 24 Jul 20 04:54:53 PM PDT 24 5220845493 ps
T390 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3304472084 Jul 20 04:54:54 PM PDT 24 Jul 20 04:56:43 PM PDT 24 42368662140 ps
T294 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2261432818 Jul 20 04:54:52 PM PDT 24 Jul 20 04:54:56 PM PDT 24 2119930760 ps
T850 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2897825338 Jul 20 04:55:23 PM PDT 24 Jul 20 04:55:25 PM PDT 24 2034155357 ps
T851 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2346226742 Jul 20 04:55:16 PM PDT 24 Jul 20 04:55:19 PM PDT 24 2028629593 ps
T852 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2569940705 Jul 20 04:54:31 PM PDT 24 Jul 20 04:55:08 PM PDT 24 10157682575 ps
T853 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1157595086 Jul 20 04:53:59 PM PDT 24 Jul 20 04:54:17 PM PDT 24 6028769661 ps
T854 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2035561127 Jul 20 04:54:05 PM PDT 24 Jul 20 04:54:17 PM PDT 24 4010132847 ps
T855 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3423246245 Jul 20 04:55:24 PM PDT 24 Jul 20 04:55:29 PM PDT 24 2010864706 ps
T856 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.469950629 Jul 20 04:54:13 PM PDT 24 Jul 20 04:54:15 PM PDT 24 2052183854 ps
T857 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1984536325 Jul 20 04:54:05 PM PDT 24 Jul 20 04:54:07 PM PDT 24 2243780118 ps
T858 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3960480055 Jul 20 04:54:14 PM PDT 24 Jul 20 04:56:46 PM PDT 24 37324115583 ps
T859 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4181170188 Jul 20 04:55:17 PM PDT 24 Jul 20 04:55:21 PM PDT 24 2016366622 ps
T860 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1892302901 Jul 20 04:55:00 PM PDT 24 Jul 20 04:55:04 PM PDT 24 2112271247 ps
T861 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1301485500 Jul 20 04:53:59 PM PDT 24 Jul 20 04:54:04 PM PDT 24 4994048195 ps
T862 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3620447994 Jul 20 04:53:59 PM PDT 24 Jul 20 04:54:06 PM PDT 24 2011220320 ps
T863 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2581102611 Jul 20 04:54:54 PM PDT 24 Jul 20 04:55:00 PM PDT 24 2013556509 ps
T864 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1663292804 Jul 20 04:54:13 PM PDT 24 Jul 20 04:54:21 PM PDT 24 2110143909 ps
T865 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4037353523 Jul 20 04:53:50 PM PDT 24 Jul 20 04:55:44 PM PDT 24 42377919940 ps
T866 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3366839928 Jul 20 04:54:30 PM PDT 24 Jul 20 04:54:33 PM PDT 24 2157898957 ps
T867 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.521978675 Jul 20 04:54:22 PM PDT 24 Jul 20 04:54:33 PM PDT 24 4400265533 ps
T868 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.131160331 Jul 20 04:55:27 PM PDT 24 Jul 20 04:55:33 PM PDT 24 2043476810 ps
T869 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2546309314 Jul 20 04:55:09 PM PDT 24 Jul 20 04:55:41 PM PDT 24 7565037910 ps
T870 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1612269778 Jul 20 04:54:28 PM PDT 24 Jul 20 04:56:24 PM PDT 24 42468884534 ps
T871 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2603853159 Jul 20 04:54:20 PM PDT 24 Jul 20 04:54:25 PM PDT 24 2680353945 ps
T872 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1293224287 Jul 20 04:54:29 PM PDT 24 Jul 20 04:54:36 PM PDT 24 2070290446 ps
T873 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.74866172 Jul 20 04:54:13 PM PDT 24 Jul 20 04:54:21 PM PDT 24 6059411485 ps
T874 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3566692606 Jul 20 04:54:22 PM PDT 24 Jul 20 04:54:38 PM PDT 24 22275968499 ps
T875 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2728620361 Jul 20 04:54:38 PM PDT 24 Jul 20 04:54:40 PM PDT 24 2277846722 ps
T876 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.470859948 Jul 20 04:53:51 PM PDT 24 Jul 20 04:53:58 PM PDT 24 2064083712 ps
T877 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2271454351 Jul 20 04:55:10 PM PDT 24 Jul 20 04:55:25 PM PDT 24 22424976982 ps
T878 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.767241385 Jul 20 04:54:46 PM PDT 24 Jul 20 04:54:49 PM PDT 24 2026929779 ps
T879 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.886015176 Jul 20 04:54:47 PM PDT 24 Jul 20 04:54:55 PM PDT 24 2122736572 ps
T880 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1012462813 Jul 20 04:55:22 PM PDT 24 Jul 20 04:55:26 PM PDT 24 2030798109 ps
T881 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3929056062 Jul 20 04:54:46 PM PDT 24 Jul 20 04:54:48 PM PDT 24 2269664741 ps
T882 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.185733462 Jul 20 04:54:05 PM PDT 24 Jul 20 04:54:09 PM PDT 24 2558032800 ps
T883 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1947787035 Jul 20 04:54:45 PM PDT 24 Jul 20 04:54:47 PM PDT 24 2073503061 ps
T884 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3323291337 Jul 20 04:55:00 PM PDT 24 Jul 20 04:55:07 PM PDT 24 2030942094 ps
T885 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2215485390 Jul 20 04:55:22 PM PDT 24 Jul 20 04:55:29 PM PDT 24 2014183444 ps
T886 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3045556760 Jul 20 04:55:19 PM PDT 24 Jul 20 04:55:21 PM PDT 24 2035760267 ps
T887 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3307925108 Jul 20 04:55:34 PM PDT 24 Jul 20 04:55:41 PM PDT 24 2011958180 ps
T888 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3730779821 Jul 20 04:55:32 PM PDT 24 Jul 20 04:55:38 PM PDT 24 2009236217 ps
T889 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.432252695 Jul 20 04:54:04 PM PDT 24 Jul 20 04:54:14 PM PDT 24 2902983812 ps
T890 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3209444026 Jul 20 04:53:59 PM PDT 24 Jul 20 04:54:06 PM PDT 24 7324927196 ps
T891 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.197257501 Jul 20 04:54:46 PM PDT 24 Jul 20 04:54:52 PM PDT 24 7766729048 ps
T892 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.596818233 Jul 20 04:54:44 PM PDT 24 Jul 20 04:54:48 PM PDT 24 2066746012 ps
T893 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3097213220 Jul 20 04:54:45 PM PDT 24 Jul 20 04:54:48 PM PDT 24 2105912158 ps
T894 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.4216502061 Jul 20 04:55:10 PM PDT 24 Jul 20 04:55:18 PM PDT 24 5212253289 ps
T895 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1211692971 Jul 20 04:55:00 PM PDT 24 Jul 20 04:55:05 PM PDT 24 4987069318 ps
T896 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.612865430 Jul 20 04:54:52 PM PDT 24 Jul 20 04:54:56 PM PDT 24 2046152117 ps
T897 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3977425888 Jul 20 04:53:57 PM PDT 24 Jul 20 04:54:08 PM PDT 24 2681161257 ps
T898 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1836188837 Jul 20 04:54:13 PM PDT 24 Jul 20 04:54:31 PM PDT 24 22267356637 ps
T899 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.542831272 Jul 20 04:54:29 PM PDT 24 Jul 20 04:54:32 PM PDT 24 2039793834 ps
T900 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.4187520674 Jul 20 04:54:20 PM PDT 24 Jul 20 04:54:24 PM PDT 24 2844397512 ps
T901 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2777647878 Jul 20 04:53:59 PM PDT 24 Jul 20 04:54:37 PM PDT 24 7615872602 ps
T902 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4102316796 Jul 20 04:55:16 PM PDT 24 Jul 20 04:55:18 PM PDT 24 2065647187 ps
T903 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3409906335 Jul 20 04:55:16 PM PDT 24 Jul 20 04:55:18 PM PDT 24 2030816098 ps
T904 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1910637253 Jul 20 04:55:25 PM PDT 24 Jul 20 04:55:28 PM PDT 24 2033504486 ps
T905 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2475231008 Jul 20 04:54:54 PM PDT 24 Jul 20 04:55:00 PM PDT 24 2010561951 ps
T906 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3626261677 Jul 20 04:54:13 PM PDT 24 Jul 20 04:54:31 PM PDT 24 8055672171 ps
T907 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.195592059 Jul 20 04:54:37 PM PDT 24 Jul 20 04:54:40 PM PDT 24 2114259245 ps
T908 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2138631528 Jul 20 04:54:30 PM PDT 24 Jul 20 04:54:33 PM PDT 24 2111283617 ps
T909 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.561993689 Jul 20 04:55:08 PM PDT 24 Jul 20 04:56:34 PM PDT 24 42442767033 ps
T910 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4064010497 Jul 20 04:53:57 PM PDT 24 Jul 20 04:54:01 PM PDT 24 4032183550 ps
T911 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3685516437 Jul 20 04:55:02 PM PDT 24 Jul 20 04:55:33 PM PDT 24 22336123181 ps
T912 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.30601404 Jul 20 04:55:00 PM PDT 24 Jul 20 04:55:03 PM PDT 24 2191281818 ps
T913 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4179718031 Jul 20 04:55:22 PM PDT 24 Jul 20 04:55:28 PM PDT 24 2015376868 ps
T914 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3203115882 Jul 20 04:54:05 PM PDT 24 Jul 20 04:54:30 PM PDT 24 7702756299 ps
T915 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.696744382 Jul 20 04:55:17 PM PDT 24 Jul 20 04:55:23 PM PDT 24 2012923285 ps

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2725892661
Short name T15
Test name
Test status
Simulation time 160900784813 ps
CPU time 435.94 seconds
Started Jul 20 04:43:15 PM PDT 24
Finished Jul 20 04:50:33 PM PDT 24
Peak memory 201816 kb
Host smart-0f610bdd-62db-476c-b5e0-2b2e63959826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725892661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.2725892661
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.2748786127
Short name T31
Test name
Test status
Simulation time 97245436114 ps
CPU time 136.05 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:43:43 PM PDT 24
Peak memory 201748 kb
Host smart-ba03b7a0-6ec1-4c47-b765-710c816c3178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748786127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.2748786127
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3470586558
Short name T131
Test name
Test status
Simulation time 1145399419236 ps
CPU time 452.13 seconds
Started Jul 20 04:41:15 PM PDT 24
Finished Jul 20 04:48:49 PM PDT 24
Peak memory 210216 kb
Host smart-9e0cebe5-5df2-46a8-a907-48e3e71c8999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470586558 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3470586558
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.3550399478
Short name T40
Test name
Test status
Simulation time 11807246158 ps
CPU time 26.71 seconds
Started Jul 20 04:42:54 PM PDT 24
Finished Jul 20 04:43:22 PM PDT 24
Peak memory 201460 kb
Host smart-e774fdd4-b74b-4331-b630-a5a9960e7a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550399478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.3550399478
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.2569879416
Short name T59
Test name
Test status
Simulation time 230579478031 ps
CPU time 168.69 seconds
Started Jul 20 04:41:32 PM PDT 24
Finished Jul 20 04:44:22 PM PDT 24
Peak memory 201704 kb
Host smart-f1c63e77-a32e-42c4-8468-b47efdfb2d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569879416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.2569879416
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1606165704
Short name T47
Test name
Test status
Simulation time 26133893502 ps
CPU time 62.24 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:43:46 PM PDT 24
Peak memory 209896 kb
Host smart-fb46b95f-259b-4980-beef-d94e4f35d0ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606165704 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1606165704
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2333393251
Short name T11
Test name
Test status
Simulation time 2826137658 ps
CPU time 6.84 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:42:50 PM PDT 24
Peak memory 201444 kb
Host smart-28927bc4-7b53-4107-b61e-5eda6b1614e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333393251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.2333393251
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4168501565
Short name T100
Test name
Test status
Simulation time 32046334349 ps
CPU time 21.31 seconds
Started Jul 20 04:41:06 PM PDT 24
Finished Jul 20 04:41:28 PM PDT 24
Peak memory 201544 kb
Host smart-49009b3f-79fb-4536-87cc-4c84ad02d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168501565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.4168501565
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3837402449
Short name T51
Test name
Test status
Simulation time 110501303469 ps
CPU time 46.12 seconds
Started Jul 20 04:43:11 PM PDT 24
Finished Jul 20 04:44:00 PM PDT 24
Peak memory 201880 kb
Host smart-7256e935-939d-47d6-8051-0190c2ad4bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837402449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.3837402449
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1353040034
Short name T281
Test name
Test status
Simulation time 22272294307 ps
CPU time 23.82 seconds
Started Jul 20 04:54:29 PM PDT 24
Finished Jul 20 04:54:53 PM PDT 24
Peak memory 202188 kb
Host smart-803595e6-07bf-4868-b46a-3e1b92005fba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353040034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.1353040034
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1909680885
Short name T107
Test name
Test status
Simulation time 81481655954 ps
CPU time 52.84 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:43:24 PM PDT 24
Peak memory 210128 kb
Host smart-71ec2d60-7b43-46d7-bf26-1f3d9a886c83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909680885 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.1909680885
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3474030734
Short name T129
Test name
Test status
Simulation time 251781363438 ps
CPU time 173.48 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:45:55 PM PDT 24
Peak memory 201724 kb
Host smart-84fd0539-7241-4577-af0f-290014324f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474030734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3474030734
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2286144992
Short name T19
Test name
Test status
Simulation time 2520130454 ps
CPU time 4.04 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201448 kb
Host smart-1cec7a2a-2174-460d-b0bc-974148838fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286144992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2286144992
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1203904619
Short name T85
Test name
Test status
Simulation time 163460192243 ps
CPU time 400.18 seconds
Started Jul 20 04:43:14 PM PDT 24
Finished Jul 20 04:49:57 PM PDT 24
Peak memory 201724 kb
Host smart-73526e41-c6f3-4f50-be4c-eb15c486bcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203904619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.1203904619
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1560980694
Short name T321
Test name
Test status
Simulation time 1441892664728 ps
CPU time 95.66 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:44:39 PM PDT 24
Peak memory 210164 kb
Host smart-3f8d4e27-5280-45e4-8272-f13e848ae733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560980694 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.1560980694
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.3543779850
Short name T97
Test name
Test status
Simulation time 22071882751 ps
CPU time 12.02 seconds
Started Jul 20 04:41:15 PM PDT 24
Finished Jul 20 04:41:29 PM PDT 24
Peak memory 220700 kb
Host smart-032c8c2e-4d9b-422c-9a43-95e34b50e710
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543779850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.3543779850
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2723913179
Short name T102
Test name
Test status
Simulation time 5476881704 ps
CPU time 2.79 seconds
Started Jul 20 04:41:19 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201444 kb
Host smart-7e203991-2cda-4e01-b35e-f0e8e6db87d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723913179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2723913179
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.984955852
Short name T48
Test name
Test status
Simulation time 2738068101 ps
CPU time 6.58 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:26 PM PDT 24
Peak memory 201548 kb
Host smart-1e1c07e8-e65f-4cb5-acaf-408fbb6e7329
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984955852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl
_edge_detect.984955852
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2876203379
Short name T94
Test name
Test status
Simulation time 44687675633 ps
CPU time 118.58 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:44:02 PM PDT 24
Peak memory 210120 kb
Host smart-892a66d6-ba77-4ab7-a284-11afd1e7da86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876203379 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.2876203379
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.73911535
Short name T257
Test name
Test status
Simulation time 108325821030 ps
CPU time 108.3 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:43:41 PM PDT 24
Peak memory 201728 kb
Host smart-cedede98-7210-4055-bcde-8cce1dbc6c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73911535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_wit
h_pre_cond.73911535
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.4049409565
Short name T282
Test name
Test status
Simulation time 2177283892 ps
CPU time 4.76 seconds
Started Jul 20 04:53:57 PM PDT 24
Finished Jul 20 04:54:03 PM PDT 24
Peak memory 202180 kb
Host smart-caed6b0c-ddd5-496a-95ed-1352934be544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049409565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.4049409565
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.156753521
Short name T119
Test name
Test status
Simulation time 217427572578 ps
CPU time 29.59 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 212156 kb
Host smart-8b91c189-3af4-4de7-bb88-385b8bde7768
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156753521 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.156753521
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2556293967
Short name T254
Test name
Test status
Simulation time 72296834894 ps
CPU time 53.84 seconds
Started Jul 20 04:41:56 PM PDT 24
Finished Jul 20 04:42:51 PM PDT 24
Peak memory 201760 kb
Host smart-4928935c-88a4-49a7-bf5c-40bc83ea3273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556293967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.2556293967
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.2321721959
Short name T183
Test name
Test status
Simulation time 4967686893 ps
CPU time 9.23 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:10 PM PDT 24
Peak memory 201444 kb
Host smart-3b781a85-1aea-4b70-b90b-4521c06f093d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321721959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.2321721959
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3418349595
Short name T228
Test name
Test status
Simulation time 45191299989 ps
CPU time 111.49 seconds
Started Jul 20 04:42:16 PM PDT 24
Finished Jul 20 04:44:10 PM PDT 24
Peak memory 210020 kb
Host smart-8cf6a622-9a79-4f97-9cb2-8e151cd22c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418349595 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.3418349595
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1699111756
Short name T337
Test name
Test status
Simulation time 37465567970 ps
CPU time 53.04 seconds
Started Jul 20 04:54:05 PM PDT 24
Finished Jul 20 04:54:59 PM PDT 24
Peak memory 202180 kb
Host smart-36052f3f-0059-4e3c-83be-0cf28fe170cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699111756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.1699111756
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1661243771
Short name T137
Test name
Test status
Simulation time 78204582124 ps
CPU time 113.41 seconds
Started Jul 20 04:42:12 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 218192 kb
Host smart-99b42323-a730-466f-a097-e67ec39c5263
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661243771 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.1661243771
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.1814406421
Short name T208
Test name
Test status
Simulation time 3832399416 ps
CPU time 5.09 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:42:24 PM PDT 24
Peak memory 201468 kb
Host smart-20717857-d4c7-4c96-bb7f-ff73c8891f32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814406421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.1814406421
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1921841712
Short name T198
Test name
Test status
Simulation time 32935604203 ps
CPU time 75.01 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:43:38 PM PDT 24
Peak memory 211052 kb
Host smart-2ca2ae1c-dc81-4051-9964-1cef1013a55b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921841712 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.1921841712
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.4112702727
Short name T12
Test name
Test status
Simulation time 165279040656 ps
CPU time 129.96 seconds
Started Jul 20 04:42:23 PM PDT 24
Finished Jul 20 04:44:35 PM PDT 24
Peak memory 201588 kb
Host smart-6d5d901a-653b-439d-a93f-9b0ec1169150
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112702727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.4112702727
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.482786288
Short name T262
Test name
Test status
Simulation time 50188176654 ps
CPU time 129.32 seconds
Started Jul 20 04:42:49 PM PDT 24
Finished Jul 20 04:45:00 PM PDT 24
Peak memory 201812 kb
Host smart-9a35e693-7616-4f2b-927e-fa5dfe0c43c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482786288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_wi
th_pre_cond.482786288
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4048144438
Short name T379
Test name
Test status
Simulation time 92775628221 ps
CPU time 35.94 seconds
Started Jul 20 04:43:17 PM PDT 24
Finished Jul 20 04:43:54 PM PDT 24
Peak memory 201708 kb
Host smart-2b31c065-07ab-4528-84e8-0d11f650eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048144438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.4048144438
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3257709998
Short name T167
Test name
Test status
Simulation time 43756286558 ps
CPU time 32.61 seconds
Started Jul 20 04:42:44 PM PDT 24
Finished Jul 20 04:43:18 PM PDT 24
Peak memory 218196 kb
Host smart-02365686-3018-48c7-a8d9-8b1d9ac88cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257709998 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.3257709998
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3866097177
Short name T293
Test name
Test status
Simulation time 2873897639 ps
CPU time 2.61 seconds
Started Jul 20 04:54:44 PM PDT 24
Finished Jul 20 04:54:47 PM PDT 24
Peak memory 202072 kb
Host smart-de1b40c2-1ef6-4e18-b944-b3547feda43f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866097177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.3866097177
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3748688337
Short name T67
Test name
Test status
Simulation time 37987881551 ps
CPU time 101.6 seconds
Started Jul 20 04:41:06 PM PDT 24
Finished Jul 20 04:42:49 PM PDT 24
Peak memory 201568 kb
Host smart-35492db6-fa2a-4e35-98ef-735942c0816c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748688337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3748688337
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1960163809
Short name T26
Test name
Test status
Simulation time 4821136618 ps
CPU time 12.11 seconds
Started Jul 20 04:55:17 PM PDT 24
Finished Jul 20 04:55:29 PM PDT 24
Peak memory 202168 kb
Host smart-760ffe6b-388c-4b62-b01a-7d47cab8680e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960163809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.1960163809
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1557829891
Short name T350
Test name
Test status
Simulation time 147613537923 ps
CPU time 203.24 seconds
Started Jul 20 04:42:49 PM PDT 24
Finished Jul 20 04:46:14 PM PDT 24
Peak memory 201656 kb
Host smart-4dba2aa0-ffbb-4379-843e-3f5a8290eda6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557829891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1557829891
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.2904189665
Short name T25
Test name
Test status
Simulation time 2013545018 ps
CPU time 5.78 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 201460 kb
Host smart-86078609-5ac3-4b59-9caf-a96422223261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904189665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.2904189665
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1752356514
Short name T363
Test name
Test status
Simulation time 167350455591 ps
CPU time 216.6 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:44:56 PM PDT 24
Peak memory 201784 kb
Host smart-9b2c1f0f-ac95-45ee-8048-464c20dfb2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752356514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.1752356514
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3325766959
Short name T90
Test name
Test status
Simulation time 8155839423 ps
CPU time 2.59 seconds
Started Jul 20 04:41:50 PM PDT 24
Finished Jul 20 04:41:53 PM PDT 24
Peak memory 201364 kb
Host smart-349333a2-2d12-4530-ad43-23a1c9431743
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325766959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.3325766959
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1581954532
Short name T35
Test name
Test status
Simulation time 52717772834 ps
CPU time 138.48 seconds
Started Jul 20 04:43:15 PM PDT 24
Finished Jul 20 04:45:36 PM PDT 24
Peak memory 201532 kb
Host smart-17ee8b11-4351-40f2-b5d9-82a54172caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581954532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.1581954532
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.312945302
Short name T265
Test name
Test status
Simulation time 188568161941 ps
CPU time 96 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:43:04 PM PDT 24
Peak memory 218128 kb
Host smart-1bbc1c4d-03b9-4480-b4b5-494a382a9175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312945302 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.312945302
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.909780380
Short name T310
Test name
Test status
Simulation time 52870732800 ps
CPU time 137.42 seconds
Started Jul 20 04:42:56 PM PDT 24
Finished Jul 20 04:45:15 PM PDT 24
Peak memory 218308 kb
Host smart-c902ae1f-1916-444d-94c4-b60b10bfaed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909780380 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.909780380
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.63697482
Short name T389
Test name
Test status
Simulation time 42406764111 ps
CPU time 102.18 seconds
Started Jul 20 04:54:54 PM PDT 24
Finished Jul 20 04:56:36 PM PDT 24
Peak memory 202232 kb
Host smart-e55962ca-e496-4218-95db-2bc825582177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63697482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_tl_intg_err.63697482
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1199835450
Short name T365
Test name
Test status
Simulation time 77001952295 ps
CPU time 75.02 seconds
Started Jul 20 04:41:34 PM PDT 24
Finished Jul 20 04:42:50 PM PDT 24
Peak memory 201956 kb
Host smart-5953ac50-40e5-48c1-b608-a44d1eadc21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199835450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.1199835450
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1174299832
Short name T364
Test name
Test status
Simulation time 61625652760 ps
CPU time 28.18 seconds
Started Jul 20 04:42:43 PM PDT 24
Finished Jul 20 04:43:13 PM PDT 24
Peak memory 201660 kb
Host smart-258637b6-f77a-4446-9fbd-d7ab97f905df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174299832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.1174299832
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1026355902
Short name T56
Test name
Test status
Simulation time 3401028133 ps
CPU time 2.78 seconds
Started Jul 20 04:41:30 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 201428 kb
Host smart-bf689c7a-9d3d-4fe9-a348-ee3b6ff04e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026355902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.1
026355902
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1757128528
Short name T715
Test name
Test status
Simulation time 171162613678 ps
CPU time 211.2 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:45:23 PM PDT 24
Peak memory 201740 kb
Host smart-cd81f3ec-4721-49c0-9fe5-f1db71708d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757128528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1757128528
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3898663369
Short name T366
Test name
Test status
Simulation time 57472569463 ps
CPU time 140.64 seconds
Started Jul 20 04:42:02 PM PDT 24
Finished Jul 20 04:44:25 PM PDT 24
Peak memory 201792 kb
Host smart-07327b79-f0d4-4496-a330-4b3d7860ba70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898663369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.3898663369
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2575402151
Short name T370
Test name
Test status
Simulation time 157108902793 ps
CPU time 94.78 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:43:55 PM PDT 24
Peak memory 201812 kb
Host smart-4edb637a-60f7-4d3c-98cf-8885fdece44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575402151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.2575402151
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3059953791
Short name T362
Test name
Test status
Simulation time 152189587911 ps
CPU time 408.56 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:48:06 PM PDT 24
Peak memory 201860 kb
Host smart-c5fd79a3-0a8e-40b1-94cf-1fdb7ed8f128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059953791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3059953791
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.4225303898
Short name T316
Test name
Test status
Simulation time 130668654513 ps
CPU time 138.87 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:45:22 PM PDT 24
Peak memory 201664 kb
Host smart-d4aba6a7-930a-43c4-9d4f-068efd825edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225303898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.4225303898
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2378520502
Short name T199
Test name
Test status
Simulation time 88935655079 ps
CPU time 58.91 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:44:02 PM PDT 24
Peak memory 210192 kb
Host smart-15146fe4-f5ca-4780-a113-8c2c2e9af0b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378520502 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.2378520502
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1658667621
Short name T170
Test name
Test status
Simulation time 48057128525 ps
CPU time 30.17 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:42:22 PM PDT 24
Peak memory 217692 kb
Host smart-2a283071-5edf-4592-84b4-bf70528299e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658667621 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.1658667621
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2168358178
Short name T275
Test name
Test status
Simulation time 49998156188 ps
CPU time 64.32 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:43:53 PM PDT 24
Peak memory 201844 kb
Host smart-6a54105b-402e-4eb1-b6d4-c5412829388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168358178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2168358178
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3042885490
Short name T13
Test name
Test status
Simulation time 83777030343 ps
CPU time 223.83 seconds
Started Jul 20 04:41:29 PM PDT 24
Finished Jul 20 04:45:14 PM PDT 24
Peak memory 201672 kb
Host smart-b520e26c-7943-4f36-a6c7-9c483ab69708
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042885490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.3042885490
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.3924544088
Short name T7
Test name
Test status
Simulation time 114574730496 ps
CPU time 277.68 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:46:04 PM PDT 24
Peak memory 201728 kb
Host smart-4881c850-4960-402b-bcb8-8383b29e6d35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924544088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.3924544088
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2870055881
Short name T235
Test name
Test status
Simulation time 34076995154 ps
CPU time 47.11 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:42:41 PM PDT 24
Peak memory 201728 kb
Host smart-a7ba8105-dda8-4eff-b525-3b74964d6646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870055881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.2870055881
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2928745129
Short name T385
Test name
Test status
Simulation time 39954758393 ps
CPU time 9.8 seconds
Started Jul 20 04:43:05 PM PDT 24
Finished Jul 20 04:43:15 PM PDT 24
Peak memory 201752 kb
Host smart-5d4f1427-c07d-493e-a3b1-1a89098dc135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928745129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.2928745129
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3936509165
Short name T270
Test name
Test status
Simulation time 106641977553 ps
CPU time 148.69 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:43:46 PM PDT 24
Peak memory 201800 kb
Host smart-9f75272b-cae9-45b5-be29-62c3aedeee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936509165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.3936509165
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2554516573
Short name T372
Test name
Test status
Simulation time 100293359200 ps
CPU time 234.18 seconds
Started Jul 20 04:43:11 PM PDT 24
Finished Jul 20 04:47:08 PM PDT 24
Peak memory 201736 kb
Host smart-5e7b0efb-3e8d-4f59-b93d-94319cf34897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554516573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.2554516573
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1617769756
Short name T278
Test name
Test status
Simulation time 89218467081 ps
CPU time 47.13 seconds
Started Jul 20 04:43:18 PM PDT 24
Finished Jul 20 04:44:06 PM PDT 24
Peak memory 201820 kb
Host smart-b54dac10-9957-4b97-ac82-c973044fb629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617769756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.1617769756
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1067433557
Short name T384
Test name
Test status
Simulation time 127736837666 ps
CPU time 81.59 seconds
Started Jul 20 04:43:14 PM PDT 24
Finished Jul 20 04:44:38 PM PDT 24
Peak memory 201792 kb
Host smart-95e35d77-0aa6-423e-b19b-d23e32836197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067433557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.1067433557
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1684315540
Short name T276
Test name
Test status
Simulation time 36619995199 ps
CPU time 26.57 seconds
Started Jul 20 04:43:15 PM PDT 24
Finished Jul 20 04:43:44 PM PDT 24
Peak memory 201956 kb
Host smart-b62c3cb1-5045-4e85-81e4-3801b1746a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684315540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.1684315540
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.4152609869
Short name T358
Test name
Test status
Simulation time 43914198838 ps
CPU time 116.32 seconds
Started Jul 20 04:43:12 PM PDT 24
Finished Jul 20 04:45:11 PM PDT 24
Peak memory 201820 kb
Host smart-6beb4823-396c-433c-bb4b-8c425ff476b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152609869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.4152609869
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.3122370241
Short name T242
Test name
Test status
Simulation time 3530615739 ps
CPU time 2.29 seconds
Started Jul 20 04:41:41 PM PDT 24
Finished Jul 20 04:41:44 PM PDT 24
Peak memory 201500 kb
Host smart-66283913-04d0-4a4b-97f5-ed0f2729431e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122370241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.3122370241
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3122004659
Short name T196
Test name
Test status
Simulation time 75155961244 ps
CPU time 154.76 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:44:45 PM PDT 24
Peak memory 210020 kb
Host smart-9d75e494-9a1c-4238-ab41-112231a5cfa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122004659 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.3122004659
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.737092505
Short name T289
Test name
Test status
Simulation time 2474104923 ps
CPU time 4.01 seconds
Started Jul 20 04:54:45 PM PDT 24
Finished Jul 20 04:54:50 PM PDT 24
Peak memory 210388 kb
Host smart-da621044-045f-4309-8ecc-ea7fbe413475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737092505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_error
s.737092505
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.4279367059
Short name T348
Test name
Test status
Simulation time 3162145406 ps
CPU time 5.58 seconds
Started Jul 20 04:53:59 PM PDT 24
Finished Jul 20 04:54:05 PM PDT 24
Peak memory 202200 kb
Host smart-70a8de35-b147-4f39-844f-93fe50ebaf55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279367059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.4279367059
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1157686923
Short name T339
Test name
Test status
Simulation time 75548820531 ps
CPU time 186.64 seconds
Started Jul 20 04:53:52 PM PDT 24
Finished Jul 20 04:56:59 PM PDT 24
Peak memory 202088 kb
Host smart-2a63c42d-ba0f-42f8-9523-9a7fd036a7b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157686923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.1157686923
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2103247326
Short name T341
Test name
Test status
Simulation time 4008617245 ps
CPU time 9.9 seconds
Started Jul 20 04:53:52 PM PDT 24
Finished Jul 20 04:54:02 PM PDT 24
Peak memory 201960 kb
Host smart-e45ed0be-d4b6-43d8-a91b-43f79d5526f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103247326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.2103247326
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4035027132
Short name T821
Test name
Test status
Simulation time 2077586025 ps
CPU time 5.37 seconds
Started Jul 20 04:53:57 PM PDT 24
Finished Jul 20 04:54:03 PM PDT 24
Peak memory 202076 kb
Host smart-78120ba5-00fa-493f-890f-ea85f6964850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035027132 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4035027132
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2964446122
Short name T343
Test name
Test status
Simulation time 2087228928 ps
CPU time 2 seconds
Started Jul 20 04:53:51 PM PDT 24
Finished Jul 20 04:53:53 PM PDT 24
Peak memory 201824 kb
Host smart-534a36b2-cd2f-47b2-bd06-ef5a56823d99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964446122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.2964446122
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.4098535812
Short name T839
Test name
Test status
Simulation time 2088865823 ps
CPU time 1.1 seconds
Started Jul 20 04:53:49 PM PDT 24
Finished Jul 20 04:53:51 PM PDT 24
Peak memory 201776 kb
Host smart-43566562-95c1-4afd-98ad-9e9f76d363f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098535812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.4098535812
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3209444026
Short name T890
Test name
Test status
Simulation time 7324927196 ps
CPU time 6.11 seconds
Started Jul 20 04:53:59 PM PDT 24
Finished Jul 20 04:54:06 PM PDT 24
Peak memory 202180 kb
Host smart-885a439b-93e9-43f0-b5c6-34add6fa1e75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209444026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.3209444026
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.470859948
Short name T876
Test name
Test status
Simulation time 2064083712 ps
CPU time 6.45 seconds
Started Jul 20 04:53:51 PM PDT 24
Finished Jul 20 04:53:58 PM PDT 24
Peak memory 202140 kb
Host smart-0503e7ad-2e3e-4a46-9f60-7ef273fd52be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470859948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors
.470859948
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4037353523
Short name T865
Test name
Test status
Simulation time 42377919940 ps
CPU time 113.61 seconds
Started Jul 20 04:53:50 PM PDT 24
Finished Jul 20 04:55:44 PM PDT 24
Peak memory 202232 kb
Host smart-195889cd-d96c-4c69-96b1-0cbe6dd5dfcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037353523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.4037353523
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3977425888
Short name T897
Test name
Test status
Simulation time 2681161257 ps
CPU time 10.36 seconds
Started Jul 20 04:53:57 PM PDT 24
Finished Jul 20 04:54:08 PM PDT 24
Peak memory 202144 kb
Host smart-c588d764-900b-4f71-9c41-a2a31833d6fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977425888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.3977425888
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2777647878
Short name T901
Test name
Test status
Simulation time 7615872602 ps
CPU time 36.78 seconds
Started Jul 20 04:53:59 PM PDT 24
Finished Jul 20 04:54:37 PM PDT 24
Peak memory 202100 kb
Host smart-3aa76f80-85c9-4b46-a244-87c4396c177d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777647878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.2777647878
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1157595086
Short name T853
Test name
Test status
Simulation time 6028769661 ps
CPU time 17.16 seconds
Started Jul 20 04:53:59 PM PDT 24
Finished Jul 20 04:54:17 PM PDT 24
Peak memory 202008 kb
Host smart-ed160b26-179c-4c37-bcf8-bc801c8f3a97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157595086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.1157595086
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.519900138
Short name T836
Test name
Test status
Simulation time 2075954656 ps
CPU time 5.93 seconds
Started Jul 20 04:53:58 PM PDT 24
Finished Jul 20 04:54:05 PM PDT 24
Peak memory 201900 kb
Host smart-287e9eda-8f75-460e-abff-2fb0e23f2cad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519900138 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.519900138
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1185030126
Short name T347
Test name
Test status
Simulation time 2101417142 ps
CPU time 2.31 seconds
Started Jul 20 04:53:58 PM PDT 24
Finished Jul 20 04:54:01 PM PDT 24
Peak memory 201836 kb
Host smart-f61cf335-1dc4-4f3a-b89e-4b2b60ba528b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185030126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.1185030126
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1819727400
Short name T840
Test name
Test status
Simulation time 2014022275 ps
CPU time 6.06 seconds
Started Jul 20 04:53:59 PM PDT 24
Finished Jul 20 04:54:06 PM PDT 24
Peak memory 201668 kb
Host smart-c3e26044-2a76-4c34-b849-47c81736884b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819727400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1819727400
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1301485500
Short name T861
Test name
Test status
Simulation time 4994048195 ps
CPU time 4.13 seconds
Started Jul 20 04:53:59 PM PDT 24
Finished Jul 20 04:54:04 PM PDT 24
Peak memory 202216 kb
Host smart-ac98a821-8d97-40f0-8622-4769b857d449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301485500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.1301485500
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.406452608
Short name T296
Test name
Test status
Simulation time 42538206564 ps
CPU time 59.55 seconds
Started Jul 20 04:53:56 PM PDT 24
Finished Jul 20 04:54:56 PM PDT 24
Peak memory 202204 kb
Host smart-b5c4a3e4-389e-405e-a229-48d032753c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406452608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_tl_intg_err.406452608
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.946416568
Short name T393
Test name
Test status
Simulation time 2111458960 ps
CPU time 6.19 seconds
Started Jul 20 04:54:46 PM PDT 24
Finished Jul 20 04:54:53 PM PDT 24
Peak memory 201896 kb
Host smart-05524f24-f5fd-4f65-8c85-9a8398b6bd35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946416568 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.946416568
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3929056062
Short name T881
Test name
Test status
Simulation time 2269664741 ps
CPU time 1.39 seconds
Started Jul 20 04:54:46 PM PDT 24
Finished Jul 20 04:54:48 PM PDT 24
Peak memory 202036 kb
Host smart-73da8ab3-8945-41b6-97fa-e234e682c5ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929056062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3929056062
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.697396406
Short name T842
Test name
Test status
Simulation time 2020746575 ps
CPU time 3.23 seconds
Started Jul 20 04:54:43 PM PDT 24
Finished Jul 20 04:54:47 PM PDT 24
Peak memory 201568 kb
Host smart-8822d72f-751a-4671-b90e-0c3b07085c71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697396406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_tes
t.697396406
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3007637654
Short name T828
Test name
Test status
Simulation time 9289118331 ps
CPU time 19.35 seconds
Started Jul 20 04:54:48 PM PDT 24
Finished Jul 20 04:55:08 PM PDT 24
Peak memory 202168 kb
Host smart-46fd16bf-8680-46bf-a600-a34867429619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007637654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.3007637654
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3172048938
Short name T290
Test name
Test status
Simulation time 2399222036 ps
CPU time 3.51 seconds
Started Jul 20 04:54:44 PM PDT 24
Finished Jul 20 04:54:48 PM PDT 24
Peak memory 202100 kb
Host smart-c5b0cefc-9734-4c0d-942a-a600267d7221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172048938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.3172048938
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2576226806
Short name T297
Test name
Test status
Simulation time 42522560194 ps
CPU time 58.31 seconds
Started Jul 20 04:54:46 PM PDT 24
Finished Jul 20 04:55:45 PM PDT 24
Peak memory 202152 kb
Host smart-f0e634cc-1d1d-4a49-b743-8036efbfcac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576226806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.2576226806
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2126168106
Short name T848
Test name
Test status
Simulation time 2047003866 ps
CPU time 5.75 seconds
Started Jul 20 04:54:44 PM PDT 24
Finished Jul 20 04:54:51 PM PDT 24
Peak memory 201856 kb
Host smart-4baccc8b-7879-49fe-bb74-3c910d0c8429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126168106 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2126168106
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1947787035
Short name T883
Test name
Test status
Simulation time 2073503061 ps
CPU time 1.8 seconds
Started Jul 20 04:54:45 PM PDT 24
Finished Jul 20 04:54:47 PM PDT 24
Peak memory 201816 kb
Host smart-8402907e-8ca5-441b-8ba1-7e1dbb273a0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947787035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.1947787035
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.767241385
Short name T878
Test name
Test status
Simulation time 2026929779 ps
CPU time 2.55 seconds
Started Jul 20 04:54:46 PM PDT 24
Finished Jul 20 04:54:49 PM PDT 24
Peak memory 201600 kb
Host smart-6c6bcba9-7381-4c19-b158-dbb0e582cfef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767241385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.767241385
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.197257501
Short name T891
Test name
Test status
Simulation time 7766729048 ps
CPU time 5.36 seconds
Started Jul 20 04:54:46 PM PDT 24
Finished Jul 20 04:54:52 PM PDT 24
Peak memory 202208 kb
Host smart-2af271f2-1487-4a96-85c4-1148f017ccb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197257501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_same_csr_outstanding.197257501
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1459706532
Short name T847
Test name
Test status
Simulation time 42372432360 ps
CPU time 106.2 seconds
Started Jul 20 04:54:47 PM PDT 24
Finished Jul 20 04:56:34 PM PDT 24
Peak memory 202232 kb
Host smart-118b8425-992c-4671-a2ad-c7d1822bfc84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459706532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.1459706532
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098199031
Short name T295
Test name
Test status
Simulation time 2145723671 ps
CPU time 6.46 seconds
Started Jul 20 04:54:54 PM PDT 24
Finished Jul 20 04:55:01 PM PDT 24
Peak memory 201940 kb
Host smart-ced2ce5e-cdd5-41ce-8417-1d9b3ec5c2e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098199031 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098199031
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.612865430
Short name T896
Test name
Test status
Simulation time 2046152117 ps
CPU time 2.62 seconds
Started Jul 20 04:54:52 PM PDT 24
Finished Jul 20 04:54:56 PM PDT 24
Peak memory 201816 kb
Host smart-17bd6196-8647-47e2-8a31-73f4df75e894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612865430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r
w.612865430
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2581102611
Short name T863
Test name
Test status
Simulation time 2013556509 ps
CPU time 5.41 seconds
Started Jul 20 04:54:54 PM PDT 24
Finished Jul 20 04:55:00 PM PDT 24
Peak memory 201544 kb
Host smart-8fafd07c-c690-4ce0-9941-7928364aa9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581102611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2581102611
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4064598940
Short name T835
Test name
Test status
Simulation time 4977101872 ps
CPU time 12.32 seconds
Started Jul 20 04:54:52 PM PDT 24
Finished Jul 20 04:55:05 PM PDT 24
Peak memory 202176 kb
Host smart-77cc8cec-c781-436d-af48-7669d5486d3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064598940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.4064598940
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.886015176
Short name T879
Test name
Test status
Simulation time 2122736572 ps
CPU time 7.57 seconds
Started Jul 20 04:54:47 PM PDT 24
Finished Jul 20 04:54:55 PM PDT 24
Peak memory 201968 kb
Host smart-a705c932-b702-4278-93cd-ced4064c4f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886015176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_error
s.886015176
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3304472084
Short name T390
Test name
Test status
Simulation time 42368662140 ps
CPU time 109 seconds
Started Jul 20 04:54:54 PM PDT 24
Finished Jul 20 04:56:43 PM PDT 24
Peak memory 202244 kb
Host smart-de593897-3f16-44fb-8b86-0eb75ddeb489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304472084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.3304472084
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098115413
Short name T285
Test name
Test status
Simulation time 2144851792 ps
CPU time 2.28 seconds
Started Jul 20 04:54:55 PM PDT 24
Finished Jul 20 04:54:57 PM PDT 24
Peak memory 201804 kb
Host smart-306b9f5a-d404-440a-adf9-99b008005ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098115413 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1098115413
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.903975198
Short name T338
Test name
Test status
Simulation time 2030285039 ps
CPU time 3.25 seconds
Started Jul 20 04:54:52 PM PDT 24
Finished Jul 20 04:54:55 PM PDT 24
Peak memory 201728 kb
Host smart-7a930f29-9552-4617-9379-86e4895b374c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903975198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_r
w.903975198
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2475231008
Short name T905
Test name
Test status
Simulation time 2010561951 ps
CPU time 5.41 seconds
Started Jul 20 04:54:54 PM PDT 24
Finished Jul 20 04:55:00 PM PDT 24
Peak memory 201592 kb
Host smart-7417ac1b-7577-4645-80c3-c9e5341545b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475231008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.2475231008
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1842909188
Short name T826
Test name
Test status
Simulation time 4805319397 ps
CPU time 12.06 seconds
Started Jul 20 04:54:53 PM PDT 24
Finished Jul 20 04:55:05 PM PDT 24
Peak memory 202148 kb
Host smart-cab3fecd-2ccc-4a13-8d83-d169ae88c5b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842909188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.1842909188
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.282076070
Short name T292
Test name
Test status
Simulation time 2043447363 ps
CPU time 7.56 seconds
Started Jul 20 04:54:54 PM PDT 24
Finished Jul 20 04:55:02 PM PDT 24
Peak memory 202012 kb
Host smart-1547bd12-10a0-44f7-a1c1-aed1b9377a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282076070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.282076070
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1501364409
Short name T830
Test name
Test status
Simulation time 2061028819 ps
CPU time 5.85 seconds
Started Jul 20 04:55:00 PM PDT 24
Finished Jul 20 04:55:07 PM PDT 24
Peak memory 201828 kb
Host smart-203e2eaa-2f66-4b86-8930-7386b3ca2543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501364409 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1501364409
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.707646253
Short name T344
Test name
Test status
Simulation time 2146135498 ps
CPU time 1.21 seconds
Started Jul 20 04:54:53 PM PDT 24
Finished Jul 20 04:54:54 PM PDT 24
Peak memory 201712 kb
Host smart-fdcc209a-ac8c-496e-b547-1da2e218371e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707646253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.707646253
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2323554361
Short name T809
Test name
Test status
Simulation time 2047120641 ps
CPU time 1.5 seconds
Started Jul 20 04:54:54 PM PDT 24
Finished Jul 20 04:54:56 PM PDT 24
Peak memory 201608 kb
Host smart-964c9504-937b-487b-ba16-2739e4f18192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323554361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.2323554361
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3281203432
Short name T819
Test name
Test status
Simulation time 4711771523 ps
CPU time 17.14 seconds
Started Jul 20 04:55:00 PM PDT 24
Finished Jul 20 04:55:18 PM PDT 24
Peak memory 202100 kb
Host smart-f261084d-5011-408a-b494-5dd88c7d26b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281203432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.3281203432
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2261432818
Short name T294
Test name
Test status
Simulation time 2119930760 ps
CPU time 2.92 seconds
Started Jul 20 04:54:52 PM PDT 24
Finished Jul 20 04:54:56 PM PDT 24
Peak memory 202012 kb
Host smart-5ec11acf-4623-4195-b361-ebee3220c78f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261432818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2261432818
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1198879700
Short name T298
Test name
Test status
Simulation time 22300728762 ps
CPU time 15.28 seconds
Started Jul 20 04:54:52 PM PDT 24
Finished Jul 20 04:55:08 PM PDT 24
Peak memory 202140 kb
Host smart-32ccb026-985b-460d-88cb-f2c5ac92332c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198879700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1198879700
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3586820223
Short name T287
Test name
Test status
Simulation time 2083120803 ps
CPU time 3.62 seconds
Started Jul 20 04:55:00 PM PDT 24
Finished Jul 20 04:55:04 PM PDT 24
Peak memory 201912 kb
Host smart-002df764-c7db-48ad-b329-86de312363de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586820223 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3586820223
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2690661804
Short name T346
Test name
Test status
Simulation time 2025381483 ps
CPU time 5.86 seconds
Started Jul 20 04:55:01 PM PDT 24
Finished Jul 20 04:55:08 PM PDT 24
Peak memory 201728 kb
Host smart-f62e2f70-1b11-4b68-a7b8-00e3621159df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690661804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.2690661804
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3408680166
Short name T823
Test name
Test status
Simulation time 2014267636 ps
CPU time 5.51 seconds
Started Jul 20 04:55:01 PM PDT 24
Finished Jul 20 04:55:07 PM PDT 24
Peak memory 201792 kb
Host smart-cf3ac75f-59f4-4acc-9e78-aa0c00869f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408680166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.3408680166
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1211692971
Short name T895
Test name
Test status
Simulation time 4987069318 ps
CPU time 3.98 seconds
Started Jul 20 04:55:00 PM PDT 24
Finished Jul 20 04:55:05 PM PDT 24
Peak memory 202180 kb
Host smart-de6a84b0-98f8-4b2c-a9e9-2c1e78090ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211692971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.1211692971
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3323291337
Short name T884
Test name
Test status
Simulation time 2030942094 ps
CPU time 6.92 seconds
Started Jul 20 04:55:00 PM PDT 24
Finished Jul 20 04:55:07 PM PDT 24
Peak memory 202008 kb
Host smart-fb2538bc-838f-4b8b-ab3c-ca899ee2e0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323291337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3323291337
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3685516437
Short name T911
Test name
Test status
Simulation time 22336123181 ps
CPU time 30.31 seconds
Started Jul 20 04:55:02 PM PDT 24
Finished Jul 20 04:55:33 PM PDT 24
Peak memory 202212 kb
Host smart-5d8a473b-a717-47d1-bcfd-51392fcdf127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685516437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.3685516437
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.30601404
Short name T912
Test name
Test status
Simulation time 2191281818 ps
CPU time 2.63 seconds
Started Jul 20 04:55:00 PM PDT 24
Finished Jul 20 04:55:03 PM PDT 24
Peak memory 202004 kb
Host smart-e1dc7a7d-bbd7-4c2b-adb4-0b47848cae5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30601404 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.30601404
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2227919433
Short name T345
Test name
Test status
Simulation time 2056870809 ps
CPU time 2.22 seconds
Started Jul 20 04:55:01 PM PDT 24
Finished Jul 20 04:55:04 PM PDT 24
Peak memory 201672 kb
Host smart-491cdf40-8e2e-409b-b3b8-bec3438a783f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227919433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.2227919433
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4279604161
Short name T801
Test name
Test status
Simulation time 2014938296 ps
CPU time 5.64 seconds
Started Jul 20 04:55:01 PM PDT 24
Finished Jul 20 04:55:07 PM PDT 24
Peak memory 201612 kb
Host smart-7f85e768-6136-4a32-accb-ba8f5b92dc82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279604161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.4279604161
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2742541170
Short name T28
Test name
Test status
Simulation time 4601453752 ps
CPU time 5.9 seconds
Started Jul 20 04:55:01 PM PDT 24
Finished Jul 20 04:55:07 PM PDT 24
Peak memory 202204 kb
Host smart-6b54b2b8-4411-45aa-99c8-fd16880dd29a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742541170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2742541170
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1892302901
Short name T860
Test name
Test status
Simulation time 2112271247 ps
CPU time 3.06 seconds
Started Jul 20 04:55:00 PM PDT 24
Finished Jul 20 04:55:04 PM PDT 24
Peak memory 201936 kb
Host smart-c499bc9a-a9e2-4993-8457-234a193f242b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892302901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1892302901
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3400439252
Short name T283
Test name
Test status
Simulation time 22195127185 ps
CPU time 56.67 seconds
Started Jul 20 04:55:00 PM PDT 24
Finished Jul 20 04:55:57 PM PDT 24
Peak memory 202136 kb
Host smart-5ce70eb4-da04-4180-abb6-a4ef878ab01b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400439252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.3400439252
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1507523726
Short name T37
Test name
Test status
Simulation time 2131805063 ps
CPU time 6.47 seconds
Started Jul 20 04:55:09 PM PDT 24
Finished Jul 20 04:55:16 PM PDT 24
Peak memory 201896 kb
Host smart-fc8fd29e-421e-443f-b5df-b9088cdd084c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507523726 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1507523726
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3895236739
Short name T813
Test name
Test status
Simulation time 2061543279 ps
CPU time 6.16 seconds
Started Jul 20 04:55:06 PM PDT 24
Finished Jul 20 04:55:12 PM PDT 24
Peak memory 201916 kb
Host smart-928c719e-9719-4a6e-b750-a839d7bf0cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895236739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.3895236739
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3269058016
Short name T814
Test name
Test status
Simulation time 2032012319 ps
CPU time 2.02 seconds
Started Jul 20 04:55:10 PM PDT 24
Finished Jul 20 04:55:13 PM PDT 24
Peak memory 201708 kb
Host smart-aa997fc6-e7c7-41f1-9167-3cd90ab03679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269058016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3269058016
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.4216502061
Short name T894
Test name
Test status
Simulation time 5212253289 ps
CPU time 7.68 seconds
Started Jul 20 04:55:10 PM PDT 24
Finished Jul 20 04:55:18 PM PDT 24
Peak memory 202120 kb
Host smart-20b14fd0-878d-4976-9356-1825ca9302c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216502061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.4216502061
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.735014024
Short name T805
Test name
Test status
Simulation time 2027907994 ps
CPU time 6.83 seconds
Started Jul 20 04:55:09 PM PDT 24
Finished Jul 20 04:55:17 PM PDT 24
Peak memory 201968 kb
Host smart-0064397c-dc96-4b01-bee0-9f9d31bd47c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735014024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_error
s.735014024
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3690570532
Short name T391
Test name
Test status
Simulation time 42380860042 ps
CPU time 113.47 seconds
Started Jul 20 04:55:10 PM PDT 24
Finished Jul 20 04:57:04 PM PDT 24
Peak memory 202132 kb
Host smart-eb1dc9a3-e652-4ee2-ae49-b40dae48ecc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690570532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3690570532
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.388300324
Short name T816
Test name
Test status
Simulation time 2136373698 ps
CPU time 2.24 seconds
Started Jul 20 04:55:08 PM PDT 24
Finished Jul 20 04:55:11 PM PDT 24
Peak memory 201728 kb
Host smart-edf35da0-6511-441c-a906-daaf3adca652
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388300324 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.388300324
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.864166218
Short name T844
Test name
Test status
Simulation time 2052852405 ps
CPU time 3.31 seconds
Started Jul 20 04:55:09 PM PDT 24
Finished Jul 20 04:55:13 PM PDT 24
Peak memory 201884 kb
Host smart-39901fae-7573-424d-a9b3-86cf2d0b7c6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864166218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_r
w.864166218
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1538128671
Short name T797
Test name
Test status
Simulation time 2011211553 ps
CPU time 5.44 seconds
Started Jul 20 04:55:08 PM PDT 24
Finished Jul 20 04:55:14 PM PDT 24
Peak memory 201556 kb
Host smart-af7b09c0-0fc3-4e49-9222-54306c9193a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538128671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.1538128671
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2546309314
Short name T869
Test name
Test status
Simulation time 7565037910 ps
CPU time 31.4 seconds
Started Jul 20 04:55:09 PM PDT 24
Finished Jul 20 04:55:41 PM PDT 24
Peak memory 202148 kb
Host smart-36702814-9c20-4ab7-a127-01ca34086b5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546309314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.2546309314
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2665899131
Short name T291
Test name
Test status
Simulation time 2024645001 ps
CPU time 6.14 seconds
Started Jul 20 04:55:10 PM PDT 24
Finished Jul 20 04:55:17 PM PDT 24
Peak memory 202036 kb
Host smart-87956f77-ef1d-4585-865c-835128746d08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665899131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.2665899131
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2271454351
Short name T877
Test name
Test status
Simulation time 22424976982 ps
CPU time 14.34 seconds
Started Jul 20 04:55:10 PM PDT 24
Finished Jul 20 04:55:25 PM PDT 24
Peak memory 202128 kb
Host smart-abbcb75c-e133-4fa6-821c-a47e3cd63ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271454351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.2271454351
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.131160331
Short name T868
Test name
Test status
Simulation time 2043476810 ps
CPU time 5.94 seconds
Started Jul 20 04:55:27 PM PDT 24
Finished Jul 20 04:55:33 PM PDT 24
Peak memory 201896 kb
Host smart-6aa673a6-3b62-4444-9b55-023a711e7129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131160331 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.131160331
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3652116475
Short name T334
Test name
Test status
Simulation time 2028095629 ps
CPU time 5.75 seconds
Started Jul 20 04:55:06 PM PDT 24
Finished Jul 20 04:55:13 PM PDT 24
Peak memory 201688 kb
Host smart-7cb4c867-03fa-4843-9c46-d08f9ddb1516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652116475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.3652116475
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1311788930
Short name T804
Test name
Test status
Simulation time 2032040618 ps
CPU time 2 seconds
Started Jul 20 04:55:07 PM PDT 24
Finished Jul 20 04:55:09 PM PDT 24
Peak memory 201548 kb
Host smart-26db028e-c43c-43b6-9fb8-bde93755e5dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311788930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.1311788930
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3343925235
Short name T288
Test name
Test status
Simulation time 2043221272 ps
CPU time 6.66 seconds
Started Jul 20 04:55:08 PM PDT 24
Finished Jul 20 04:55:16 PM PDT 24
Peak memory 202064 kb
Host smart-d9b4f86b-8ef9-422e-a7ea-8f833d0ab027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343925235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3343925235
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.561993689
Short name T909
Test name
Test status
Simulation time 42442767033 ps
CPU time 84.76 seconds
Started Jul 20 04:55:08 PM PDT 24
Finished Jul 20 04:56:34 PM PDT 24
Peak memory 202176 kb
Host smart-852b27a4-9765-4992-90e4-d089d1f37fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561993689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_tl_intg_err.561993689
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.432252695
Short name T889
Test name
Test status
Simulation time 2902983812 ps
CPU time 10.14 seconds
Started Jul 20 04:54:04 PM PDT 24
Finished Jul 20 04:54:14 PM PDT 24
Peak memory 202096 kb
Host smart-703441b7-9b97-4429-a249-c6eb7e3aa11d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432252695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_aliasing.432252695
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2035561127
Short name T854
Test name
Test status
Simulation time 4010132847 ps
CPU time 10.95 seconds
Started Jul 20 04:54:05 PM PDT 24
Finished Jul 20 04:54:17 PM PDT 24
Peak memory 202028 kb
Host smart-9580d512-c7c9-4189-9d6c-df2692a81355
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035561127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.2035561127
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1984536325
Short name T857
Test name
Test status
Simulation time 2243780118 ps
CPU time 2.42 seconds
Started Jul 20 04:54:05 PM PDT 24
Finished Jul 20 04:54:07 PM PDT 24
Peak memory 201988 kb
Host smart-c5ff465b-b10d-4cda-bb5e-c0272cfc574c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984536325 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1984536325
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3183457003
Short name T342
Test name
Test status
Simulation time 2057743553 ps
CPU time 1.92 seconds
Started Jul 20 04:54:03 PM PDT 24
Finished Jul 20 04:54:06 PM PDT 24
Peak memory 201828 kb
Host smart-baf92507-996a-4950-b9e0-1ddec3e84fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183457003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3183457003
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3620447994
Short name T862
Test name
Test status
Simulation time 2011220320 ps
CPU time 5.86 seconds
Started Jul 20 04:53:59 PM PDT 24
Finished Jul 20 04:54:06 PM PDT 24
Peak memory 201612 kb
Host smart-720210c1-11c2-4a2c-9834-72ab43c5b74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620447994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.3620447994
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3203115882
Short name T914
Test name
Test status
Simulation time 7702756299 ps
CPU time 24.95 seconds
Started Jul 20 04:54:05 PM PDT 24
Finished Jul 20 04:54:30 PM PDT 24
Peak memory 202228 kb
Host smart-4495bd23-fc92-42ef-91c4-282c9e30c50e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203115882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.3203115882
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4064010497
Short name T910
Test name
Test status
Simulation time 4032183550 ps
CPU time 2.98 seconds
Started Jul 20 04:53:57 PM PDT 24
Finished Jul 20 04:54:01 PM PDT 24
Peak memory 210332 kb
Host smart-6267a0a0-a3de-4843-96f3-53c190bf5076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064010497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.4064010497
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.804072042
Short name T284
Test name
Test status
Simulation time 22207313745 ps
CPU time 45.37 seconds
Started Jul 20 04:53:58 PM PDT 24
Finished Jul 20 04:54:44 PM PDT 24
Peak memory 202140 kb
Host smart-9e8872b2-0591-433e-b8a7-89b29aedab12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804072042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_tl_intg_err.804072042
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2525357844
Short name T833
Test name
Test status
Simulation time 2039059701 ps
CPU time 1.86 seconds
Started Jul 20 04:55:17 PM PDT 24
Finished Jul 20 04:55:19 PM PDT 24
Peak memory 201460 kb
Host smart-62fa7d2b-be10-4734-a859-d02320c2c197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525357844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2525357844
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4181170188
Short name T859
Test name
Test status
Simulation time 2016366622 ps
CPU time 3.4 seconds
Started Jul 20 04:55:17 PM PDT 24
Finished Jul 20 04:55:21 PM PDT 24
Peak memory 201560 kb
Host smart-c77a9168-de4a-4219-9cdb-d7386210986a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181170188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.4181170188
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3007424670
Short name T820
Test name
Test status
Simulation time 2092219330 ps
CPU time 1.23 seconds
Started Jul 20 04:55:16 PM PDT 24
Finished Jul 20 04:55:17 PM PDT 24
Peak memory 201648 kb
Host smart-b9b76c34-4c06-4a26-8c5d-218853a24415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007424670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.3007424670
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4102316796
Short name T902
Test name
Test status
Simulation time 2065647187 ps
CPU time 1.38 seconds
Started Jul 20 04:55:16 PM PDT 24
Finished Jul 20 04:55:18 PM PDT 24
Peak memory 201672 kb
Host smart-68809a2a-068e-4cf2-83e0-bca3e5c82638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102316796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.4102316796
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.696744382
Short name T915
Test name
Test status
Simulation time 2012923285 ps
CPU time 5.33 seconds
Started Jul 20 04:55:17 PM PDT 24
Finished Jul 20 04:55:23 PM PDT 24
Peak memory 201520 kb
Host smart-0d4d47b7-6192-4e17-a25f-78611fc9f272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696744382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_tes
t.696744382
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3409906335
Short name T903
Test name
Test status
Simulation time 2030816098 ps
CPU time 1.91 seconds
Started Jul 20 04:55:16 PM PDT 24
Finished Jul 20 04:55:18 PM PDT 24
Peak memory 201776 kb
Host smart-24fcad75-2f7f-4830-a500-adfc2749d575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409906335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.3409906335
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1910637253
Short name T904
Test name
Test status
Simulation time 2033504486 ps
CPU time 2.14 seconds
Started Jul 20 04:55:25 PM PDT 24
Finished Jul 20 04:55:28 PM PDT 24
Peak memory 201612 kb
Host smart-72bb8eca-63ea-4c43-a47c-b111a28b8413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910637253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.1910637253
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3045556760
Short name T886
Test name
Test status
Simulation time 2035760267 ps
CPU time 1.95 seconds
Started Jul 20 04:55:19 PM PDT 24
Finished Jul 20 04:55:21 PM PDT 24
Peak memory 201708 kb
Host smart-a902db9d-5fd0-4ee9-aeb6-53b3d39f3c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045556760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.3045556760
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2215485390
Short name T885
Test name
Test status
Simulation time 2014183444 ps
CPU time 5.56 seconds
Started Jul 20 04:55:22 PM PDT 24
Finished Jul 20 04:55:29 PM PDT 24
Peak memory 201612 kb
Host smart-e4934926-0b84-4061-9d62-dec92078c1a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215485390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.2215485390
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2346226742
Short name T851
Test name
Test status
Simulation time 2028629593 ps
CPU time 2.35 seconds
Started Jul 20 04:55:16 PM PDT 24
Finished Jul 20 04:55:19 PM PDT 24
Peak memory 201772 kb
Host smart-06c5ab0f-8fb3-43be-ad59-b3ba6bae5ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346226742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.2346226742
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.4230490850
Short name T340
Test name
Test status
Simulation time 2118640199 ps
CPU time 7.33 seconds
Started Jul 20 04:54:14 PM PDT 24
Finished Jul 20 04:54:22 PM PDT 24
Peak memory 201848 kb
Host smart-f3ebda67-9e7e-4786-8b4d-81b0ca9d94d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230490850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.4230490850
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3960480055
Short name T858
Test name
Test status
Simulation time 37324115583 ps
CPU time 151.36 seconds
Started Jul 20 04:54:14 PM PDT 24
Finished Jul 20 04:56:46 PM PDT 24
Peak memory 202200 kb
Host smart-485c9717-c263-4e86-a4a2-e1ed8e763fca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960480055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3960480055
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.74866172
Short name T873
Test name
Test status
Simulation time 6059411485 ps
CPU time 8.47 seconds
Started Jul 20 04:54:13 PM PDT 24
Finished Jul 20 04:54:21 PM PDT 24
Peak memory 202040 kb
Host smart-26bfafb2-4ca8-4008-890b-b81a5f759524
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74866172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_c
sr_hw_reset.74866172
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1448287359
Short name T846
Test name
Test status
Simulation time 2404810479 ps
CPU time 1.16 seconds
Started Jul 20 04:54:13 PM PDT 24
Finished Jul 20 04:54:15 PM PDT 24
Peak memory 201844 kb
Host smart-a5b24be3-b7d2-4994-92f7-e93ed39aa302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448287359 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1448287359
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2611258272
Short name T335
Test name
Test status
Simulation time 2047153372 ps
CPU time 5.65 seconds
Started Jul 20 04:54:15 PM PDT 24
Finished Jul 20 04:54:21 PM PDT 24
Peak memory 201880 kb
Host smart-b6900cba-f8f1-42b1-a7df-d5b6964ce358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611258272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.2611258272
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.598347628
Short name T799
Test name
Test status
Simulation time 2026865109 ps
CPU time 3.06 seconds
Started Jul 20 04:54:14 PM PDT 24
Finished Jul 20 04:54:17 PM PDT 24
Peak memory 201632 kb
Host smart-b3f56213-448b-4897-a96e-1e790049c25b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598347628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test
.598347628
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3626261677
Short name T906
Test name
Test status
Simulation time 8055672171 ps
CPU time 17.29 seconds
Started Jul 20 04:54:13 PM PDT 24
Finished Jul 20 04:54:31 PM PDT 24
Peak memory 202172 kb
Host smart-8e82d1a9-0963-469c-a1a7-20122d43c1f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626261677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.3626261677
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.185733462
Short name T882
Test name
Test status
Simulation time 2558032800 ps
CPU time 3.1 seconds
Started Jul 20 04:54:05 PM PDT 24
Finished Jul 20 04:54:09 PM PDT 24
Peak memory 210368 kb
Host smart-a2ced4bf-dd4d-44b5-97f2-b741b6fa0831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185733462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors
.185733462
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3062259297
Short name T843
Test name
Test status
Simulation time 22182476397 ps
CPU time 54.62 seconds
Started Jul 20 04:54:14 PM PDT 24
Finished Jul 20 04:55:09 PM PDT 24
Peak memory 202164 kb
Host smart-3138d317-cc56-40c4-8c3f-b25bf999542b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062259297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3062259297
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.423375643
Short name T808
Test name
Test status
Simulation time 2018405174 ps
CPU time 5.83 seconds
Started Jul 20 04:55:16 PM PDT 24
Finished Jul 20 04:55:22 PM PDT 24
Peak memory 201660 kb
Host smart-e05f47f9-dd48-401c-8a58-3dd26012be9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423375643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_tes
t.423375643
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2661182923
Short name T803
Test name
Test status
Simulation time 2069666102 ps
CPU time 1.09 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:35 PM PDT 24
Peak memory 201724 kb
Host smart-6588f966-c013-44e2-baf7-1e250b1dc370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661182923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2661182923
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.121767554
Short name T810
Test name
Test status
Simulation time 2047802539 ps
CPU time 1.61 seconds
Started Jul 20 04:55:21 PM PDT 24
Finished Jul 20 04:55:23 PM PDT 24
Peak memory 201552 kb
Host smart-62fd6440-47e9-48a5-9bc8-d1267de69fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121767554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_tes
t.121767554
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1012462813
Short name T880
Test name
Test status
Simulation time 2030798109 ps
CPU time 3.1 seconds
Started Jul 20 04:55:22 PM PDT 24
Finished Jul 20 04:55:26 PM PDT 24
Peak memory 201548 kb
Host smart-9b98daca-fbcb-461f-8a07-5e91b796e7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012462813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.1012462813
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.837450022
Short name T815
Test name
Test status
Simulation time 2013009875 ps
CPU time 5.49 seconds
Started Jul 20 04:55:23 PM PDT 24
Finished Jul 20 04:55:29 PM PDT 24
Peak memory 201644 kb
Host smart-6538e7fb-dad5-4fea-a736-614eb996b74b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837450022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_tes
t.837450022
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2790017359
Short name T795
Test name
Test status
Simulation time 2012915271 ps
CPU time 5.54 seconds
Started Jul 20 04:55:33 PM PDT 24
Finished Jul 20 04:55:39 PM PDT 24
Peak memory 201556 kb
Host smart-70cb057c-5243-498c-a8fd-e58b5abc5c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790017359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2790017359
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3486715786
Short name T825
Test name
Test status
Simulation time 2058909828 ps
CPU time 1.46 seconds
Started Jul 20 04:55:35 PM PDT 24
Finished Jul 20 04:55:37 PM PDT 24
Peak memory 201728 kb
Host smart-68eb97b1-0b1d-4d32-a302-6e9af21557c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486715786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.3486715786
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3423246245
Short name T855
Test name
Test status
Simulation time 2010864706 ps
CPU time 5.4 seconds
Started Jul 20 04:55:24 PM PDT 24
Finished Jul 20 04:55:29 PM PDT 24
Peak memory 201768 kb
Host smart-43ca864b-5596-4f5b-a899-d30def8f10da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423246245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.3423246245
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3994920891
Short name T818
Test name
Test status
Simulation time 2014592497 ps
CPU time 5.64 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:40 PM PDT 24
Peak memory 201556 kb
Host smart-970d879a-5c8c-471a-8a18-19ac218b057e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994920891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.3994920891
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1796296219
Short name T837
Test name
Test status
Simulation time 2023201511 ps
CPU time 3.27 seconds
Started Jul 20 04:55:23 PM PDT 24
Finished Jul 20 04:55:27 PM PDT 24
Peak memory 201592 kb
Host smart-01c638c4-e6df-4530-b215-87bac29618ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796296219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.1796296219
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.243295643
Short name T824
Test name
Test status
Simulation time 3082459457 ps
CPU time 2.92 seconds
Started Jul 20 04:54:20 PM PDT 24
Finished Jul 20 04:54:23 PM PDT 24
Peak memory 202044 kb
Host smart-01006abe-e4b1-4762-bd14-e788483e3bd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243295643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_aliasing.243295643
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1275190718
Short name T392
Test name
Test status
Simulation time 39188821948 ps
CPU time 75.54 seconds
Started Jul 20 04:54:12 PM PDT 24
Finished Jul 20 04:55:28 PM PDT 24
Peak memory 202132 kb
Host smart-625e5a31-d4cb-4afc-a4dd-329988dd18a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275190718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.1275190718
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2516029218
Short name T336
Test name
Test status
Simulation time 4065365694 ps
CPU time 2.44 seconds
Started Jul 20 04:54:13 PM PDT 24
Finished Jul 20 04:54:16 PM PDT 24
Peak memory 201908 kb
Host smart-88fcf6f9-91b7-4c24-a56e-ca8af672f3cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516029218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.2516029218
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2430696799
Short name T838
Test name
Test status
Simulation time 2149728519 ps
CPU time 2.54 seconds
Started Jul 20 04:54:23 PM PDT 24
Finished Jul 20 04:54:26 PM PDT 24
Peak memory 201984 kb
Host smart-3a9d9cdf-4c9e-4c3b-a577-bcb98fc6fcd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430696799 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2430696799
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.469950629
Short name T856
Test name
Test status
Simulation time 2052183854 ps
CPU time 1.91 seconds
Started Jul 20 04:54:13 PM PDT 24
Finished Jul 20 04:54:15 PM PDT 24
Peak memory 201712 kb
Host smart-51526506-ab11-496b-b98d-8ff0616cb82e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469950629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw
.469950629
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1249880945
Short name T798
Test name
Test status
Simulation time 2013969811 ps
CPU time 5.77 seconds
Started Jul 20 04:54:14 PM PDT 24
Finished Jul 20 04:54:20 PM PDT 24
Peak memory 201604 kb
Host smart-85a21a90-6584-441f-8d98-b90287690586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249880945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.1249880945
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.521978675
Short name T867
Test name
Test status
Simulation time 4400265533 ps
CPU time 11.24 seconds
Started Jul 20 04:54:22 PM PDT 24
Finished Jul 20 04:54:33 PM PDT 24
Peak memory 201864 kb
Host smart-c6df9221-c14d-4cb7-b311-6c006d9b8d0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521978675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
sysrst_ctrl_same_csr_outstanding.521978675
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1663292804
Short name T864
Test name
Test status
Simulation time 2110143909 ps
CPU time 7.57 seconds
Started Jul 20 04:54:13 PM PDT 24
Finished Jul 20 04:54:21 PM PDT 24
Peak memory 210188 kb
Host smart-27035b3e-243e-4b24-93df-0e9f6c611497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663292804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.1663292804
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1836188837
Short name T898
Test name
Test status
Simulation time 22267356637 ps
CPU time 16.77 seconds
Started Jul 20 04:54:13 PM PDT 24
Finished Jul 20 04:54:31 PM PDT 24
Peak memory 202136 kb
Host smart-9b9a2765-9a65-47db-bf9b-e1c1646745f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836188837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.1836188837
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3701472626
Short name T812
Test name
Test status
Simulation time 2032947527 ps
CPU time 1.92 seconds
Started Jul 20 04:55:25 PM PDT 24
Finished Jul 20 04:55:27 PM PDT 24
Peak memory 201544 kb
Host smart-8c741509-10f8-4d8f-938f-bed12a5d342b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701472626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.3701472626
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3444482151
Short name T802
Test name
Test status
Simulation time 2044582743 ps
CPU time 1.48 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:36 PM PDT 24
Peak memory 201724 kb
Host smart-ca3884df-7389-409e-9f88-5ff19f23c192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444482151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3444482151
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1411651689
Short name T834
Test name
Test status
Simulation time 2049431315 ps
CPU time 1.85 seconds
Started Jul 20 04:55:35 PM PDT 24
Finished Jul 20 04:55:38 PM PDT 24
Peak memory 201556 kb
Host smart-65113cbd-6a48-429f-a9e5-7303dac468df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411651689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1411651689
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2897825338
Short name T850
Test name
Test status
Simulation time 2034155357 ps
CPU time 1.9 seconds
Started Jul 20 04:55:23 PM PDT 24
Finished Jul 20 04:55:25 PM PDT 24
Peak memory 201732 kb
Host smart-9195f0ae-4ab3-4b1f-8881-254d7a968024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897825338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.2897825338
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4179718031
Short name T913
Test name
Test status
Simulation time 2015376868 ps
CPU time 5.41 seconds
Started Jul 20 04:55:22 PM PDT 24
Finished Jul 20 04:55:28 PM PDT 24
Peak memory 201732 kb
Host smart-784dacfc-f1a3-4b6b-b2d5-ec7985998eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179718031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.4179718031
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2771657164
Short name T841
Test name
Test status
Simulation time 2012925503 ps
CPU time 5.73 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:40 PM PDT 24
Peak memory 201584 kb
Host smart-5b6ac279-48a4-4b84-b9a1-6561bab9aa05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771657164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.2771657164
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1501289314
Short name T845
Test name
Test status
Simulation time 2014615459 ps
CPU time 5.23 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:40 PM PDT 24
Peak memory 201760 kb
Host smart-25e26846-f155-4ffc-8b18-2a67fae9ac72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501289314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1501289314
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3730779821
Short name T888
Test name
Test status
Simulation time 2009236217 ps
CPU time 5.23 seconds
Started Jul 20 04:55:32 PM PDT 24
Finished Jul 20 04:55:38 PM PDT 24
Peak memory 201796 kb
Host smart-4c419804-3bd5-45ac-8bca-fe617d72fd38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730779821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3730779821
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.648824206
Short name T800
Test name
Test status
Simulation time 2031949453 ps
CPU time 2.13 seconds
Started Jul 20 04:55:33 PM PDT 24
Finished Jul 20 04:55:35 PM PDT 24
Peak memory 201568 kb
Host smart-33951a74-0829-4a3d-8c29-83b04659d29c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648824206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_tes
t.648824206
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3307925108
Short name T887
Test name
Test status
Simulation time 2011958180 ps
CPU time 5.65 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:41 PM PDT 24
Peak memory 201920 kb
Host smart-6ce9f16a-c070-4488-b850-fe0cfa8efe3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307925108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.3307925108
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1144157412
Short name T39
Test name
Test status
Simulation time 2065863495 ps
CPU time 6.32 seconds
Started Jul 20 04:54:21 PM PDT 24
Finished Jul 20 04:54:27 PM PDT 24
Peak memory 201840 kb
Host smart-86245f7b-8fa5-4e54-8917-e4033250a87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144157412 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1144157412
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1773779323
Short name T38
Test name
Test status
Simulation time 2088775748 ps
CPU time 2.26 seconds
Started Jul 20 04:54:24 PM PDT 24
Finished Jul 20 04:54:27 PM PDT 24
Peak memory 201816 kb
Host smart-2e7e3ff9-331d-4470-88ce-a22408a9ebbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773779323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.1773779323
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1415360612
Short name T796
Test name
Test status
Simulation time 2036435488 ps
CPU time 1.92 seconds
Started Jul 20 04:54:21 PM PDT 24
Finished Jul 20 04:54:24 PM PDT 24
Peak memory 201716 kb
Host smart-6dfc22d7-3f47-4ef9-b465-eb248aca9924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415360612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.1415360612
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3832485269
Short name T829
Test name
Test status
Simulation time 4191276114 ps
CPU time 6.61 seconds
Started Jul 20 04:54:22 PM PDT 24
Finished Jul 20 04:54:29 PM PDT 24
Peak memory 201924 kb
Host smart-dbe4bf90-2ec0-44c4-bd00-94b3172f2f62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832485269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.3832485269
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2603853159
Short name T871
Test name
Test status
Simulation time 2680353945 ps
CPU time 3.84 seconds
Started Jul 20 04:54:20 PM PDT 24
Finished Jul 20 04:54:25 PM PDT 24
Peak memory 202052 kb
Host smart-77c75874-58a2-47c5-b614-8072ef4ccc89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603853159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2603853159
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3566692606
Short name T874
Test name
Test status
Simulation time 22275968499 ps
CPU time 15.36 seconds
Started Jul 20 04:54:22 PM PDT 24
Finished Jul 20 04:54:38 PM PDT 24
Peak memory 202148 kb
Host smart-5cef0be2-24c5-4724-9726-4a6934c18dec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566692606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3566692606
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3366839928
Short name T866
Test name
Test status
Simulation time 2157898957 ps
CPU time 2.73 seconds
Started Jul 20 04:54:30 PM PDT 24
Finished Jul 20 04:54:33 PM PDT 24
Peak memory 201860 kb
Host smart-8a929c6b-fa9f-4ff1-85a9-66f3e256215b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366839928 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3366839928
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2138631528
Short name T908
Test name
Test status
Simulation time 2111283617 ps
CPU time 2.19 seconds
Started Jul 20 04:54:30 PM PDT 24
Finished Jul 20 04:54:33 PM PDT 24
Peak memory 201820 kb
Host smart-fed0f948-033b-4719-86d0-6670dbcec4c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138631528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.2138631528
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3281245062
Short name T811
Test name
Test status
Simulation time 2019404788 ps
CPU time 3 seconds
Started Jul 20 04:54:27 PM PDT 24
Finished Jul 20 04:54:30 PM PDT 24
Peak memory 201700 kb
Host smart-ba5435ba-0f5a-48d3-878f-6fce30153945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281245062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.3281245062
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2569940705
Short name T852
Test name
Test status
Simulation time 10157682575 ps
CPU time 35.94 seconds
Started Jul 20 04:54:31 PM PDT 24
Finished Jul 20 04:55:08 PM PDT 24
Peak memory 202124 kb
Host smart-b7752acb-dfda-470b-a107-1b84e33e3071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569940705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.2569940705
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.4187520674
Short name T900
Test name
Test status
Simulation time 2844397512 ps
CPU time 3.84 seconds
Started Jul 20 04:54:20 PM PDT 24
Finished Jul 20 04:54:24 PM PDT 24
Peak memory 202104 kb
Host smart-34dc9586-2085-43b5-9b69-850301881bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187520674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.4187520674
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2434554758
Short name T822
Test name
Test status
Simulation time 2148830829 ps
CPU time 6.18 seconds
Started Jul 20 04:54:39 PM PDT 24
Finished Jul 20 04:54:46 PM PDT 24
Peak memory 202056 kb
Host smart-9b73a360-8f05-40de-a7f7-2f75cd67a605
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434554758 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2434554758
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.195592059
Short name T907
Test name
Test status
Simulation time 2114259245 ps
CPU time 2.02 seconds
Started Jul 20 04:54:37 PM PDT 24
Finished Jul 20 04:54:40 PM PDT 24
Peak memory 201860 kb
Host smart-f45e60b4-8c45-4c5e-9f19-7f550bebb3b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195592059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw
.195592059
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.542831272
Short name T899
Test name
Test status
Simulation time 2039793834 ps
CPU time 1.92 seconds
Started Jul 20 04:54:29 PM PDT 24
Finished Jul 20 04:54:32 PM PDT 24
Peak memory 201488 kb
Host smart-e02d5e4b-88aa-434b-b1a4-6db316e4f02d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542831272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test
.542831272
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3461250895
Short name T849
Test name
Test status
Simulation time 5220845493 ps
CPU time 14.28 seconds
Started Jul 20 04:54:38 PM PDT 24
Finished Jul 20 04:54:53 PM PDT 24
Peak memory 202140 kb
Host smart-5995e725-10ed-4642-b209-7cd1e202ab4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461250895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.3461250895
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1293224287
Short name T872
Test name
Test status
Simulation time 2070290446 ps
CPU time 6.49 seconds
Started Jul 20 04:54:29 PM PDT 24
Finished Jul 20 04:54:36 PM PDT 24
Peak memory 202124 kb
Host smart-8205a5f4-d1ec-4582-b53f-b205fb71bba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293224287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1293224287
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1612269778
Short name T870
Test name
Test status
Simulation time 42468884534 ps
CPU time 115.87 seconds
Started Jul 20 04:54:28 PM PDT 24
Finished Jul 20 04:56:24 PM PDT 24
Peak memory 202116 kb
Host smart-f6f36967-2f9b-4295-ab7a-2b8a1e5bb4db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612269778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.1612269778
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3750654280
Short name T817
Test name
Test status
Simulation time 2072896809 ps
CPU time 5.91 seconds
Started Jul 20 04:54:39 PM PDT 24
Finished Jul 20 04:54:46 PM PDT 24
Peak memory 201868 kb
Host smart-6c646aba-6757-4d7e-b29d-74839bfe8b76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750654280 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3750654280
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3665940696
Short name T286
Test name
Test status
Simulation time 2151525087 ps
CPU time 1.27 seconds
Started Jul 20 04:54:39 PM PDT 24
Finished Jul 20 04:54:41 PM PDT 24
Peak memory 201944 kb
Host smart-b447eed1-b0b2-4209-a6f7-e2cc391112e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665940696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3665940696
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2307175653
Short name T806
Test name
Test status
Simulation time 2021332997 ps
CPU time 3.32 seconds
Started Jul 20 04:54:39 PM PDT 24
Finished Jul 20 04:54:43 PM PDT 24
Peak memory 201524 kb
Host smart-2f0d0935-5141-45c5-b329-d3bd02031f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307175653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.2307175653
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.789828226
Short name T827
Test name
Test status
Simulation time 9989421352 ps
CPU time 10.67 seconds
Started Jul 20 04:54:39 PM PDT 24
Finished Jul 20 04:54:50 PM PDT 24
Peak memory 202200 kb
Host smart-d2b59968-b34c-46f9-8747-bcd987cd6f6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789828226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
sysrst_ctrl_same_csr_outstanding.789828226
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2728620361
Short name T875
Test name
Test status
Simulation time 2277846722 ps
CPU time 2.09 seconds
Started Jul 20 04:54:38 PM PDT 24
Finished Jul 20 04:54:40 PM PDT 24
Peak memory 202324 kb
Host smart-1aef5319-3291-4a17-ad8a-c01f645fd963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728620361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.2728620361
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1932724745
Short name T832
Test name
Test status
Simulation time 42578847487 ps
CPU time 55.49 seconds
Started Jul 20 04:54:39 PM PDT 24
Finished Jul 20 04:55:35 PM PDT 24
Peak memory 202156 kb
Host smart-11ddb682-2e36-47db-992f-967649ad3a85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932724745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1932724745
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3097213220
Short name T893
Test name
Test status
Simulation time 2105912158 ps
CPU time 2.09 seconds
Started Jul 20 04:54:45 PM PDT 24
Finished Jul 20 04:54:48 PM PDT 24
Peak memory 201872 kb
Host smart-533a298a-ef43-4664-be22-63b621feb30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097213220 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3097213220
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.596818233
Short name T892
Test name
Test status
Simulation time 2066746012 ps
CPU time 3.4 seconds
Started Jul 20 04:54:44 PM PDT 24
Finished Jul 20 04:54:48 PM PDT 24
Peak memory 202024 kb
Host smart-267af21c-45d1-4cc5-9574-293d7e31aba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596818233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw
.596818233
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.708036971
Short name T807
Test name
Test status
Simulation time 2014271240 ps
CPU time 5.93 seconds
Started Jul 20 04:54:46 PM PDT 24
Finished Jul 20 04:54:53 PM PDT 24
Peak memory 201784 kb
Host smart-db18a23c-6ad4-4bf6-ad32-6588e560feb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708036971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test
.708036971
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3302823208
Short name T27
Test name
Test status
Simulation time 4850970273 ps
CPU time 5.28 seconds
Started Jul 20 04:54:47 PM PDT 24
Finished Jul 20 04:54:53 PM PDT 24
Peak memory 202088 kb
Host smart-130801ad-3551-45d1-85ff-e9203bc98a52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302823208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.3302823208
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3862778763
Short name T831
Test name
Test status
Simulation time 23805914971 ps
CPU time 5.94 seconds
Started Jul 20 04:54:46 PM PDT 24
Finished Jul 20 04:54:53 PM PDT 24
Peak memory 202148 kb
Host smart-3b499373-ff45-4be5-bd2a-1b935ec33534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862778763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.3862778763
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.315898350
Short name T684
Test name
Test status
Simulation time 2019571728 ps
CPU time 1.98 seconds
Started Jul 20 04:41:04 PM PDT 24
Finished Jul 20 04:41:07 PM PDT 24
Peak memory 201456 kb
Host smart-00dea77c-b99c-4a29-b140-9ac6f0ddf9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315898350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.315898350
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.598677123
Short name T592
Test name
Test status
Simulation time 3602690689 ps
CPU time 4.97 seconds
Started Jul 20 04:41:11 PM PDT 24
Finished Jul 20 04:41:17 PM PDT 24
Peak memory 201540 kb
Host smart-12aaa29e-f753-44a1-92e7-543a1a3a6ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598677123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.598677123
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.3944702854
Short name T661
Test name
Test status
Simulation time 64637649529 ps
CPU time 39.24 seconds
Started Jul 20 04:41:06 PM PDT 24
Finished Jul 20 04:41:45 PM PDT 24
Peak memory 201716 kb
Host smart-9b7a71ce-a1f0-4356-816f-38b99cd23511
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944702854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.3944702854
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.709826593
Short name T500
Test name
Test status
Simulation time 2457023238 ps
CPU time 1.36 seconds
Started Jul 20 04:41:15 PM PDT 24
Finished Jul 20 04:41:18 PM PDT 24
Peak memory 201464 kb
Host smart-6390e42b-be24-4623-90c5-7a606fe85463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709826593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.709826593
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1445672462
Short name T420
Test name
Test status
Simulation time 2534649960 ps
CPU time 7.09 seconds
Started Jul 20 04:41:02 PM PDT 24
Finished Jul 20 04:41:10 PM PDT 24
Peak memory 201544 kb
Host smart-d605bf4a-fbeb-49c5-97df-de4d714c175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445672462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1445672462
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.797367604
Short name T36
Test name
Test status
Simulation time 79505259771 ps
CPU time 148.71 seconds
Started Jul 20 04:41:08 PM PDT 24
Finished Jul 20 04:43:37 PM PDT 24
Peak memory 201844 kb
Host smart-5ffa4cfd-7b1d-48ab-8e3b-f659a6bfb7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797367604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wit
h_pre_cond.797367604
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4055506382
Short name T743
Test name
Test status
Simulation time 3844791304 ps
CPU time 3.08 seconds
Started Jul 20 04:41:12 PM PDT 24
Finished Jul 20 04:41:15 PM PDT 24
Peak memory 201444 kb
Host smart-5eac30b5-b6fe-4857-b977-487c6852eef0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055506382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.4055506382
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1635291027
Short name T153
Test name
Test status
Simulation time 4706644282 ps
CPU time 5.76 seconds
Started Jul 20 04:41:02 PM PDT 24
Finished Jul 20 04:41:08 PM PDT 24
Peak memory 201472 kb
Host smart-8e79261d-f47e-41d4-83a6-2dd59d430673
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635291027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.1635291027
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.394625281
Short name T578
Test name
Test status
Simulation time 2610293202 ps
CPU time 6.89 seconds
Started Jul 20 04:41:13 PM PDT 24
Finished Jul 20 04:41:20 PM PDT 24
Peak memory 201460 kb
Host smart-40ac9239-0990-4fd3-ac4e-837f07e5a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394625281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.394625281
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1606986920
Short name T616
Test name
Test status
Simulation time 2476690487 ps
CPU time 7.03 seconds
Started Jul 20 04:41:08 PM PDT 24
Finished Jul 20 04:41:16 PM PDT 24
Peak memory 201492 kb
Host smart-0e540b7b-dfee-4c41-89f5-7c5a34c1d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606986920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1606986920
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.2745692719
Short name T692
Test name
Test status
Simulation time 2144169420 ps
CPU time 5.99 seconds
Started Jul 20 04:41:01 PM PDT 24
Finished Jul 20 04:41:08 PM PDT 24
Peak memory 201336 kb
Host smart-3f16cf06-548e-4efe-8aa6-ab512d4f0221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745692719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.2745692719
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1949649117
Short name T301
Test name
Test status
Simulation time 2547469627 ps
CPU time 1.39 seconds
Started Jul 20 04:40:59 PM PDT 24
Finished Jul 20 04:41:01 PM PDT 24
Peak memory 201436 kb
Host smart-96b77035-b354-48f5-b410-7465566f3513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949649117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1949649117
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.4282865455
Short name T96
Test name
Test status
Simulation time 42035418134 ps
CPU time 53.16 seconds
Started Jul 20 04:41:02 PM PDT 24
Finished Jul 20 04:41:56 PM PDT 24
Peak memory 218664 kb
Host smart-52a5b0c5-5a12-4668-abb8-1574df8c7661
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282865455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.4282865455
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.485072220
Short name T695
Test name
Test status
Simulation time 2109545369 ps
CPU time 5.99 seconds
Started Jul 20 04:41:06 PM PDT 24
Finished Jul 20 04:41:13 PM PDT 24
Peak memory 201444 kb
Host smart-4e8c9f11-3486-40f5-8232-ec496a866a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485072220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.485072220
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.2870365587
Short name T665
Test name
Test status
Simulation time 14979665408 ps
CPU time 7.17 seconds
Started Jul 20 04:41:07 PM PDT 24
Finished Jul 20 04:41:15 PM PDT 24
Peak memory 201716 kb
Host smart-6bb5bdae-45c3-4355-add1-c4bc5986db3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870365587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.2870365587
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.950601183
Short name T243
Test name
Test status
Simulation time 36965398266 ps
CPU time 82.8 seconds
Started Jul 20 04:41:00 PM PDT 24
Finished Jul 20 04:42:24 PM PDT 24
Peak memory 210100 kb
Host smart-13f55577-8467-4d61-aa0b-1711dfabcbf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950601183 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.950601183
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1077621079
Short name T574
Test name
Test status
Simulation time 3548358027 ps
CPU time 6.62 seconds
Started Jul 20 04:41:01 PM PDT 24
Finished Jul 20 04:41:08 PM PDT 24
Peak memory 201460 kb
Host smart-60752623-9603-43f1-8877-e19eac1ff080
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077621079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.1077621079
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.1299323541
Short name T689
Test name
Test status
Simulation time 2032614876 ps
CPU time 1.92 seconds
Started Jul 20 04:41:13 PM PDT 24
Finished Jul 20 04:41:15 PM PDT 24
Peak memory 201480 kb
Host smart-5be24d41-1b64-4e65-8685-7c7e50f1266d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299323541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.1299323541
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.591875458
Short name T468
Test name
Test status
Simulation time 3528051576 ps
CPU time 9.23 seconds
Started Jul 20 04:41:01 PM PDT 24
Finished Jul 20 04:41:11 PM PDT 24
Peak memory 201524 kb
Host smart-f916aa5e-cc09-4a27-92eb-9193f811f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591875458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.591875458
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2763297361
Short name T1
Test name
Test status
Simulation time 175157950060 ps
CPU time 452.25 seconds
Started Jul 20 04:41:02 PM PDT 24
Finished Jul 20 04:48:35 PM PDT 24
Peak memory 201748 kb
Host smart-f401e81a-0e35-4ccb-b5e5-f82d2ebefac1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763297361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.2763297361
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1691973811
Short name T127
Test name
Test status
Simulation time 2397162757 ps
CPU time 6.7 seconds
Started Jul 20 04:41:09 PM PDT 24
Finished Jul 20 04:41:17 PM PDT 24
Peak memory 201536 kb
Host smart-8d754f8a-b117-4bf3-b646-b43a25579354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691973811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1691973811
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3666836100
Short name T333
Test name
Test status
Simulation time 2521028981 ps
CPU time 2.2 seconds
Started Jul 20 04:41:02 PM PDT 24
Finished Jul 20 04:41:05 PM PDT 24
Peak memory 201480 kb
Host smart-809f4aa9-ac13-4c51-97e2-6f0b7a378f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666836100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3666836100
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2763436081
Short name T52
Test name
Test status
Simulation time 53282502334 ps
CPU time 37.83 seconds
Started Jul 20 04:41:06 PM PDT 24
Finished Jul 20 04:41:45 PM PDT 24
Peak memory 201784 kb
Host smart-12ea57ec-afe3-4116-b083-961b0613e492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763436081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2763436081
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2717563857
Short name T325
Test name
Test status
Simulation time 4422367578 ps
CPU time 3.58 seconds
Started Jul 20 04:41:04 PM PDT 24
Finished Jul 20 04:41:08 PM PDT 24
Peak memory 201440 kb
Host smart-6665d1d1-fea1-4385-b43e-e80e5159c265
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717563857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.2717563857
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1681247990
Short name T45
Test name
Test status
Simulation time 2708307224 ps
CPU time 1.99 seconds
Started Jul 20 04:41:03 PM PDT 24
Finished Jul 20 04:41:05 PM PDT 24
Peak memory 201476 kb
Host smart-5bb8e8a5-ee7d-433c-9c24-eaca8aa99d03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681247990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1681247990
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2091973493
Short name T232
Test name
Test status
Simulation time 2626593718 ps
CPU time 2.48 seconds
Started Jul 20 04:41:05 PM PDT 24
Finished Jul 20 04:41:08 PM PDT 24
Peak memory 201448 kb
Host smart-0602b3fd-b2f9-432c-8fb4-7e2115c5e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091973493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2091973493
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.1133606594
Short name T4
Test name
Test status
Simulation time 2468694854 ps
CPU time 7.2 seconds
Started Jul 20 04:41:02 PM PDT 24
Finished Jul 20 04:41:10 PM PDT 24
Peak memory 199644 kb
Host smart-258f3e23-3edd-4a41-8638-505e19d07b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133606594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.1133606594
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.853411157
Short name T403
Test name
Test status
Simulation time 2240162712 ps
CPU time 6.05 seconds
Started Jul 20 04:41:04 PM PDT 24
Finished Jul 20 04:41:11 PM PDT 24
Peak memory 201548 kb
Host smart-adb1efdf-477d-4bc9-a590-12e1a9ca3c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853411157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.853411157
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.438159159
Short name T448
Test name
Test status
Simulation time 2507941837 ps
CPU time 7.47 seconds
Started Jul 20 04:41:05 PM PDT 24
Finished Jul 20 04:41:13 PM PDT 24
Peak memory 201464 kb
Host smart-31ab30d5-c123-43a0-9144-01e0d64c1084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438159159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.438159159
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.220287920
Short name T219
Test name
Test status
Simulation time 42009989770 ps
CPU time 116.01 seconds
Started Jul 20 04:41:08 PM PDT 24
Finished Jul 20 04:43:05 PM PDT 24
Peak memory 220936 kb
Host smart-7bc0af20-8c84-4141-89cc-07221b97e5b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220287920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.220287920
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2184197753
Short name T63
Test name
Test status
Simulation time 2116257778 ps
CPU time 3.24 seconds
Started Jul 20 04:41:01 PM PDT 24
Finished Jul 20 04:41:04 PM PDT 24
Peak memory 201364 kb
Host smart-d42c64ee-7cd3-4ffc-968e-5d79d026e908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184197753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2184197753
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.3171682200
Short name T311
Test name
Test status
Simulation time 6482582326 ps
CPU time 4.73 seconds
Started Jul 20 04:41:03 PM PDT 24
Finished Jul 20 04:41:08 PM PDT 24
Peak memory 201456 kb
Host smart-15c38595-eacf-4607-8513-efbba5d78755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171682200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.3171682200
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3376682395
Short name T146
Test name
Test status
Simulation time 7466331869 ps
CPU time 2.06 seconds
Started Jul 20 04:41:04 PM PDT 24
Finished Jul 20 04:41:07 PM PDT 24
Peak memory 201464 kb
Host smart-697b45ea-2431-4f6c-b37c-ff14748cc392
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376682395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.3376682395
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.1211525202
Short name T747
Test name
Test status
Simulation time 2010240918 ps
CPU time 5.76 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:35 PM PDT 24
Peak memory 201456 kb
Host smart-e3549831-ca77-4045-8c2a-f5df4b4ee9d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211525202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.1211525202
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.837989630
Short name T644
Test name
Test status
Simulation time 26095501185 ps
CPU time 23.45 seconds
Started Jul 20 04:41:29 PM PDT 24
Finished Jul 20 04:41:54 PM PDT 24
Peak memory 201780 kb
Host smart-ea8ddbaa-07a4-430d-a52e-05b76581443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837989630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_wi
th_pre_cond.837989630
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.307998263
Short name T596
Test name
Test status
Simulation time 4454085045 ps
CPU time 2.28 seconds
Started Jul 20 04:41:30 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201340 kb
Host smart-3abf1669-cdb2-4513-9f65-33cab6c8fa9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307998263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ec_pwr_on_rst.307998263
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.425486051
Short name T181
Test name
Test status
Simulation time 3764763616 ps
CPU time 8.16 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 201428 kb
Host smart-6379ed0a-4786-4558-bcb6-abd6f0a26c8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425486051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctr
l_edge_detect.425486051
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2418397835
Short name T493
Test name
Test status
Simulation time 2625279188 ps
CPU time 2.61 seconds
Started Jul 20 04:41:30 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 201688 kb
Host smart-cc7d2fb0-9a74-4de5-aa97-8cde0390eda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418397835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2418397835
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1377142737
Short name T78
Test name
Test status
Simulation time 2485024826 ps
CPU time 2.52 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:41:29 PM PDT 24
Peak memory 201444 kb
Host smart-983cd8c2-689f-4732-a49d-39902a3a002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377142737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1377142737
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.1720778058
Short name T791
Test name
Test status
Simulation time 2293546078 ps
CPU time 1 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:30 PM PDT 24
Peak memory 201452 kb
Host smart-e5cabf3f-098e-41ea-8cf4-c247313501b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720778058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.1720778058
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1022770663
Short name T764
Test name
Test status
Simulation time 2520295560 ps
CPU time 4.61 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201536 kb
Host smart-f6ba9ede-18f9-4f78-af04-823adc175918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022770663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1022770663
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.1836678914
Short name T84
Test name
Test status
Simulation time 2108743103 ps
CPU time 6.27 seconds
Started Jul 20 04:41:27 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 201376 kb
Host smart-bae014c6-802d-4a1d-8900-7e379b81256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836678914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.1836678914
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.3882452374
Short name T133
Test name
Test status
Simulation time 15122288334 ps
CPU time 34.25 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:42:03 PM PDT 24
Peak memory 201472 kb
Host smart-a4e92501-1e48-47f3-9226-29c4e97964c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882452374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.3882452374
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1882931207
Short name T194
Test name
Test status
Simulation time 133979145229 ps
CPU time 83.04 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:42:53 PM PDT 24
Peak memory 210012 kb
Host smart-044d568b-72b8-43a5-ae39-47c46808b3b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882931207 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1882931207
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.4294627217
Short name T503
Test name
Test status
Simulation time 4084677755 ps
CPU time 3.38 seconds
Started Jul 20 04:41:27 PM PDT 24
Finished Jul 20 04:41:31 PM PDT 24
Peak memory 201440 kb
Host smart-b77fb5f0-7bfe-446b-8811-a1552a98ddfc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294627217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.4294627217
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.2752440445
Short name T510
Test name
Test status
Simulation time 2107889812 ps
CPU time 0.94 seconds
Started Jul 20 04:41:32 PM PDT 24
Finished Jul 20 04:41:35 PM PDT 24
Peak memory 201460 kb
Host smart-72fe94ef-b8b0-48be-8ded-9d2880a64736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752440445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.2752440445
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2015127918
Short name T496
Test name
Test status
Simulation time 3425247069 ps
CPU time 3.11 seconds
Started Jul 20 04:41:30 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 201748 kb
Host smart-25d01020-552c-48db-9e5d-feeaf8057c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015127918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
015127918
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.586796531
Short name T464
Test name
Test status
Simulation time 26347561571 ps
CPU time 20.57 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:50 PM PDT 24
Peak memory 201852 kb
Host smart-dd5d5bae-c1d9-4a6a-a2b1-8b6286ea3fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586796531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_wi
th_pre_cond.586796531
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2168044032
Short name T682
Test name
Test status
Simulation time 3703495489 ps
CPU time 5.64 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201448 kb
Host smart-a9a02190-6a15-41c6-a0d4-14cb15ac437d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168044032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.2168044032
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.949939166
Short name T779
Test name
Test status
Simulation time 2571314547 ps
CPU time 2.32 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:41:29 PM PDT 24
Peak memory 201536 kb
Host smart-dbee0b4a-f9b8-4e36-a4cb-2cff54a5e37c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949939166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctr
l_edge_detect.949939166
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1293202251
Short name T793
Test name
Test status
Simulation time 2613717104 ps
CPU time 3.85 seconds
Started Jul 20 04:41:27 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201476 kb
Host smart-0e7ee417-fd41-4034-8da7-5ad08b29f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293202251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1293202251
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3878465985
Short name T489
Test name
Test status
Simulation time 2465459237 ps
CPU time 7.53 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 201464 kb
Host smart-fda0fc35-7035-4aa6-a5c5-9aefe6b15392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878465985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3878465985
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.2391554469
Short name T330
Test name
Test status
Simulation time 2199664738 ps
CPU time 5.79 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:35 PM PDT 24
Peak memory 201396 kb
Host smart-cd1baa3f-a575-4a44-8810-784ddf8523a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391554469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.2391554469
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2151785865
Short name T660
Test name
Test status
Simulation time 2510743834 ps
CPU time 7.5 seconds
Started Jul 20 04:41:24 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201436 kb
Host smart-92fdd2ca-d828-4645-ba61-fb8c5c1a91c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151785865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2151785865
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.3996052253
Short name T527
Test name
Test status
Simulation time 2117809454 ps
CPU time 3.36 seconds
Started Jul 20 04:41:30 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 201288 kb
Host smart-052bc0bb-6fe1-4f4e-b24f-f59e280224cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996052253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.3996052253
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2122695310
Short name T300
Test name
Test status
Simulation time 38359588832 ps
CPU time 5.86 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 210088 kb
Host smart-ec6a5bc0-7365-4761-a774-875ca57da9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122695310 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2122695310
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1026291181
Short name T587
Test name
Test status
Simulation time 4255151243 ps
CPU time 1.26 seconds
Started Jul 20 04:41:30 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201340 kb
Host smart-b01a9206-8b19-4a95-bc65-00c3db5d42bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026291181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1026291181
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.447174097
Short name T436
Test name
Test status
Simulation time 2012396315 ps
CPU time 5.97 seconds
Started Jul 20 04:41:33 PM PDT 24
Finished Jul 20 04:41:40 PM PDT 24
Peak memory 201468 kb
Host smart-7ab5f271-a7b0-491f-a49a-51c18486a309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447174097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_tes
t.447174097
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3208525542
Short name T156
Test name
Test status
Simulation time 3562451381 ps
CPU time 5.71 seconds
Started Jul 20 04:41:34 PM PDT 24
Finished Jul 20 04:41:41 PM PDT 24
Peak memory 201540 kb
Host smart-410928ae-d693-4d03-8196-7990c268a032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208525542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3
208525542
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1127281035
Short name T355
Test name
Test status
Simulation time 150757563315 ps
CPU time 39.09 seconds
Started Jul 20 04:41:35 PM PDT 24
Finished Jul 20 04:42:15 PM PDT 24
Peak memory 201732 kb
Host smart-4b54a21a-d326-434e-a738-4c67b81c9be1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127281035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1127281035
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3695026472
Short name T220
Test name
Test status
Simulation time 30877452668 ps
CPU time 75.48 seconds
Started Jul 20 04:41:32 PM PDT 24
Finished Jul 20 04:42:49 PM PDT 24
Peak memory 201848 kb
Host smart-36520d92-3418-4d95-9f3f-4a8a01a9e02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695026472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.3695026472
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2666324558
Short name T121
Test name
Test status
Simulation time 2553747321 ps
CPU time 2.5 seconds
Started Jul 20 04:41:33 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 201412 kb
Host smart-976a0608-3cf5-4f46-bb70-92cf59fab82b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666324558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.2666324558
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.1223916944
Short name T230
Test name
Test status
Simulation time 2479179503 ps
CPU time 1.19 seconds
Started Jul 20 04:41:33 PM PDT 24
Finished Jul 20 04:41:36 PM PDT 24
Peak memory 201520 kb
Host smart-18868414-6638-4f44-9efd-2ed9253cef5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223916944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.1223916944
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.4278480871
Short name T124
Test name
Test status
Simulation time 2619554238 ps
CPU time 3.68 seconds
Started Jul 20 04:41:36 PM PDT 24
Finished Jul 20 04:41:41 PM PDT 24
Peak memory 201452 kb
Host smart-268e8c3d-c55f-4225-9e43-d1f71c7ebb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278480871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.4278480871
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2654515988
Short name T327
Test name
Test status
Simulation time 2463928659 ps
CPU time 7.2 seconds
Started Jul 20 04:41:33 PM PDT 24
Finished Jul 20 04:41:41 PM PDT 24
Peak memory 201540 kb
Host smart-6623fb69-a54a-4961-87ac-23de18a9f00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654515988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2654515988
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.887642397
Short name T411
Test name
Test status
Simulation time 2190647470 ps
CPU time 2.04 seconds
Started Jul 20 04:41:34 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 201440 kb
Host smart-c4eb447d-9d70-4560-8d3c-ca9970a26e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887642397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.887642397
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3451334785
Short name T629
Test name
Test status
Simulation time 2552657404 ps
CPU time 1.7 seconds
Started Jul 20 04:41:35 PM PDT 24
Finished Jul 20 04:41:38 PM PDT 24
Peak memory 201448 kb
Host smart-3c66f281-a861-4ea5-ba90-35b2f9702aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451334785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3451334785
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.835394568
Short name T73
Test name
Test status
Simulation time 2107429607 ps
CPU time 5.43 seconds
Started Jul 20 04:41:35 PM PDT 24
Finished Jul 20 04:41:41 PM PDT 24
Peak memory 201424 kb
Host smart-f340c7f7-238e-46a4-a173-433915c871ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835394568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.835394568
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.2304631573
Short name T240
Test name
Test status
Simulation time 17493448031 ps
CPU time 4.63 seconds
Started Jul 20 04:41:36 PM PDT 24
Finished Jul 20 04:41:42 PM PDT 24
Peak memory 201576 kb
Host smart-e009c292-6984-4dfd-b4c5-148eb8dd4353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304631573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.2304631573
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.256165636
Short name T104
Test name
Test status
Simulation time 7618137751 ps
CPU time 1.94 seconds
Started Jul 20 04:41:32 PM PDT 24
Finished Jul 20 04:41:35 PM PDT 24
Peak memory 201528 kb
Host smart-15b4da1d-e791-4b8f-a828-61e6bc48e026
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256165636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ultra_low_pwr.256165636
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.455357163
Short name T522
Test name
Test status
Simulation time 2010603142 ps
CPU time 6.08 seconds
Started Jul 20 04:41:32 PM PDT 24
Finished Jul 20 04:41:39 PM PDT 24
Peak memory 201444 kb
Host smart-406603b9-30c0-46ec-8cb4-638e8131fdcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455357163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_tes
t.455357163
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2952227934
Short name T614
Test name
Test status
Simulation time 3713046705 ps
CPU time 2.18 seconds
Started Jul 20 04:41:32 PM PDT 24
Finished Jul 20 04:41:36 PM PDT 24
Peak memory 201448 kb
Host smart-dffda3f4-36e3-4bf8-a50c-b7914b991bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952227934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2
952227934
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.4253881174
Short name T249
Test name
Test status
Simulation time 164267449865 ps
CPU time 106.79 seconds
Started Jul 20 04:41:34 PM PDT 24
Finished Jul 20 04:43:22 PM PDT 24
Peak memory 201804 kb
Host smart-9e8dce63-2aef-4fc1-bdf4-89bde68a528c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253881174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.4253881174
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3983628803
Short name T413
Test name
Test status
Simulation time 3580484819 ps
CPU time 2.81 seconds
Started Jul 20 04:41:36 PM PDT 24
Finished Jul 20 04:41:40 PM PDT 24
Peak memory 201520 kb
Host smart-762b1ba8-eee4-4dc2-a264-1f3f9af10838
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983628803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.3983628803
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.81166595
Short name T563
Test name
Test status
Simulation time 3122489607 ps
CPU time 5 seconds
Started Jul 20 04:41:34 PM PDT 24
Finished Jul 20 04:41:40 PM PDT 24
Peak memory 201460 kb
Host smart-4d8888fc-e9ad-4e43-8fed-f526f323048a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81166595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl
_edge_detect.81166595
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.191128028
Short name T570
Test name
Test status
Simulation time 2613997936 ps
CPU time 4.07 seconds
Started Jul 20 04:41:33 PM PDT 24
Finished Jul 20 04:41:39 PM PDT 24
Peak memory 201460 kb
Host smart-add156b6-a209-4791-b38c-81b4621d7dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191128028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.191128028
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.686086332
Short name T79
Test name
Test status
Simulation time 2484239481 ps
CPU time 2.16 seconds
Started Jul 20 04:41:31 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 201712 kb
Host smart-90beb771-d39f-4620-8e27-f812c40b6596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686086332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.686086332
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.832865655
Short name T423
Test name
Test status
Simulation time 2076707996 ps
CPU time 1.3 seconds
Started Jul 20 04:41:36 PM PDT 24
Finished Jul 20 04:41:38 PM PDT 24
Peak memory 201368 kb
Host smart-f537735d-69fc-4b2e-a189-a8e00184154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832865655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.832865655
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.964798249
Short name T494
Test name
Test status
Simulation time 2517528971 ps
CPU time 3.92 seconds
Started Jul 20 04:41:35 PM PDT 24
Finished Jul 20 04:41:40 PM PDT 24
Peak memory 201684 kb
Host smart-42e38c65-ba50-4e39-9c5c-f753bd12dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964798249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.964798249
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.2598805728
Short name T582
Test name
Test status
Simulation time 2127562359 ps
CPU time 2 seconds
Started Jul 20 04:41:36 PM PDT 24
Finished Jul 20 04:41:39 PM PDT 24
Peak memory 201376 kb
Host smart-9ae7b7ff-8187-4d71-a719-1c2186bdc11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598805728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2598805728
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.351661065
Short name T135
Test name
Test status
Simulation time 350314777871 ps
CPU time 11.99 seconds
Started Jul 20 04:41:32 PM PDT 24
Finished Jul 20 04:41:44 PM PDT 24
Peak memory 201964 kb
Host smart-65e754c3-a863-4b23-a1dd-c4c7d2ea062b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351661065 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.351661065
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3949822315
Short name T435
Test name
Test status
Simulation time 4129874379 ps
CPU time 2.06 seconds
Started Jul 20 04:41:34 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 201516 kb
Host smart-6b28b0f4-dab2-4675-9115-bdcbf070890c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949822315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.3949822315
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.1528413096
Short name T706
Test name
Test status
Simulation time 2011098573 ps
CPU time 5.88 seconds
Started Jul 20 04:41:49 PM PDT 24
Finished Jul 20 04:41:56 PM PDT 24
Peak memory 201500 kb
Host smart-96bbbe19-b8bd-42cd-90b3-2d6ab66bbc71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528413096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.1528413096
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3192847476
Short name T536
Test name
Test status
Simulation time 3511007282 ps
CPU time 7.76 seconds
Started Jul 20 04:41:44 PM PDT 24
Finished Jul 20 04:41:53 PM PDT 24
Peak memory 201536 kb
Host smart-7c2e0b6c-4d13-4fe1-b6f9-ae88ed3224f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192847476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.3
192847476
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3630851362
Short name T2
Test name
Test status
Simulation time 93106089530 ps
CPU time 26.43 seconds
Started Jul 20 04:41:41 PM PDT 24
Finished Jul 20 04:42:09 PM PDT 24
Peak memory 201704 kb
Host smart-542e85d5-d4df-4a41-b5fa-ca502870de9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630851362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3630851362
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1120462
Short name T600
Test name
Test status
Simulation time 48699910672 ps
CPU time 11.26 seconds
Started Jul 20 04:41:43 PM PDT 24
Finished Jul 20 04:41:55 PM PDT 24
Peak memory 201780 kb
Host smart-e7302328-67d2-4f97-82bc-6219a947b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with
_pre_cond.1120462
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3669053182
Short name T794
Test name
Test status
Simulation time 2738675369 ps
CPU time 8.18 seconds
Started Jul 20 04:41:52 PM PDT 24
Finished Jul 20 04:42:01 PM PDT 24
Peak memory 201408 kb
Host smart-0d3b9110-87a1-413e-8578-161859b2fd35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669053182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.3669053182
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1720445452
Short name T517
Test name
Test status
Simulation time 2612319007 ps
CPU time 7.05 seconds
Started Jul 20 04:41:34 PM PDT 24
Finished Jul 20 04:41:42 PM PDT 24
Peak memory 201520 kb
Host smart-bb9e142c-0542-474a-b0c2-e830dba33fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720445452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1720445452
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.2179622316
Short name T313
Test name
Test status
Simulation time 2496228723 ps
CPU time 2.33 seconds
Started Jul 20 04:41:36 PM PDT 24
Finished Jul 20 04:41:39 PM PDT 24
Peak memory 201540 kb
Host smart-0c9ae62d-b740-4ffc-a377-28115b8eef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179622316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.2179622316
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2924752914
Short name T521
Test name
Test status
Simulation time 2275386009 ps
CPU time 2.11 seconds
Started Jul 20 04:41:37 PM PDT 24
Finished Jul 20 04:41:40 PM PDT 24
Peak memory 201436 kb
Host smart-e05495fe-16d9-431f-806e-c9d8ea4169d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924752914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2924752914
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1675097811
Short name T20
Test name
Test status
Simulation time 2639411487 ps
CPU time 1.28 seconds
Started Jul 20 04:41:35 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 201460 kb
Host smart-10659d08-d601-477e-880a-9be37add3c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675097811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1675097811
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3525316344
Short name T535
Test name
Test status
Simulation time 2135490260 ps
CPU time 1.83 seconds
Started Jul 20 04:41:34 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 201396 kb
Host smart-22af9402-730a-41e8-8b3e-e187aa1a2a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525316344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3525316344
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2915850371
Short name T567
Test name
Test status
Simulation time 16590166135 ps
CPU time 43.27 seconds
Started Jul 20 04:41:43 PM PDT 24
Finished Jul 20 04:42:27 PM PDT 24
Peak memory 201508 kb
Host smart-5b283095-59b2-41bd-b0fe-05cecdb02fba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915850371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2915850371
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1324916093
Short name T320
Test name
Test status
Simulation time 20796254267 ps
CPU time 46.79 seconds
Started Jul 20 04:41:42 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 210048 kb
Host smart-6627c2e5-b8db-482c-b1eb-f52c6565deaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324916093 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1324916093
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2955623072
Short name T648
Test name
Test status
Simulation time 2725275697 ps
CPU time 3.91 seconds
Started Jul 20 04:41:47 PM PDT 24
Finished Jul 20 04:41:51 PM PDT 24
Peak memory 201436 kb
Host smart-788ddf16-0922-43f6-a6ce-17a5c65f3391
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955623072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.2955623072
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.454480832
Short name T414
Test name
Test status
Simulation time 2008667774 ps
CPU time 5.7 seconds
Started Jul 20 04:41:44 PM PDT 24
Finished Jul 20 04:41:51 PM PDT 24
Peak memory 201476 kb
Host smart-10c3a7e3-1380-475f-8ab5-3848f349ee99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454480832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.454480832
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3792511079
Short name T783
Test name
Test status
Simulation time 3363983579 ps
CPU time 9.11 seconds
Started Jul 20 04:41:46 PM PDT 24
Finished Jul 20 04:41:56 PM PDT 24
Peak memory 201528 kb
Host smart-070c1c5b-2b73-4f5c-b530-266d5c464af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792511079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.3
792511079
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2513140185
Short name T114
Test name
Test status
Simulation time 121812437527 ps
CPU time 163.3 seconds
Started Jul 20 04:41:49 PM PDT 24
Finished Jul 20 04:44:33 PM PDT 24
Peak memory 201700 kb
Host smart-d911105b-a946-46aa-9630-7e6062e201c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513140185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2513140185
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1685802459
Short name T410
Test name
Test status
Simulation time 569057593317 ps
CPU time 204.83 seconds
Started Jul 20 04:41:43 PM PDT 24
Finished Jul 20 04:45:09 PM PDT 24
Peak memory 201492 kb
Host smart-a810800b-f8cf-48a2-a908-ce61ca021d44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685802459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.1685802459
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3650797290
Short name T180
Test name
Test status
Simulation time 2966075472 ps
CPU time 4.54 seconds
Started Jul 20 04:41:45 PM PDT 24
Finished Jul 20 04:41:50 PM PDT 24
Peak memory 201448 kb
Host smart-d17b93bc-cd56-4c6f-937f-260814d27430
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650797290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.3650797290
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.591810280
Short name T449
Test name
Test status
Simulation time 2630934491 ps
CPU time 2.28 seconds
Started Jul 20 04:41:44 PM PDT 24
Finished Jul 20 04:41:47 PM PDT 24
Peak memory 201512 kb
Host smart-52808f1c-73cd-4eed-9add-326534dcf8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591810280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.591810280
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2873193904
Short name T315
Test name
Test status
Simulation time 2464359838 ps
CPU time 3.77 seconds
Started Jul 20 04:41:45 PM PDT 24
Finished Jul 20 04:41:50 PM PDT 24
Peak memory 201464 kb
Host smart-55e1b614-3d60-46e3-bae1-18f8403446be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873193904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2873193904
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.2643263401
Short name T458
Test name
Test status
Simulation time 2234328596 ps
CPU time 1.86 seconds
Started Jul 20 04:41:42 PM PDT 24
Finished Jul 20 04:41:45 PM PDT 24
Peak memory 201528 kb
Host smart-77c36f6c-458f-44d0-a4bf-76c1a7bf77c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643263401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.2643263401
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1614571403
Short name T157
Test name
Test status
Simulation time 2516857547 ps
CPU time 3.79 seconds
Started Jul 20 04:41:50 PM PDT 24
Finished Jul 20 04:41:54 PM PDT 24
Peak memory 201448 kb
Host smart-95e4e272-cddb-4b92-b3a6-e9421391f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614571403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.1614571403
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.2243092882
Short name T492
Test name
Test status
Simulation time 2111206925 ps
CPU time 5.87 seconds
Started Jul 20 04:41:45 PM PDT 24
Finished Jul 20 04:41:52 PM PDT 24
Peak memory 201400 kb
Host smart-e884feb6-26c9-40a0-9d14-cf01577c4310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243092882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.2243092882
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.1832502229
Short name T329
Test name
Test status
Simulation time 149701470903 ps
CPU time 97.82 seconds
Started Jul 20 04:41:41 PM PDT 24
Finished Jul 20 04:43:20 PM PDT 24
Peak memory 201732 kb
Host smart-db434ea8-fa06-4ebc-910b-95cfbf22c516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832502229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.1832502229
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1066324975
Short name T158
Test name
Test status
Simulation time 57432722586 ps
CPU time 143.28 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 210028 kb
Host smart-85657052-6d4d-422e-90cf-507610edbbfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066324975 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.1066324975
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.3107849561
Short name T416
Test name
Test status
Simulation time 2017585249 ps
CPU time 3.22 seconds
Started Jul 20 04:41:43 PM PDT 24
Finished Jul 20 04:41:47 PM PDT 24
Peak memory 201468 kb
Host smart-4f7cfcfc-bdd2-4c00-bfd9-092215828f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107849561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.3107849561
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3940004997
Short name T109
Test name
Test status
Simulation time 4004957655 ps
CPU time 3.17 seconds
Started Jul 20 04:41:56 PM PDT 24
Finished Jul 20 04:42:00 PM PDT 24
Peak memory 201604 kb
Host smart-9854a991-8efa-4836-a322-4f120749825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940004997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3
940004997
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.570573894
Short name T274
Test name
Test status
Simulation time 76747476010 ps
CPU time 50.25 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:42:42 PM PDT 24
Peak memory 201588 kb
Host smart-7a752552-830b-44a5-9f03-cc2e22fc1e0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570573894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_combo_detect.570573894
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2388927598
Short name T261
Test name
Test status
Simulation time 76657804913 ps
CPU time 51.41 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:42:43 PM PDT 24
Peak memory 201884 kb
Host smart-2d00115f-85b9-4dcb-a974-4b8377faae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388927598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2388927598
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2184031350
Short name T18
Test name
Test status
Simulation time 5124983646 ps
CPU time 2.55 seconds
Started Jul 20 04:41:48 PM PDT 24
Finished Jul 20 04:41:51 PM PDT 24
Peak memory 201516 kb
Host smart-b7873ec2-750a-4eb8-8be0-4304562b518c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184031350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.2184031350
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.1985656046
Short name T702
Test name
Test status
Simulation time 3127134080 ps
CPU time 1.33 seconds
Started Jul 20 04:41:45 PM PDT 24
Finished Jul 20 04:41:47 PM PDT 24
Peak memory 201464 kb
Host smart-340508d7-6caf-4a0b-a9f1-6754f80ed70b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985656046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.1985656046
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3947870769
Short name T309
Test name
Test status
Simulation time 2615348904 ps
CPU time 4.23 seconds
Started Jul 20 04:41:42 PM PDT 24
Finished Jul 20 04:41:47 PM PDT 24
Peak memory 201460 kb
Host smart-ab584fb4-04fa-49fc-8e93-c95478bba1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947870769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3947870769
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.3725253651
Short name T76
Test name
Test status
Simulation time 2543882904 ps
CPU time 1.25 seconds
Started Jul 20 04:41:44 PM PDT 24
Finished Jul 20 04:41:46 PM PDT 24
Peak memory 201476 kb
Host smart-5475225d-a4e9-4984-8adf-1a00407248d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725253651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3725253651
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1696066150
Short name T415
Test name
Test status
Simulation time 2220445529 ps
CPU time 3.32 seconds
Started Jul 20 04:41:41 PM PDT 24
Finished Jul 20 04:41:45 PM PDT 24
Peak memory 201440 kb
Host smart-d77348ea-8ec3-427f-84eb-758a8b539d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696066150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1696066150
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.951230897
Short name T670
Test name
Test status
Simulation time 2511677082 ps
CPU time 7.35 seconds
Started Jul 20 04:41:48 PM PDT 24
Finished Jul 20 04:41:56 PM PDT 24
Peak memory 201468 kb
Host smart-0dde6b58-2e41-495a-a837-b459a99b43ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951230897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.951230897
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.49095074
Short name T556
Test name
Test status
Simulation time 2141310470 ps
CPU time 2.11 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:41:57 PM PDT 24
Peak memory 201612 kb
Host smart-56f5bff5-89f3-4cc6-bebc-e090891d7ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49095074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.49095074
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.460686472
Short name T142
Test name
Test status
Simulation time 1240730364588 ps
CPU time 35.06 seconds
Started Jul 20 04:41:50 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201512 kb
Host smart-d492d84a-03ba-4b71-ba47-417e1a3bde12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460686472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_st
ress_all.460686472
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.584077252
Short name T136
Test name
Test status
Simulation time 150108118664 ps
CPU time 24.11 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:42:17 PM PDT 24
Peak memory 212768 kb
Host smart-1f112d2e-67e6-4ef1-9149-b5811017465e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584077252 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.584077252
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.157530796
Short name T130
Test name
Test status
Simulation time 7059401265 ps
CPU time 1.27 seconds
Started Jul 20 04:41:49 PM PDT 24
Finished Jul 20 04:41:51 PM PDT 24
Peak memory 201428 kb
Host smart-c637b9f8-18d2-4939-8686-e2e8a2301892
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157530796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ultra_low_pwr.157530796
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1601741236
Short name T564
Test name
Test status
Simulation time 2025618416 ps
CPU time 3.07 seconds
Started Jul 20 04:41:52 PM PDT 24
Finished Jul 20 04:41:56 PM PDT 24
Peak memory 201528 kb
Host smart-7dd0ff44-f26c-4a05-869f-3bb1c6ab612e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601741236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1601741236
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1082053882
Short name T207
Test name
Test status
Simulation time 3542241875 ps
CPU time 9.49 seconds
Started Jul 20 04:41:44 PM PDT 24
Finished Jul 20 04:41:54 PM PDT 24
Peak memory 201536 kb
Host smart-76e7b790-65b3-49ba-88ad-168e386114d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082053882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
082053882
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.2612478982
Short name T279
Test name
Test status
Simulation time 108725463093 ps
CPU time 68.87 seconds
Started Jul 20 04:41:43 PM PDT 24
Finished Jul 20 04:42:53 PM PDT 24
Peak memory 201664 kb
Host smart-eef65861-f77c-49ce-90d7-c4acbef08e28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612478982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.2612478982
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2807891190
Short name T351
Test name
Test status
Simulation time 40807741803 ps
CPU time 108.54 seconds
Started Jul 20 04:41:47 PM PDT 24
Finished Jul 20 04:43:36 PM PDT 24
Peak memory 201864 kb
Host smart-e250df00-863f-452a-aa71-18d7db726320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807891190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.2807891190
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2123280169
Short name T646
Test name
Test status
Simulation time 3253600289 ps
CPU time 1.04 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:41:56 PM PDT 24
Peak memory 201420 kb
Host smart-27f7fb6c-1ef9-4133-a353-320751041e55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123280169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.2123280169
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1369298365
Short name T713
Test name
Test status
Simulation time 2875448633 ps
CPU time 2.35 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:41:54 PM PDT 24
Peak memory 201440 kb
Host smart-c64fd7db-985b-4276-87ea-1c0c9a0e2eb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369298365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.1369298365
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3183946899
Short name T173
Test name
Test status
Simulation time 2610732276 ps
CPU time 7.64 seconds
Started Jul 20 04:41:55 PM PDT 24
Finished Jul 20 04:42:04 PM PDT 24
Peak memory 201452 kb
Host smart-63433eea-aef5-4458-9a3e-8b5af4b0dc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183946899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.3183946899
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.4055535281
Short name T314
Test name
Test status
Simulation time 2465761974 ps
CPU time 2.49 seconds
Started Jul 20 04:41:55 PM PDT 24
Finished Jul 20 04:41:59 PM PDT 24
Peak memory 201468 kb
Host smart-1f0a9010-c6a0-4cc8-9111-68fa07d9d7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055535281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.4055535281
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.259037659
Short name T260
Test name
Test status
Simulation time 2223476280 ps
CPU time 3.87 seconds
Started Jul 20 04:41:42 PM PDT 24
Finished Jul 20 04:41:46 PM PDT 24
Peak memory 201520 kb
Host smart-a8686f3f-e37f-4493-9e04-377562739e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259037659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.259037659
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2606667157
Short name T590
Test name
Test status
Simulation time 2531058616 ps
CPU time 2.28 seconds
Started Jul 20 04:41:41 PM PDT 24
Finished Jul 20 04:41:44 PM PDT 24
Peak memory 201340 kb
Host smart-7e1f0a93-ce01-485e-93e3-b71aca9d61c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606667157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2606667157
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.1056732092
Short name T577
Test name
Test status
Simulation time 2110798992 ps
CPU time 5.91 seconds
Started Jul 20 04:41:48 PM PDT 24
Finished Jul 20 04:41:55 PM PDT 24
Peak memory 201396 kb
Host smart-be4e2b5e-17ef-4617-a973-91935ec2d8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056732092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.1056732092
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.245457553
Short name T30
Test name
Test status
Simulation time 14304064687 ps
CPU time 18.73 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:42:14 PM PDT 24
Peak memory 201516 kb
Host smart-9abf234a-c34b-41c5-acff-6ddc1e5b4129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245457553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_st
ress_all.245457553
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2000459712
Short name T318
Test name
Test status
Simulation time 80814926120 ps
CPU time 98.47 seconds
Started Jul 20 04:41:41 PM PDT 24
Finished Jul 20 04:43:20 PM PDT 24
Peak memory 210136 kb
Host smart-4b46bae2-ffd2-41b3-a081-f08c5cbc015e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000459712 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.2000459712
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3171235029
Short name T737
Test name
Test status
Simulation time 7223094328 ps
CPU time 7.23 seconds
Started Jul 20 04:41:43 PM PDT 24
Finished Jul 20 04:41:51 PM PDT 24
Peak memory 201448 kb
Host smart-e0a3a59d-814c-46e8-9849-d71a087df16b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171235029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.3171235029
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1954756541
Short name T581
Test name
Test status
Simulation time 3621543384 ps
CPU time 3.07 seconds
Started Jul 20 04:41:59 PM PDT 24
Finished Jul 20 04:42:02 PM PDT 24
Peak memory 201508 kb
Host smart-28174bdc-d512-42b4-af91-1434c7df52bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954756541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
954756541
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.2069538621
Short name T213
Test name
Test status
Simulation time 116887432244 ps
CPU time 150.47 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:44:33 PM PDT 24
Peak memory 201732 kb
Host smart-64951d22-2929-42e6-98fb-53429977feb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069538621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.2069538621
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.889055304
Short name T637
Test name
Test status
Simulation time 3825345785 ps
CPU time 3.17 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:41:55 PM PDT 24
Peak memory 201520 kb
Host smart-40c90215-d5d4-4062-9624-a33543ca1f63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889055304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ec_pwr_on_rst.889055304
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.785768960
Short name T651
Test name
Test status
Simulation time 2612966801 ps
CPU time 7.29 seconds
Started Jul 20 04:41:59 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201476 kb
Host smart-3470f591-f6f5-4b8d-984c-b151eb651ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785768960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.785768960
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1977310481
Short name T487
Test name
Test status
Simulation time 2479334156 ps
CPU time 1.56 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:41:54 PM PDT 24
Peak memory 201464 kb
Host smart-bf9f28a0-75cf-44c4-8c88-e479d0e7653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977310481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1977310481
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.1820499943
Short name T602
Test name
Test status
Simulation time 2211324086 ps
CPU time 3.28 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 201532 kb
Host smart-0514eb26-ac7e-496c-a109-6e0588ab0193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820499943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1820499943
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.907057212
Short name T515
Test name
Test status
Simulation time 2524139424 ps
CPU time 2.37 seconds
Started Jul 20 04:41:50 PM PDT 24
Finished Jul 20 04:41:54 PM PDT 24
Peak memory 201452 kb
Host smart-e5b46303-9c29-4654-acde-3da0768ede34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907057212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.907057212
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.2241816127
Short name T528
Test name
Test status
Simulation time 2115944714 ps
CPU time 6.19 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:42:02 PM PDT 24
Peak memory 201284 kb
Host smart-ff7a8790-d920-4dc2-b6dd-4b7c07d38e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241816127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2241816127
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.2984027995
Short name T598
Test name
Test status
Simulation time 6721187113 ps
CPU time 17.69 seconds
Started Jul 20 04:41:57 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201356 kb
Host smart-e27b55a4-b33c-498f-a412-3240eedb0ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984027995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.2984027995
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.554904967
Short name T540
Test name
Test status
Simulation time 7760735349 ps
CPU time 3.82 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:41:57 PM PDT 24
Peak memory 201520 kb
Host smart-93adab22-eb7b-4f5e-a521-b211424994db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554904967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ultra_low_pwr.554904967
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1589112253
Short name T659
Test name
Test status
Simulation time 2017376512 ps
CPU time 3.89 seconds
Started Jul 20 04:41:57 PM PDT 24
Finished Jul 20 04:42:02 PM PDT 24
Peak memory 201384 kb
Host smart-da75774b-d74f-44c0-ba3e-6f9fe13a0f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589112253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.1589112253
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1010658209
Short name T34
Test name
Test status
Simulation time 3907555645 ps
CPU time 2.74 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:41:56 PM PDT 24
Peak memory 201604 kb
Host smart-d10dd6b9-9294-45d6-93d2-7b06238e9d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010658209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
010658209
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3256028370
Short name T690
Test name
Test status
Simulation time 175718877740 ps
CPU time 446.1 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:49:22 PM PDT 24
Peak memory 201644 kb
Host smart-44e9afa5-2b8c-4a13-8438-adf76a400a0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256028370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3256028370
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.998551523
Short name T744
Test name
Test status
Simulation time 3531133254 ps
CPU time 9.51 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:42:05 PM PDT 24
Peak memory 201424 kb
Host smart-168b02d7-b78c-45f5-bef5-db6e19912a1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998551523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.998551523
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.739978944
Short name T150
Test name
Test status
Simulation time 5575371160 ps
CPU time 3.97 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:41:59 PM PDT 24
Peak memory 201444 kb
Host smart-47153713-b04f-462d-8629-830c6afc7eb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739978944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctr
l_edge_detect.739978944
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2465154512
Short name T308
Test name
Test status
Simulation time 2611025473 ps
CPU time 5.38 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:42:00 PM PDT 24
Peak memory 201672 kb
Host smart-2e3e2c35-c4b9-4915-b75e-d77a39916b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465154512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2465154512
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.2250017516
Short name T766
Test name
Test status
Simulation time 2478107788 ps
CPU time 7.98 seconds
Started Jul 20 04:41:52 PM PDT 24
Finished Jul 20 04:42:01 PM PDT 24
Peak memory 201532 kb
Host smart-dcbb7d23-64a1-4478-9624-99dc8b748d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250017516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.2250017516
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1311223703
Short name T404
Test name
Test status
Simulation time 2182448829 ps
CPU time 6.41 seconds
Started Jul 20 04:41:57 PM PDT 24
Finished Jul 20 04:42:05 PM PDT 24
Peak memory 201380 kb
Host smart-14f6321e-291c-4f3e-9458-7b3efd7a7760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311223703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1311223703
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1026282206
Short name T738
Test name
Test status
Simulation time 2534510657 ps
CPU time 2.31 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 201460 kb
Host smart-a464473a-dd2e-4d16-9dcc-f38e4982127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026282206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.1026282206
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.1215241848
Short name T615
Test name
Test status
Simulation time 2111694149 ps
CPU time 5.98 seconds
Started Jul 20 04:41:58 PM PDT 24
Finished Jul 20 04:42:04 PM PDT 24
Peak memory 201404 kb
Host smart-d814b92d-85d5-460e-939a-786a6f69a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215241848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.1215241848
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3114318566
Short name T302
Test name
Test status
Simulation time 29317866082 ps
CPU time 80.07 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:43:12 PM PDT 24
Peak memory 201908 kb
Host smart-1a4c7daf-0915-4551-8e87-98045d14d254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114318566 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.3114318566
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3591785364
Short name T735
Test name
Test status
Simulation time 835545977530 ps
CPU time 23.54 seconds
Started Jul 20 04:41:55 PM PDT 24
Finished Jul 20 04:42:20 PM PDT 24
Peak memory 201336 kb
Host smart-72b6bb06-2546-4f81-bacd-ddd503c451f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591785364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.3591785364
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.2072530345
Short name T21
Test name
Test status
Simulation time 2011159977 ps
CPU time 5.78 seconds
Started Jul 20 04:41:09 PM PDT 24
Finished Jul 20 04:41:15 PM PDT 24
Peak memory 201456 kb
Host smart-cd451577-0323-4e00-8dde-db2f66a496d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072530345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.2072530345
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2014785937
Short name T60
Test name
Test status
Simulation time 3418690967 ps
CPU time 9.1 seconds
Started Jul 20 04:41:06 PM PDT 24
Finished Jul 20 04:41:16 PM PDT 24
Peak memory 201592 kb
Host smart-bfac08b3-b471-4ba0-b6e1-812c35f5331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014785937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.2014785937
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.1530876792
Short name T126
Test name
Test status
Simulation time 107586218982 ps
CPU time 27.59 seconds
Started Jul 20 04:41:08 PM PDT 24
Finished Jul 20 04:41:36 PM PDT 24
Peak memory 201744 kb
Host smart-2eeba27f-145e-4415-b65a-2088112060fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530876792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.1530876792
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2067845843
Short name T664
Test name
Test status
Simulation time 2236107145 ps
CPU time 1.72 seconds
Started Jul 20 04:41:13 PM PDT 24
Finished Jul 20 04:41:15 PM PDT 24
Peak memory 201444 kb
Host smart-46584d53-6820-4ad1-87c8-22bab46686f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067845843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.2067845843
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1055966907
Short name T441
Test name
Test status
Simulation time 2321158010 ps
CPU time 1.97 seconds
Started Jul 20 04:41:03 PM PDT 24
Finished Jul 20 04:41:06 PM PDT 24
Peak memory 201468 kb
Host smart-91b77726-7e20-457c-b1a2-01b101ac7abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055966907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1055966907
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3340866934
Short name T359
Test name
Test status
Simulation time 94114408062 ps
CPU time 66.64 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201788 kb
Host smart-07f29443-3249-4746-b98a-c33f35d51952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340866934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.3340866934
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3072809134
Short name T513
Test name
Test status
Simulation time 4676604413 ps
CPU time 12.7 seconds
Started Jul 20 04:41:05 PM PDT 24
Finished Jul 20 04:41:18 PM PDT 24
Peak memory 201424 kb
Host smart-152ed2a5-b071-45f2-9bf8-ce6c10c8d9d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072809134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.3072809134
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.431635208
Short name T739
Test name
Test status
Simulation time 2986396658 ps
CPU time 1.83 seconds
Started Jul 20 04:41:12 PM PDT 24
Finished Jul 20 04:41:15 PM PDT 24
Peak memory 201444 kb
Host smart-51e29bd1-dcf2-4fa5-8592-fc195eb10e3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431635208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_edge_detect.431635208
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3323314378
Short name T474
Test name
Test status
Simulation time 2614743413 ps
CPU time 7.36 seconds
Started Jul 20 04:41:06 PM PDT 24
Finished Jul 20 04:41:14 PM PDT 24
Peak memory 201512 kb
Host smart-31b8044f-7b53-41e2-8925-8a53678a5e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323314378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3323314378
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.3834015041
Short name T708
Test name
Test status
Simulation time 2471760227 ps
CPU time 4.18 seconds
Started Jul 20 04:41:05 PM PDT 24
Finished Jul 20 04:41:10 PM PDT 24
Peak memory 201476 kb
Host smart-48bbcc5f-2c5b-4124-8d5c-338c9b747008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834015041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3834015041
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.66562446
Short name T729
Test name
Test status
Simulation time 2145784564 ps
CPU time 5.65 seconds
Started Jul 20 04:41:08 PM PDT 24
Finished Jul 20 04:41:15 PM PDT 24
Peak memory 201400 kb
Host smart-dd5e1940-68c5-4787-8b63-7e88e4f94576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66562446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.66562446
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3067212635
Short name T761
Test name
Test status
Simulation time 2531134134 ps
CPU time 2.38 seconds
Started Jul 20 04:41:08 PM PDT 24
Finished Jul 20 04:41:11 PM PDT 24
Peak memory 201464 kb
Host smart-38553a22-218c-4348-9696-78df12866734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067212635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3067212635
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.197989025
Short name T459
Test name
Test status
Simulation time 2142612495 ps
CPU time 1.44 seconds
Started Jul 20 04:41:07 PM PDT 24
Finished Jul 20 04:41:09 PM PDT 24
Peak memory 201440 kb
Host smart-be0db64a-3725-4551-bf93-4e2a5b032acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197989025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.197989025
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.2002489196
Short name T151
Test name
Test status
Simulation time 10305130352 ps
CPU time 22.32 seconds
Started Jul 20 04:41:14 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 201424 kb
Host smart-6ad6e571-1f7d-482a-a31f-4017e617c49a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002489196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.2002489196
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3346352903
Short name T787
Test name
Test status
Simulation time 34127879097 ps
CPU time 47.21 seconds
Started Jul 20 04:41:10 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 218336 kb
Host smart-a71ea3be-e08b-4e17-a2e5-052b12b7fd52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346352903 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.3346352903
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3447548786
Short name T233
Test name
Test status
Simulation time 2012738961 ps
CPU time 5.9 seconds
Started Jul 20 04:41:55 PM PDT 24
Finished Jul 20 04:42:03 PM PDT 24
Peak memory 201540 kb
Host smart-90fb5b78-91cb-414b-8634-e6f321433fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447548786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3447548786
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2688783759
Short name T642
Test name
Test status
Simulation time 3501432772 ps
CPU time 5.36 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:42:01 PM PDT 24
Peak memory 201416 kb
Host smart-a24901b3-ff81-4491-890f-8799a667be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688783759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.2
688783759
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.145763659
Short name T128
Test name
Test status
Simulation time 53619013489 ps
CPU time 9.75 seconds
Started Jul 20 04:42:02 PM PDT 24
Finished Jul 20 04:42:14 PM PDT 24
Peak memory 201716 kb
Host smart-b0a1f399-e443-41ce-b927-df77978455bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145763659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_combo_detect.145763659
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.865075907
Short name T643
Test name
Test status
Simulation time 2669622105 ps
CPU time 6.48 seconds
Started Jul 20 04:41:56 PM PDT 24
Finished Jul 20 04:42:03 PM PDT 24
Peak memory 201432 kb
Host smart-ac45f8e8-0ecf-4748-b112-63cbee30e6ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865075907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ec_pwr_on_rst.865075907
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3514360101
Short name T192
Test name
Test status
Simulation time 3189449231 ps
CPU time 4.21 seconds
Started Jul 20 04:41:52 PM PDT 24
Finished Jul 20 04:41:57 PM PDT 24
Peak memory 201460 kb
Host smart-a82fa498-e418-4ef4-82dd-e14e729181e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514360101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.3514360101
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1294975255
Short name T557
Test name
Test status
Simulation time 2612195555 ps
CPU time 7.05 seconds
Started Jul 20 04:41:50 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 201488 kb
Host smart-088f69cd-0142-4f55-8478-410cef1b714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294975255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.1294975255
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.477681005
Short name T700
Test name
Test status
Simulation time 2483857302 ps
CPU time 2.23 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:04 PM PDT 24
Peak memory 201448 kb
Host smart-46086347-9670-4283-884e-fa538e960808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477681005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.477681005
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.2977944254
Short name T417
Test name
Test status
Simulation time 2334663730 ps
CPU time 1.11 seconds
Started Jul 20 04:41:55 PM PDT 24
Finished Jul 20 04:41:57 PM PDT 24
Peak memory 201460 kb
Host smart-622ab0c9-88ef-4738-8ff0-cdf3a945918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977944254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.2977944254
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.1107674595
Short name T190
Test name
Test status
Simulation time 2509924419 ps
CPU time 6.94 seconds
Started Jul 20 04:41:59 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201444 kb
Host smart-798bb29c-83b0-4ec9-b4dd-c5eed40c0523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107674595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.1107674595
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1051997325
Short name T547
Test name
Test status
Simulation time 2112785052 ps
CPU time 6.05 seconds
Started Jul 20 04:41:57 PM PDT 24
Finished Jul 20 04:42:04 PM PDT 24
Peak memory 201384 kb
Host smart-04533b00-506a-43c7-8705-ae9155ff8c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051997325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1051997325
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.4222126001
Short name T652
Test name
Test status
Simulation time 15802406630 ps
CPU time 15 seconds
Started Jul 20 04:41:59 PM PDT 24
Finished Jul 20 04:42:15 PM PDT 24
Peak memory 201440 kb
Host smart-c9e888fb-c693-4841-b748-d07579a86061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222126001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.4222126001
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.4231006984
Short name T115
Test name
Test status
Simulation time 89761258534 ps
CPU time 32.85 seconds
Started Jul 20 04:41:57 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 212740 kb
Host smart-20ff2f8c-76c0-4024-b44c-f9a0f60ae6d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231006984 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.4231006984
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.443312367
Short name T70
Test name
Test status
Simulation time 6152034410 ps
CPU time 2.43 seconds
Started Jul 20 04:41:55 PM PDT 24
Finished Jul 20 04:41:59 PM PDT 24
Peak memory 201460 kb
Host smart-c7e014bc-4a59-40ea-9a4c-baab856056c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443312367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ultra_low_pwr.443312367
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.1392099417
Short name T160
Test name
Test status
Simulation time 2014025909 ps
CPU time 5.96 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201440 kb
Host smart-6d2194f2-0547-42fc-b699-5711e979d2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392099417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.1392099417
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2755004465
Short name T324
Test name
Test status
Simulation time 3900044300 ps
CPU time 1.24 seconds
Started Jul 20 04:41:55 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 201404 kb
Host smart-1fea7349-0e72-450a-96a4-7acc9fabc906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755004465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.2
755004465
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3397922788
Short name T387
Test name
Test status
Simulation time 56255868828 ps
CPU time 136.57 seconds
Started Jul 20 04:41:51 PM PDT 24
Finished Jul 20 04:44:09 PM PDT 24
Peak memory 201676 kb
Host smart-28137e27-bd42-4674-98e0-0d65ca691c23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397922788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3397922788
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.2311391856
Short name T382
Test name
Test status
Simulation time 107550555492 ps
CPU time 287.89 seconds
Started Jul 20 04:41:56 PM PDT 24
Finished Jul 20 04:46:45 PM PDT 24
Peak memory 201872 kb
Host smart-f0cebee1-f84a-436b-99fc-0460df8d6463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311391856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.2311391856
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.984997815
Short name T438
Test name
Test status
Simulation time 3257474728 ps
CPU time 2.64 seconds
Started Jul 20 04:41:57 PM PDT 24
Finished Jul 20 04:42:00 PM PDT 24
Peak memory 201516 kb
Host smart-2c4b2f42-9504-4cd9-9ac4-03a78022e232
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984997815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ec_pwr_on_rst.984997815
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.664808372
Short name T728
Test name
Test status
Simulation time 140278582459 ps
CPU time 9.58 seconds
Started Jul 20 04:41:57 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201444 kb
Host smart-4859fc34-afb8-4dc2-a6c6-8083e2682fa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664808372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctr
l_edge_detect.664808372
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.487762626
Short name T597
Test name
Test status
Simulation time 2611488286 ps
CPU time 3.97 seconds
Started Jul 20 04:41:52 PM PDT 24
Finished Jul 20 04:41:57 PM PDT 24
Peak memory 201448 kb
Host smart-9d74c911-98b2-4300-8cae-7aab2f5d35de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487762626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.487762626
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.1336081215
Short name T406
Test name
Test status
Simulation time 2499988414 ps
CPU time 1.49 seconds
Started Jul 20 04:41:59 PM PDT 24
Finished Jul 20 04:42:01 PM PDT 24
Peak memory 201464 kb
Host smart-3cab139f-3003-4ab1-884e-fcd7b38885bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336081215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.1336081215
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.677579719
Short name T672
Test name
Test status
Simulation time 2188483032 ps
CPU time 3.45 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:41:59 PM PDT 24
Peak memory 201408 kb
Host smart-5a1ddaae-33d3-45bb-9e40-a9abc4435e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677579719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.677579719
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1013268907
Short name T585
Test name
Test status
Simulation time 2549688497 ps
CPU time 1.68 seconds
Started Jul 20 04:41:49 PM PDT 24
Finished Jul 20 04:41:52 PM PDT 24
Peak memory 201540 kb
Host smart-457612b1-1f3b-4c9d-93b1-83f65c218c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013268907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.1013268907
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.731236316
Short name T486
Test name
Test status
Simulation time 2109482917 ps
CPU time 4.89 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:41:59 PM PDT 24
Peak memory 201452 kb
Host smart-1ece2e0b-ae57-45fb-ae23-94cc93ae9c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731236316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.731236316
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.1119502038
Short name T723
Test name
Test status
Simulation time 10743258184 ps
CPU time 14.48 seconds
Started Jul 20 04:42:02 PM PDT 24
Finished Jul 20 04:42:19 PM PDT 24
Peak memory 201360 kb
Host smart-76c26bef-74e8-437a-ac46-32da678c8cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119502038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.1119502038
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.944654387
Short name T163
Test name
Test status
Simulation time 22202110669 ps
CPU time 58.18 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:42:52 PM PDT 24
Peak memory 218216 kb
Host smart-ca1458ee-be67-455a-a16a-7e1fe9b3374f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944654387 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.944654387
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.606829531
Short name T519
Test name
Test status
Simulation time 10496454852 ps
CPU time 1.72 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:03 PM PDT 24
Peak memory 201444 kb
Host smart-d74a71a8-8254-46e2-a89c-cc1447d4102f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606829531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ultra_low_pwr.606829531
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.3136147092
Short name T605
Test name
Test status
Simulation time 2042445767 ps
CPU time 1.94 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:42:05 PM PDT 24
Peak memory 201232 kb
Host smart-a506aa18-3b0d-46e0-920b-4463596785f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136147092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.3136147092
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2085400573
Short name T543
Test name
Test status
Simulation time 3341459147 ps
CPU time 2.6 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:08 PM PDT 24
Peak memory 201512 kb
Host smart-fe6844a5-b5e1-410d-9c92-9042d3d64c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085400573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2
085400573
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.804933448
Short name T654
Test name
Test status
Simulation time 93708509035 ps
CPU time 58.51 seconds
Started Jul 20 04:42:02 PM PDT 24
Finished Jul 20 04:43:02 PM PDT 24
Peak memory 201688 kb
Host smart-6c69e346-654e-4112-b7ed-73a8c51d4254
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804933448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_combo_detect.804933448
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2273736325
Short name T118
Test name
Test status
Simulation time 27082162775 ps
CPU time 62.13 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:43:04 PM PDT 24
Peak memory 201812 kb
Host smart-1119596b-cd18-41f9-89d7-baf7caa66a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273736325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.2273736325
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.4109483397
Short name T224
Test name
Test status
Simulation time 3742569038 ps
CPU time 3.46 seconds
Started Jul 20 04:42:02 PM PDT 24
Finished Jul 20 04:42:08 PM PDT 24
Peak memory 201456 kb
Host smart-f9f03b56-76f8-4aab-81b4-b6d85b8203c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109483397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.4109483397
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.3225905820
Short name T229
Test name
Test status
Simulation time 5362853104 ps
CPU time 7.6 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:13 PM PDT 24
Peak memory 201436 kb
Host smart-fe68189d-4216-4a12-9955-eb347dd48222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225905820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.3225905820
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1794344124
Short name T405
Test name
Test status
Simulation time 2629103401 ps
CPU time 2.39 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:08 PM PDT 24
Peak memory 201492 kb
Host smart-c1dad194-95ba-41bb-8797-6301e86a7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794344124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.1794344124
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2226938264
Short name T722
Test name
Test status
Simulation time 2463550019 ps
CPU time 2.38 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 201432 kb
Host smart-358c9fbf-177a-40eb-8904-8ce67a796b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226938264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2226938264
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3970528606
Short name T730
Test name
Test status
Simulation time 2030124467 ps
CPU time 3.21 seconds
Started Jul 20 04:41:53 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 201404 kb
Host smart-e73bb007-8992-4071-8bed-632637eb35a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970528606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3970528606
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1705337514
Short name T205
Test name
Test status
Simulation time 2511964085 ps
CPU time 7.4 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:42:11 PM PDT 24
Peak memory 201448 kb
Host smart-7118fda6-fac8-493e-aed8-2c9807698303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705337514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.1705337514
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.2464323546
Short name T727
Test name
Test status
Simulation time 2108228560 ps
CPU time 5.97 seconds
Started Jul 20 04:41:54 PM PDT 24
Finished Jul 20 04:42:01 PM PDT 24
Peak memory 201288 kb
Host smart-4c2b3cfa-edb7-4dfb-9599-1523eaccd602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464323546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2464323546
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.396467052
Short name T356
Test name
Test status
Simulation time 113061930908 ps
CPU time 149.85 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:44:31 PM PDT 24
Peak memory 201768 kb
Host smart-6683294e-b6bc-4116-b5d6-c1de36a6ef1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396467052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.396467052
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1032124473
Short name T89
Test name
Test status
Simulation time 3079942462 ps
CPU time 6.6 seconds
Started Jul 20 04:42:08 PM PDT 24
Finished Jul 20 04:42:15 PM PDT 24
Peak memory 201428 kb
Host smart-48696ae8-ca6a-4245-9bcf-29d7d82bc109
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032124473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.1032124473
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.975341608
Short name T471
Test name
Test status
Simulation time 2014590205 ps
CPU time 5.41 seconds
Started Jul 20 04:42:05 PM PDT 24
Finished Jul 20 04:42:12 PM PDT 24
Peak memory 201540 kb
Host smart-5afb9820-85c3-4946-b903-66746f3b66a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975341608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_tes
t.975341608
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.574021306
Short name T641
Test name
Test status
Simulation time 240566471426 ps
CPU time 313.72 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:47:17 PM PDT 24
Peak memory 201636 kb
Host smart-b6922222-cf1d-460e-a108-8b56882a6ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574021306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.574021306
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3626251655
Short name T264
Test name
Test status
Simulation time 33980195934 ps
CPU time 90.28 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:43:34 PM PDT 24
Peak memory 201736 kb
Host smart-9e17519a-beba-42b2-8870-a1773e940e4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626251655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.3626251655
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1659582565
Short name T368
Test name
Test status
Simulation time 86286535927 ps
CPU time 210.38 seconds
Started Jul 20 04:42:05 PM PDT 24
Finished Jul 20 04:45:37 PM PDT 24
Peak memory 201796 kb
Host smart-fd6ae402-555a-4173-8818-455aaa45cbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659582565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.1659582565
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2713796359
Short name T442
Test name
Test status
Simulation time 3318406668 ps
CPU time 8.98 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:11 PM PDT 24
Peak memory 201512 kb
Host smart-27a3076a-ae54-4678-a822-df3503e08875
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713796359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.2713796359
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2791089975
Short name T210
Test name
Test status
Simulation time 2797187992 ps
CPU time 3.4 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201416 kb
Host smart-81328342-7c0f-499d-b961-727b5ec29e60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791089975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.2791089975
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.288986487
Short name T775
Test name
Test status
Simulation time 2609617697 ps
CPU time 7.35 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:09 PM PDT 24
Peak memory 201448 kb
Host smart-84630fee-6ab0-4f06-98e7-367476f3cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288986487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.288986487
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3531615442
Short name T579
Test name
Test status
Simulation time 2469774498 ps
CPU time 2.69 seconds
Started Jul 20 04:42:07 PM PDT 24
Finished Jul 20 04:42:10 PM PDT 24
Peak memory 201476 kb
Host smart-517a88a4-6a13-48db-865e-2f4314615abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531615442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.3531615442
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3921958896
Short name T98
Test name
Test status
Simulation time 2277062887 ps
CPU time 2.12 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201352 kb
Host smart-97dd0c51-8e78-45df-8cec-6362f32ee841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921958896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.3921958896
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2074272440
Short name T81
Test name
Test status
Simulation time 2523074566 ps
CPU time 3.57 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:06 PM PDT 24
Peak memory 201444 kb
Host smart-48b39108-2665-46cf-92c4-174b03188ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074272440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2074272440
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.314925126
Short name T453
Test name
Test status
Simulation time 2136825762 ps
CPU time 1.81 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:04 PM PDT 24
Peak memory 201388 kb
Host smart-6ad248fc-8050-48a3-a732-5670cfd61e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314925126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.314925126
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.3015306603
Short name T138
Test name
Test status
Simulation time 9073216446 ps
CPU time 11.83 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201468 kb
Host smart-d36bcf7b-c6fb-429f-9d8e-e2c1e8a14ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015306603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.3015306603
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.4167601706
Short name T69
Test name
Test status
Simulation time 8282104985 ps
CPU time 7.67 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:42:11 PM PDT 24
Peak memory 201492 kb
Host smart-4bedc1e3-e07b-4681-85f9-fd0c57465ec2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167601706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.4167601706
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.3634512861
Short name T490
Test name
Test status
Simulation time 2015476448 ps
CPU time 3.28 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:06 PM PDT 24
Peak memory 201456 kb
Host smart-8cb4e38e-7fb8-4084-9248-758e0bb3cfa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634512861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.3634512861
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.279526198
Short name T422
Test name
Test status
Simulation time 290101147566 ps
CPU time 714.85 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:54:00 PM PDT 24
Peak memory 201524 kb
Host smart-0a6bb60b-857d-44fd-bfc3-534866e3177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279526198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.279526198
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.705101091
Short name T773
Test name
Test status
Simulation time 52917391720 ps
CPU time 40.59 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:46 PM PDT 24
Peak memory 201720 kb
Host smart-06e232fe-c8de-458e-99e0-90e7053e2fd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705101091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_combo_detect.705101091
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1528565787
Short name T172
Test name
Test status
Simulation time 1105390764476 ps
CPU time 1442.86 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 05:06:06 PM PDT 24
Peak memory 201448 kb
Host smart-6633c12b-9f9d-4d1d-8c20-a58305ee301e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528565787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.1528565787
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.469503330
Short name T209
Test name
Test status
Simulation time 4936836129 ps
CPU time 9.57 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:12 PM PDT 24
Peak memory 201484 kb
Host smart-a07af978-d3bf-447c-97c0-730a3261c9a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469503330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctr
l_edge_detect.469503330
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.459437352
Short name T64
Test name
Test status
Simulation time 2623121613 ps
CPU time 2.39 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:42:06 PM PDT 24
Peak memory 201524 kb
Host smart-2c46dc0a-c99a-45bb-a447-c617ebdf1725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459437352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.459437352
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2697595287
Short name T250
Test name
Test status
Simulation time 2458162643 ps
CPU time 4.37 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:10 PM PDT 24
Peak memory 201448 kb
Host smart-26e0bc3f-8a6d-47d6-85af-4544ed70db3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697595287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.2697595287
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3620643104
Short name T541
Test name
Test status
Simulation time 2129835287 ps
CPU time 6.21 seconds
Started Jul 20 04:42:09 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201392 kb
Host smart-37b7c4a8-8b19-48e7-8de1-c3f0adbb91d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620643104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3620643104
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3867328354
Short name T398
Test name
Test status
Simulation time 2579015930 ps
CPU time 1.26 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:03 PM PDT 24
Peak memory 201464 kb
Host smart-7a6a453d-0487-4f4d-8677-b1f67226227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867328354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.3867328354
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.3470853540
Short name T465
Test name
Test status
Simulation time 2120643427 ps
CPU time 2.62 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:08 PM PDT 24
Peak memory 201404 kb
Host smart-9bfb7939-3d02-4d29-a12e-831ced7024e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470853540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.3470853540
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.2133522834
Short name T618
Test name
Test status
Simulation time 10619232117 ps
CPU time 22.35 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:28 PM PDT 24
Peak memory 201424 kb
Host smart-d99a67b7-b59d-4e40-ad04-f26ccf99f269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133522834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.2133522834
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2344113891
Short name T141
Test name
Test status
Simulation time 619309539357 ps
CPU time 196.94 seconds
Started Jul 20 04:42:07 PM PDT 24
Finished Jul 20 04:45:24 PM PDT 24
Peak memory 209988 kb
Host smart-b499bea2-3a93-4ccc-8c34-4e3dda83fa0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344113891 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2344113891
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.255875517
Short name T41
Test name
Test status
Simulation time 3509684524 ps
CPU time 6.21 seconds
Started Jul 20 04:42:12 PM PDT 24
Finished Jul 20 04:42:20 PM PDT 24
Peak memory 201520 kb
Host smart-62027a40-ffc3-4c00-a2b9-a8a8e49dcc99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255875517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ultra_low_pwr.255875517
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.612119035
Short name T473
Test name
Test status
Simulation time 2124627865 ps
CPU time 1.04 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:06 PM PDT 24
Peak memory 201472 kb
Host smart-1e00c29b-8fb4-4e7f-a054-a44060887fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612119035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_tes
t.612119035
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2449883197
Short name T217
Test name
Test status
Simulation time 113126642853 ps
CPU time 17.8 seconds
Started Jul 20 04:42:02 PM PDT 24
Finished Jul 20 04:42:22 PM PDT 24
Peak memory 201604 kb
Host smart-3446b83e-75e0-4421-a6c1-04c02389e28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449883197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.2
449883197
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2495356531
Short name T266
Test name
Test status
Simulation time 115407494441 ps
CPU time 142 seconds
Started Jul 20 04:42:09 PM PDT 24
Finished Jul 20 04:44:32 PM PDT 24
Peak memory 201732 kb
Host smart-2fa83629-f735-43b9-9e99-46de8248f772
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495356531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.2495356531
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2684714355
Short name T259
Test name
Test status
Simulation time 4115128736 ps
CPU time 1.68 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201524 kb
Host smart-0c584a1e-84b7-452a-a128-219eaba3d7bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684714355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.2684714355
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3684033652
Short name T49
Test name
Test status
Simulation time 3080149870 ps
CPU time 3.84 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:06 PM PDT 24
Peak memory 201520 kb
Host smart-14006d5f-a0d0-4b42-972a-3b870fca4984
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684033652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.3684033652
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3109013470
Short name T463
Test name
Test status
Simulation time 2611487154 ps
CPU time 7.38 seconds
Started Jul 20 04:42:02 PM PDT 24
Finished Jul 20 04:42:12 PM PDT 24
Peak memory 201464 kb
Host smart-bfeb7d43-554f-4b80-9f91-f67cf842208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109013470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3109013470
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.215186424
Short name T632
Test name
Test status
Simulation time 2454004298 ps
CPU time 7.43 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:13 PM PDT 24
Peak memory 201520 kb
Host smart-19ea9514-fac2-4252-b3a3-d239018ad20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215186424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.215186424
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.387363000
Short name T746
Test name
Test status
Simulation time 2015383394 ps
CPU time 5.52 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:11 PM PDT 24
Peak memory 201380 kb
Host smart-c1ffa6e2-a252-4d5b-80c7-072307035b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387363000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.387363000
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.524989180
Short name T649
Test name
Test status
Simulation time 2530277682 ps
CPU time 2.45 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:42:06 PM PDT 24
Peak memory 201148 kb
Host smart-62a6268f-4406-4fb8-b58a-23a5061996e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524989180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.524989180
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2228884259
Short name T236
Test name
Test status
Simulation time 2122555623 ps
CPU time 2.33 seconds
Started Jul 20 04:42:02 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201396 kb
Host smart-3f8c3a11-5633-4023-ae7b-e53fa3f0bff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228884259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2228884259
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.753720532
Short name T388
Test name
Test status
Simulation time 192786139368 ps
CPU time 126.48 seconds
Started Jul 20 04:41:59 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 201628 kb
Host smart-013e5278-2baa-44f5-9909-bcb0bae0d6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753720532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_st
ress_all.753720532
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2583153272
Short name T505
Test name
Test status
Simulation time 6331126241 ps
CPU time 4.39 seconds
Started Jul 20 04:42:00 PM PDT 24
Finished Jul 20 04:42:05 PM PDT 24
Peak memory 201496 kb
Host smart-1fc50e92-1a1b-409f-9099-fa3aabaee2bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583153272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.2583153272
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.2292933729
Short name T166
Test name
Test status
Simulation time 2012761232 ps
CPU time 5.61 seconds
Started Jul 20 04:42:12 PM PDT 24
Finished Jul 20 04:42:19 PM PDT 24
Peak memory 201452 kb
Host smart-32a4192b-f560-4ec5-9c5e-5f5a252be9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292933729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.2292933729
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1876686061
Short name T566
Test name
Test status
Simulation time 3176386364 ps
CPU time 8.6 seconds
Started Jul 20 04:42:11 PM PDT 24
Finished Jul 20 04:42:22 PM PDT 24
Peak memory 201536 kb
Host smart-f6a39e80-6098-4aad-99a6-9179e1432326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876686061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.1
876686061
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1957141347
Short name T612
Test name
Test status
Simulation time 100246684007 ps
CPU time 134.45 seconds
Started Jul 20 04:42:08 PM PDT 24
Finished Jul 20 04:44:24 PM PDT 24
Peak memory 201712 kb
Host smart-877186c1-a51c-4f72-bde3-ad704e725a97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957141347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.1957141347
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4128905478
Short name T450
Test name
Test status
Simulation time 53323979509 ps
CPU time 17.23 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:28 PM PDT 24
Peak memory 201916 kb
Host smart-b62bf4e8-d9b5-4e05-8542-8a1732d944d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128905478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.4128905478
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.464435140
Short name T555
Test name
Test status
Simulation time 2643369878 ps
CPU time 6.9 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:17 PM PDT 24
Peak memory 201432 kb
Host smart-6543511c-375d-4a34-bed1-3b3b755850dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464435140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ec_pwr_on_rst.464435140
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.974703229
Short name T218
Test name
Test status
Simulation time 3178263761 ps
CPU time 2.6 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:14 PM PDT 24
Peak memory 201536 kb
Host smart-f4f908b8-d12a-4c01-9e74-2b9eb2db5978
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974703229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctr
l_edge_detect.974703229
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1525123921
Short name T786
Test name
Test status
Simulation time 2612297959 ps
CPU time 7.21 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:22 PM PDT 24
Peak memory 201264 kb
Host smart-ec17ad4a-3bf8-497a-8c95-1ffa3bbc4f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525123921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1525123921
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1821747697
Short name T546
Test name
Test status
Simulation time 2453418240 ps
CPU time 4.03 seconds
Started Jul 20 04:42:03 PM PDT 24
Finished Jul 20 04:42:09 PM PDT 24
Peak memory 201460 kb
Host smart-94cf6f02-bffc-4009-ac6c-77cd48cb5cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821747697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1821747697
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.4151098365
Short name T303
Test name
Test status
Simulation time 2224701321 ps
CPU time 3.52 seconds
Started Jul 20 04:42:11 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201472 kb
Host smart-bf2256d9-85a7-4edc-b5cd-6ca214f90e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151098365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.4151098365
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.2943143617
Short name T221
Test name
Test status
Simulation time 2521934569 ps
CPU time 2.22 seconds
Started Jul 20 04:42:11 PM PDT 24
Finished Jul 20 04:42:14 PM PDT 24
Peak memory 201448 kb
Host smart-6eec8b0c-6780-4008-aab4-be6485b1f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943143617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.2943143617
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.194499940
Short name T498
Test name
Test status
Simulation time 2111520249 ps
CPU time 6.3 seconds
Started Jul 20 04:42:01 PM PDT 24
Finished Jul 20 04:42:09 PM PDT 24
Peak memory 201372 kb
Host smart-a8d3dd7e-a5f0-48a3-b747-107841b715cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194499940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.194499940
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.3743399636
Short name T145
Test name
Test status
Simulation time 48837228950 ps
CPU time 9.22 seconds
Started Jul 20 04:42:23 PM PDT 24
Finished Jul 20 04:42:34 PM PDT 24
Peak memory 201352 kb
Host smart-2fb0015c-d6ee-40a7-ab65-03c48d191470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743399636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.3743399636
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.642372116
Short name T185
Test name
Test status
Simulation time 49764291215 ps
CPU time 132.37 seconds
Started Jul 20 04:42:14 PM PDT 24
Finished Jul 20 04:44:28 PM PDT 24
Peak memory 213928 kb
Host smart-6e593a0d-85f8-4af0-8c06-c6ec1bd5ccb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642372116 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.642372116
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2812681305
Short name T782
Test name
Test status
Simulation time 3179084565 ps
CPU time 1.03 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:22 PM PDT 24
Peak memory 201444 kb
Host smart-1daa9ed0-861a-4359-8b63-a1baea24ec0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812681305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.2812681305
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.1373324516
Short name T66
Test name
Test status
Simulation time 2065250288 ps
CPU time 1.26 seconds
Started Jul 20 04:42:08 PM PDT 24
Finished Jul 20 04:42:10 PM PDT 24
Peak memory 201496 kb
Host smart-c163c7fd-be5b-49ee-b52c-4028fd117b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373324516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.1373324516
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2244559818
Short name T470
Test name
Test status
Simulation time 3158649564 ps
CPU time 2.78 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:14 PM PDT 24
Peak memory 201604 kb
Host smart-54b734dc-0ce4-442f-ad15-fca569204b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244559818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
244559818
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.73745111
Short name T520
Test name
Test status
Simulation time 28129648188 ps
CPU time 11.56 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 201780 kb
Host smart-60a43c08-742c-451b-b999-9a45f2d5d731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73745111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_wit
h_pre_cond.73745111
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2820487573
Short name T444
Test name
Test status
Simulation time 4217874629 ps
CPU time 3.39 seconds
Started Jul 20 04:42:15 PM PDT 24
Finished Jul 20 04:42:19 PM PDT 24
Peak memory 201440 kb
Host smart-6e99372b-50a1-4ee9-b8c7-a9ea5e95d5fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820487573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.2820487573
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.2646894830
Short name T523
Test name
Test status
Simulation time 2602853899 ps
CPU time 6.83 seconds
Started Jul 20 04:42:08 PM PDT 24
Finished Jul 20 04:42:15 PM PDT 24
Peak memory 201492 kb
Host smart-0d8aae5e-e26d-4198-85ae-cb1d5b959f18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646894830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.2646894830
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3059241197
Short name T326
Test name
Test status
Simulation time 2617684963 ps
CPU time 3.91 seconds
Started Jul 20 04:42:08 PM PDT 24
Finished Jul 20 04:42:13 PM PDT 24
Peak memory 201468 kb
Host smart-9d73a883-489b-4392-bbe2-6d6cfb3f8fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059241197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.3059241197
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3340824682
Short name T640
Test name
Test status
Simulation time 2488853982 ps
CPU time 3.3 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:18 PM PDT 24
Peak memory 201464 kb
Host smart-4d8ccd20-7b99-4e6a-9895-d6fc71cdbef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340824682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3340824682
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3116698124
Short name T466
Test name
Test status
Simulation time 2223429500 ps
CPU time 1.97 seconds
Started Jul 20 04:42:09 PM PDT 24
Finished Jul 20 04:42:12 PM PDT 24
Peak memory 201424 kb
Host smart-78904608-7967-47e5-8f97-860de3d6165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116698124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.3116698124
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.3426295999
Short name T476
Test name
Test status
Simulation time 2513208136 ps
CPU time 5.8 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:20 PM PDT 24
Peak memory 201440 kb
Host smart-d6891e5f-1de3-4f03-970b-df1d7beea706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426295999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.3426295999
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.2542413754
Short name T212
Test name
Test status
Simulation time 2132628906 ps
CPU time 2.08 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:17 PM PDT 24
Peak memory 201348 kb
Host smart-43f3a975-7e84-4327-b2f3-5c79d42f8702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542413754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2542413754
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.3612980793
Short name T204
Test name
Test status
Simulation time 6937816944 ps
CPU time 4.71 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:19 PM PDT 24
Peak memory 201436 kb
Host smart-5b84770f-af1c-4f7c-a70a-8e428de990f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612980793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.3612980793
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2051956778
Short name T134
Test name
Test status
Simulation time 1725516475758 ps
CPU time 87.88 seconds
Started Jul 20 04:42:09 PM PDT 24
Finished Jul 20 04:43:38 PM PDT 24
Peak memory 201548 kb
Host smart-09ccb0a1-cd37-4cec-8c3b-e093defb862f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051956778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.2051956778
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.1904502133
Short name T425
Test name
Test status
Simulation time 2012721832 ps
CPU time 6.08 seconds
Started Jul 20 04:42:09 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201360 kb
Host smart-b8294b53-fba0-4ff9-9759-639900f5fff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904502133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.1904502133
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.148959745
Short name T703
Test name
Test status
Simulation time 3672196109 ps
CPU time 5.31 seconds
Started Jul 20 04:42:11 PM PDT 24
Finished Jul 20 04:42:17 PM PDT 24
Peak memory 201528 kb
Host smart-b1e09c92-954a-4e03-b17d-5e290c6418d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148959745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.148959745
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.3911024917
Short name T396
Test name
Test status
Simulation time 107543020569 ps
CPU time 254.3 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:46:33 PM PDT 24
Peak memory 201664 kb
Host smart-844e1f59-fdb3-40cc-b23a-f893a59d0488
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911024917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.3911024917
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2822187143
Short name T650
Test name
Test status
Simulation time 114107562439 ps
CPU time 71.91 seconds
Started Jul 20 04:42:23 PM PDT 24
Finished Jul 20 04:43:37 PM PDT 24
Peak memory 201732 kb
Host smart-cde26935-ca47-4fe9-9622-55734553d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822187143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.2822187143
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1797030552
Short name T604
Test name
Test status
Simulation time 3248099575 ps
CPU time 8.47 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:42:27 PM PDT 24
Peak memory 201444 kb
Host smart-6ed64ece-9fd4-459b-bcf1-371e58b73a59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797030552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.1797030552
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3721841033
Short name T82
Test name
Test status
Simulation time 3328020202 ps
CPU time 7.03 seconds
Started Jul 20 04:42:08 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201492 kb
Host smart-2b232ff1-05d4-40db-8b76-93c0a1b87485
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721841033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.3721841033
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1990413549
Short name T475
Test name
Test status
Simulation time 2626537528 ps
CPU time 2.86 seconds
Started Jul 20 04:42:11 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201536 kb
Host smart-65a6a7de-c480-41ea-b82e-cf60a5a40ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990413549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.1990413549
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.3452051356
Short name T412
Test name
Test status
Simulation time 2526120987 ps
CPU time 1.33 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:13 PM PDT 24
Peak memory 201468 kb
Host smart-1869503c-9c04-4d02-a84a-1e03ca764355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452051356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.3452051356
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.3591633674
Short name T710
Test name
Test status
Simulation time 2125382990 ps
CPU time 5.77 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201384 kb
Host smart-38b2eca1-c593-4308-a138-a7c324e47cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591633674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.3591633674
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2227970877
Short name T502
Test name
Test status
Simulation time 2529711147 ps
CPU time 2.17 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:14 PM PDT 24
Peak memory 201448 kb
Host smart-ed316eec-1d51-44ed-a2e2-3b0652577c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227970877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2227970877
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.532433037
Short name T554
Test name
Test status
Simulation time 2132896344 ps
CPU time 1.72 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201612 kb
Host smart-f4d0fe0c-4137-4b8e-a97a-a6b8bebabb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532433037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.532433037
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.648470491
Short name T434
Test name
Test status
Simulation time 9154204518 ps
CPU time 24.48 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:39 PM PDT 24
Peak memory 201436 kb
Host smart-8669481a-b239-4a6a-92cf-bf5b15b991bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648470491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_st
ress_all.648470491
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.69737102
Short name T149
Test name
Test status
Simulation time 5009708607 ps
CPU time 2.48 seconds
Started Jul 20 04:42:14 PM PDT 24
Finished Jul 20 04:42:17 PM PDT 24
Peak memory 201400 kb
Host smart-476d5ed6-9c06-472c-bc91-d67905e42407
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69737102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_ultra_low_pwr.69737102
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.4264223194
Short name T206
Test name
Test status
Simulation time 2033503410 ps
CPU time 1.91 seconds
Started Jul 20 04:42:23 PM PDT 24
Finished Jul 20 04:42:27 PM PDT 24
Peak memory 201376 kb
Host smart-3134ef88-06f5-4bba-a41c-76619c28bda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264223194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.4264223194
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2975084819
Short name T762
Test name
Test status
Simulation time 3371675639 ps
CPU time 9.02 seconds
Started Jul 20 04:42:15 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201532 kb
Host smart-38afb86a-7999-474b-a6b5-e5a9bef65d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975084819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.2
975084819
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3576794284
Short name T349
Test name
Test status
Simulation time 167623663917 ps
CPU time 464.92 seconds
Started Jul 20 04:42:12 PM PDT 24
Finished Jul 20 04:49:59 PM PDT 24
Peak memory 201740 kb
Host smart-15852690-1327-4b4b-9b86-cb9c184cc4e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576794284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.3576794284
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.246620781
Short name T258
Test name
Test status
Simulation time 161360149505 ps
CPU time 97.47 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:43:52 PM PDT 24
Peak memory 201564 kb
Host smart-f279fa0d-38d3-447d-86d9-bb009cd8c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246620781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_wi
th_pre_cond.246620781
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.364918454
Short name T472
Test name
Test status
Simulation time 3403821220 ps
CPU time 2.42 seconds
Started Jul 20 04:42:14 PM PDT 24
Finished Jul 20 04:42:18 PM PDT 24
Peak memory 201448 kb
Host smart-f1f670c2-7ab5-40ab-a61a-8d4807c165ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364918454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_ec_pwr_on_rst.364918454
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2282296261
Short name T241
Test name
Test status
Simulation time 2700800857 ps
CPU time 1.76 seconds
Started Jul 20 04:42:22 PM PDT 24
Finished Jul 20 04:42:27 PM PDT 24
Peak memory 201356 kb
Host smart-b502f573-9fbe-4f47-b1ed-84a4ac81e056
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282296261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.2282296261
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3732742315
Short name T525
Test name
Test status
Simulation time 2614772391 ps
CPU time 4.23 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:19 PM PDT 24
Peak memory 201540 kb
Host smart-fae83bfa-a79a-4e82-bb11-4bf0e91061ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732742315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3732742315
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.252663715
Short name T580
Test name
Test status
Simulation time 2486169168 ps
CPU time 3.62 seconds
Started Jul 20 04:42:13 PM PDT 24
Finished Jul 20 04:42:18 PM PDT 24
Peak memory 201464 kb
Host smart-e6c3f0f8-2035-450c-87b0-f7543162f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252663715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.252663715
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.554697427
Short name T720
Test name
Test status
Simulation time 2119741165 ps
CPU time 1.42 seconds
Started Jul 20 04:42:11 PM PDT 24
Finished Jul 20 04:42:14 PM PDT 24
Peak memory 201380 kb
Host smart-a88a0e34-a999-4c4f-8f14-38b68065a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554697427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.554697427
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3595549707
Short name T501
Test name
Test status
Simulation time 2514045515 ps
CPU time 7.26 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:19 PM PDT 24
Peak memory 201524 kb
Host smart-ad2fd6dc-fd96-4943-bb3a-7b6fa4e024aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595549707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3595549707
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.3042993937
Short name T714
Test name
Test status
Simulation time 2112163278 ps
CPU time 5.72 seconds
Started Jul 20 04:42:14 PM PDT 24
Finished Jul 20 04:42:21 PM PDT 24
Peak memory 201612 kb
Host smart-ca0cd8a0-f174-4fd6-9548-0972e234428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042993937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3042993937
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.74429259
Short name T397
Test name
Test status
Simulation time 9679255460 ps
CPU time 4.63 seconds
Started Jul 20 04:42:10 PM PDT 24
Finished Jul 20 04:42:16 PM PDT 24
Peak memory 201452 kb
Host smart-3e1fb892-5879-4041-a59d-c8ddbe51a636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74429259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_str
ess_all.74429259
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.228657404
Short name T175
Test name
Test status
Simulation time 80374205696 ps
CPU time 91.95 seconds
Started Jul 20 04:42:11 PM PDT 24
Finished Jul 20 04:43:44 PM PDT 24
Peak memory 218164 kb
Host smart-611184c9-9678-430e-a26d-9e5a715c4484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228657404 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.228657404
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1263041514
Short name T662
Test name
Test status
Simulation time 2671438152 ps
CPU time 1.63 seconds
Started Jul 20 04:42:11 PM PDT 24
Finished Jul 20 04:42:15 PM PDT 24
Peak memory 201552 kb
Host smart-f3205d0f-4d87-41fe-9913-dfd32fdfa2d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263041514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.1263041514
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.3684211320
Short name T688
Test name
Test status
Simulation time 2009730848 ps
CPU time 5.65 seconds
Started Jul 20 04:41:09 PM PDT 24
Finished Jul 20 04:41:16 PM PDT 24
Peak memory 201552 kb
Host smart-d1acdce4-70f8-4da5-95a0-e197018b280f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684211320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.3684211320
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3075903250
Short name T790
Test name
Test status
Simulation time 3980315844 ps
CPU time 2.3 seconds
Started Jul 20 04:41:14 PM PDT 24
Finished Jul 20 04:41:17 PM PDT 24
Peak memory 201536 kb
Host smart-dde9ac51-bc58-4943-b911-1b42393559d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075903250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3075903250
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.3130280034
Short name T386
Test name
Test status
Simulation time 138613959365 ps
CPU time 69.03 seconds
Started Jul 20 04:41:12 PM PDT 24
Finished Jul 20 04:42:21 PM PDT 24
Peak memory 201764 kb
Host smart-9a8d0e75-c2c4-4d70-b4a4-c341e664b8f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130280034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.3130280034
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2830446591
Short name T482
Test name
Test status
Simulation time 2448791493 ps
CPU time 2.2 seconds
Started Jul 20 04:41:11 PM PDT 24
Finished Jul 20 04:41:14 PM PDT 24
Peak memory 201464 kb
Host smart-2b7df3f7-bf6e-4a62-a120-84deff8d9fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830446591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.2830446591
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.449551645
Short name T256
Test name
Test status
Simulation time 2536266764 ps
CPU time 6.89 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:26 PM PDT 24
Peak memory 201464 kb
Host smart-86339f95-c4c6-49d5-bc79-d298678272a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449551645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.449551645
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1108497305
Short name T87
Test name
Test status
Simulation time 103883039907 ps
CPU time 266.77 seconds
Started Jul 20 04:41:09 PM PDT 24
Finished Jul 20 04:45:37 PM PDT 24
Peak memory 201632 kb
Host smart-8288631a-2227-4ba6-8b46-f05f6439577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108497305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1108497305
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2406064879
Short name T461
Test name
Test status
Simulation time 2616265704 ps
CPU time 2.23 seconds
Started Jul 20 04:41:10 PM PDT 24
Finished Jul 20 04:41:13 PM PDT 24
Peak memory 201448 kb
Host smart-8e7bf963-9cf6-45d4-b117-1db1b4e3f7b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406064879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.2406064879
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3830955227
Short name T176
Test name
Test status
Simulation time 3055682486 ps
CPU time 5.95 seconds
Started Jul 20 04:41:15 PM PDT 24
Finished Jul 20 04:41:22 PM PDT 24
Peak memory 201428 kb
Host smart-a375baa2-fa36-4614-b516-ad95074580e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830955227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.3830955227
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3133761729
Short name T191
Test name
Test status
Simulation time 2613006085 ps
CPU time 7.61 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:27 PM PDT 24
Peak memory 201460 kb
Host smart-c1259015-95e9-4583-940a-d877b2dc7178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133761729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3133761729
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1142876234
Short name T409
Test name
Test status
Simulation time 2534371504 ps
CPU time 1.11 seconds
Started Jul 20 04:41:10 PM PDT 24
Finished Jul 20 04:41:12 PM PDT 24
Peak memory 201444 kb
Host smart-57025467-6880-4e78-b473-59343bb89637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142876234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1142876234
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3254688566
Short name T319
Test name
Test status
Simulation time 2142152172 ps
CPU time 3.57 seconds
Started Jul 20 04:41:15 PM PDT 24
Finished Jul 20 04:41:19 PM PDT 24
Peak memory 201380 kb
Host smart-f54b74c0-8d40-4a27-aa17-989adec3f344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254688566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3254688566
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.4140547344
Short name T634
Test name
Test status
Simulation time 2510538920 ps
CPU time 6.8 seconds
Started Jul 20 04:41:12 PM PDT 24
Finished Jul 20 04:41:20 PM PDT 24
Peak memory 201520 kb
Host smart-18bb4abf-24f6-4ade-92f1-19818ddeebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140547344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.4140547344
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.1759139266
Short name T225
Test name
Test status
Simulation time 22018999283 ps
CPU time 29.66 seconds
Started Jul 20 04:41:07 PM PDT 24
Finished Jul 20 04:41:38 PM PDT 24
Peak memory 220868 kb
Host smart-915c8779-f333-4a43-b755-736ba6dedaac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759139266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1759139266
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2887037409
Short name T125
Test name
Test status
Simulation time 2138590642 ps
CPU time 1.82 seconds
Started Jul 20 04:41:10 PM PDT 24
Finished Jul 20 04:41:13 PM PDT 24
Peak memory 201392 kb
Host smart-8a001863-8c45-4302-ae6c-35db2b0ac4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887037409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2887037409
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.4278595126
Short name T571
Test name
Test status
Simulation time 10181168808 ps
CPU time 6.51 seconds
Started Jul 20 04:41:10 PM PDT 24
Finished Jul 20 04:41:17 PM PDT 24
Peak memory 201528 kb
Host smart-2af6b130-891f-44a1-86d3-a195b789d1a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278595126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.4278595126
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1184158354
Short name T105
Test name
Test status
Simulation time 51888865452 ps
CPU time 62.25 seconds
Started Jul 20 04:41:09 PM PDT 24
Finished Jul 20 04:42:12 PM PDT 24
Peak memory 210004 kb
Host smart-04c7a57e-d02d-4034-859c-c144115fd6c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184158354 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1184158354
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.46876008
Short name T91
Test name
Test status
Simulation time 3854206108 ps
CPU time 6.17 seconds
Started Jul 20 04:41:13 PM PDT 24
Finished Jul 20 04:41:20 PM PDT 24
Peak memory 201344 kb
Host smart-3ee467b3-ab37-4203-aa18-7d4e3524a68c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46876008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_ultra_low_pwr.46876008
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.3782447828
Short name T122
Test name
Test status
Simulation time 2019609639 ps
CPU time 3.11 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201468 kb
Host smart-c49f9645-3087-4ccd-a5e1-e10f5db05960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782447828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.3782447828
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1867400416
Short name T680
Test name
Test status
Simulation time 3751826883 ps
CPU time 5.06 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201536 kb
Host smart-0b2be497-b8f0-43d6-a94d-a7a679e24427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867400416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.1
867400416
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2304710605
Short name T328
Test name
Test status
Simulation time 70783570680 ps
CPU time 187.4 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:45:27 PM PDT 24
Peak memory 201680 kb
Host smart-391f3f25-b24c-4104-8438-e1ce070d21a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304710605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.2304710605
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2348476311
Short name T591
Test name
Test status
Simulation time 2674895687 ps
CPU time 2.23 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:42:21 PM PDT 24
Peak memory 201420 kb
Host smart-01db4d1c-3de6-494a-982e-d06686499af5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348476311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.2348476311
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3271789811
Short name T252
Test name
Test status
Simulation time 2910307242 ps
CPU time 2.48 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201536 kb
Host smart-3ee31665-1e3c-495e-9f5e-55e4121fbeb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271789811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.3271789811
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.857932327
Short name T628
Test name
Test status
Simulation time 2613162121 ps
CPU time 4.04 seconds
Started Jul 20 04:42:16 PM PDT 24
Finished Jul 20 04:42:21 PM PDT 24
Peak memory 201464 kb
Host smart-96cc6a2f-d1f0-4156-95a5-9f68fdc7377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857932327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.857932327
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1981145518
Short name T626
Test name
Test status
Simulation time 2457843750 ps
CPU time 7.02 seconds
Started Jul 20 04:42:15 PM PDT 24
Finished Jul 20 04:42:23 PM PDT 24
Peak memory 201680 kb
Host smart-cbc7e001-29c6-453e-bdaf-8dd17c595665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981145518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1981145518
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.533931202
Short name T495
Test name
Test status
Simulation time 2029565330 ps
CPU time 5.61 seconds
Started Jul 20 04:42:16 PM PDT 24
Finished Jul 20 04:42:23 PM PDT 24
Peak memory 201380 kb
Host smart-9a39715f-6cf5-4469-a78e-7324eb51b196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533931202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.533931202
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3066178742
Short name T245
Test name
Test status
Simulation time 2768333377 ps
CPU time 1.12 seconds
Started Jul 20 04:42:23 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201448 kb
Host smart-647ec2d7-5711-49b2-9a3f-4afb4b4f5664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066178742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3066178742
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.38601705
Short name T428
Test name
Test status
Simulation time 2132604827 ps
CPU time 1.92 seconds
Started Jul 20 04:42:20 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201312 kb
Host smart-60a1acbe-9304-4fbe-909f-a9dfb1c617cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38601705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.38601705
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3703586933
Short name T44
Test name
Test status
Simulation time 145025280224 ps
CPU time 64.57 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:43:28 PM PDT 24
Peak memory 201752 kb
Host smart-4c15e4fa-1d11-48fe-b14a-08946f5ef22d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703586933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.3703586933
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.331633082
Short name T455
Test name
Test status
Simulation time 2050972947 ps
CPU time 1.93 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201540 kb
Host smart-d75bdd24-9fba-44f0-bb7b-2015913bffad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331633082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_tes
t.331633082
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.443282711
Short name T214
Test name
Test status
Simulation time 3592460080 ps
CPU time 3.09 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:42:23 PM PDT 24
Peak memory 201496 kb
Host smart-b801d57f-d346-4388-9a94-c6d73f518e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443282711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.443282711
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.472035653
Short name T357
Test name
Test status
Simulation time 57258989307 ps
CPU time 151.45 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:44:52 PM PDT 24
Peak memory 201716 kb
Host smart-e610384e-9549-478d-8d65-d470d901734a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472035653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_combo_detect.472035653
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2900044139
Short name T53
Test name
Test status
Simulation time 33321101570 ps
CPU time 43.95 seconds
Started Jul 20 04:42:16 PM PDT 24
Finished Jul 20 04:43:01 PM PDT 24
Peak memory 201708 kb
Host smart-b7babee1-f537-4cf3-bca9-9a1f56331332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900044139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2900044139
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.720458549
Short name T671
Test name
Test status
Simulation time 3179190566 ps
CPU time 9.02 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:42:29 PM PDT 24
Peak memory 201484 kb
Host smart-098931f1-4b7e-4962-8485-b6608df006e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720458549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_ec_pwr_on_rst.720458549
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3150374097
Short name T757
Test name
Test status
Simulation time 2611167550 ps
CPU time 7.34 seconds
Started Jul 20 04:42:20 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 201464 kb
Host smart-38acadcf-eeb8-4c26-a94d-3fe43330d2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150374097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.3150374097
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.4038390802
Short name T718
Test name
Test status
Simulation time 2487619060 ps
CPU time 2.1 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201456 kb
Host smart-382fcff9-9eb0-4dea-b5e4-56f57ec781b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038390802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.4038390802
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2869946524
Short name T551
Test name
Test status
Simulation time 2134330614 ps
CPU time 5.48 seconds
Started Jul 20 04:42:20 PM PDT 24
Finished Jul 20 04:42:28 PM PDT 24
Peak memory 200956 kb
Host smart-c2a76f7a-f36e-4f4d-ac4b-50d11e0548e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869946524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2869946524
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.677909220
Short name T696
Test name
Test status
Simulation time 2509066453 ps
CPU time 7.14 seconds
Started Jul 20 04:42:20 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 201540 kb
Host smart-8e1add3a-9526-466e-b4e6-5314f41b89d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677909220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.677909220
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.1586356269
Short name T485
Test name
Test status
Simulation time 2151936971 ps
CPU time 1.44 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:23 PM PDT 24
Peak memory 201464 kb
Host smart-5e7ebdb6-5aeb-4cf1-9675-0eb86b523e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586356269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.1586356269
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1145095628
Short name T711
Test name
Test status
Simulation time 9232800116 ps
CPU time 19.88 seconds
Started Jul 20 04:42:16 PM PDT 24
Finished Jul 20 04:42:38 PM PDT 24
Peak memory 201492 kb
Host smart-4d140929-fdcf-459e-a546-eb219a96cfbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145095628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1145095628
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.4162131566
Short name T80
Test name
Test status
Simulation time 25705222624 ps
CPU time 42.17 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:43:01 PM PDT 24
Peak memory 218188 kb
Host smart-34041e2c-087b-4531-9056-e884fbe90287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162131566 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.4162131566
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.676719967
Short name T679
Test name
Test status
Simulation time 9111153128 ps
CPU time 7.43 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:31 PM PDT 24
Peak memory 201340 kb
Host smart-26d2d12c-37de-4b00-9bf6-e47ef4cdaf52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676719967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_ultra_low_pwr.676719967
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.3598860244
Short name T429
Test name
Test status
Simulation time 2069797167 ps
CPU time 1.38 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:42:21 PM PDT 24
Peak memory 201532 kb
Host smart-cc332f52-9ebc-4d65-8ad7-43de2b86851c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598860244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.3598860244
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3789048484
Short name T58
Test name
Test status
Simulation time 92706760806 ps
CPU time 58.73 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:43:21 PM PDT 24
Peak memory 201508 kb
Host smart-fcbaedaf-2ae8-407c-916f-f3f72c31b728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789048484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3
789048484
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.2120711641
Short name T271
Test name
Test status
Simulation time 45752901076 ps
CPU time 22.18 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:44 PM PDT 24
Peak memory 201648 kb
Host smart-819f6095-38d7-4ce4-aa72-23cb3d388845
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120711641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.2120711641
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3942649218
Short name T369
Test name
Test status
Simulation time 51565080208 ps
CPU time 127.15 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 201856 kb
Host smart-9aeafe72-2f43-4c48-90c0-e00f0c25870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942649218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.3942649218
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1984610530
Short name T187
Test name
Test status
Simulation time 4476822749 ps
CPU time 2.58 seconds
Started Jul 20 04:42:22 PM PDT 24
Finished Jul 20 04:42:27 PM PDT 24
Peak memory 201296 kb
Host smart-d22c2ed9-b161-4754-85f1-8b07892bc575
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984610530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.1984610530
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1461720746
Short name T106
Test name
Test status
Simulation time 3768128663 ps
CPU time 2.91 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201456 kb
Host smart-b213a3d7-3e7a-4ae3-9b16-1af8bd95d6ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461720746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.1461720746
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.4251352414
Short name T154
Test name
Test status
Simulation time 2640500924 ps
CPU time 2.1 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:24 PM PDT 24
Peak memory 201476 kb
Host smart-2e75fea5-abf9-4eb2-a439-aca87e29d2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251352414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.4251352414
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.963226076
Short name T697
Test name
Test status
Simulation time 2463963639 ps
CPU time 3.8 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:28 PM PDT 24
Peak memory 201452 kb
Host smart-ebd0e437-51e3-4418-9646-ef04b7474446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963226076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.963226076
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.65680497
Short name T545
Test name
Test status
Simulation time 2110178150 ps
CPU time 1.94 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:24 PM PDT 24
Peak memory 201484 kb
Host smart-cd532ff9-9af9-4c8d-b4d9-4bb062503a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65680497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.65680497
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3549637019
Short name T623
Test name
Test status
Simulation time 2544540143 ps
CPU time 2.02 seconds
Started Jul 20 04:42:20 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201448 kb
Host smart-0227ffd6-6ce8-4a99-9e9c-ba9e9b8344eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549637019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.3549637019
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.277967442
Short name T625
Test name
Test status
Simulation time 2113528212 ps
CPU time 6.26 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:28 PM PDT 24
Peak memory 201456 kb
Host smart-670bb66a-cd7c-4eeb-8a3d-71e93e3895a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277967442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.277967442
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.558262495
Short name T202
Test name
Test status
Simulation time 7075338011 ps
CPU time 5.12 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201436 kb
Host smart-f5a9afe2-fda6-49d8-b070-7563f93b3e52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558262495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_st
ress_all.558262495
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3841665513
Short name T186
Test name
Test status
Simulation time 29888402849 ps
CPU time 19.6 seconds
Started Jul 20 04:42:16 PM PDT 24
Finished Jul 20 04:42:37 PM PDT 24
Peak memory 202112 kb
Host smart-64bc616c-5b76-45fb-ac66-32cf353f49b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841665513 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3841665513
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.684337453
Short name T694
Test name
Test status
Simulation time 6051645270 ps
CPU time 1.96 seconds
Started Jul 20 04:42:27 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 201680 kb
Host smart-ac9d9761-0121-40a9-8fe3-78781e1da2cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684337453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_ultra_low_pwr.684337453
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.3210522154
Short name T419
Test name
Test status
Simulation time 2013665632 ps
CPU time 5.77 seconds
Started Jul 20 04:42:26 PM PDT 24
Finished Jul 20 04:42:33 PM PDT 24
Peak memory 201688 kb
Host smart-9ece2b49-1445-44d9-845d-7d6cf6e41fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210522154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.3210522154
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.424880714
Short name T767
Test name
Test status
Simulation time 3238173988 ps
CPU time 2.48 seconds
Started Jul 20 04:42:16 PM PDT 24
Finished Jul 20 04:42:20 PM PDT 24
Peak memory 201492 kb
Host smart-0739ed77-2355-4984-b6a7-e3f979ff5a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424880714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.424880714
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1809725868
Short name T655
Test name
Test status
Simulation time 52750991377 ps
CPU time 29.4 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:50 PM PDT 24
Peak memory 201652 kb
Host smart-6c63a9e1-f112-461c-a4fc-f4488d05cd1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809725868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.1809725868
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3732472960
Short name T784
Test name
Test status
Simulation time 69218241019 ps
CPU time 178.92 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:45:20 PM PDT 24
Peak memory 201732 kb
Host smart-9b0c6554-9646-415d-8dfe-e51ac614d4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732472960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.3732472960
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.219242267
Short name T24
Test name
Test status
Simulation time 3254395674 ps
CPU time 4.66 seconds
Started Jul 20 04:42:27 PM PDT 24
Finished Jul 20 04:42:32 PM PDT 24
Peak memory 201648 kb
Host smart-659d0eb4-2536-4101-9129-74eaeead196d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219242267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ec_pwr_on_rst.219242267
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1681444617
Short name T184
Test name
Test status
Simulation time 2528050444 ps
CPU time 2.06 seconds
Started Jul 20 04:42:20 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 200980 kb
Host smart-da43a798-8c34-4cc2-8dbb-cf47b447dc8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681444617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.1681444617
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.682688278
Short name T774
Test name
Test status
Simulation time 2607503801 ps
CPU time 7.55 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:28 PM PDT 24
Peak memory 201532 kb
Host smart-00a3062b-fc73-464d-b5e1-c439c8e0526a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682688278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.682688278
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.4046002352
Short name T685
Test name
Test status
Simulation time 2499882189 ps
CPU time 1.39 seconds
Started Jul 20 04:42:17 PM PDT 24
Finished Jul 20 04:42:21 PM PDT 24
Peak memory 201544 kb
Host smart-e930b647-63e0-4124-8bcd-386efca2378f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046002352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.4046002352
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3996469755
Short name T562
Test name
Test status
Simulation time 2169959497 ps
CPU time 6.33 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201444 kb
Host smart-6f31b298-10d9-4bb5-8c18-4f9369ddee88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996469755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3996469755
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1866383225
Short name T484
Test name
Test status
Simulation time 2513659683 ps
CPU time 7.15 seconds
Started Jul 20 04:42:27 PM PDT 24
Finished Jul 20 04:42:35 PM PDT 24
Peak memory 201608 kb
Host smart-af007f72-753b-4ec8-a258-602be1e08b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866383225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1866383225
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.704000894
Short name T244
Test name
Test status
Simulation time 2120590946 ps
CPU time 3.12 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201376 kb
Host smart-7192f88c-f79d-4460-9956-a548670cc58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704000894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.704000894
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.1153298962
Short name T508
Test name
Test status
Simulation time 11759596338 ps
CPU time 5 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201424 kb
Host smart-33ff9ff5-b521-4971-a0e5-688426100acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153298962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.1153298962
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.4273546937
Short name T617
Test name
Test status
Simulation time 33720179993 ps
CPU time 43.69 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:43:08 PM PDT 24
Peak memory 218388 kb
Host smart-8b5c2271-287b-4924-bf0d-b37bf5695976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273546937 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.4273546937
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.528000295
Short name T407
Test name
Test status
Simulation time 2022807551 ps
CPU time 3.13 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:27 PM PDT 24
Peak memory 201456 kb
Host smart-0ea1dfbf-aebd-4fe1-a3c0-91fa1d7be7c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528000295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes
t.528000295
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.127305850
Short name T675
Test name
Test status
Simulation time 3556042753 ps
CPU time 10.23 seconds
Started Jul 20 04:42:22 PM PDT 24
Finished Jul 20 04:42:35 PM PDT 24
Peak memory 201608 kb
Host smart-ea9cd207-4830-4d96-aaba-5cad233d2670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127305850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.127305850
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.4097938878
Short name T280
Test name
Test status
Simulation time 98973764316 ps
CPU time 57.92 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:43:22 PM PDT 24
Peak memory 201652 kb
Host smart-4df3678d-d713-4f9e-93f9-1c56e2c3a1f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097938878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.4097938878
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1123347294
Short name T534
Test name
Test status
Simulation time 28830907300 ps
CPU time 71.26 seconds
Started Jul 20 04:42:26 PM PDT 24
Finished Jul 20 04:43:39 PM PDT 24
Peak memory 202016 kb
Host smart-88a810b1-d17f-4256-81b7-6a97f55bb1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123347294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.1123347294
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.75198108
Short name T427
Test name
Test status
Simulation time 3558173102 ps
CPU time 3.66 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:42:24 PM PDT 24
Peak memory 201460 kb
Host smart-4b64bfd5-53f1-4268-a2b5-8b35f9017cbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75198108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_ec_pwr_on_rst.75198108
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2168514241
Short name T3
Test name
Test status
Simulation time 3702866844 ps
CPU time 8.96 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:33 PM PDT 24
Peak memory 201460 kb
Host smart-729c0835-36f8-4586-9848-f3e1a945cdc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168514241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.2168514241
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1833679061
Short name T65
Test name
Test status
Simulation time 2636454803 ps
CPU time 2.28 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:27 PM PDT 24
Peak memory 201364 kb
Host smart-a23fa12d-082e-4bb3-8387-13bc1313c33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833679061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1833679061
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1347029275
Short name T752
Test name
Test status
Simulation time 2494965250 ps
CPU time 3.63 seconds
Started Jul 20 04:42:19 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201540 kb
Host smart-b041230b-70a5-45f8-a21f-14d7c64baafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347029275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1347029275
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.4105864481
Short name T99
Test name
Test status
Simulation time 2172299205 ps
CPU time 5.86 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 201444 kb
Host smart-68b73ca3-8328-47a9-8dae-022c24d69938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105864481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.4105864481
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.814514826
Short name T140
Test name
Test status
Simulation time 2517401154 ps
CPU time 4.19 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:28 PM PDT 24
Peak memory 201364 kb
Host smart-cb48e2de-31c0-477b-be78-d1fc4dfa4b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814514826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.814514826
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.1655644503
Short name T698
Test name
Test status
Simulation time 2123378954 ps
CPU time 1.97 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201612 kb
Host smart-4784df3f-5d6f-4e5b-adfd-791abf8d2d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655644503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.1655644503
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.4146873910
Short name T621
Test name
Test status
Simulation time 12039188213 ps
CPU time 29.3 seconds
Started Jul 20 04:42:22 PM PDT 24
Finished Jul 20 04:42:54 PM PDT 24
Peak memory 201572 kb
Host smart-c89ca673-410b-42c1-8f35-db2f7862d738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146873910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.4146873910
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2494164490
Short name T531
Test name
Test status
Simulation time 9030591281 ps
CPU time 2.34 seconds
Started Jul 20 04:42:20 PM PDT 24
Finished Jul 20 04:42:25 PM PDT 24
Peak memory 201472 kb
Host smart-ad9cfa22-32ba-43ad-83b7-17e114aded53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494164490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2494164490
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3547471085
Short name T511
Test name
Test status
Simulation time 2032879343 ps
CPU time 1.83 seconds
Started Jul 20 04:42:27 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 201468 kb
Host smart-f85648aa-fd10-41ab-8eac-8fe77b555472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547471085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3547471085
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1544490838
Short name T584
Test name
Test status
Simulation time 3595653181 ps
CPU time 5.35 seconds
Started Jul 20 04:42:32 PM PDT 24
Finished Jul 20 04:42:39 PM PDT 24
Peak memory 201560 kb
Host smart-bea7116b-bb45-4558-8e16-018d9640dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544490838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1
544490838
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.856165670
Short name T273
Test name
Test status
Simulation time 96695011896 ps
CPU time 255.51 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:46:47 PM PDT 24
Peak memory 201740 kb
Host smart-619f7816-aacf-46dd-9226-49926677c67b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856165670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.856165670
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3368799958
Short name T381
Test name
Test status
Simulation time 56384029560 ps
CPU time 35.87 seconds
Started Jul 20 04:42:30 PM PDT 24
Finished Jul 20 04:43:08 PM PDT 24
Peak memory 201784 kb
Host smart-0608814c-ace7-45e1-a518-089d5f2e1fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368799958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.3368799958
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1345978236
Short name T704
Test name
Test status
Simulation time 3560857271 ps
CPU time 9.86 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:40 PM PDT 24
Peak memory 201432 kb
Host smart-5e51b9c7-013c-43dc-86eb-29b291a5ed2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345978236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.1345978236
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.4080463599
Short name T754
Test name
Test status
Simulation time 2757283093 ps
CPU time 2.13 seconds
Started Jul 20 04:42:30 PM PDT 24
Finished Jul 20 04:42:34 PM PDT 24
Peak memory 201492 kb
Host smart-6aa68701-5536-4bf7-a36c-f1c18b095bea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080463599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.4080463599
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2464756437
Short name T248
Test name
Test status
Simulation time 2610474007 ps
CPU time 7.59 seconds
Started Jul 20 04:42:30 PM PDT 24
Finished Jul 20 04:42:39 PM PDT 24
Peak memory 201476 kb
Host smart-b7d175a3-83ad-441a-b933-16f199d826de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464756437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2464756437
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2630973786
Short name T663
Test name
Test status
Simulation time 2471612960 ps
CPU time 2.14 seconds
Started Jul 20 04:42:21 PM PDT 24
Finished Jul 20 04:42:26 PM PDT 24
Peak memory 201536 kb
Host smart-1038e136-3466-466a-9bbb-9599eaa6e8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630973786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2630973786
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2770549639
Short name T159
Test name
Test status
Simulation time 2118491711 ps
CPU time 3.35 seconds
Started Jul 20 04:42:18 PM PDT 24
Finished Jul 20 04:42:23 PM PDT 24
Peak memory 201400 kb
Host smart-3b0c6906-bed0-454a-a83b-c1b25735c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770549639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2770549639
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1788750671
Short name T533
Test name
Test status
Simulation time 2515029786 ps
CPU time 3.79 seconds
Started Jul 20 04:42:30 PM PDT 24
Finished Jul 20 04:42:36 PM PDT 24
Peak memory 201464 kb
Host smart-172b1b10-90c3-4708-beaf-11e98f9aa2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788750671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1788750671
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.2991090492
Short name T426
Test name
Test status
Simulation time 2114715797 ps
CPU time 5.13 seconds
Started Jul 20 04:42:22 PM PDT 24
Finished Jul 20 04:42:29 PM PDT 24
Peak memory 201256 kb
Host smart-2c607579-9dc5-4f66-9c04-8f8c13464ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991090492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2991090492
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.4247516690
Short name T454
Test name
Test status
Simulation time 11248398750 ps
CPU time 5.92 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:37 PM PDT 24
Peak memory 201744 kb
Host smart-2fb20f2e-243a-4b1c-aea1-65108d3822d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247516690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.4247516690
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2173066145
Short name T537
Test name
Test status
Simulation time 4103841210 ps
CPU time 2.19 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:33 PM PDT 24
Peak memory 201492 kb
Host smart-e4014668-9bfa-4b05-b3b4-0da6da13376b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173066145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.2173066145
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.3862692002
Short name T467
Test name
Test status
Simulation time 2011375098 ps
CPU time 5.86 seconds
Started Jul 20 04:42:28 PM PDT 24
Finished Jul 20 04:42:35 PM PDT 24
Peak memory 201512 kb
Host smart-054a5065-b101-4df0-af37-a4a317d2fe84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862692002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.3862692002
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1729002594
Short name T565
Test name
Test status
Simulation time 3839901405 ps
CPU time 10.89 seconds
Started Jul 20 04:42:31 PM PDT 24
Finished Jul 20 04:42:43 PM PDT 24
Peak memory 201528 kb
Host smart-e827d16e-e31d-4019-8f2b-40174c86c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729002594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1
729002594
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.2843210954
Short name T267
Test name
Test status
Simulation time 65403156823 ps
CPU time 156.5 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:45:08 PM PDT 24
Peak memory 201728 kb
Host smart-9563f5a3-5edb-42ec-888f-820426950e38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843210954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.2843210954
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.868266712
Short name T603
Test name
Test status
Simulation time 58096942864 ps
CPU time 35.35 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201792 kb
Host smart-a2c017f0-47a3-49b5-8c00-c8ce0678bef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868266712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_wi
th_pre_cond.868266712
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2505431353
Short name T633
Test name
Test status
Simulation time 2777709098 ps
CPU time 2.31 seconds
Started Jul 20 04:42:31 PM PDT 24
Finished Jul 20 04:42:35 PM PDT 24
Peak memory 201500 kb
Host smart-efdc8f3d-2320-47ff-9e5b-192210910052
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505431353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.2505431353
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2785349710
Short name T10
Test name
Test status
Simulation time 3388484723 ps
CPU time 6.2 seconds
Started Jul 20 04:42:31 PM PDT 24
Finished Jul 20 04:42:39 PM PDT 24
Peak memory 201432 kb
Host smart-4eab7e77-adfe-40fe-821b-4232bbb7732e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785349710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.2785349710
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.363394450
Short name T610
Test name
Test status
Simulation time 2609886948 ps
CPU time 7.76 seconds
Started Jul 20 04:42:31 PM PDT 24
Finished Jul 20 04:42:40 PM PDT 24
Peak memory 201524 kb
Host smart-620130ec-8771-4e38-aac5-5202df4a4c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363394450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.363394450
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.1159808414
Short name T673
Test name
Test status
Simulation time 2474138627 ps
CPU time 2.71 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:32 PM PDT 24
Peak memory 201540 kb
Host smart-c62e1667-3a59-4c03-a19d-834268ab2ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159808414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.1159808414
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2156427069
Short name T203
Test name
Test status
Simulation time 2063338224 ps
CPU time 1.31 seconds
Started Jul 20 04:42:28 PM PDT 24
Finished Jul 20 04:42:31 PM PDT 24
Peak memory 201468 kb
Host smart-308f6216-2142-4ce2-a94b-898415480041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156427069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2156427069
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3136037261
Short name T622
Test name
Test status
Simulation time 2526377988 ps
CPU time 2.38 seconds
Started Jul 20 04:42:33 PM PDT 24
Finished Jul 20 04:42:36 PM PDT 24
Peak memory 201460 kb
Host smart-30fed1f0-8290-4eb9-b043-8f70f5cb98f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136037261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.3136037261
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.1511184282
Short name T620
Test name
Test status
Simulation time 2129461884 ps
CPU time 2.04 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:33 PM PDT 24
Peak memory 201384 kb
Host smart-e8a20a07-76dc-4ac5-b8c1-90dc19c9f01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511184282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1511184282
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.28155887
Short name T583
Test name
Test status
Simulation time 14203552620 ps
CPU time 34.03 seconds
Started Jul 20 04:42:31 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201484 kb
Host smart-fa5961a5-7fb8-4165-8a11-f84c2f87810a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28155887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_str
ess_all.28155887
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1326392767
Short name T317
Test name
Test status
Simulation time 4372756495 ps
CPU time 2.21 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:32 PM PDT 24
Peak memory 201340 kb
Host smart-215265ba-edf5-498e-a483-b2dc63bc5366
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326392767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.1326392767
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.3959478103
Short name T469
Test name
Test status
Simulation time 2011499191 ps
CPU time 6.02 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:48 PM PDT 24
Peak memory 201532 kb
Host smart-30570430-be74-4aec-8abf-2a1b1cb06d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959478103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.3959478103
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.4237662245
Short name T595
Test name
Test status
Simulation time 3331645614 ps
CPU time 1.69 seconds
Started Jul 20 04:42:38 PM PDT 24
Finished Jul 20 04:42:41 PM PDT 24
Peak memory 201512 kb
Host smart-bb2af84c-c5a6-45d1-8322-dc3041da1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237662245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.4
237662245
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.1489614887
Short name T352
Test name
Test status
Simulation time 139940461447 ps
CPU time 325.87 seconds
Started Jul 20 04:42:42 PM PDT 24
Finished Jul 20 04:48:10 PM PDT 24
Peak memory 201736 kb
Host smart-f9844774-628a-4069-b043-40845e4d13eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489614887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.1489614887
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2185865189
Short name T647
Test name
Test status
Simulation time 91070679427 ps
CPU time 110.34 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:44:31 PM PDT 24
Peak memory 201864 kb
Host smart-55868e56-8d3c-4f4d-8e09-ab1534dcdf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185865189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.2185865189
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3132735835
Short name T717
Test name
Test status
Simulation time 4115917952 ps
CPU time 3.77 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:34 PM PDT 24
Peak memory 201464 kb
Host smart-722e1614-1ec9-445b-b422-de25d62c85f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132735835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.3132735835
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.1342062513
Short name T174
Test name
Test status
Simulation time 3111055987 ps
CPU time 1.73 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:42 PM PDT 24
Peak memory 201464 kb
Host smart-8c44c281-f651-41af-b322-a9b760cd16fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342062513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.1342062513
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3389647202
Short name T227
Test name
Test status
Simulation time 2611553564 ps
CPU time 7.24 seconds
Started Jul 20 04:42:28 PM PDT 24
Finished Jul 20 04:42:37 PM PDT 24
Peak memory 201468 kb
Host smart-0303c47c-8d49-4950-aff3-39b82c693aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389647202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3389647202
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2102337925
Short name T430
Test name
Test status
Simulation time 2477555484 ps
CPU time 7.03 seconds
Started Jul 20 04:42:31 PM PDT 24
Finished Jul 20 04:42:40 PM PDT 24
Peak memory 201444 kb
Host smart-22c989ad-d074-43bb-bc49-4e1ca50fdb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102337925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2102337925
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1793564817
Short name T401
Test name
Test status
Simulation time 2192276683 ps
CPU time 5.75 seconds
Started Jul 20 04:42:29 PM PDT 24
Finished Jul 20 04:42:36 PM PDT 24
Peak memory 201536 kb
Host smart-6efb179c-e09d-4e5a-a5b4-f838a46b3265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793564817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.1793564817
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.127849151
Short name T497
Test name
Test status
Simulation time 2509696033 ps
CPU time 7.62 seconds
Started Jul 20 04:42:28 PM PDT 24
Finished Jul 20 04:42:37 PM PDT 24
Peak memory 201452 kb
Host smart-e827c2b5-836a-430c-9df2-4ee6d5c340f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127849151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.127849151
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.850399277
Short name T215
Test name
Test status
Simulation time 2110500420 ps
CPU time 6.13 seconds
Started Jul 20 04:42:31 PM PDT 24
Finished Jul 20 04:42:38 PM PDT 24
Peak memory 201444 kb
Host smart-a9b42a21-09cf-4c41-ac90-cccdf50ceb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850399277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.850399277
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.1084494516
Short name T594
Test name
Test status
Simulation time 8690006362 ps
CPU time 23.6 seconds
Started Jul 20 04:42:38 PM PDT 24
Finished Jul 20 04:43:03 PM PDT 24
Peak memory 201476 kb
Host smart-c65f44f7-369e-41e9-86a2-58e85e4c9bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084494516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.1084494516
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2945410912
Short name T147
Test name
Test status
Simulation time 3825127174 ps
CPU time 7.08 seconds
Started Jul 20 04:42:43 PM PDT 24
Finished Jul 20 04:42:52 PM PDT 24
Peak memory 201420 kb
Host smart-5391493f-88e3-4456-8663-d77824f5c43f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945410912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2945410912
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.2268854103
Short name T144
Test name
Test status
Simulation time 2036982010 ps
CPU time 1.61 seconds
Started Jul 20 04:42:37 PM PDT 24
Finished Jul 20 04:42:39 PM PDT 24
Peak memory 201448 kb
Host smart-f2e9802a-4ff5-4a99-9692-86d2cb60b36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268854103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.2268854103
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2803983773
Short name T699
Test name
Test status
Simulation time 3095778831 ps
CPU time 5.58 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:42:49 PM PDT 24
Peak memory 201524 kb
Host smart-b6c2c269-f53a-4f7f-8a7c-34d17006bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803983773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2
803983773
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.3441320077
Short name T116
Test name
Test status
Simulation time 147474577371 ps
CPU time 382.91 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:49:03 PM PDT 24
Peak memory 201728 kb
Host smart-0acea4ad-e392-4ce9-934f-ae66745af839
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441320077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.3441320077
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.866465341
Short name T601
Test name
Test status
Simulation time 2958720145 ps
CPU time 1.55 seconds
Started Jul 20 04:42:38 PM PDT 24
Finished Jul 20 04:42:41 PM PDT 24
Peak memory 201440 kb
Host smart-be0a7f56-6607-4962-810b-51161b6faea4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866465341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.866465341
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.1972486176
Short name T197
Test name
Test status
Simulation time 4655060932 ps
CPU time 2.62 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:42:46 PM PDT 24
Peak memory 201572 kb
Host smart-995cdcb8-6bb2-43f0-9ce8-f08184c5f4c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972486176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.1972486176
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1672130397
Short name T216
Test name
Test status
Simulation time 2613305073 ps
CPU time 7.57 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:42:51 PM PDT 24
Peak memory 201460 kb
Host smart-4080237a-52e1-4637-8d52-779d0fff9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672130397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1672130397
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1191780921
Short name T681
Test name
Test status
Simulation time 2452849895 ps
CPU time 7.17 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:48 PM PDT 24
Peak memory 201468 kb
Host smart-44b5b493-a9d2-4000-8efa-9ee441433fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191780921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1191780921
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3401939580
Short name T529
Test name
Test status
Simulation time 2079261610 ps
CPU time 1.92 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:42 PM PDT 24
Peak memory 201612 kb
Host smart-20d9acea-2e3c-44cd-8fc3-2f12f2c4aeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401939580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3401939580
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.317063236
Short name T223
Test name
Test status
Simulation time 2514980077 ps
CPU time 4.83 seconds
Started Jul 20 04:42:38 PM PDT 24
Finished Jul 20 04:42:44 PM PDT 24
Peak memory 201508 kb
Host smart-ec7210cd-c8de-4755-9d11-7e5bcf1e5f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317063236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.317063236
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.4168828015
Short name T687
Test name
Test status
Simulation time 2118874139 ps
CPU time 3.14 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:43 PM PDT 24
Peak memory 201392 kb
Host smart-3d43d349-361e-4b28-91ff-9cc269f07ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168828015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.4168828015
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.963832636
Short name T332
Test name
Test status
Simulation time 6097794638 ps
CPU time 16.48 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:58 PM PDT 24
Peak memory 201468 kb
Host smart-57c05b8d-802e-4f31-a697-9b107814bb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963832636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.963832636
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3872626490
Short name T164
Test name
Test status
Simulation time 42318930412 ps
CPU time 27.07 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:43:11 PM PDT 24
Peak memory 218060 kb
Host smart-204652e0-7fff-4c2b-98be-f5d4c5f677e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872626490 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3872626490
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.517596060
Short name T132
Test name
Test status
Simulation time 3525159074699 ps
CPU time 101.07 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:44:22 PM PDT 24
Peak memory 201432 kb
Host smart-f082adff-6963-45b2-a169-59464c170ec3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517596060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ultra_low_pwr.517596060
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3032413161
Short name T123
Test name
Test status
Simulation time 2039787377 ps
CPU time 1.94 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:42 PM PDT 24
Peak memory 201464 kb
Host smart-1aa7ca43-75df-45e2-9a2a-e2386e5b0f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032413161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3032413161
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3370490124
Short name T33
Test name
Test status
Simulation time 3830435450 ps
CPU time 4.93 seconds
Started Jul 20 04:42:42 PM PDT 24
Finished Jul 20 04:42:49 PM PDT 24
Peak memory 201480 kb
Host smart-78b7b878-4858-48f4-8cf5-b9a18aa8e7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370490124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.3
370490124
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1073340347
Short name T9
Test name
Test status
Simulation time 79530077831 ps
CPU time 204.55 seconds
Started Jul 20 04:42:42 PM PDT 24
Finished Jul 20 04:46:09 PM PDT 24
Peak memory 201584 kb
Host smart-58dcff7d-3983-4825-8407-0d4fa64e204f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073340347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1073340347
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1093314168
Short name T255
Test name
Test status
Simulation time 54702104428 ps
CPU time 74.26 seconds
Started Jul 20 04:42:38 PM PDT 24
Finished Jul 20 04:43:54 PM PDT 24
Peak memory 201900 kb
Host smart-818b796a-73c9-456a-88d4-e7ea86832bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093314168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1093314168
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1715024093
Short name T178
Test name
Test status
Simulation time 3755155880 ps
CPU time 10.8 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:42:54 PM PDT 24
Peak memory 201424 kb
Host smart-dd3051c6-f4e9-4548-8099-790216935592
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715024093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.1715024093
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.920928711
Short name T607
Test name
Test status
Simulation time 3023456828 ps
CPU time 6.48 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:42:49 PM PDT 24
Peak memory 201448 kb
Host smart-9c5bd846-ec89-4011-a4de-6c0fd978657c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920928711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.920928711
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2277038941
Short name T443
Test name
Test status
Simulation time 2612124598 ps
CPU time 6.65 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:48 PM PDT 24
Peak memory 201540 kb
Host smart-e4bf4291-88ca-4760-a263-6e77e917cc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277038941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.2277038941
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.159560451
Short name T74
Test name
Test status
Simulation time 2558307858 ps
CPU time 1.1 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:44 PM PDT 24
Peak memory 201448 kb
Host smart-ab51f8db-92e6-456f-8518-7bd5864c05a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159560451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.159560451
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2535805653
Short name T480
Test name
Test status
Simulation time 2203617090 ps
CPU time 6.22 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:48 PM PDT 24
Peak memory 201528 kb
Host smart-a73fba5d-a9cf-4d61-9845-ebcdc57722f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535805653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2535805653
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1366952186
Short name T599
Test name
Test status
Simulation time 2530580273 ps
CPU time 2.47 seconds
Started Jul 20 04:42:43 PM PDT 24
Finished Jul 20 04:42:47 PM PDT 24
Peak memory 201404 kb
Host smart-5af2be8e-57c5-4bd3-b693-1601cab33c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366952186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1366952186
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.201332211
Short name T421
Test name
Test status
Simulation time 2112229743 ps
CPU time 3.23 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:44 PM PDT 24
Peak memory 201380 kb
Host smart-5d6bf340-b22b-4535-9fb8-e768a23c36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201332211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.201332211
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.1367493224
Short name T635
Test name
Test status
Simulation time 11802545800 ps
CPU time 15.48 seconds
Started Jul 20 04:42:46 PM PDT 24
Finished Jul 20 04:43:02 PM PDT 24
Peak memory 201528 kb
Host smart-bf7f830b-71e3-4541-8566-33e1ec6b9106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367493224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.1367493224
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.558005837
Short name T239
Test name
Test status
Simulation time 61543212060 ps
CPU time 32.06 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:43:13 PM PDT 24
Peak memory 217424 kb
Host smart-008c452d-d23e-41a4-abbf-c1b1bb8d1a4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558005837 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.558005837
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.4118017030
Short name T674
Test name
Test status
Simulation time 6772073328 ps
CPU time 7.24 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:50 PM PDT 24
Peak memory 201408 kb
Host smart-b3e06994-151f-4fc4-b20f-be9faf4d4e72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118017030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.4118017030
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.939845531
Short name T789
Test name
Test status
Simulation time 2021692625 ps
CPU time 3.09 seconds
Started Jul 20 04:41:19 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201388 kb
Host smart-f800d3de-594f-411a-93a5-6cd0ba303dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939845531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test
.939845531
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1046717901
Short name T701
Test name
Test status
Simulation time 46484291419 ps
CPU time 22.95 seconds
Started Jul 20 04:41:11 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 201600 kb
Host smart-e0f9544f-c080-4c0b-8c16-13000928d6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046717901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.1046717901
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.2463932664
Short name T353
Test name
Test status
Simulation time 95681513744 ps
CPU time 94.3 seconds
Started Jul 20 04:41:11 PM PDT 24
Finished Jul 20 04:42:47 PM PDT 24
Peak memory 201736 kb
Host smart-09c4a2df-d837-4d69-8407-0f5ab88b64fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463932664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.2463932664
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2402750445
Short name T108
Test name
Test status
Simulation time 2175565415 ps
CPU time 6.17 seconds
Started Jul 20 04:41:10 PM PDT 24
Finished Jul 20 04:41:17 PM PDT 24
Peak memory 201464 kb
Host smart-36f7d75b-240a-48d1-9fd8-f70db43d4269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402750445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2402750445
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3929712159
Short name T532
Test name
Test status
Simulation time 2315763913 ps
CPU time 6.42 seconds
Started Jul 20 04:41:11 PM PDT 24
Finished Jul 20 04:41:18 PM PDT 24
Peak memory 201500 kb
Host smart-54bcceed-a683-4717-8388-a7545b13f324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929712159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3929712159
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1998196320
Short name T657
Test name
Test status
Simulation time 3088596422 ps
CPU time 2.32 seconds
Started Jul 20 04:41:09 PM PDT 24
Finished Jul 20 04:41:12 PM PDT 24
Peak memory 201440 kb
Host smart-c0a811b2-9a98-47b9-803c-554c5932959b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998196320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1998196320
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2014824275
Short name T666
Test name
Test status
Simulation time 2744272263 ps
CPU time 7.68 seconds
Started Jul 20 04:41:12 PM PDT 24
Finished Jul 20 04:41:21 PM PDT 24
Peak memory 201452 kb
Host smart-f1a36d42-6292-4b45-a2d8-9df3e38cda6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014824275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.2014824275
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.748758610
Short name T188
Test name
Test status
Simulation time 2611714359 ps
CPU time 7.49 seconds
Started Jul 20 04:41:10 PM PDT 24
Finished Jul 20 04:41:18 PM PDT 24
Peak memory 201452 kb
Host smart-51395143-c770-4a4b-a5b6-5a52e4782c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748758610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.748758610
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.836509631
Short name T576
Test name
Test status
Simulation time 2455376591 ps
CPU time 6.35 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:26 PM PDT 24
Peak memory 201464 kb
Host smart-1dc294e1-dd6a-49f3-bfba-dcfd7780f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836509631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.836509631
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1496965307
Short name T200
Test name
Test status
Simulation time 2056389659 ps
CPU time 3.03 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:22 PM PDT 24
Peak memory 201404 kb
Host smart-9e20fcc5-1032-4022-842a-bdeb84e10098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496965307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1496965307
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1652533762
Short name T507
Test name
Test status
Simulation time 2522235894 ps
CPU time 3.89 seconds
Started Jul 20 04:41:11 PM PDT 24
Finished Jul 20 04:41:16 PM PDT 24
Peak memory 201676 kb
Host smart-9322300f-6f22-4ef5-8b1b-3299ee60bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652533762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1652533762
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.702556560
Short name T299
Test name
Test status
Simulation time 22018462678 ps
CPU time 29.86 seconds
Started Jul 20 04:41:19 PM PDT 24
Finished Jul 20 04:41:51 PM PDT 24
Peak memory 220112 kb
Host smart-98f528e8-abab-420c-aef4-cef537b0c7ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702556560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.702556560
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.1634970558
Short name T606
Test name
Test status
Simulation time 2110992439 ps
CPU time 5.58 seconds
Started Jul 20 04:41:07 PM PDT 24
Finished Jul 20 04:41:14 PM PDT 24
Peak memory 201360 kb
Host smart-835ed36e-643d-4e67-a623-09d0c6d09e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634970558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1634970558
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.1497732571
Short name T636
Test name
Test status
Simulation time 13180418365 ps
CPU time 32.87 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:52 PM PDT 24
Peak memory 201496 kb
Host smart-fcc8e8a0-f863-40f3-8fd3-b63426e75747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497732571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.1497732571
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.596305478
Short name T765
Test name
Test status
Simulation time 16958612890 ps
CPU time 42.93 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:42:00 PM PDT 24
Peak memory 210028 kb
Host smart-160fe9cd-f143-4ab9-b961-643bd806ed61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596305478 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.596305478
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.4027040228
Short name T457
Test name
Test status
Simulation time 7552292062 ps
CPU time 5.9 seconds
Started Jul 20 04:41:10 PM PDT 24
Finished Jul 20 04:41:16 PM PDT 24
Peak memory 201524 kb
Host smart-db9e19b4-e421-438f-b0b7-4744a2529209
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027040228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.4027040228
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.3381141679
Short name T721
Test name
Test status
Simulation time 2011621483 ps
CPU time 5.4 seconds
Started Jul 20 04:42:42 PM PDT 24
Finished Jul 20 04:42:50 PM PDT 24
Peak memory 201440 kb
Host smart-4445081a-1446-4a78-be78-8f4236f051f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381141679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.3381141679
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1990719322
Short name T32
Test name
Test status
Simulation time 3324052085 ps
CPU time 4.86 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:47 PM PDT 24
Peak memory 201560 kb
Host smart-335bd336-9c51-4c5a-be8a-5dad98f351b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990719322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1
990719322
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3736551756
Short name T54
Test name
Test status
Simulation time 61341981067 ps
CPU time 40.81 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:43:24 PM PDT 24
Peak memory 201656 kb
Host smart-77aaa4b3-2a65-4ef5-be17-3626a1062d13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736551756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3736551756
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2787871285
Short name T111
Test name
Test status
Simulation time 25362600842 ps
CPU time 17.84 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:57 PM PDT 24
Peak memory 201808 kb
Host smart-6bcd1772-e491-43fe-8c53-78798873b931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787871285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.2787871285
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.575782038
Short name T447
Test name
Test status
Simulation time 3186030221 ps
CPU time 8.82 seconds
Started Jul 20 04:42:38 PM PDT 24
Finished Jul 20 04:42:48 PM PDT 24
Peak memory 201520 kb
Host smart-21808ea4-aa5c-4221-b636-0b320b9a9dba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575782038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ec_pwr_on_rst.575782038
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3895483783
Short name T742
Test name
Test status
Simulation time 2468707163 ps
CPU time 2.05 seconds
Started Jul 20 04:42:45 PM PDT 24
Finished Jul 20 04:42:48 PM PDT 24
Peak memory 201524 kb
Host smart-c042d258-e627-4b9f-bcb9-ff23e46fe83d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895483783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.3895483783
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1444138684
Short name T481
Test name
Test status
Simulation time 2639451458 ps
CPU time 2.45 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:45 PM PDT 24
Peak memory 201512 kb
Host smart-1d9a31f3-b3cd-47ed-a2b3-e74b38986fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444138684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1444138684
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3860035291
Short name T561
Test name
Test status
Simulation time 2455636378 ps
CPU time 6.39 seconds
Started Jul 20 04:42:44 PM PDT 24
Finished Jul 20 04:42:52 PM PDT 24
Peak memory 201480 kb
Host smart-dd6404ba-5ea0-41ad-9d39-e70b80280f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860035291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3860035291
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.220201450
Short name T530
Test name
Test status
Simulation time 2210445544 ps
CPU time 6.56 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:49 PM PDT 24
Peak memory 201464 kb
Host smart-ea810532-b4b5-4229-80ad-cc4d6009cc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220201450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.220201450
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.42600498
Short name T177
Test name
Test status
Simulation time 2513725665 ps
CPU time 4.05 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:45 PM PDT 24
Peak memory 201472 kb
Host smart-95b55bc9-4659-49f9-932e-6528d95146d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42600498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.42600498
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.110475343
Short name T408
Test name
Test status
Simulation time 2159683157 ps
CPU time 1.1 seconds
Started Jul 20 04:42:39 PM PDT 24
Finished Jul 20 04:42:42 PM PDT 24
Peak memory 201400 kb
Host smart-64927a91-2ffb-432e-8b56-3f8229f58840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110475343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.110475343
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.1510741315
Short name T446
Test name
Test status
Simulation time 194800479662 ps
CPU time 223.5 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:46:27 PM PDT 24
Peak memory 201580 kb
Host smart-0bde715d-72b8-49a8-80f7-37486c357975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510741315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.1510741315
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.323755191
Short name T627
Test name
Test status
Simulation time 39924580505 ps
CPU time 93.81 seconds
Started Jul 20 04:42:43 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 218040 kb
Host smart-2d31af42-4c8b-4afd-88d1-055706974b23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323755191 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.323755191
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1154643253
Short name T731
Test name
Test status
Simulation time 3531286600 ps
CPU time 3.84 seconds
Started Jul 20 04:42:46 PM PDT 24
Finished Jul 20 04:42:50 PM PDT 24
Peak memory 201544 kb
Host smart-6775f811-64c9-44e3-8ceb-8b3edbea3888
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154643253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.1154643253
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.3048465851
Short name T168
Test name
Test status
Simulation time 2028231915 ps
CPU time 1.76 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:42:53 PM PDT 24
Peak memory 201348 kb
Host smart-6e071b0a-4968-48b6-8d45-b172731c73a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048465851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.3048465851
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.4252927100
Short name T61
Test name
Test status
Simulation time 3094891605 ps
CPU time 8.43 seconds
Started Jul 20 04:42:43 PM PDT 24
Finished Jul 20 04:42:53 PM PDT 24
Peak memory 201568 kb
Host smart-4fc7780e-978d-4f5d-b9b4-555f48ef2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252927100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.4
252927100
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.4057167342
Short name T360
Test name
Test status
Simulation time 34564114067 ps
CPU time 49.57 seconds
Started Jul 20 04:42:45 PM PDT 24
Finished Jul 20 04:43:35 PM PDT 24
Peak memory 201740 kb
Host smart-9e0f1c02-ca3c-4c74-ab55-8b283337a05b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057167342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.4057167342
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.468147398
Short name T380
Test name
Test status
Simulation time 123024087081 ps
CPU time 318.4 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:48:01 PM PDT 24
Peak memory 201728 kb
Host smart-0e0763a1-affd-4ead-a5c9-b9117da3e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468147398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_wi
th_pre_cond.468147398
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1182636601
Short name T432
Test name
Test status
Simulation time 4450974333 ps
CPU time 1.46 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:42:45 PM PDT 24
Peak memory 201640 kb
Host smart-70b51d4a-0933-4e80-83d9-7e85fb4f0ae1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182636601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.1182636601
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.338544360
Short name T43
Test name
Test status
Simulation time 3631310846 ps
CPU time 6.94 seconds
Started Jul 20 04:42:43 PM PDT 24
Finished Jul 20 04:42:52 PM PDT 24
Peak memory 201384 kb
Host smart-2aabed72-9052-460e-a428-5afc78e40aae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338544360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctr
l_edge_detect.338544360
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2338609729
Short name T226
Test name
Test status
Simulation time 2615632437 ps
CPU time 6.93 seconds
Started Jul 20 04:42:41 PM PDT 24
Finished Jul 20 04:42:51 PM PDT 24
Peak memory 201380 kb
Host smart-5ecaa0f7-cc71-4a14-908a-9ef157f68e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338609729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2338609729
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2944643136
Short name T499
Test name
Test status
Simulation time 2470675322 ps
CPU time 4.42 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:46 PM PDT 24
Peak memory 201540 kb
Host smart-fe6ca812-0cf1-455a-b4bc-a945a673cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944643136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2944643136
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2866103642
Short name T656
Test name
Test status
Simulation time 2093545887 ps
CPU time 2.06 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:45 PM PDT 24
Peak memory 201444 kb
Host smart-9266f627-3628-41d6-877c-fbb4ce327ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866103642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2866103642
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2983144687
Short name T785
Test name
Test status
Simulation time 2511167777 ps
CPU time 6.74 seconds
Started Jul 20 04:42:43 PM PDT 24
Finished Jul 20 04:42:51 PM PDT 24
Peak memory 201404 kb
Host smart-91c50af7-17a8-43a1-97a6-2c637b9e876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983144687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2983144687
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.673310707
Short name T231
Test name
Test status
Simulation time 2110532330 ps
CPU time 5.74 seconds
Started Jul 20 04:42:40 PM PDT 24
Finished Jul 20 04:42:48 PM PDT 24
Peak memory 201360 kb
Host smart-a7eb181d-732b-46e9-a645-c38b980fd710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673310707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.673310707
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.3138081859
Short name T780
Test name
Test status
Simulation time 8226262679 ps
CPU time 18.4 seconds
Started Jul 20 04:42:43 PM PDT 24
Finished Jul 20 04:43:03 PM PDT 24
Peak memory 201416 kb
Host smart-f1a8ba93-a730-418b-ab43-f6087f0e7f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138081859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.3138081859
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.2368460156
Short name T83
Test name
Test status
Simulation time 2032355316 ps
CPU time 1.91 seconds
Started Jul 20 04:42:52 PM PDT 24
Finished Jul 20 04:42:55 PM PDT 24
Peak memory 201440 kb
Host smart-649c8d24-0bbb-40de-8cef-60133f8472eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368460156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.2368460156
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3258447284
Short name T725
Test name
Test status
Simulation time 307258022986 ps
CPU time 824.52 seconds
Started Jul 20 04:42:55 PM PDT 24
Finished Jul 20 04:56:41 PM PDT 24
Peak memory 201560 kb
Host smart-6f1d519a-dabf-4b11-b661-5d9789abc525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258447284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3
258447284
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.176332551
Short name T139
Test name
Test status
Simulation time 76479293237 ps
CPU time 52.71 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:56 PM PDT 24
Peak memory 201204 kb
Host smart-61b118d8-fb5e-4446-8f7e-bc8e393c4b66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176332551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_combo_detect.176332551
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.491159340
Short name T439
Test name
Test status
Simulation time 3150566565 ps
CPU time 8.88 seconds
Started Jul 20 04:42:46 PM PDT 24
Finished Jul 20 04:42:56 PM PDT 24
Peak memory 201448 kb
Host smart-481cb542-766c-4d52-980d-bd3fd5176b10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491159340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.491159340
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3438098620
Short name T152
Test name
Test status
Simulation time 3376789926 ps
CPU time 2.47 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:42:54 PM PDT 24
Peak memory 201452 kb
Host smart-cdc67a94-1400-4d2e-b85a-7219407fd793
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438098620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.3438098620
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1167722297
Short name T544
Test name
Test status
Simulation time 2632718560 ps
CPU time 2.21 seconds
Started Jul 20 04:42:46 PM PDT 24
Finished Jul 20 04:42:49 PM PDT 24
Peak memory 201452 kb
Host smart-8fbd6012-1e35-4baf-b57b-e2a5d01c2e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167722297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1167722297
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1635382286
Short name T22
Test name
Test status
Simulation time 2546723687 ps
CPU time 1.31 seconds
Started Jul 20 04:42:51 PM PDT 24
Finished Jul 20 04:42:54 PM PDT 24
Peak memory 201448 kb
Host smart-67294d0c-233b-4984-a9d2-2a0b4ff6301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635382286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1635382286
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3564726445
Short name T456
Test name
Test status
Simulation time 2258309048 ps
CPU time 2.27 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:42:52 PM PDT 24
Peak memory 201512 kb
Host smart-47eb97f5-8106-4a1d-88e6-de341e504de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564726445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3564726445
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2751423856
Short name T516
Test name
Test status
Simulation time 2513928716 ps
CPU time 3.87 seconds
Started Jul 20 04:42:55 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 201364 kb
Host smart-adb81244-b7d6-4274-99cf-fa5ba7dd31ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751423856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2751423856
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.525934319
Short name T763
Test name
Test status
Simulation time 2124176390 ps
CPU time 2.06 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:42:52 PM PDT 24
Peak memory 201436 kb
Host smart-787412b5-f2fe-453f-9340-fb4bbc5fcf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525934319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.525934319
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.6380628
Short name T312
Test name
Test status
Simulation time 11993738365 ps
CPU time 5.85 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:42:58 PM PDT 24
Peak memory 201488 kb
Host smart-304102cc-bb40-4e72-b99d-499aec9eacf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6380628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stre
ss_all.6380628
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1749052793
Short name T46
Test name
Test status
Simulation time 31540561849 ps
CPU time 74.11 seconds
Started Jul 20 04:42:47 PM PDT 24
Finished Jul 20 04:44:02 PM PDT 24
Peak memory 218280 kb
Host smart-fb5ebffd-1951-4876-8159-f29b3477980e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749052793 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.1749052793
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2881834280
Short name T71
Test name
Test status
Simulation time 5605419843 ps
CPU time 2.54 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:42:51 PM PDT 24
Peak memory 201448 kb
Host smart-a747e393-09f7-4bd5-9114-9f7e7b3a039a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881834280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.2881834280
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.780595605
Short name T568
Test name
Test status
Simulation time 2012922456 ps
CPU time 5.7 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:42:56 PM PDT 24
Peak memory 201460 kb
Host smart-d02996b2-2b37-4ca7-b0d1-5f4074903d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780595605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_tes
t.780595605
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3849615001
Short name T322
Test name
Test status
Simulation time 70115287746 ps
CPU time 21.45 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:43:13 PM PDT 24
Peak memory 201532 kb
Host smart-c2e2e207-53de-45d7-be44-5336f60acec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849615001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3
849615001
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1730242786
Short name T371
Test name
Test status
Simulation time 115689485239 ps
CPU time 29.35 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:43:19 PM PDT 24
Peak memory 201808 kb
Host smart-46550ab8-246d-463f-8395-5e47c9b71cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730242786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.1730242786
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3423760606
Short name T668
Test name
Test status
Simulation time 3384390727 ps
CPU time 8.65 seconds
Started Jul 20 04:42:47 PM PDT 24
Finished Jul 20 04:42:57 PM PDT 24
Peak memory 201472 kb
Host smart-f821d94d-c02d-4012-8b69-fad5a5d7ce90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423760606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.3423760606
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2800341170
Short name T201
Test name
Test status
Simulation time 2610410586 ps
CPU time 7.69 seconds
Started Jul 20 04:42:49 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 201524 kb
Host smart-50b61c01-ce6f-40d8-93c3-94f510af2da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800341170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2800341170
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3745937657
Short name T753
Test name
Test status
Simulation time 2475744269 ps
CPU time 4.76 seconds
Started Jul 20 04:42:52 PM PDT 24
Finished Jul 20 04:42:58 PM PDT 24
Peak memory 201540 kb
Host smart-172d8aab-9f53-4412-80d5-43f4b506f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745937657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3745937657
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.675031262
Short name T246
Test name
Test status
Simulation time 2244230385 ps
CPU time 3.47 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:42:55 PM PDT 24
Peak memory 201468 kb
Host smart-096a28b8-fba3-49a9-a3d4-bb3f2a864159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675031262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.675031262
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2678230463
Short name T734
Test name
Test status
Simulation time 2510254714 ps
CPU time 6.93 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 201464 kb
Host smart-5cae074f-ac54-48cf-8b1f-10f363a9fa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678230463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.2678230463
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.417841256
Short name T211
Test name
Test status
Simulation time 2119545356 ps
CPU time 3.25 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:42:53 PM PDT 24
Peak memory 201304 kb
Host smart-17883c40-12a5-4230-b83c-2acf362be706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417841256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.417841256
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3357828609
Short name T693
Test name
Test status
Simulation time 9879453926 ps
CPU time 8.25 seconds
Started Jul 20 04:42:49 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 201456 kb
Host smart-85482fb6-38ca-49ed-bad3-47ad7c3b6bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357828609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3357828609
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2145394933
Short name T120
Test name
Test status
Simulation time 46076126063 ps
CPU time 45.86 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:43:38 PM PDT 24
Peak memory 210080 kb
Host smart-1d3b5487-368e-4dfa-ba02-2dfbb52edb33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145394933 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2145394933
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2674839702
Short name T402
Test name
Test status
Simulation time 5393894148 ps
CPU time 6 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:42:57 PM PDT 24
Peak memory 201432 kb
Host smart-e6e79715-2de9-4af4-8d7c-e6948e6bf718
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674839702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.2674839702
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.501528632
Short name T514
Test name
Test status
Simulation time 2012343725 ps
CPU time 5.64 seconds
Started Jul 20 04:42:52 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 201452 kb
Host smart-8b7416b5-b2bc-46d0-bc40-28337cc69dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501528632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_tes
t.501528632
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2617440477
Short name T483
Test name
Test status
Simulation time 3441778896 ps
CPU time 9.23 seconds
Started Jul 20 04:42:54 PM PDT 24
Finished Jul 20 04:43:04 PM PDT 24
Peak memory 201524 kb
Host smart-c8428980-bff0-4e47-ac9f-9d5c0c7a58be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617440477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.2
617440477
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1050504648
Short name T354
Test name
Test status
Simulation time 190362542706 ps
CPU time 119.7 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:44:52 PM PDT 24
Peak memory 201732 kb
Host smart-163ec5ea-94a8-4d04-97db-29b9b4bac9fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050504648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1050504648
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1936768800
Short name T741
Test name
Test status
Simulation time 3462009594 ps
CPU time 5.36 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:42:54 PM PDT 24
Peak memory 201464 kb
Host smart-dc112984-21c9-4cfa-a753-37fc8f9aaa0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936768800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1936768800
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.1851773628
Short name T169
Test name
Test status
Simulation time 5171007155 ps
CPU time 10.27 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:14 PM PDT 24
Peak memory 201448 kb
Host smart-c10fc531-9f22-43e4-8c8e-b385d450d227
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851773628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.1851773628
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1739339484
Short name T549
Test name
Test status
Simulation time 2611069354 ps
CPU time 7.62 seconds
Started Jul 20 04:42:49 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 201452 kb
Host smart-945dfe33-78cc-4b1e-9b9f-9d7f7e742669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739339484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1739339484
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3882313948
Short name T611
Test name
Test status
Simulation time 2485841994 ps
CPU time 2.64 seconds
Started Jul 20 04:42:47 PM PDT 24
Finished Jul 20 04:42:50 PM PDT 24
Peak memory 201544 kb
Host smart-6e164307-ec05-4132-bb09-90b904d7d850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882313948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.3882313948
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3628441572
Short name T307
Test name
Test status
Simulation time 2099731222 ps
CPU time 6.06 seconds
Started Jul 20 04:42:51 PM PDT 24
Finished Jul 20 04:42:58 PM PDT 24
Peak memory 201400 kb
Host smart-11a2ca32-f5f6-469d-b13c-d710cb441c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628441572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3628441572
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.576583127
Short name T477
Test name
Test status
Simulation time 2530624830 ps
CPU time 2.74 seconds
Started Jul 20 04:42:52 PM PDT 24
Finished Jul 20 04:42:56 PM PDT 24
Peak memory 201448 kb
Host smart-39461ca7-1064-4ef6-86f8-ea6d0252430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576583127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.576583127
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.734115654
Short name T14
Test name
Test status
Simulation time 2118571756 ps
CPU time 3.47 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:42:55 PM PDT 24
Peak memory 201452 kb
Host smart-773e75b9-b062-4cd1-be0f-0f7ce404e33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734115654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.734115654
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2765735701
Short name T559
Test name
Test status
Simulation time 20398768681 ps
CPU time 52.58 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:56 PM PDT 24
Peak memory 216768 kb
Host smart-866d289d-3052-4286-afd3-422050c731c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765735701 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.2765735701
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3402309921
Short name T772
Test name
Test status
Simulation time 245681668920 ps
CPU time 17.42 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:43:07 PM PDT 24
Peak memory 201444 kb
Host smart-e11d0ac2-2e85-42d6-9d43-684cf2f8b540
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402309921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.3402309921
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.3230982619
Short name T759
Test name
Test status
Simulation time 2011882321 ps
CPU time 5.74 seconds
Started Jul 20 04:42:54 PM PDT 24
Finished Jul 20 04:43:00 PM PDT 24
Peak memory 201360 kb
Host smart-29f478f1-b2ab-433e-9b3c-d1e871354c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230982619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.3230982619
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2867084830
Short name T573
Test name
Test status
Simulation time 3640604055 ps
CPU time 9.54 seconds
Started Jul 20 04:42:54 PM PDT 24
Finished Jul 20 04:43:04 PM PDT 24
Peak memory 201196 kb
Host smart-d4ae2119-a73b-4b4b-9389-e2bbbce4e1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867084830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.2
867084830
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.1785522891
Short name T707
Test name
Test status
Simulation time 67815922261 ps
CPU time 35.79 seconds
Started Jul 20 04:42:53 PM PDT 24
Finished Jul 20 04:43:29 PM PDT 24
Peak memory 201708 kb
Host smart-3c898fc8-4129-458b-90b2-685577bf6640
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785522891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.1785522891
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4136283269
Short name T263
Test name
Test status
Simulation time 88751175274 ps
CPU time 50.59 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:54 PM PDT 24
Peak memory 201716 kb
Host smart-b682b2ed-c6db-432c-bc44-636ab21c1206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136283269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.4136283269
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2422567869
Short name T331
Test name
Test status
Simulation time 2873741639 ps
CPU time 2.62 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:43:02 PM PDT 24
Peak memory 201424 kb
Host smart-9427bc14-ce29-4114-9d2b-2af1ba4e6924
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422567869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.2422567869
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3388239586
Short name T50
Test name
Test status
Simulation time 3828389787 ps
CPU time 7.53 seconds
Started Jul 20 04:42:51 PM PDT 24
Finished Jul 20 04:43:00 PM PDT 24
Peak memory 201460 kb
Host smart-2f3bfc4a-9d34-415e-a072-fbacd895096f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388239586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.3388239586
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3856470103
Short name T645
Test name
Test status
Simulation time 2626515748 ps
CPU time 2.71 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201452 kb
Host smart-fe22d954-d156-4b05-b6b2-d0d8bc44ee4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856470103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3856470103
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3936228860
Short name T222
Test name
Test status
Simulation time 2488243377 ps
CPU time 7.82 seconds
Started Jul 20 04:42:56 PM PDT 24
Finished Jul 20 04:43:04 PM PDT 24
Peak memory 201464 kb
Host smart-2815dfc8-48cf-492d-8e7e-d4473234bf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936228860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3936228860
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.25138720
Short name T5
Test name
Test status
Simulation time 2179262037 ps
CPU time 5.7 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:09 PM PDT 24
Peak memory 201432 kb
Host smart-19977d99-a997-4e73-ab5e-f0ef3d53a540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25138720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.25138720
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3847934724
Short name T504
Test name
Test status
Simulation time 2521911068 ps
CPU time 2.55 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:42:52 PM PDT 24
Peak memory 201464 kb
Host smart-de34fc16-b105-4bf0-9ed7-5a1e9e1ecc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847934724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.3847934724
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.2542745859
Short name T431
Test name
Test status
Simulation time 2108876154 ps
CPU time 5.81 seconds
Started Jul 20 04:42:52 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 201396 kb
Host smart-f759c9ff-068d-43cc-8b2d-baa5f4e62d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542745859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2542745859
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.3765231799
Short name T569
Test name
Test status
Simulation time 16377969063 ps
CPU time 43.36 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:43:33 PM PDT 24
Peak memory 201668 kb
Host smart-7ca79759-3c4b-40d8-b12b-7273a267cdd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765231799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.3765231799
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3267227005
Short name T29
Test name
Test status
Simulation time 6044561218 ps
CPU time 2.41 seconds
Started Jul 20 04:42:50 PM PDT 24
Finished Jul 20 04:42:55 PM PDT 24
Peak memory 201480 kb
Host smart-42d39e48-6072-49ac-9357-7c1765a0ee53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267227005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.3267227005
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.3700769491
Short name T768
Test name
Test status
Simulation time 2039445484 ps
CPU time 1.56 seconds
Started Jul 20 04:42:57 PM PDT 24
Finished Jul 20 04:43:00 PM PDT 24
Peak memory 201440 kb
Host smart-16106796-1f8a-496a-a2e4-9a5f5691fa77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700769491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.3700769491
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.614087160
Short name T613
Test name
Test status
Simulation time 3148921729 ps
CPU time 1.27 seconds
Started Jul 20 04:43:03 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201560 kb
Host smart-9b8e36c1-88b4-4654-9ad6-53774ad53cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614087160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.614087160
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.2374457478
Short name T588
Test name
Test status
Simulation time 53221305402 ps
CPU time 141.15 seconds
Started Jul 20 04:43:05 PM PDT 24
Finished Jul 20 04:45:26 PM PDT 24
Peak memory 201656 kb
Host smart-8a83edea-5f7c-4fc0-9223-6bc38a2d8824
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374457478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.2374457478
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1499489952
Short name T306
Test name
Test status
Simulation time 3742673040 ps
CPU time 9.95 seconds
Started Jul 20 04:43:00 PM PDT 24
Finished Jul 20 04:43:12 PM PDT 24
Peak memory 201432 kb
Host smart-c69d0080-9cb8-45cd-b0b2-a2789e7a6359
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499489952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.1499489952
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.893264997
Short name T769
Test name
Test status
Simulation time 2939764389 ps
CPU time 8.27 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:43:09 PM PDT 24
Peak memory 201428 kb
Host smart-4371e8db-c949-4382-854c-2d34f454f287
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893264997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctr
l_edge_detect.893264997
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2876215578
Short name T781
Test name
Test status
Simulation time 2618609386 ps
CPU time 4.16 seconds
Started Jul 20 04:42:57 PM PDT 24
Finished Jul 20 04:43:03 PM PDT 24
Peak memory 201384 kb
Host smart-633b6303-942d-487d-9d7f-7533d8882526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876215578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.2876215578
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3100811576
Short name T234
Test name
Test status
Simulation time 2473197694 ps
CPU time 3.69 seconds
Started Jul 20 04:42:48 PM PDT 24
Finished Jul 20 04:42:53 PM PDT 24
Peak memory 201536 kb
Host smart-2c5872b9-e8c1-43c2-bd6e-a9b93edc21aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100811576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3100811576
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.4126239739
Short name T462
Test name
Test status
Simulation time 2145618973 ps
CPU time 3.69 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:43:03 PM PDT 24
Peak memory 201320 kb
Host smart-83a0b3ba-00ab-44a6-be6f-50576463eb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126239739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.4126239739
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2148728531
Short name T6
Test name
Test status
Simulation time 2514324320 ps
CPU time 7.18 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:10 PM PDT 24
Peak memory 201468 kb
Host smart-95fc925f-cfac-4ad5-b4cb-bb2d1bb7d696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148728531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2148728531
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.3260430572
Short name T558
Test name
Test status
Simulation time 2124317083 ps
CPU time 1.92 seconds
Started Jul 20 04:42:54 PM PDT 24
Finished Jul 20 04:42:56 PM PDT 24
Peak memory 201156 kb
Host smart-060bbb8f-bdc0-45fe-9f50-1fef8caa3342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260430572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.3260430572
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.544795362
Short name T792
Test name
Test status
Simulation time 14411919911 ps
CPU time 36.9 seconds
Started Jul 20 04:42:55 PM PDT 24
Finished Jul 20 04:43:32 PM PDT 24
Peak memory 201524 kb
Host smart-2ac4108b-b63e-4e91-b2ec-8677be633c0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544795362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_st
ress_all.544795362
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2130634700
Short name T586
Test name
Test status
Simulation time 7441707757 ps
CPU time 2.65 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:43:04 PM PDT 24
Peak memory 201448 kb
Host smart-eca32566-8a89-4d2e-af73-1080399b0752
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130634700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.2130634700
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.3616346514
Short name T171
Test name
Test status
Simulation time 2074612509 ps
CPU time 1.32 seconds
Started Jul 20 04:43:00 PM PDT 24
Finished Jul 20 04:43:03 PM PDT 24
Peak memory 201532 kb
Host smart-f6c7ec1f-6c2a-49fe-bdba-71534d7b533d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616346514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.3616346514
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3266144947
Short name T491
Test name
Test status
Simulation time 3543682139 ps
CPU time 8.98 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:43:10 PM PDT 24
Peak memory 201744 kb
Host smart-595afa35-3991-47cc-90c3-ca672e8fb431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266144947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3
266144947
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.1427937776
Short name T272
Test name
Test status
Simulation time 72396907672 ps
CPU time 192.73 seconds
Started Jul 20 04:43:02 PM PDT 24
Finished Jul 20 04:46:17 PM PDT 24
Peak memory 201640 kb
Host smart-8ba38b41-4edf-4825-9dda-295b0568bc79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427937776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.1427937776
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2929847530
Short name T653
Test name
Test status
Simulation time 37813905900 ps
CPU time 51.17 seconds
Started Jul 20 04:43:00 PM PDT 24
Finished Jul 20 04:43:53 PM PDT 24
Peak memory 201748 kb
Host smart-5403aa52-0fa2-4bbc-abe3-45374e3c111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929847530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2929847530
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2900031528
Short name T17
Test name
Test status
Simulation time 2832355366 ps
CPU time 2.61 seconds
Started Jul 20 04:42:56 PM PDT 24
Finished Jul 20 04:43:00 PM PDT 24
Peak memory 201444 kb
Host smart-8896cbb4-4b68-41b8-9dfe-3660ef0f045e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900031528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.2900031528
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.520602042
Short name T162
Test name
Test status
Simulation time 4882286947 ps
CPU time 3.92 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:08 PM PDT 24
Peak memory 201516 kb
Host smart-d079dc82-3f00-46bd-87e4-078dcd7d91f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520602042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctr
l_edge_detect.520602042
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3506566588
Short name T724
Test name
Test status
Simulation time 2608772647 ps
CPU time 7.82 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:43:09 PM PDT 24
Peak memory 201448 kb
Host smart-3cb55cf6-56a3-41dc-b6b5-c5dd2355f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506566588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.3506566588
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2088235830
Short name T77
Test name
Test status
Simulation time 2483593736 ps
CPU time 2.27 seconds
Started Jul 20 04:42:56 PM PDT 24
Finished Jul 20 04:42:59 PM PDT 24
Peak memory 201464 kb
Host smart-471ac244-548d-4bb7-b573-68b8c875776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088235830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2088235830
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2103764247
Short name T95
Test name
Test status
Simulation time 2119764831 ps
CPU time 1.09 seconds
Started Jul 20 04:42:54 PM PDT 24
Finished Jul 20 04:42:56 PM PDT 24
Peak memory 201380 kb
Host smart-8ff5782f-3033-4481-8988-28746b4d6d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103764247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2103764247
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1233522143
Short name T709
Test name
Test status
Simulation time 2530622119 ps
CPU time 2.37 seconds
Started Jul 20 04:43:02 PM PDT 24
Finished Jul 20 04:43:07 PM PDT 24
Peak memory 201540 kb
Host smart-ec7a138e-8719-4076-9340-c0db8b65ba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233522143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1233522143
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.3883422134
Short name T749
Test name
Test status
Simulation time 2111521075 ps
CPU time 5.85 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:43:07 PM PDT 24
Peak memory 201472 kb
Host smart-a4c96f47-2884-47fd-867e-14b3ca84c4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883422134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3883422134
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3726055747
Short name T182
Test name
Test status
Simulation time 150639255065 ps
CPU time 43.82 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:47 PM PDT 24
Peak memory 201828 kb
Host smart-06a4c48d-c81b-4c7c-b740-ecea54edd920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726055747 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.3726055747
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1443161693
Short name T639
Test name
Test status
Simulation time 7511541217 ps
CPU time 1.94 seconds
Started Jul 20 04:43:02 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201340 kb
Host smart-e8560932-5666-4d9d-89da-b50c254f771c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443161693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.1443161693
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.681811996
Short name T771
Test name
Test status
Simulation time 2013434743 ps
CPU time 6.05 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201680 kb
Host smart-7fd40726-631c-4149-8435-3c04fe9ec941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681811996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_tes
t.681811996
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1295780958
Short name T55
Test name
Test status
Simulation time 281704223228 ps
CPU time 690.35 seconds
Started Jul 20 04:43:05 PM PDT 24
Finished Jul 20 04:54:36 PM PDT 24
Peak memory 201520 kb
Host smart-1b08a56b-a9a2-4b95-bdbe-392c169654fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295780958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1
295780958
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3032496661
Short name T733
Test name
Test status
Simulation time 119410389580 ps
CPU time 294.21 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:47:55 PM PDT 24
Peak memory 201800 kb
Host smart-59af98ef-00d5-4ef2-b5f0-666b0459fdd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032496661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.3032496661
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.554926529
Short name T101
Test name
Test status
Simulation time 101734700437 ps
CPU time 265.65 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:47:27 PM PDT 24
Peak memory 201884 kb
Host smart-bc02a799-3c7e-4104-9a9c-a0f143dc8dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554926529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_wi
th_pre_cond.554926529
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.829610381
Short name T776
Test name
Test status
Simulation time 3863599109 ps
CPU time 3.21 seconds
Started Jul 20 04:43:04 PM PDT 24
Finished Jul 20 04:43:08 PM PDT 24
Peak memory 201436 kb
Host smart-80bd2c80-44ec-4750-b329-7583fd1dd154
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829610381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_ec_pwr_on_rst.829610381
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2107010067
Short name T195
Test name
Test status
Simulation time 4507320178 ps
CPU time 1.19 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:43:02 PM PDT 24
Peak memory 201452 kb
Host smart-09a2407b-f9d7-4404-9934-9954faa6b1e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107010067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.2107010067
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2777933576
Short name T305
Test name
Test status
Simulation time 2620869585 ps
CPU time 3.73 seconds
Started Jul 20 04:42:56 PM PDT 24
Finished Jul 20 04:43:01 PM PDT 24
Peak memory 201540 kb
Host smart-39f90b72-82dd-4ddc-8c54-a9f5d97a8c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777933576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.2777933576
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2431046205
Short name T748
Test name
Test status
Simulation time 2467343575 ps
CPU time 7.32 seconds
Started Jul 20 04:42:57 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201468 kb
Host smart-3e7119cf-0e2a-45dd-865d-7cd125a2fd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431046205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2431046205
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.4092179241
Short name T488
Test name
Test status
Simulation time 2085081183 ps
CPU time 3.58 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201468 kb
Host smart-8d465818-63ec-46b0-8479-56931fce4a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092179241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.4092179241
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4029574257
Short name T542
Test name
Test status
Simulation time 2509799639 ps
CPU time 6.92 seconds
Started Jul 20 04:42:57 PM PDT 24
Finished Jul 20 04:43:05 PM PDT 24
Peak memory 201340 kb
Host smart-32c87602-92da-4a6c-8bb8-963906ab7a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029574257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.4029574257
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.239773317
Short name T424
Test name
Test status
Simulation time 2111562155 ps
CPU time 6.14 seconds
Started Jul 20 04:43:02 PM PDT 24
Finished Jul 20 04:43:11 PM PDT 24
Peak memory 201400 kb
Host smart-0314c0f6-c950-4937-825d-796aacf3739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239773317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.239773317
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2640967912
Short name T93
Test name
Test status
Simulation time 1648657801676 ps
CPU time 69.36 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:44:09 PM PDT 24
Peak memory 201556 kb
Host smart-5cb4332f-bea4-4e4f-bcb9-1fdcb3b7e1e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640967912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.2640967912
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.4001176605
Short name T609
Test name
Test status
Simulation time 2009841129 ps
CPU time 6.06 seconds
Started Jul 20 04:43:03 PM PDT 24
Finished Jul 20 04:43:11 PM PDT 24
Peak memory 201452 kb
Host smart-863904fa-1268-453c-9beb-bd908acb83ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001176605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.4001176605
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4252760504
Short name T778
Test name
Test status
Simulation time 140358537803 ps
CPU time 346.99 seconds
Started Jul 20 04:43:05 PM PDT 24
Finished Jul 20 04:48:53 PM PDT 24
Peak memory 201528 kb
Host smart-2a1f14e5-4c78-48c7-af6b-082648126c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252760504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.4
252760504
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.2887611612
Short name T42
Test name
Test status
Simulation time 157470492200 ps
CPU time 400.15 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:49:41 PM PDT 24
Peak memory 201640 kb
Host smart-5ae0b13d-d6b4-4569-a527-79a3d0bdcd4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887611612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.2887611612
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3952619097
Short name T676
Test name
Test status
Simulation time 111809880484 ps
CPU time 35.38 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:43:36 PM PDT 24
Peak memory 201776 kb
Host smart-0c0a9d20-7017-4cf5-a24a-d75f1f5a9f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952619097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.3952619097
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.913441329
Short name T589
Test name
Test status
Simulation time 3392373391 ps
CPU time 8.91 seconds
Started Jul 20 04:43:04 PM PDT 24
Finished Jul 20 04:43:14 PM PDT 24
Peak memory 201444 kb
Host smart-baa5a8fc-f6bd-4589-b391-0c16b04ad57d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913441329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ec_pwr_on_rst.913441329
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.71572100
Short name T509
Test name
Test status
Simulation time 4572441647 ps
CPU time 5.45 seconds
Started Jul 20 04:42:59 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201436 kb
Host smart-50c38fb2-b277-4c44-b03f-94ea77dcffc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71572100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl
_edge_detect.71572100
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2725500016
Short name T751
Test name
Test status
Simulation time 2624393607 ps
CPU time 2.07 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:43:02 PM PDT 24
Peak memory 201540 kb
Host smart-807a1a59-173e-4d51-84d9-718ec746d61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725500016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.2725500016
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3629696005
Short name T460
Test name
Test status
Simulation time 2453174988 ps
CPU time 7.17 seconds
Started Jul 20 04:42:57 PM PDT 24
Finished Jul 20 04:43:05 PM PDT 24
Peak memory 201468 kb
Host smart-350dd3be-30bb-4433-b50b-d08cf5541185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629696005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3629696005
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1009883247
Short name T691
Test name
Test status
Simulation time 2275670981 ps
CPU time 2.03 seconds
Started Jul 20 04:43:02 PM PDT 24
Finished Jul 20 04:43:06 PM PDT 24
Peak memory 201452 kb
Host smart-5604b06d-fd89-4f41-8277-4042606d96cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009883247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1009883247
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.292269949
Short name T756
Test name
Test status
Simulation time 2525251362 ps
CPU time 2.49 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:43:02 PM PDT 24
Peak memory 201452 kb
Host smart-b4ddcf9f-6986-43b9-b4eb-0e5d2a77b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292269949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.292269949
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.2472845849
Short name T23
Test name
Test status
Simulation time 2112694975 ps
CPU time 5.57 seconds
Started Jul 20 04:42:57 PM PDT 24
Finished Jul 20 04:43:03 PM PDT 24
Peak memory 201464 kb
Host smart-0bac957a-f096-4617-ab82-e97a2f13b05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472845849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.2472845849
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2519077528
Short name T92
Test name
Test status
Simulation time 19385254748 ps
CPU time 10.75 seconds
Started Jul 20 04:43:02 PM PDT 24
Finished Jul 20 04:43:15 PM PDT 24
Peak memory 201512 kb
Host smart-37140599-338f-4f6d-a83f-6f40d4183539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519077528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.2519077528
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1213313961
Short name T624
Test name
Test status
Simulation time 4113110357 ps
CPU time 5.94 seconds
Started Jul 20 04:43:00 PM PDT 24
Finished Jul 20 04:43:07 PM PDT 24
Peak memory 201404 kb
Host smart-b56d5bdb-afc1-4b52-8bf0-c5e254dbb33d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213313961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.1213313961
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.2750041975
Short name T452
Test name
Test status
Simulation time 2014802754 ps
CPU time 3.41 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:41:21 PM PDT 24
Peak memory 201468 kb
Host smart-5463834e-8ee6-45d1-99fa-0d0b9cd479da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750041975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.2750041975
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1291369395
Short name T732
Test name
Test status
Simulation time 3319114772 ps
CPU time 2.73 seconds
Started Jul 20 04:41:19 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 200764 kb
Host smart-14212801-4ed8-444d-b385-ef7a2e1cb09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291369395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1291369395
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2775421941
Short name T268
Test name
Test status
Simulation time 121420874177 ps
CPU time 119.73 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:43:17 PM PDT 24
Peak memory 201736 kb
Host smart-139689a1-c468-42b4-9c7a-6ff614d5365e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775421941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.2775421941
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.4120119155
Short name T418
Test name
Test status
Simulation time 2654350170 ps
CPU time 3.66 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:23 PM PDT 24
Peak memory 201440 kb
Host smart-140ada85-5621-401c-838c-4d16b4639c5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120119155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.4120119155
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.2281544875
Short name T179
Test name
Test status
Simulation time 5513973829 ps
CPU time 5.44 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201464 kb
Host smart-1e97eb79-79a5-4b3a-b305-4f1e6e939013
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281544875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.2281544875
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1659190469
Short name T619
Test name
Test status
Simulation time 2624663926 ps
CPU time 2.3 seconds
Started Jul 20 04:41:19 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201524 kb
Host smart-ae88f887-7dab-4dd9-a7d8-1f84ad3ab024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659190469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1659190469
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2204069951
Short name T719
Test name
Test status
Simulation time 2472051711 ps
CPU time 2.27 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:41:20 PM PDT 24
Peak memory 201440 kb
Host smart-93ff19da-2d54-4f9b-8da6-96cef62a58d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204069951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.2204069951
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2520143016
Short name T72
Test name
Test status
Simulation time 2058775943 ps
CPU time 5.97 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201384 kb
Host smart-339f3041-907f-4b77-9c7f-3b4f6955ee4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520143016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2520143016
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.2919775932
Short name T165
Test name
Test status
Simulation time 2124825830 ps
CPU time 1.92 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:41:22 PM PDT 24
Peak memory 201608 kb
Host smart-5e307409-1a21-4d70-a66f-b4d4f23c1008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919775932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.2919775932
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.3923972650
Short name T440
Test name
Test status
Simulation time 10295499671 ps
CPU time 10.5 seconds
Started Jul 20 04:41:20 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201512 kb
Host smart-bc1d6008-dee8-43a2-9174-cbaf3f62df47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923972650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.3923972650
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3078343322
Short name T8
Test name
Test status
Simulation time 7667757988 ps
CPU time 2.3 seconds
Started Jul 20 04:41:15 PM PDT 24
Finished Jul 20 04:41:19 PM PDT 24
Peak memory 201500 kb
Host smart-966095ca-e676-40a7-bb4a-0fa34f852746
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078343322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.3078343322
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3446634823
Short name T277
Test name
Test status
Simulation time 28587303759 ps
CPU time 47.28 seconds
Started Jul 20 04:42:57 PM PDT 24
Finished Jul 20 04:43:45 PM PDT 24
Peak memory 201816 kb
Host smart-eb7e68df-3f5c-491e-a980-832b424443bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446634823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.3446634823
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1626848089
Short name T705
Test name
Test status
Simulation time 64469334119 ps
CPU time 169.84 seconds
Started Jul 20 04:42:58 PM PDT 24
Finished Jul 20 04:45:50 PM PDT 24
Peak memory 201716 kb
Host smart-49c8700e-b16e-4a7c-af9e-d57de0d3d730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626848089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.1626848089
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.115252892
Short name T552
Test name
Test status
Simulation time 48873497477 ps
CPU time 123.04 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:45:06 PM PDT 24
Peak memory 201784 kb
Host smart-5c004a1e-131d-49be-8ba9-2cdcafbbc8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115252892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_wi
th_pre_cond.115252892
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2531237660
Short name T524
Test name
Test status
Simulation time 23142832787 ps
CPU time 5.24 seconds
Started Jul 20 04:43:01 PM PDT 24
Finished Jul 20 04:43:09 PM PDT 24
Peak memory 201876 kb
Host smart-ed13fd5b-a387-4d65-b89c-82f7103cab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531237660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.2531237660
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.4286274535
Short name T253
Test name
Test status
Simulation time 61833417069 ps
CPU time 86.62 seconds
Started Jul 20 04:43:09 PM PDT 24
Finished Jul 20 04:44:38 PM PDT 24
Peak memory 201804 kb
Host smart-d4a4fb9a-76b7-42f8-afa6-b8acb3fd8912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286274535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.4286274535
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.794737630
Short name T478
Test name
Test status
Simulation time 28589665117 ps
CPU time 36.41 seconds
Started Jul 20 04:43:12 PM PDT 24
Finished Jul 20 04:43:51 PM PDT 24
Peak memory 201796 kb
Host smart-390e4932-a5e5-4361-8267-c6ecf7cb5d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794737630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_wi
th_pre_cond.794737630
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3469644553
Short name T758
Test name
Test status
Simulation time 32627202689 ps
CPU time 82.51 seconds
Started Jul 20 04:43:12 PM PDT 24
Finished Jul 20 04:44:37 PM PDT 24
Peak memory 201720 kb
Host smart-e7be8da1-7008-4ce1-ab3b-b111577175ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469644553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3469644553
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2274007012
Short name T361
Test name
Test status
Simulation time 97466385566 ps
CPU time 33.56 seconds
Started Jul 20 04:43:13 PM PDT 24
Finished Jul 20 04:43:49 PM PDT 24
Peak memory 201688 kb
Host smart-e50e1995-74b4-4845-87e1-27db682ae613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274007012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.2274007012
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.995907237
Short name T304
Test name
Test status
Simulation time 2038341690 ps
CPU time 1.94 seconds
Started Jul 20 04:41:20 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201496 kb
Host smart-191992e8-0114-4c89-8348-6caa75b4fa32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995907237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test
.995907237
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2284369551
Short name T548
Test name
Test status
Simulation time 133651433331 ps
CPU time 328.65 seconds
Started Jul 20 04:41:20 PM PDT 24
Finished Jul 20 04:46:51 PM PDT 24
Peak memory 201604 kb
Host smart-82380f7f-94ab-419d-b1f3-debc8cc3173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284369551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.2284369551
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.722049902
Short name T237
Test name
Test status
Simulation time 47101526366 ps
CPU time 108.9 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:43:10 PM PDT 24
Peak memory 201676 kb
Host smart-dacbe68b-aefc-43df-9b89-f7445f146eca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722049902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_combo_detect.722049902
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2903599401
Short name T678
Test name
Test status
Simulation time 5133684858 ps
CPU time 13.42 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201444 kb
Host smart-70f51afa-b99a-4d51-801b-a74e041e315b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903599401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2903599401
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.325191727
Short name T479
Test name
Test status
Simulation time 2638386893 ps
CPU time 2.2 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:41:21 PM PDT 24
Peak memory 201452 kb
Host smart-ca7e72ef-c1b3-4977-9c9d-cb98acedc611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325191727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.325191727
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.250813944
Short name T572
Test name
Test status
Simulation time 2458105131 ps
CPU time 7.9 seconds
Started Jul 20 04:41:17 PM PDT 24
Finished Jul 20 04:41:27 PM PDT 24
Peak memory 201452 kb
Host smart-39a2f864-7b32-4863-9571-064c7219ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250813944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.250813944
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1682867921
Short name T451
Test name
Test status
Simulation time 2036884514 ps
CPU time 1.83 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:41:20 PM PDT 24
Peak memory 201376 kb
Host smart-aa6b2cc1-b555-4d0c-9e19-0db3dc28569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682867921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.1682867921
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.499156166
Short name T608
Test name
Test status
Simulation time 2511743080 ps
CPU time 7.22 seconds
Started Jul 20 04:41:16 PM PDT 24
Finished Jul 20 04:41:26 PM PDT 24
Peak memory 201404 kb
Host smart-1af23221-af63-4a5f-af8b-34871f933303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499156166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.499156166
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.2061029495
Short name T575
Test name
Test status
Simulation time 2127902058 ps
CPU time 1.84 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:41:22 PM PDT 24
Peak memory 201396 kb
Host smart-3d0701c6-b7ee-4500-97f4-1d73e52b56b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061029495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.2061029495
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1450863918
Short name T68
Test name
Test status
Simulation time 9960283641 ps
CPU time 19.26 seconds
Started Jul 20 04:41:19 PM PDT 24
Finished Jul 20 04:41:41 PM PDT 24
Peak memory 201460 kb
Host smart-9f459ef4-5e90-411d-8f1c-3acc133cda8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450863918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1450863918
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1754787952
Short name T155
Test name
Test status
Simulation time 18801607731 ps
CPU time 52.39 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:42:12 PM PDT 24
Peak memory 210084 kb
Host smart-bec81606-4bd8-4317-b84a-1315170c6c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754787952 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1754787952
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1239560618
Short name T143
Test name
Test status
Simulation time 8853065775 ps
CPU time 2.19 seconds
Started Jul 20 04:41:20 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201520 kb
Host smart-989dae2c-97c4-4b4b-a561-109473f66cbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239560618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1239560618
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1406571898
Short name T86
Test name
Test status
Simulation time 28337379907 ps
CPU time 35.75 seconds
Started Jul 20 04:43:14 PM PDT 24
Finished Jul 20 04:43:52 PM PDT 24
Peak memory 201768 kb
Host smart-564953ec-b848-43e6-801e-62159b862d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406571898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.1406571898
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1980898576
Short name T395
Test name
Test status
Simulation time 37471788130 ps
CPU time 88.73 seconds
Started Jul 20 04:43:07 PM PDT 24
Finished Jul 20 04:44:37 PM PDT 24
Peak memory 201776 kb
Host smart-27d72a6b-a489-4d03-bdc1-85f25542d3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980898576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.1980898576
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3408160539
Short name T110
Test name
Test status
Simulation time 25831606053 ps
CPU time 64.18 seconds
Started Jul 20 04:43:08 PM PDT 24
Finished Jul 20 04:44:13 PM PDT 24
Peak memory 201864 kb
Host smart-67eea292-2cba-4488-bc7e-1326d44b7aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408160539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.3408160539
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.402514612
Short name T377
Test name
Test status
Simulation time 140104675239 ps
CPU time 351.99 seconds
Started Jul 20 04:43:08 PM PDT 24
Finished Jul 20 04:49:01 PM PDT 24
Peak memory 201796 kb
Host smart-7aa94613-441c-4b07-8c2b-9ad547c84dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402514612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_wi
th_pre_cond.402514612
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3163347005
Short name T760
Test name
Test status
Simulation time 27353162508 ps
CPU time 16.72 seconds
Started Jul 20 04:43:09 PM PDT 24
Finished Jul 20 04:43:29 PM PDT 24
Peak memory 201836 kb
Host smart-86213994-c123-4a32-a58d-7f6534414c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163347005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.3163347005
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2661105546
Short name T374
Test name
Test status
Simulation time 201679884207 ps
CPU time 537.25 seconds
Started Jul 20 04:43:08 PM PDT 24
Finished Jul 20 04:52:08 PM PDT 24
Peak memory 201892 kb
Host smart-e7326629-90c9-415a-b981-69db7d75a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661105546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.2661105546
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.2040342800
Short name T560
Test name
Test status
Simulation time 2024169085 ps
CPU time 3.11 seconds
Started Jul 20 04:41:24 PM PDT 24
Finished Jul 20 04:41:28 PM PDT 24
Peak memory 201524 kb
Host smart-e2c52a4e-c49e-4eaa-8018-9e8fcac25281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040342800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.2040342800
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4113783112
Short name T57
Test name
Test status
Simulation time 3327634055 ps
CPU time 2.84 seconds
Started Jul 20 04:41:20 PM PDT 24
Finished Jul 20 04:41:25 PM PDT 24
Peak memory 201560 kb
Host smart-d74ec3b3-b318-4bea-9ab6-b61b91247e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113783112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.4113783112
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.996321313
Short name T323
Test name
Test status
Simulation time 146757344516 ps
CPU time 89.75 seconds
Started Jul 20 04:41:19 PM PDT 24
Finished Jul 20 04:42:51 PM PDT 24
Peak memory 201772 kb
Host smart-1f69fcde-5b4f-4717-9931-2ae7a9442288
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996321313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_combo_detect.996321313
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.587849492
Short name T247
Test name
Test status
Simulation time 31469352092 ps
CPU time 80.6 seconds
Started Jul 20 04:41:20 PM PDT 24
Finished Jul 20 04:42:42 PM PDT 24
Peak memory 201724 kb
Host smart-641198b8-e134-4877-8f94-66f90957abad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587849492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wit
h_pre_cond.587849492
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1801409065
Short name T16
Test name
Test status
Simulation time 3679626733 ps
CPU time 2.83 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:41:23 PM PDT 24
Peak memory 201444 kb
Host smart-12657614-a9a6-4de1-a0eb-661646c4921a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801409065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.1801409065
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2203668027
Short name T518
Test name
Test status
Simulation time 2641171047 ps
CPU time 2.18 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:41:22 PM PDT 24
Peak memory 201444 kb
Host smart-dd1aa19e-9750-4936-8fe3-00317d2483f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203668027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2203668027
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.189941881
Short name T683
Test name
Test status
Simulation time 2465967666 ps
CPU time 3.71 seconds
Started Jul 20 04:41:18 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201676 kb
Host smart-53be6782-d98b-4239-b8ab-9a9c76ac3428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189941881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.189941881
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3413622937
Short name T75
Test name
Test status
Simulation time 2234012143 ps
CPU time 2.16 seconds
Started Jul 20 04:41:20 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 201448 kb
Host smart-316e879e-5ffa-4351-bfcd-630ae7c008a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413622937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.3413622937
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.825172812
Short name T669
Test name
Test status
Simulation time 2597201561 ps
CPU time 1.34 seconds
Started Jul 20 04:41:15 PM PDT 24
Finished Jul 20 04:41:17 PM PDT 24
Peak memory 201464 kb
Host smart-7f333002-af7d-46ab-8dd2-3bc629cf2aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825172812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.825172812
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.2777097512
Short name T506
Test name
Test status
Simulation time 2161202587 ps
CPU time 1.12 seconds
Started Jul 20 04:41:19 PM PDT 24
Finished Jul 20 04:41:22 PM PDT 24
Peak memory 201428 kb
Host smart-3a5df65d-c328-4c9c-8220-f69b3466fd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777097512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2777097512
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.2172873133
Short name T512
Test name
Test status
Simulation time 9735508362 ps
CPU time 12.56 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:41:39 PM PDT 24
Peak memory 201540 kb
Host smart-2e93a399-31a5-4e9a-8077-c8124fc55bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172873133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.2172873133
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3557951309
Short name T193
Test name
Test status
Simulation time 7499970611 ps
CPU time 6.87 seconds
Started Jul 20 04:41:20 PM PDT 24
Finished Jul 20 04:41:29 PM PDT 24
Peak memory 201480 kb
Host smart-201709bd-7e16-4f90-b62b-7e753eac2e7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557951309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.3557951309
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2326587763
Short name T112
Test name
Test status
Simulation time 27333233640 ps
CPU time 68.44 seconds
Started Jul 20 04:43:19 PM PDT 24
Finished Jul 20 04:44:28 PM PDT 24
Peak memory 201808 kb
Host smart-992ff104-c9ec-4a2e-96c3-a8b012cdd4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326587763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2326587763
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3568844598
Short name T375
Test name
Test status
Simulation time 87714686518 ps
CPU time 56.32 seconds
Started Jul 20 04:43:10 PM PDT 24
Finished Jul 20 04:44:09 PM PDT 24
Peak memory 201800 kb
Host smart-f899975c-1ad6-40a3-a496-b71c792aa80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568844598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.3568844598
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2859110909
Short name T658
Test name
Test status
Simulation time 37457834123 ps
CPU time 25.23 seconds
Started Jul 20 04:43:10 PM PDT 24
Finished Jul 20 04:43:38 PM PDT 24
Peak memory 201736 kb
Host smart-9ce72aff-50b9-4396-b080-6f59ae6cb88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859110909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.2859110909
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.150847951
Short name T740
Test name
Test status
Simulation time 45540957896 ps
CPU time 30.78 seconds
Started Jul 20 04:43:18 PM PDT 24
Finished Jul 20 04:43:50 PM PDT 24
Peak memory 201840 kb
Host smart-9dccedf8-2f12-4ff4-bdcb-da81c7ea93e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150847951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_wi
th_pre_cond.150847951
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3670442952
Short name T736
Test name
Test status
Simulation time 68040346383 ps
CPU time 47.9 seconds
Started Jul 20 04:43:08 PM PDT 24
Finished Jul 20 04:43:57 PM PDT 24
Peak memory 201800 kb
Host smart-bb5f6dcf-24a8-40f5-a0d9-64ba0d0f5fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670442952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.3670442952
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3816448243
Short name T103
Test name
Test status
Simulation time 27928546442 ps
CPU time 17.67 seconds
Started Jul 20 04:43:08 PM PDT 24
Finished Jul 20 04:43:28 PM PDT 24
Peak memory 201832 kb
Host smart-fda49eb6-f857-4949-a125-14210c56f863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816448243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.3816448243
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.2440304015
Short name T667
Test name
Test status
Simulation time 2122963014 ps
CPU time 0.93 seconds
Started Jul 20 04:41:30 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201688 kb
Host smart-2a500796-86a9-4b4e-a0e0-545bca887299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440304015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.2440304015
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3260221054
Short name T593
Test name
Test status
Simulation time 3789052642 ps
CPU time 2.14 seconds
Started Jul 20 04:41:24 PM PDT 24
Finished Jul 20 04:41:28 PM PDT 24
Peak memory 201564 kb
Host smart-ada73364-39c5-4eaa-bf88-a292f1f9faff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260221054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.3260221054
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.2166187791
Short name T269
Test name
Test status
Simulation time 86177098631 ps
CPU time 224.97 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:45:11 PM PDT 24
Peak memory 201660 kb
Host smart-61877f47-2a5d-4164-baa2-c204fe9e029a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166187791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.2166187791
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2376994537
Short name T712
Test name
Test status
Simulation time 27589860721 ps
CPU time 36.2 seconds
Started Jul 20 04:41:30 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 201984 kb
Host smart-185b1b17-afd5-48da-880a-7c5213cb23f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376994537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.2376994537
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1956506129
Short name T550
Test name
Test status
Simulation time 2596624980 ps
CPU time 1.21 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:31 PM PDT 24
Peak memory 201404 kb
Host smart-f16e21d8-c393-4148-955b-4bcd7dd75fb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956506129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1956506129
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2283942511
Short name T745
Test name
Test status
Simulation time 4386875571 ps
CPU time 5.4 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201524 kb
Host smart-e69618b2-2971-48a9-ab77-87a7319ee550
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283942511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2283942511
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1535169408
Short name T62
Test name
Test status
Simulation time 2627281726 ps
CPU time 2.7 seconds
Started Jul 20 04:41:29 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201448 kb
Host smart-34635408-a2a3-486f-ac6a-528dfd67e70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535169408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1535169408
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1215702123
Short name T433
Test name
Test status
Simulation time 2465295442 ps
CPU time 7.32 seconds
Started Jul 20 04:41:24 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201400 kb
Host smart-823b94d9-68f7-4eb0-b902-7b46fe446bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215702123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1215702123
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3343408909
Short name T538
Test name
Test status
Simulation time 2066468701 ps
CPU time 3.29 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:41:31 PM PDT 24
Peak memory 201476 kb
Host smart-1fa0284f-fd4b-4419-8667-ba8c266d6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343408909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3343408909
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1541009979
Short name T770
Test name
Test status
Simulation time 2516505879 ps
CPU time 6.21 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201540 kb
Host smart-65b08cc2-a80e-4f81-829a-61a931500997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541009979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1541009979
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.1367861041
Short name T686
Test name
Test status
Simulation time 2124360779 ps
CPU time 1.8 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:41:30 PM PDT 24
Peak memory 201376 kb
Host smart-c20d8c5b-4227-45c2-953b-53705447d029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367861041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1367861041
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.411047439
Short name T716
Test name
Test status
Simulation time 18306981271 ps
CPU time 44.87 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:42:14 PM PDT 24
Peak memory 201452 kb
Host smart-63f42e4a-9cf9-4a06-b1e9-ae8226a4eef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411047439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_str
ess_all.411047439
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.24176140
Short name T445
Test name
Test status
Simulation time 4040749144 ps
CPU time 6.13 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:36 PM PDT 24
Peak memory 201412 kb
Host smart-cdc38bb7-7be8-4350-af32-1b5efce9a85e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24176140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_ultra_low_pwr.24176140
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.400500374
Short name T88
Test name
Test status
Simulation time 24581819964 ps
CPU time 62.7 seconds
Started Jul 20 04:43:10 PM PDT 24
Finished Jul 20 04:44:16 PM PDT 24
Peak memory 201768 kb
Host smart-25fe1f91-5d4b-4694-aa76-74ffe20341dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400500374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_wi
th_pre_cond.400500374
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.957600805
Short name T117
Test name
Test status
Simulation time 25830947330 ps
CPU time 60.95 seconds
Started Jul 20 04:43:10 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 201792 kb
Host smart-c519fb2d-eac9-431b-87b7-04fac18adebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957600805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_wi
th_pre_cond.957600805
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1205877878
Short name T726
Test name
Test status
Simulation time 47436404963 ps
CPU time 116.24 seconds
Started Jul 20 04:43:10 PM PDT 24
Finished Jul 20 04:45:09 PM PDT 24
Peak memory 201904 kb
Host smart-3186f20c-afcc-40be-9053-12298fc6c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205877878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1205877878
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2750660292
Short name T376
Test name
Test status
Simulation time 63206159040 ps
CPU time 40.85 seconds
Started Jul 20 04:43:10 PM PDT 24
Finished Jul 20 04:43:54 PM PDT 24
Peak memory 201772 kb
Host smart-061700a6-a7c4-49fc-bb52-de15bb088db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750660292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.2750660292
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.4029419038
Short name T788
Test name
Test status
Simulation time 80050323814 ps
CPU time 211.53 seconds
Started Jul 20 04:43:19 PM PDT 24
Finished Jul 20 04:46:51 PM PDT 24
Peak memory 201820 kb
Host smart-47f7289a-f89b-42ce-aa07-5649b0030a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029419038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.4029419038
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.356626134
Short name T367
Test name
Test status
Simulation time 155015088619 ps
CPU time 105.92 seconds
Started Jul 20 04:43:17 PM PDT 24
Finished Jul 20 04:45:05 PM PDT 24
Peak memory 201748 kb
Host smart-2963691c-dec6-417a-b369-1e84ca80374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356626134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_wi
th_pre_cond.356626134
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2795699160
Short name T777
Test name
Test status
Simulation time 110913339966 ps
CPU time 82.91 seconds
Started Jul 20 04:43:15 PM PDT 24
Finished Jul 20 04:44:40 PM PDT 24
Peak memory 201780 kb
Host smart-28ec5eee-fd5e-4d74-a583-d63f71629e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795699160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.2795699160
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.2859881699
Short name T553
Test name
Test status
Simulation time 2037165014 ps
CPU time 1.85 seconds
Started Jul 20 04:41:26 PM PDT 24
Finished Jul 20 04:41:29 PM PDT 24
Peak memory 201544 kb
Host smart-c840033b-7043-496a-b80c-4b70979103a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859881699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.2859881699
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2464480111
Short name T750
Test name
Test status
Simulation time 3150381500 ps
CPU time 7.94 seconds
Started Jul 20 04:41:24 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201548 kb
Host smart-fe421aad-6336-4d3d-ac83-22826a146f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464480111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.2464480111
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.552566121
Short name T189
Test name
Test status
Simulation time 27449846829 ps
CPU time 19.4 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:49 PM PDT 24
Peak memory 201668 kb
Host smart-00e38aab-90d7-4f78-a6bc-955ffe26df29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552566121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_combo_detect.552566121
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.675759051
Short name T677
Test name
Test status
Simulation time 67361210659 ps
CPU time 163.67 seconds
Started Jul 20 04:41:27 PM PDT 24
Finished Jul 20 04:44:12 PM PDT 24
Peak memory 201864 kb
Host smart-b782189e-0d17-4e4a-99b1-5eaf10dd41d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675759051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wit
h_pre_cond.675759051
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3851308191
Short name T630
Test name
Test status
Simulation time 5435538970 ps
CPU time 2.25 seconds
Started Jul 20 04:41:29 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201448 kb
Host smart-bea80e2c-e844-4706-a1af-1c238888c607
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851308191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3851308191
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.839707162
Short name T251
Test name
Test status
Simulation time 588773780575 ps
CPU time 104.15 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:43:10 PM PDT 24
Peak memory 201544 kb
Host smart-c4991287-3b8f-4968-a32a-933e01c1e509
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839707162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl
_edge_detect.839707162
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3898500509
Short name T755
Test name
Test status
Simulation time 2619948980 ps
CPU time 2.91 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201520 kb
Host smart-f3b859f6-4a99-4e85-9f9f-def00213ac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898500509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.3898500509
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1886944604
Short name T638
Test name
Test status
Simulation time 2461595500 ps
CPU time 7.77 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 201548 kb
Host smart-87988196-9f5a-4359-8d22-d11b44a4b2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886944604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1886944604
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1739457540
Short name T437
Test name
Test status
Simulation time 2220601901 ps
CPU time 2.19 seconds
Started Jul 20 04:41:24 PM PDT 24
Finished Jul 20 04:41:27 PM PDT 24
Peak memory 201344 kb
Host smart-7a4b61e0-7f53-4eb0-b1b3-9651cc1dfa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739457540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1739457540
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2532711647
Short name T399
Test name
Test status
Simulation time 2517241410 ps
CPU time 3.99 seconds
Started Jul 20 04:41:27 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201464 kb
Host smart-26e472d2-5778-4ae9-8120-a98de415a8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532711647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2532711647
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.668356924
Short name T161
Test name
Test status
Simulation time 2128344618 ps
CPU time 1.95 seconds
Started Jul 20 04:41:27 PM PDT 24
Finished Jul 20 04:41:30 PM PDT 24
Peak memory 201408 kb
Host smart-11edbdb4-3235-43ed-8274-bf5c61815a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668356924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.668356924
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1093390164
Short name T400
Test name
Test status
Simulation time 9867774075 ps
CPU time 12.83 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:41:39 PM PDT 24
Peak memory 201516 kb
Host smart-54fb89ca-324a-4621-9359-4938fcdedcce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093390164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1093390164
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.410883196
Short name T148
Test name
Test status
Simulation time 85466688921 ps
CPU time 104.66 seconds
Started Jul 20 04:41:28 PM PDT 24
Finished Jul 20 04:43:14 PM PDT 24
Peak memory 210136 kb
Host smart-5ba123d4-df64-4266-8509-5beea38e304e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410883196 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.410883196
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2728330764
Short name T526
Test name
Test status
Simulation time 5098583474 ps
CPU time 6.34 seconds
Started Jul 20 04:41:25 PM PDT 24
Finished Jul 20 04:41:32 PM PDT 24
Peak memory 201444 kb
Host smart-e2ab205d-c6c0-4a71-b3f6-030032550805
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728330764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.2728330764
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2887011436
Short name T113
Test name
Test status
Simulation time 22843090633 ps
CPU time 14.47 seconds
Started Jul 20 04:43:14 PM PDT 24
Finished Jul 20 04:43:31 PM PDT 24
Peak memory 201780 kb
Host smart-a138329a-de9f-42b0-84ba-fd3b6cfd7168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887011436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.2887011436
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.4132162853
Short name T383
Test name
Test status
Simulation time 129799771371 ps
CPU time 302.92 seconds
Started Jul 20 04:43:11 PM PDT 24
Finished Jul 20 04:48:17 PM PDT 24
Peak memory 201744 kb
Host smart-48515f3d-3949-4246-a2ee-1a6eae892fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132162853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.4132162853
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3645503808
Short name T373
Test name
Test status
Simulation time 85386121903 ps
CPU time 38.2 seconds
Started Jul 20 04:43:09 PM PDT 24
Finished Jul 20 04:43:49 PM PDT 24
Peak memory 201864 kb
Host smart-deec127c-298f-45a9-adf9-f78938d8b41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645503808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.3645503808
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1052118709
Short name T394
Test name
Test status
Simulation time 76331765208 ps
CPU time 183.54 seconds
Started Jul 20 04:43:10 PM PDT 24
Finished Jul 20 04:46:16 PM PDT 24
Peak memory 201752 kb
Host smart-5840bdc4-bc6f-4989-9df2-715f95230774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052118709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.1052118709
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.4148383857
Short name T539
Test name
Test status
Simulation time 36208302581 ps
CPU time 10.01 seconds
Started Jul 20 04:43:16 PM PDT 24
Finished Jul 20 04:43:28 PM PDT 24
Peak memory 201840 kb
Host smart-85f04c89-324b-40df-9aa9-10fd69b1d369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148383857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.4148383857
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3127181089
Short name T378
Test name
Test status
Simulation time 105467565264 ps
CPU time 100.2 seconds
Started Jul 20 04:43:09 PM PDT 24
Finished Jul 20 04:44:52 PM PDT 24
Peak memory 201864 kb
Host smart-92c2d140-5332-4fe0-aeeb-3d7893394d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127181089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.3127181089
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2780759514
Short name T238
Test name
Test status
Simulation time 96340634769 ps
CPU time 252.25 seconds
Started Jul 20 04:43:08 PM PDT 24
Finished Jul 20 04:47:21 PM PDT 24
Peak memory 201800 kb
Host smart-e28f97c0-6376-4652-9a67-c15b5bf6fa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780759514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.2780759514
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1727050732
Short name T631
Test name
Test status
Simulation time 24850070353 ps
CPU time 14.8 seconds
Started Jul 20 04:43:09 PM PDT 24
Finished Jul 20 04:43:26 PM PDT 24
Peak memory 201824 kb
Host smart-82d57adb-ad01-4988-8c36-65dc1702a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727050732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.1727050732
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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