Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T4 |
10 |
|
T17 |
11 |
|
T2 |
9 |
| auto[1] |
782 |
1 |
|
|
T4 |
10 |
|
T17 |
9 |
|
T2 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T4 |
3 |
|
T17 |
15 |
|
T2 |
9 |
| auto[1] |
794 |
1 |
|
|
T4 |
17 |
|
T17 |
5 |
|
T2 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
807 |
1 |
|
|
T4 |
10 |
|
T17 |
12 |
|
T2 |
10 |
| auto[1] |
793 |
1 |
|
|
T4 |
10 |
|
T17 |
8 |
|
T2 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
822 |
1 |
|
|
T4 |
12 |
|
T17 |
8 |
|
T2 |
13 |
| auto[1] |
778 |
1 |
|
|
T4 |
8 |
|
T17 |
12 |
|
T2 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T4 |
11 |
|
T17 |
10 |
|
T2 |
10 |
| auto[1] |
777 |
1 |
|
|
T4 |
9 |
|
T17 |
10 |
|
T2 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T4 |
12 |
|
T17 |
8 |
|
T2 |
11 |
| auto[1] |
752 |
1 |
|
|
T4 |
8 |
|
T17 |
12 |
|
T2 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
784 |
1 |
|
|
T4 |
8 |
|
T17 |
10 |
|
T2 |
13 |
| auto[1] |
816 |
1 |
|
|
T4 |
12 |
|
T17 |
10 |
|
T2 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
819 |
1 |
|
|
T4 |
10 |
|
T17 |
11 |
|
T2 |
11 |
| auto[1] |
781 |
1 |
|
|
T4 |
10 |
|
T17 |
9 |
|
T2 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
799 |
1 |
|
|
T4 |
11 |
|
T17 |
5 |
|
T2 |
9 |
| auto[1] |
801 |
1 |
|
|
T4 |
9 |
|
T17 |
15 |
|
T2 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
788 |
1 |
|
|
T4 |
14 |
|
T17 |
11 |
|
T2 |
8 |
| auto[1] |
812 |
1 |
|
|
T4 |
6 |
|
T17 |
9 |
|
T2 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T4 |
14 |
|
T17 |
6 |
|
T2 |
5 |
| auto[1] |
813 |
1 |
|
|
T4 |
6 |
|
T17 |
14 |
|
T2 |
15 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T4 |
12 |
|
T17 |
8 |
|
T2 |
12 |
| auto[1] |
788 |
1 |
|
|
T4 |
8 |
|
T17 |
12 |
|
T2 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
749 |
1 |
|
|
T4 |
7 |
|
T17 |
5 |
|
T2 |
14 |
| auto[1] |
851 |
1 |
|
|
T4 |
13 |
|
T17 |
15 |
|
T2 |
6 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T4 |
3 |
|
T17 |
15 |
|
T2 |
9 |
| auto[1] |
794 |
1 |
|
|
T4 |
17 |
|
T17 |
5 |
|
T2 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
767 |
1 |
|
|
T4 |
8 |
|
T17 |
11 |
|
T2 |
13 |
| auto[1] |
833 |
1 |
|
|
T4 |
12 |
|
T17 |
9 |
|
T2 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
782 |
1 |
|
|
T4 |
8 |
|
T17 |
13 |
|
T2 |
10 |
| auto[1] |
818 |
1 |
|
|
T4 |
12 |
|
T17 |
7 |
|
T2 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
784 |
1 |
|
|
T4 |
8 |
|
T17 |
9 |
|
T2 |
12 |
| auto[1] |
816 |
1 |
|
|
T4 |
12 |
|
T17 |
11 |
|
T2 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T4 |
9 |
|
T17 |
9 |
|
T2 |
11 |
| auto[1] |
799 |
1 |
|
|
T4 |
11 |
|
T17 |
11 |
|
T2 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
765 |
1 |
|
|
T4 |
10 |
|
T17 |
11 |
|
T2 |
8 |
| auto[1] |
835 |
1 |
|
|
T4 |
10 |
|
T17 |
9 |
|
T2 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
760 |
1 |
|
|
T4 |
10 |
|
T17 |
10 |
|
T2 |
12 |
| auto[1] |
840 |
1 |
|
|
T4 |
10 |
|
T17 |
10 |
|
T2 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T4 |
8 |
|
T17 |
11 |
|
T2 |
11 |
| auto[1] |
805 |
1 |
|
|
T4 |
12 |
|
T17 |
9 |
|
T2 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T4 |
11 |
|
T17 |
8 |
|
T2 |
8 |
| auto[1] |
786 |
1 |
|
|
T4 |
9 |
|
T17 |
12 |
|
T2 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
785 |
1 |
|
|
T4 |
13 |
|
T17 |
11 |
|
T2 |
9 |
| auto[1] |
815 |
1 |
|
|
T4 |
7 |
|
T17 |
9 |
|
T2 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T4 |
12 |
|
T17 |
8 |
|
T2 |
12 |
| auto[1] |
788 |
1 |
|
|
T4 |
8 |
|
T17 |
12 |
|
T2 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
390 |
1 |
|
|
T4 |
3 |
|
T17 |
6 |
|
T2 |
7 |
| auto[0] |
auto[1] |
377 |
1 |
|
|
T4 |
5 |
|
T17 |
5 |
|
T2 |
6 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T4 |
7 |
|
T17 |
6 |
|
T2 |
3 |
| auto[1] |
auto[1] |
416 |
1 |
|
|
T4 |
5 |
|
T17 |
3 |
|
T2 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
405 |
1 |
|
|
T4 |
4 |
|
T17 |
5 |
|
T2 |
7 |
| auto[0] |
auto[1] |
377 |
1 |
|
|
T4 |
4 |
|
T17 |
8 |
|
T2 |
3 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T4 |
8 |
|
T17 |
3 |
|
T2 |
6 |
| auto[1] |
auto[1] |
401 |
1 |
|
|
T4 |
4 |
|
T17 |
4 |
|
T2 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
406 |
1 |
|
|
T4 |
5 |
|
T17 |
5 |
|
T2 |
6 |
| auto[0] |
auto[1] |
378 |
1 |
|
|
T4 |
3 |
|
T17 |
4 |
|
T2 |
6 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T4 |
6 |
|
T17 |
5 |
|
T2 |
4 |
| auto[1] |
auto[1] |
399 |
1 |
|
|
T4 |
6 |
|
T17 |
6 |
|
T2 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T4 |
6 |
|
T17 |
4 |
|
T2 |
6 |
| auto[0] |
auto[1] |
374 |
1 |
|
|
T4 |
3 |
|
T17 |
5 |
|
T2 |
5 |
| auto[1] |
auto[0] |
421 |
1 |
|
|
T4 |
6 |
|
T17 |
4 |
|
T2 |
5 |
| auto[1] |
auto[1] |
378 |
1 |
|
|
T4 |
5 |
|
T17 |
7 |
|
T2 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
361 |
1 |
|
|
T4 |
3 |
|
T17 |
7 |
|
T2 |
4 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T4 |
7 |
|
T17 |
4 |
|
T2 |
4 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T4 |
5 |
|
T17 |
3 |
|
T2 |
9 |
| auto[1] |
auto[1] |
412 |
1 |
|
|
T4 |
5 |
|
T17 |
6 |
|
T2 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
376 |
1 |
|
|
T4 |
4 |
|
T17 |
7 |
|
T2 |
5 |
| auto[0] |
auto[1] |
384 |
1 |
|
|
T4 |
6 |
|
T17 |
3 |
|
T2 |
7 |
| auto[1] |
auto[0] |
443 |
1 |
|
|
T4 |
6 |
|
T17 |
4 |
|
T2 |
6 |
| auto[1] |
auto[1] |
397 |
1 |
|
|
T4 |
4 |
|
T17 |
6 |
|
T2 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
394 |
1 |
|
|
T4 |
8 |
|
T17 |
3 |
|
T2 |
4 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T4 |
3 |
|
T17 |
5 |
|
T2 |
4 |
| auto[1] |
auto[0] |
394 |
1 |
|
|
T4 |
6 |
|
T17 |
8 |
|
T2 |
4 |
| auto[1] |
auto[1] |
392 |
1 |
|
|
T4 |
3 |
|
T17 |
4 |
|
T2 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
379 |
1 |
|
|
T4 |
9 |
|
T17 |
2 |
|
T2 |
3 |
| auto[0] |
auto[1] |
406 |
1 |
|
|
T4 |
4 |
|
T17 |
9 |
|
T2 |
6 |
| auto[1] |
auto[0] |
408 |
1 |
|
|
T4 |
5 |
|
T17 |
4 |
|
T2 |
2 |
| auto[1] |
auto[1] |
407 |
1 |
|
|
T4 |
2 |
|
T17 |
5 |
|
T2 |
9 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
378 |
1 |
|
|
T4 |
2 |
|
T17 |
1 |
|
T2 |
5 |
| auto[0] |
auto[1] |
371 |
1 |
|
|
T4 |
5 |
|
T17 |
4 |
|
T2 |
9 |
| auto[1] |
auto[0] |
440 |
1 |
|
|
T4 |
8 |
|
T17 |
10 |
|
T2 |
4 |
| auto[1] |
auto[1] |
411 |
1 |
|
|
T4 |
5 |
|
T17 |
5 |
|
T2 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
806 |
1 |
|
|
T4 |
3 |
|
T17 |
15 |
|
T2 |
9 |
| auto[1] |
auto[1] |
794 |
1 |
|
|
T4 |
17 |
|
T17 |
5 |
|
T2 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
401 |
1 |
|
|
T4 |
4 |
|
T17 |
4 |
|
T2 |
4 |
| auto[0] |
auto[1] |
394 |
1 |
|
|
T4 |
4 |
|
T17 |
7 |
|
T2 |
7 |
| auto[1] |
auto[0] |
398 |
1 |
|
|
T4 |
7 |
|
T17 |
1 |
|
T2 |
5 |
| auto[1] |
auto[1] |
407 |
1 |
|
|
T4 |
5 |
|
T17 |
8 |
|
T2 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
812 |
1 |
|
|
T4 |
12 |
|
T17 |
8 |
|
T2 |
12 |
| auto[1] |
auto[1] |
788 |
1 |
|
|
T4 |
8 |
|
T17 |
12 |
|
T2 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T102 |
7 |
|
T361 |
13 |
|
T165 |
10 |
| auto[1] |
112 |
1 |
|
|
T102 |
3 |
|
T361 |
7 |
|
T165 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T102 |
7 |
|
T361 |
15 |
|
T165 |
8 |
| auto[1] |
110 |
1 |
|
|
T102 |
3 |
|
T361 |
5 |
|
T165 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T102 |
6 |
|
T361 |
9 |
|
T165 |
7 |
| auto[1] |
126 |
1 |
|
|
T102 |
4 |
|
T361 |
11 |
|
T165 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T102 |
5 |
|
T361 |
9 |
|
T165 |
8 |
| auto[1] |
124 |
1 |
|
|
T102 |
5 |
|
T361 |
11 |
|
T165 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T102 |
4 |
|
T361 |
12 |
|
T165 |
10 |
| auto[1] |
127 |
1 |
|
|
T102 |
6 |
|
T361 |
8 |
|
T165 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T102 |
6 |
|
T361 |
10 |
|
T165 |
11 |
| auto[1] |
123 |
1 |
|
|
T102 |
4 |
|
T361 |
10 |
|
T165 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T102 |
3 |
|
T361 |
14 |
|
T165 |
8 |
| auto[1] |
118 |
1 |
|
|
T102 |
7 |
|
T361 |
6 |
|
T165 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T102 |
5 |
|
T361 |
11 |
|
T165 |
12 |
| auto[1] |
124 |
1 |
|
|
T102 |
5 |
|
T361 |
9 |
|
T165 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T102 |
2 |
|
T361 |
9 |
|
T165 |
10 |
| auto[1] |
126 |
1 |
|
|
T102 |
8 |
|
T361 |
11 |
|
T165 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T102 |
2 |
|
T361 |
9 |
|
T165 |
7 |
| auto[1] |
135 |
1 |
|
|
T102 |
8 |
|
T361 |
11 |
|
T165 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T102 |
7 |
|
T361 |
9 |
|
T165 |
9 |
| auto[1] |
124 |
1 |
|
|
T102 |
3 |
|
T361 |
11 |
|
T165 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T102 |
2 |
|
T361 |
7 |
|
T165 |
10 |
| auto[1] |
133 |
1 |
|
|
T102 |
8 |
|
T361 |
13 |
|
T165 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T102 |
3 |
|
T361 |
8 |
|
T165 |
10 |
| auto[1] |
128 |
1 |
|
|
T102 |
7 |
|
T361 |
12 |
|
T165 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T102 |
7 |
|
T361 |
15 |
|
T165 |
8 |
| auto[1] |
110 |
1 |
|
|
T102 |
3 |
|
T361 |
5 |
|
T165 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T102 |
5 |
|
T361 |
11 |
|
T165 |
8 |
| auto[1] |
124 |
1 |
|
|
T102 |
5 |
|
T361 |
9 |
|
T165 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T102 |
6 |
|
T361 |
11 |
|
T165 |
7 |
| auto[1] |
114 |
1 |
|
|
T102 |
4 |
|
T361 |
9 |
|
T165 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T102 |
6 |
|
T361 |
10 |
|
T165 |
7 |
| auto[1] |
120 |
1 |
|
|
T102 |
4 |
|
T361 |
10 |
|
T165 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T102 |
6 |
|
T361 |
6 |
|
T165 |
6 |
| auto[1] |
126 |
1 |
|
|
T102 |
4 |
|
T361 |
14 |
|
T165 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T102 |
5 |
|
T361 |
9 |
|
T165 |
9 |
| auto[1] |
127 |
1 |
|
|
T102 |
5 |
|
T361 |
11 |
|
T165 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T102 |
5 |
|
T361 |
6 |
|
T165 |
11 |
| auto[1] |
125 |
1 |
|
|
T102 |
5 |
|
T361 |
14 |
|
T165 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T102 |
6 |
|
T361 |
12 |
|
T165 |
9 |
| auto[1] |
122 |
1 |
|
|
T102 |
4 |
|
T361 |
8 |
|
T165 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T102 |
4 |
|
T361 |
8 |
|
T165 |
10 |
| auto[1] |
114 |
1 |
|
|
T102 |
6 |
|
T361 |
12 |
|
T165 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T102 |
3 |
|
T361 |
10 |
|
T165 |
8 |
| auto[1] |
149 |
1 |
|
|
T102 |
7 |
|
T361 |
10 |
|
T165 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T102 |
1 |
|
T361 |
7 |
|
T165 |
10 |
| auto[1] |
134 |
1 |
|
|
T102 |
9 |
|
T361 |
13 |
|
T165 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T102 |
3 |
|
T361 |
5 |
|
T165 |
2 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T102 |
2 |
|
T361 |
6 |
|
T165 |
6 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T102 |
3 |
|
T361 |
4 |
|
T165 |
5 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T102 |
2 |
|
T361 |
5 |
|
T165 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T102 |
3 |
|
T361 |
5 |
|
T165 |
2 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T102 |
3 |
|
T361 |
6 |
|
T165 |
5 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T102 |
2 |
|
T361 |
4 |
|
T165 |
6 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T102 |
2 |
|
T361 |
5 |
|
T165 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T102 |
3 |
|
T361 |
6 |
|
T165 |
5 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T102 |
3 |
|
T361 |
4 |
|
T165 |
2 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T102 |
1 |
|
T361 |
6 |
|
T165 |
5 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T102 |
3 |
|
T361 |
4 |
|
T165 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T102 |
4 |
|
T361 |
3 |
|
T165 |
5 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T102 |
2 |
|
T361 |
3 |
|
T165 |
1 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T102 |
2 |
|
T361 |
7 |
|
T165 |
6 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T102 |
2 |
|
T361 |
7 |
|
T165 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T102 |
1 |
|
T361 |
7 |
|
T165 |
4 |
| auto[0] |
auto[1] |
64 |
1 |
|
|
T102 |
4 |
|
T361 |
2 |
|
T165 |
5 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T102 |
2 |
|
T361 |
7 |
|
T165 |
4 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T102 |
3 |
|
T361 |
4 |
|
T165 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T102 |
2 |
|
T361 |
4 |
|
T165 |
7 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T102 |
3 |
|
T361 |
2 |
|
T165 |
4 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T102 |
3 |
|
T361 |
7 |
|
T165 |
5 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T102 |
2 |
|
T361 |
7 |
|
T165 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T102 |
1 |
|
T361 |
3 |
|
T165 |
1 |
| auto[0] |
auto[1] |
78 |
1 |
|
|
T102 |
3 |
|
T361 |
5 |
|
T165 |
9 |
| auto[1] |
auto[0] |
57 |
1 |
|
|
T102 |
1 |
|
T361 |
6 |
|
T165 |
6 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T102 |
5 |
|
T361 |
6 |
|
T165 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T102 |
3 |
|
T361 |
4 |
|
T165 |
1 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T361 |
6 |
|
T165 |
7 |
|
T299 |
4 |
| auto[1] |
auto[0] |
80 |
1 |
|
|
T102 |
4 |
|
T361 |
5 |
|
T165 |
8 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T102 |
3 |
|
T361 |
5 |
|
T165 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T102 |
3 |
|
T361 |
6 |
|
T165 |
6 |
| auto[0] |
auto[1] |
51 |
1 |
|
|
T361 |
2 |
|
T165 |
4 |
|
T299 |
3 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T102 |
4 |
|
T361 |
7 |
|
T165 |
4 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T102 |
3 |
|
T361 |
5 |
|
T165 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
140 |
1 |
|
|
T102 |
7 |
|
T361 |
15 |
|
T165 |
8 |
| auto[1] |
auto[1] |
110 |
1 |
|
|
T102 |
3 |
|
T361 |
5 |
|
T165 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T102 |
1 |
|
T361 |
5 |
|
T165 |
4 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T102 |
5 |
|
T361 |
7 |
|
T165 |
5 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T102 |
1 |
|
T361 |
4 |
|
T165 |
6 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T102 |
3 |
|
T361 |
4 |
|
T165 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
116 |
1 |
|
|
T102 |
1 |
|
T361 |
7 |
|
T165 |
10 |
| auto[1] |
auto[1] |
133 |
1 |
|
|
T102 |
8 |
|
T361 |
13 |
|
T165 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T361 |
11 |
|
T363 |
8 |
|
T212 |
10 |
| auto[1] |
31 |
1 |
|
|
T361 |
9 |
|
T363 |
12 |
|
T212 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T361 |
14 |
|
T363 |
9 |
|
T212 |
11 |
| auto[1] |
26 |
1 |
|
|
T361 |
6 |
|
T363 |
11 |
|
T212 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
32 |
1 |
|
|
T361 |
10 |
|
T363 |
11 |
|
T212 |
11 |
| auto[1] |
28 |
1 |
|
|
T361 |
10 |
|
T363 |
9 |
|
T212 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
27 |
1 |
|
|
T361 |
9 |
|
T363 |
9 |
|
T212 |
9 |
| auto[1] |
33 |
1 |
|
|
T361 |
11 |
|
T363 |
11 |
|
T212 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
39 |
1 |
|
|
T361 |
9 |
|
T363 |
17 |
|
T212 |
13 |
| auto[1] |
21 |
1 |
|
|
T361 |
11 |
|
T363 |
3 |
|
T212 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T361 |
12 |
|
T363 |
11 |
|
T212 |
10 |
| auto[1] |
27 |
1 |
|
|
T361 |
8 |
|
T363 |
9 |
|
T212 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
26 |
1 |
|
|
T361 |
9 |
|
T363 |
9 |
|
T212 |
8 |
| auto[1] |
34 |
1 |
|
|
T361 |
11 |
|
T363 |
11 |
|
T212 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T361 |
7 |
|
T363 |
13 |
|
T212 |
13 |
| auto[1] |
27 |
1 |
|
|
T361 |
13 |
|
T363 |
7 |
|
T212 |
7 |