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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.17 99.44 96.86 100.00 98.72 98.89 99.81 93.49


Total test records in report: 916
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T793 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2882102654 Aug 02 04:57:21 PM PDT 24 Aug 02 04:57:28 PM PDT 24 2451361168 ps
T794 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.111492888 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:32 PM PDT 24 2010910501 ps
T26 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3900451877 Aug 02 04:54:21 PM PDT 24 Aug 02 04:54:27 PM PDT 24 2039760498 ps
T27 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1924057216 Aug 02 04:54:16 PM PDT 24 Aug 02 04:54:18 PM PDT 24 2060976229 ps
T20 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.231714888 Aug 02 04:54:21 PM PDT 24 Aug 02 04:54:25 PM PDT 24 10052253449 ps
T28 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1619316657 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:47 PM PDT 24 42791911400 ps
T255 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1329654762 Aug 02 04:54:20 PM PDT 24 Aug 02 04:54:22 PM PDT 24 2115374094 ps
T249 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3724254280 Aug 02 04:54:05 PM PDT 24 Aug 02 04:55:52 PM PDT 24 42359909314 ps
T252 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.75249114 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:17 PM PDT 24 2043817096 ps
T251 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2069002057 Aug 02 04:54:25 PM PDT 24 Aug 02 04:54:33 PM PDT 24 2148092840 ps
T795 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3794134902 Aug 02 04:54:29 PM PDT 24 Aug 02 04:54:34 PM PDT 24 2012470856 ps
T287 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2433645120 Aug 02 04:54:06 PM PDT 24 Aug 02 04:54:35 PM PDT 24 39198038910 ps
T21 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.739322357 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:27 PM PDT 24 7575109413 ps
T253 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1686168796 Aug 02 04:54:05 PM PDT 24 Aug 02 04:54:10 PM PDT 24 2195153106 ps
T796 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1912117904 Aug 02 04:54:05 PM PDT 24 Aug 02 04:54:07 PM PDT 24 2041050316 ps
T797 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2836881351 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:34 PM PDT 24 2011817867 ps
T257 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2376791911 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:34 PM PDT 24 2041006502 ps
T254 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.863551629 Aug 02 04:54:15 PM PDT 24 Aug 02 04:54:18 PM PDT 24 2078569353 ps
T22 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.4008290681 Aug 02 04:54:12 PM PDT 24 Aug 02 04:54:30 PM PDT 24 4409417691 ps
T798 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1619591422 Aug 02 04:54:07 PM PDT 24 Aug 02 04:54:14 PM PDT 24 2045770517 ps
T300 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1826622957 Aug 02 04:54:21 PM PDT 24 Aug 02 04:54:24 PM PDT 24 2061562324 ps
T288 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1893152192 Aug 02 04:54:23 PM PDT 24 Aug 02 04:54:29 PM PDT 24 2030899005 ps
T799 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2162650025 Aug 02 04:54:29 PM PDT 24 Aug 02 04:54:33 PM PDT 24 2021355240 ps
T250 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1203475557 Aug 02 04:54:16 PM PDT 24 Aug 02 04:54:45 PM PDT 24 42512361641 ps
T303 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.346065416 Aug 02 04:55:21 PM PDT 24 Aug 02 04:55:25 PM PDT 24 2527914074 ps
T301 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1899022654 Aug 02 04:54:16 PM PDT 24 Aug 02 04:54:26 PM PDT 24 6996878838 ps
T342 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4200628167 Aug 02 04:53:59 PM PDT 24 Aug 02 04:56:19 PM PDT 24 38672574358 ps
T302 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.835810918 Aug 02 04:54:19 PM PDT 24 Aug 02 04:54:25 PM PDT 24 2036535302 ps
T260 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2914542314 Aug 02 04:54:28 PM PDT 24 Aug 02 04:55:26 PM PDT 24 22232684047 ps
T256 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1853672230 Aug 02 04:54:16 PM PDT 24 Aug 02 04:54:20 PM PDT 24 2409571739 ps
T289 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2008573154 Aug 02 04:54:21 PM PDT 24 Aug 02 04:54:23 PM PDT 24 2131814691 ps
T800 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2170530399 Aug 02 04:54:34 PM PDT 24 Aug 02 04:54:37 PM PDT 24 2018140325 ps
T801 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1278220480 Aug 02 04:54:18 PM PDT 24 Aug 02 04:54:20 PM PDT 24 2049492034 ps
T802 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1702513134 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:30 PM PDT 24 2051403641 ps
T803 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1100572587 Aug 02 04:54:08 PM PDT 24 Aug 02 04:54:22 PM PDT 24 4802458084 ps
T804 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3083272703 Aug 02 04:54:12 PM PDT 24 Aug 02 04:54:39 PM PDT 24 10649921581 ps
T805 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1849706991 Aug 02 04:54:23 PM PDT 24 Aug 02 04:54:25 PM PDT 24 2041068090 ps
T806 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.568895801 Aug 02 04:54:20 PM PDT 24 Aug 02 04:54:25 PM PDT 24 2015193431 ps
T807 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3032021601 Aug 02 04:54:12 PM PDT 24 Aug 02 04:54:14 PM PDT 24 2054010538 ps
T290 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3858961504 Aug 02 04:54:07 PM PDT 24 Aug 02 04:54:09 PM PDT 24 2139613635 ps
T808 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4265142742 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:32 PM PDT 24 2017218483 ps
T809 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2111736562 Aug 02 04:54:07 PM PDT 24 Aug 02 04:54:13 PM PDT 24 3560598086 ps
T810 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2685683848 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:32 PM PDT 24 2014835303 ps
T811 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3449697491 Aug 02 04:54:32 PM PDT 24 Aug 02 04:54:34 PM PDT 24 2044458008 ps
T812 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3584398778 Aug 02 04:54:25 PM PDT 24 Aug 02 04:54:26 PM PDT 24 2056575802 ps
T813 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1131265874 Aug 02 04:54:05 PM PDT 24 Aug 02 04:54:15 PM PDT 24 2679137740 ps
T259 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.60579959 Aug 02 04:54:25 PM PDT 24 Aug 02 04:54:30 PM PDT 24 2087459426 ps
T814 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1816409000 Aug 02 04:54:13 PM PDT 24 Aug 02 04:54:15 PM PDT 24 2341265497 ps
T337 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3743002731 Aug 02 04:54:16 PM PDT 24 Aug 02 04:54:31 PM PDT 24 22454898592 ps
T815 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.155030783 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:31 PM PDT 24 2015006391 ps
T816 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1937910381 Aug 02 04:54:10 PM PDT 24 Aug 02 04:54:14 PM PDT 24 2047151512 ps
T817 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1732840439 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:28 PM PDT 24 2032006406 ps
T291 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1494478426 Aug 02 04:54:00 PM PDT 24 Aug 02 04:54:07 PM PDT 24 2052364611 ps
T818 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2078403997 Aug 02 04:54:13 PM PDT 24 Aug 02 04:54:15 PM PDT 24 2109143797 ps
T819 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.4139495266 Aug 02 04:54:33 PM PDT 24 Aug 02 04:54:37 PM PDT 24 2023387324 ps
T820 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4222015203 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:32 PM PDT 24 2108894917 ps
T821 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1140959375 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:33 PM PDT 24 2076064551 ps
T822 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2450982533 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:30 PM PDT 24 2022463099 ps
T258 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2138080622 Aug 02 04:54:03 PM PDT 24 Aug 02 04:54:10 PM PDT 24 2108615245 ps
T340 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2397363715 Aug 02 04:54:26 PM PDT 24 Aug 02 04:55:26 PM PDT 24 42612907874 ps
T823 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.748009002 Aug 02 04:54:15 PM PDT 24 Aug 02 04:54:18 PM PDT 24 2122523205 ps
T261 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2118787029 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:17 PM PDT 24 2727475272 ps
T824 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1495760604 Aug 02 04:54:24 PM PDT 24 Aug 02 04:54:30 PM PDT 24 2007949428 ps
T292 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1059178110 Aug 02 04:54:09 PM PDT 24 Aug 02 04:56:40 PM PDT 24 40516911223 ps
T293 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.263526013 Aug 02 04:54:04 PM PDT 24 Aug 02 04:54:34 PM PDT 24 58581456886 ps
T825 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.249074188 Aug 02 04:54:05 PM PDT 24 Aug 02 04:54:10 PM PDT 24 5541838192 ps
T294 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2057261055 Aug 02 04:54:19 PM PDT 24 Aug 02 04:54:24 PM PDT 24 2025478753 ps
T826 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2825651159 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:34 PM PDT 24 2015318197 ps
T827 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.734478677 Aug 02 04:54:13 PM PDT 24 Aug 02 04:54:19 PM PDT 24 2031043379 ps
T828 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.475044943 Aug 02 04:54:34 PM PDT 24 Aug 02 04:54:36 PM PDT 24 2050863354 ps
T829 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2071045960 Aug 02 04:54:17 PM PDT 24 Aug 02 04:54:21 PM PDT 24 2108504872 ps
T341 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.380210782 Aug 02 04:54:16 PM PDT 24 Aug 02 04:55:12 PM PDT 24 22203203680 ps
T830 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2760506317 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:16 PM PDT 24 2044954745 ps
T831 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3057421471 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:17 PM PDT 24 2061314769 ps
T832 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.930784943 Aug 02 04:54:20 PM PDT 24 Aug 02 04:54:23 PM PDT 24 2312673735 ps
T833 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2508870180 Aug 02 04:54:22 PM PDT 24 Aug 02 04:54:50 PM PDT 24 42913903467 ps
T834 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3107021866 Aug 02 04:54:15 PM PDT 24 Aug 02 04:54:21 PM PDT 24 2014855028 ps
T835 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.873221076 Aug 02 04:54:13 PM PDT 24 Aug 02 04:54:19 PM PDT 24 2007314404 ps
T836 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2889970933 Aug 02 04:54:15 PM PDT 24 Aug 02 04:54:23 PM PDT 24 2047288376 ps
T837 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2637783420 Aug 02 04:54:25 PM PDT 24 Aug 02 04:54:28 PM PDT 24 2028915047 ps
T838 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1129761375 Aug 02 04:54:15 PM PDT 24 Aug 02 04:54:18 PM PDT 24 2030462684 ps
T839 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.813466075 Aug 02 04:54:13 PM PDT 24 Aug 02 04:54:19 PM PDT 24 2017862696 ps
T840 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2579178453 Aug 02 04:54:36 PM PDT 24 Aug 02 04:54:37 PM PDT 24 2082687556 ps
T841 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3488342674 Aug 02 04:54:25 PM PDT 24 Aug 02 04:54:30 PM PDT 24 2545935049 ps
T842 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2900426730 Aug 02 04:55:23 PM PDT 24 Aug 02 04:57:03 PM PDT 24 40642564797 ps
T843 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3093754104 Aug 02 04:54:19 PM PDT 24 Aug 02 04:54:25 PM PDT 24 2042537107 ps
T844 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2119710516 Aug 02 04:54:06 PM PDT 24 Aug 02 04:54:36 PM PDT 24 42799415182 ps
T845 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3195528312 Aug 02 04:54:19 PM PDT 24 Aug 02 04:54:27 PM PDT 24 8211704391 ps
T846 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.889909312 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:32 PM PDT 24 2012990791 ps
T847 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2326506740 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:30 PM PDT 24 2046161275 ps
T848 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1888468331 Aug 02 04:54:29 PM PDT 24 Aug 02 04:54:35 PM PDT 24 2014259754 ps
T849 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1694944538 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:39 PM PDT 24 9728212081 ps
T850 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.688608369 Aug 02 04:54:24 PM PDT 24 Aug 02 04:54:50 PM PDT 24 10314342431 ps
T851 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3906420941 Aug 02 04:54:32 PM PDT 24 Aug 02 04:54:38 PM PDT 24 2014224523 ps
T852 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1732440585 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:21 PM PDT 24 2089675881 ps
T853 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1372826348 Aug 02 04:54:25 PM PDT 24 Aug 02 04:54:27 PM PDT 24 2202120981 ps
T854 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2682455137 Aug 02 04:54:12 PM PDT 24 Aug 02 04:54:18 PM PDT 24 2044443045 ps
T855 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2893404845 Aug 02 04:54:20 PM PDT 24 Aug 02 04:54:52 PM PDT 24 8599591423 ps
T856 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2336644218 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:28 PM PDT 24 2405498554 ps
T857 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1142781385 Aug 02 04:54:08 PM PDT 24 Aug 02 04:54:18 PM PDT 24 7487851630 ps
T858 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1831019370 Aug 02 04:54:20 PM PDT 24 Aug 02 04:56:08 PM PDT 24 42383585240 ps
T859 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2910013816 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:30 PM PDT 24 2312364611 ps
T860 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2038562867 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:37 PM PDT 24 4524737188 ps
T295 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2577155514 Aug 02 04:54:07 PM PDT 24 Aug 02 04:54:09 PM PDT 24 2095757415 ps
T861 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2692843271 Aug 02 04:54:01 PM PDT 24 Aug 02 04:54:15 PM PDT 24 6032179280 ps
T338 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.545558856 Aug 02 04:54:29 PM PDT 24 Aug 02 04:55:28 PM PDT 24 22234825181 ps
T862 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1853791241 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:34 PM PDT 24 2047088525 ps
T863 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1947924502 Aug 02 04:54:21 PM PDT 24 Aug 02 04:54:27 PM PDT 24 2039869486 ps
T864 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3795368825 Aug 02 04:54:15 PM PDT 24 Aug 02 04:54:17 PM PDT 24 2243970181 ps
T865 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.805787021 Aug 02 04:54:11 PM PDT 24 Aug 02 04:54:16 PM PDT 24 5169381546 ps
T866 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3638496919 Aug 02 04:54:28 PM PDT 24 Aug 02 04:54:31 PM PDT 24 2029547998 ps
T296 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3400558924 Aug 02 04:54:07 PM PDT 24 Aug 02 04:54:16 PM PDT 24 6048707110 ps
T867 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1611044912 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:18 PM PDT 24 2304742129 ps
T868 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2404304152 Aug 02 04:54:22 PM PDT 24 Aug 02 04:54:25 PM PDT 24 2255189251 ps
T869 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2943308162 Aug 02 04:54:16 PM PDT 24 Aug 02 04:54:21 PM PDT 24 2070680668 ps
T297 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3342895387 Aug 02 04:54:10 PM PDT 24 Aug 02 04:54:16 PM PDT 24 2057602756 ps
T870 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2111603202 Aug 02 04:54:34 PM PDT 24 Aug 02 04:54:36 PM PDT 24 2046418616 ps
T871 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1646660289 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:23 PM PDT 24 9529791796 ps
T872 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3385071780 Aug 02 04:54:07 PM PDT 24 Aug 02 04:54:25 PM PDT 24 22270314343 ps
T873 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1633933796 Aug 02 04:54:05 PM PDT 24 Aug 02 04:54:11 PM PDT 24 2011326058 ps
T874 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2455190183 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:37 PM PDT 24 4486227445 ps
T339 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.19057790 Aug 02 04:54:20 PM PDT 24 Aug 02 04:55:16 PM PDT 24 22188293065 ps
T875 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1675954495 Aug 02 04:54:12 PM PDT 24 Aug 02 04:54:18 PM PDT 24 2062940379 ps
T876 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1929460744 Aug 02 04:54:09 PM PDT 24 Aug 02 04:54:14 PM PDT 24 2010996803 ps
T877 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1023638172 Aug 02 04:54:16 PM PDT 24 Aug 02 04:54:22 PM PDT 24 2012001623 ps
T878 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3267114367 Aug 02 04:54:24 PM PDT 24 Aug 02 04:55:24 PM PDT 24 42366654211 ps
T879 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4289260140 Aug 02 04:54:17 PM PDT 24 Aug 02 04:54:20 PM PDT 24 2136042327 ps
T880 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3556837578 Aug 02 04:54:31 PM PDT 24 Aug 02 04:54:33 PM PDT 24 2027905810 ps
T298 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3935345487 Aug 02 04:54:08 PM PDT 24 Aug 02 04:54:13 PM PDT 24 6045680518 ps
T881 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1149732653 Aug 02 04:54:23 PM PDT 24 Aug 02 04:54:28 PM PDT 24 5320945841 ps
T882 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.43866076 Aug 02 04:54:05 PM PDT 24 Aug 02 04:54:09 PM PDT 24 6084009280 ps
T883 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.737389160 Aug 02 04:54:15 PM PDT 24 Aug 02 04:54:21 PM PDT 24 2014016346 ps
T884 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3781305060 Aug 02 04:54:15 PM PDT 24 Aug 02 04:54:30 PM PDT 24 22447640336 ps
T885 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.806344580 Aug 02 04:54:25 PM PDT 24 Aug 02 04:55:09 PM PDT 24 22240215059 ps
T886 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2969234217 Aug 02 04:54:06 PM PDT 24 Aug 02 04:54:13 PM PDT 24 2073586301 ps
T887 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3215706457 Aug 02 04:54:27 PM PDT 24 Aug 02 04:54:33 PM PDT 24 2015170612 ps
T888 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.532903191 Aug 02 04:54:14 PM PDT 24 Aug 02 04:55:13 PM PDT 24 22253823176 ps
T889 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.796021900 Aug 02 04:54:07 PM PDT 24 Aug 02 04:54:28 PM PDT 24 5294874841 ps
T890 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3611760245 Aug 02 04:54:04 PM PDT 24 Aug 02 04:54:08 PM PDT 24 2079516899 ps
T891 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.385098603 Aug 02 04:54:20 PM PDT 24 Aug 02 04:54:23 PM PDT 24 2097585135 ps
T892 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2953512362 Aug 02 04:54:36 PM PDT 24 Aug 02 04:54:38 PM PDT 24 2024906446 ps
T893 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.771902720 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:29 PM PDT 24 2024620595 ps
T299 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3535824267 Aug 02 04:55:21 PM PDT 24 Aug 02 04:55:25 PM PDT 24 3093164974 ps
T894 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3405661397 Aug 02 04:54:21 PM PDT 24 Aug 02 04:54:29 PM PDT 24 2046435196 ps
T895 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2277731552 Aug 02 04:54:21 PM PDT 24 Aug 02 04:54:24 PM PDT 24 2115603899 ps
T896 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2062313682 Aug 02 04:54:17 PM PDT 24 Aug 02 04:54:19 PM PDT 24 2117861902 ps
T897 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1142641808 Aug 02 04:54:12 PM PDT 24 Aug 02 04:54:14 PM PDT 24 2075689705 ps
T898 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2328899613 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:42 PM PDT 24 42518929658 ps
T899 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3572912448 Aug 02 04:54:29 PM PDT 24 Aug 02 04:54:30 PM PDT 24 2126384763 ps
T900 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1461740352 Aug 02 04:54:34 PM PDT 24 Aug 02 04:54:37 PM PDT 24 2021143829 ps
T901 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4126113794 Aug 02 04:54:22 PM PDT 24 Aug 02 04:54:28 PM PDT 24 2010440160 ps
T902 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.133452538 Aug 02 04:54:29 PM PDT 24 Aug 02 04:54:31 PM PDT 24 2040109836 ps
T903 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2146667185 Aug 02 04:54:19 PM PDT 24 Aug 02 04:54:25 PM PDT 24 2017518734 ps
T904 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2874516681 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:28 PM PDT 24 2097591170 ps
T905 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2342543226 Aug 02 04:54:13 PM PDT 24 Aug 02 04:54:22 PM PDT 24 7091745580 ps
T906 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1043185212 Aug 02 04:54:21 PM PDT 24 Aug 02 04:54:25 PM PDT 24 2027190820 ps
T907 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2596778758 Aug 02 04:54:22 PM PDT 24 Aug 02 04:54:27 PM PDT 24 2081780914 ps
T908 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.370832045 Aug 02 04:54:05 PM PDT 24 Aug 02 04:54:16 PM PDT 24 4013598736 ps
T909 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1014323589 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:32 PM PDT 24 2030455210 ps
T910 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1381552529 Aug 02 04:54:07 PM PDT 24 Aug 02 04:54:13 PM PDT 24 2013245266 ps
T911 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2674199059 Aug 02 04:54:26 PM PDT 24 Aug 02 04:54:56 PM PDT 24 42791941887 ps
T912 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.66123388 Aug 02 04:54:14 PM PDT 24 Aug 02 04:54:19 PM PDT 24 2676424259 ps
T913 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2688621020 Aug 02 04:54:20 PM PDT 24 Aug 02 04:54:57 PM PDT 24 7525752313 ps
T914 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2610904003 Aug 02 04:54:25 PM PDT 24 Aug 02 04:54:27 PM PDT 24 2044959362 ps
T915 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2057884563 Aug 02 04:54:13 PM PDT 24 Aug 02 04:54:16 PM PDT 24 2115786238 ps
T916 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.442317278 Aug 02 04:55:17 PM PDT 24 Aug 02 04:55:29 PM PDT 24 22311371395 ps

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3392542982
Short name T1
Test name
Test status
Simulation time 86261664121 ps
CPU time 18.09 seconds
Started Aug 02 04:55:42 PM PDT 24
Finished Aug 02 04:56:00 PM PDT 24
Peak memory 209356 kb
Host smart-e5e2fbbb-6cc6-41cb-96b6-2736db078d1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392542982 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.3392542982
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1354107940
Short name T29
Test name
Test status
Simulation time 70851905692 ps
CPU time 45 seconds
Started Aug 02 04:56:21 PM PDT 24
Finished Aug 02 04:57:06 PM PDT 24
Peak memory 201032 kb
Host smart-c50d58f5-1800-440d-a4dc-23678a695671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354107940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.1354107940
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2935687649
Short name T45
Test name
Test status
Simulation time 1596556187128 ps
CPU time 390.43 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 05:03:06 PM PDT 24
Peak memory 217576 kb
Host smart-8ef4d944-816f-4866-a03d-c9f7579806ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935687649 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.2935687649
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2356843738
Short name T35
Test name
Test status
Simulation time 1029876220225 ps
CPU time 322.2 seconds
Started Aug 02 04:57:06 PM PDT 24
Finished Aug 02 05:02:28 PM PDT 24
Peak memory 213696 kb
Host smart-3dedfcd3-1bdc-499e-9c10-823b718ee6eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356843738 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2356843738
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3857556321
Short name T51
Test name
Test status
Simulation time 35686016850 ps
CPU time 23.13 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:56:16 PM PDT 24
Peak memory 200796 kb
Host smart-215a4989-a269-402f-8776-77e8b0541153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857556321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3857556321
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1077595446
Short name T65
Test name
Test status
Simulation time 152880074227 ps
CPU time 101.36 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:59:26 PM PDT 24
Peak memory 201084 kb
Host smart-81f8c43c-97d2-44ef-be87-b42a44f93f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077595446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.1077595446
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3724254280
Short name T249
Test name
Test status
Simulation time 42359909314 ps
CPU time 106.98 seconds
Started Aug 02 04:54:05 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 201292 kb
Host smart-57d8a81f-9b1f-4506-93bf-1842ef4619d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724254280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.3724254280
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4116515941
Short name T72
Test name
Test status
Simulation time 38937752868 ps
CPU time 18.23 seconds
Started Aug 02 04:55:48 PM PDT 24
Finished Aug 02 04:56:07 PM PDT 24
Peak memory 200776 kb
Host smart-2086b1c7-3a2b-447b-8d02-93e34e422c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116515941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.4116515941
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3890635899
Short name T153
Test name
Test status
Simulation time 233971015805 ps
CPU time 39.18 seconds
Started Aug 02 04:56:06 PM PDT 24
Finished Aug 02 04:56:45 PM PDT 24
Peak memory 209436 kb
Host smart-4f8284f3-b5c3-4ea6-a05b-ea9c63ac1b97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890635899 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.3890635899
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2270621359
Short name T8
Test name
Test status
Simulation time 127422888393 ps
CPU time 160.03 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:59:33 PM PDT 24
Peak memory 201124 kb
Host smart-236df414-0dfa-44d3-a5d6-9e4dc1f6276c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270621359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.2270621359
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3217793950
Short name T97
Test name
Test status
Simulation time 90263305870 ps
CPU time 84.59 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:58:45 PM PDT 24
Peak memory 217592 kb
Host smart-cc9ac1e0-af98-4b90-a812-d9f240233236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217793950 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3217793950
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.4157867146
Short name T13
Test name
Test status
Simulation time 42096644625 ps
CPU time 29.81 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:32 PM PDT 24
Peak memory 220656 kb
Host smart-73226f63-4efc-4dcf-8065-abf709afb1a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157867146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.4157867146
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2497715324
Short name T70
Test name
Test status
Simulation time 232363317874 ps
CPU time 35.01 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:46 PM PDT 24
Peak memory 212616 kb
Host smart-afd73392-5764-4132-a68d-91b9a09383a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497715324 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.2497715324
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.528528341
Short name T96
Test name
Test status
Simulation time 161649264856 ps
CPU time 106.58 seconds
Started Aug 02 04:56:30 PM PDT 24
Finished Aug 02 04:58:17 PM PDT 24
Peak memory 201080 kb
Host smart-0aa98234-f396-462c-8cf9-19e6c228883b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528528341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_st
ress_all.528528341
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3192266454
Short name T95
Test name
Test status
Simulation time 312011680416 ps
CPU time 138.88 seconds
Started Aug 02 04:57:51 PM PDT 24
Finished Aug 02 05:00:10 PM PDT 24
Peak memory 217516 kb
Host smart-4256f2d1-c428-4b23-a9c3-a134f5fa1ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192266454 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3192266454
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.2657589977
Short name T79
Test name
Test status
Simulation time 3081183308 ps
CPU time 2.21 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:38 PM PDT 24
Peak memory 200816 kb
Host smart-d9b2c7e5-f196-4243-8a09-0534714ea2ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657589977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.2657589977
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1474447768
Short name T130
Test name
Test status
Simulation time 28825675333 ps
CPU time 36.7 seconds
Started Aug 02 04:57:30 PM PDT 24
Finished Aug 02 04:58:07 PM PDT 24
Peak memory 217396 kb
Host smart-25497584-a0fa-420b-becd-4ef3ac3ce918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474447768 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1474447768
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1501484455
Short name T2
Test name
Test status
Simulation time 6313755531 ps
CPU time 7.76 seconds
Started Aug 02 04:56:24 PM PDT 24
Finished Aug 02 04:56:32 PM PDT 24
Peak memory 200940 kb
Host smart-095f868b-b20d-4d8a-ba2d-6b0c76b89608
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501484455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.1501484455
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1680924398
Short name T38
Test name
Test status
Simulation time 32563385356 ps
CPU time 78.33 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:58:17 PM PDT 24
Peak memory 216740 kb
Host smart-4efdcbb6-aed6-4f1f-b6de-946db95beda2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680924398 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1680924398
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1686168796
Short name T253
Test name
Test status
Simulation time 2195153106 ps
CPU time 4.68 seconds
Started Aug 02 04:54:05 PM PDT 24
Finished Aug 02 04:54:10 PM PDT 24
Peak memory 201616 kb
Host smart-608a19bf-5091-403b-98a7-39f8ac9a51c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686168796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.1686168796
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.993914339
Short name T90
Test name
Test status
Simulation time 214056577982 ps
CPU time 130.88 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:59:55 PM PDT 24
Peak memory 201028 kb
Host smart-03f69344-02db-4d9d-afd3-e73523e0637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993914339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_wi
th_pre_cond.993914339
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2497785488
Short name T23
Test name
Test status
Simulation time 4667203322 ps
CPU time 3.63 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:30 PM PDT 24
Peak memory 200760 kb
Host smart-09c69e68-fd02-42d0-97c5-fc9401d83995
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497785488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2497785488
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2433645120
Short name T287
Test name
Test status
Simulation time 39198038910 ps
CPU time 28.9 seconds
Started Aug 02 04:54:06 PM PDT 24
Finished Aug 02 04:54:35 PM PDT 24
Peak memory 201740 kb
Host smart-375e79b6-2de7-422c-bbcc-14c984be1b47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433645120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.2433645120
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2788039328
Short name T169
Test name
Test status
Simulation time 5133530616 ps
CPU time 2.71 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:30 PM PDT 24
Peak memory 200900 kb
Host smart-9bd5cade-052e-41f3-8596-d821ca171a45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788039328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.2788039328
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.4117464417
Short name T152
Test name
Test status
Simulation time 3230917159 ps
CPU time 8.87 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:08 PM PDT 24
Peak memory 200804 kb
Host smart-d6d6b8c3-58fd-4b66-b96a-749b699062c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117464417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.4117464417
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1550031921
Short name T66
Test name
Test status
Simulation time 83418091426 ps
CPU time 51.51 seconds
Started Aug 02 04:57:52 PM PDT 24
Finished Aug 02 04:58:44 PM PDT 24
Peak memory 201092 kb
Host smart-82fa6b92-67bd-4992-b3fe-900976354ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550031921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1550031921
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.1464422031
Short name T307
Test name
Test status
Simulation time 155996956636 ps
CPU time 387.18 seconds
Started Aug 02 04:56:28 PM PDT 24
Finished Aug 02 05:02:56 PM PDT 24
Peak memory 200952 kb
Host smart-6537cdd7-b3de-4627-9940-f046eb916a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464422031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.1464422031
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3279049954
Short name T269
Test name
Test status
Simulation time 360102437973 ps
CPU time 38.51 seconds
Started Aug 02 04:56:44 PM PDT 24
Finished Aug 02 04:57:23 PM PDT 24
Peak memory 209492 kb
Host smart-9a554099-f8a8-4d1f-a513-29aa1a450f7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279049954 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3279049954
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1454344213
Short name T282
Test name
Test status
Simulation time 76925008304 ps
CPU time 19.17 seconds
Started Aug 02 04:57:15 PM PDT 24
Finished Aug 02 04:57:35 PM PDT 24
Peak memory 200996 kb
Host smart-9800c38a-86a5-4016-9289-fe17e52b2d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454344213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.1454344213
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3356228242
Short name T73
Test name
Test status
Simulation time 68991763309 ps
CPU time 34.85 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:56 PM PDT 24
Peak memory 201084 kb
Host smart-703de13a-42dd-4d21-8f6a-e693b29ca6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356228242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.3356228242
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2258634101
Short name T105
Test name
Test status
Simulation time 2021737316 ps
CPU time 3.15 seconds
Started Aug 02 04:56:26 PM PDT 24
Finished Aug 02 04:56:29 PM PDT 24
Peak memory 200776 kb
Host smart-978a5139-8597-46ca-97c7-b396141923b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258634101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2258634101
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1899022654
Short name T301
Test name
Test status
Simulation time 6996878838 ps
CPU time 10.18 seconds
Started Aug 02 04:54:16 PM PDT 24
Finished Aug 02 04:54:26 PM PDT 24
Peak memory 201504 kb
Host smart-36a579a0-3fb2-4d81-883e-f082fa4e1a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899022654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.1899022654
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3273370080
Short name T81
Test name
Test status
Simulation time 149447349945 ps
CPU time 31.89 seconds
Started Aug 02 04:56:56 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 209424 kb
Host smart-20437859-ce52-42bd-acf5-128c2ab5978d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273370080 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.3273370080
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.996669715
Short name T311
Test name
Test status
Simulation time 77823950439 ps
CPU time 47.26 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 201052 kb
Host smart-c5a4a50b-b85e-4260-91f3-6c9db338e4d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996669715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_combo_detect.996669715
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.648122417
Short name T323
Test name
Test status
Simulation time 116070862448 ps
CPU time 80.76 seconds
Started Aug 02 04:56:37 PM PDT 24
Finished Aug 02 04:57:58 PM PDT 24
Peak memory 201092 kb
Host smart-5e3bf498-26e9-415c-8ba7-3e0ec1e73637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648122417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_wi
th_pre_cond.648122417
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2397363715
Short name T340
Test name
Test status
Simulation time 42612907874 ps
CPU time 60.01 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:55:26 PM PDT 24
Peak memory 201632 kb
Host smart-5cc3cb1c-27f3-4e41-a602-b3bdcfc18fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397363715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.2397363715
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2157732444
Short name T336
Test name
Test status
Simulation time 160517078889 ps
CPU time 153.24 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:59:47 PM PDT 24
Peak memory 201112 kb
Host smart-b344ec05-6643-44c7-a595-0c696fd9d7b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157732444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.2157732444
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.1123206304
Short name T304
Test name
Test status
Simulation time 153842610118 ps
CPU time 355.22 seconds
Started Aug 02 04:57:25 PM PDT 24
Finished Aug 02 05:03:20 PM PDT 24
Peak memory 201048 kb
Host smart-e69a7003-4111-40aa-83d8-8afcb5c7fd7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123206304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.1123206304
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.4290856515
Short name T85
Test name
Test status
Simulation time 141652312406 ps
CPU time 343.57 seconds
Started Aug 02 04:57:29 PM PDT 24
Finished Aug 02 05:03:13 PM PDT 24
Peak memory 201048 kb
Host smart-995e60ca-0d41-445b-a994-0224267dd93b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290856515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.4290856515
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2138080622
Short name T258
Test name
Test status
Simulation time 2108615245 ps
CPU time 6.83 seconds
Started Aug 02 04:54:03 PM PDT 24
Finished Aug 02 04:54:10 PM PDT 24
Peak memory 201724 kb
Host smart-52d2be13-6a40-47d1-8873-11ce16df9405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138080622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.2138080622
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.658757409
Short name T132
Test name
Test status
Simulation time 3237323283 ps
CPU time 2.58 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 04:56:56 PM PDT 24
Peak memory 200856 kb
Host smart-40719afc-e261-4246-90e6-dabda6572bff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658757409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctr
l_edge_detect.658757409
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1838878327
Short name T44
Test name
Test status
Simulation time 3510086684 ps
CPU time 4.78 seconds
Started Aug 02 04:56:36 PM PDT 24
Finished Aug 02 04:56:41 PM PDT 24
Peak memory 200908 kb
Host smart-5295e1bc-85ea-4b54-a14d-dfc4739724c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838878327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
838878327
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.612300034
Short name T147
Test name
Test status
Simulation time 54550175987 ps
CPU time 92.47 seconds
Started Aug 02 04:57:54 PM PDT 24
Finished Aug 02 04:59:27 PM PDT 24
Peak memory 217672 kb
Host smart-58cd27c8-332f-4e05-85be-e978415ba4f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612300034 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.612300034
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2377436416
Short name T315
Test name
Test status
Simulation time 84845920110 ps
CPU time 112.31 seconds
Started Aug 02 04:58:00 PM PDT 24
Finished Aug 02 04:59:52 PM PDT 24
Peak memory 201136 kb
Host smart-56e1d38b-6a0f-4df9-9561-0afa40d25030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377436416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.2377436416
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.851981519
Short name T180
Test name
Test status
Simulation time 2985998695 ps
CPU time 1.14 seconds
Started Aug 02 04:56:47 PM PDT 24
Finished Aug 02 04:56:49 PM PDT 24
Peak memory 200864 kb
Host smart-9b92434f-b651-49a1-894a-a7c1e4342929
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851981519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctr
l_edge_detect.851981519
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1838321464
Short name T122
Test name
Test status
Simulation time 1159939947104 ps
CPU time 69.68 seconds
Started Aug 02 04:56:13 PM PDT 24
Finished Aug 02 04:57:23 PM PDT 24
Peak memory 209488 kb
Host smart-a19c6573-fc4a-4a69-ae89-904c6f9e9409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838321464 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1838321464
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2328899613
Short name T898
Test name
Test status
Simulation time 42518929658 ps
CPU time 28.07 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:42 PM PDT 24
Peak memory 201644 kb
Host smart-cc6baec0-d8fb-4725-a060-dde23729fddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328899613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.2328899613
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.756326356
Short name T31
Test name
Test status
Simulation time 68633747520 ps
CPU time 13.02 seconds
Started Aug 02 04:56:24 PM PDT 24
Finished Aug 02 04:56:38 PM PDT 24
Peak memory 201100 kb
Host smart-912a2065-e8b7-4650-8245-207527a5aad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756326356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_wi
th_pre_cond.756326356
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.856116434
Short name T322
Test name
Test status
Simulation time 115827043995 ps
CPU time 77.07 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:57:44 PM PDT 24
Peak memory 201272 kb
Host smart-5a10ccf2-e34b-4c88-a31a-e1f375addd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856116434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi
th_pre_cond.856116434
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.558868402
Short name T331
Test name
Test status
Simulation time 57914238992 ps
CPU time 142.05 seconds
Started Aug 02 04:56:36 PM PDT 24
Finished Aug 02 04:58:58 PM PDT 24
Peak memory 201088 kb
Host smart-5185b341-472f-4331-b9ab-1686a1fed33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558868402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wi
th_pre_cond.558868402
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3711204293
Short name T12
Test name
Test status
Simulation time 64011851375 ps
CPU time 41.02 seconds
Started Aug 02 04:56:55 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 201020 kb
Host smart-2ad222af-1200-4ad8-8b88-ae20d9ee316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711204293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.3711204293
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3394657774
Short name T332
Test name
Test status
Simulation time 70755223561 ps
CPU time 187.45 seconds
Started Aug 02 04:57:06 PM PDT 24
Finished Aug 02 05:00:14 PM PDT 24
Peak memory 201168 kb
Host smart-5fc47dab-aba4-47e1-8957-81fa2d5fd7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394657774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.3394657774
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.348905926
Short name T348
Test name
Test status
Simulation time 64926753764 ps
CPU time 88.31 seconds
Started Aug 02 04:57:22 PM PDT 24
Finished Aug 02 04:58:50 PM PDT 24
Peak memory 201088 kb
Host smart-90788e09-d8f3-4421-a9d7-e12422ebcb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348905926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_wi
th_pre_cond.348905926
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1915525066
Short name T327
Test name
Test status
Simulation time 100543476474 ps
CPU time 46.07 seconds
Started Aug 02 04:57:29 PM PDT 24
Finished Aug 02 04:58:15 PM PDT 24
Peak memory 201152 kb
Host smart-caf64cd6-2c36-42f6-bde0-3c36c6c0c7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915525066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.1915525066
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1540818097
Short name T350
Test name
Test status
Simulation time 47601469631 ps
CPU time 16.9 seconds
Started Aug 02 04:57:56 PM PDT 24
Finished Aug 02 04:58:13 PM PDT 24
Peak memory 201088 kb
Host smart-35895fda-245b-4b76-b796-bae032a6656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540818097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.1540818097
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2781704001
Short name T312
Test name
Test status
Simulation time 86570720841 ps
CPU time 59.95 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:58:44 PM PDT 24
Peak memory 201132 kb
Host smart-2bb9327d-a686-489d-aad0-95eb97a3d3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781704001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2781704001
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1990578747
Short name T317
Test name
Test status
Simulation time 141833404088 ps
CPU time 49.93 seconds
Started Aug 02 04:57:51 PM PDT 24
Finished Aug 02 04:58:41 PM PDT 24
Peak memory 201148 kb
Host smart-8e8058b7-6100-4538-abfe-3c7f83f5b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990578747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.1990578747
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.806635602
Short name T329
Test name
Test status
Simulation time 150777908331 ps
CPU time 96.27 seconds
Started Aug 02 04:57:54 PM PDT 24
Finished Aug 02 04:59:30 PM PDT 24
Peak memory 201072 kb
Host smart-51fcd289-b1ae-43c6-96a0-674cfd87d9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806635602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_wi
th_pre_cond.806635602
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.4277665967
Short name T236
Test name
Test status
Simulation time 32615817384 ps
CPU time 78.25 seconds
Started Aug 02 04:56:26 PM PDT 24
Finished Aug 02 04:57:44 PM PDT 24
Peak memory 201176 kb
Host smart-8e559714-9c2c-4687-8558-2c7e7d4a2690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277665967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.4277665967
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3022871879
Short name T243
Test name
Test status
Simulation time 32555941586 ps
CPU time 86.39 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:57:17 PM PDT 24
Peak memory 201116 kb
Host smart-140fe4c6-fe01-4443-ab40-3d512e523cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022871879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.3022871879
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3368523254
Short name T217
Test name
Test status
Simulation time 54453618503 ps
CPU time 10.44 seconds
Started Aug 02 04:57:54 PM PDT 24
Finished Aug 02 04:58:04 PM PDT 24
Peak memory 201040 kb
Host smart-d9041308-82ac-40eb-934f-1186524c0c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368523254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3368523254
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2111736562
Short name T809
Test name
Test status
Simulation time 3560598086 ps
CPU time 5.89 seconds
Started Aug 02 04:54:07 PM PDT 24
Finished Aug 02 04:54:13 PM PDT 24
Peak memory 201664 kb
Host smart-aa3500b3-8572-48a2-9895-b69af4cd6f1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111736562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.2111736562
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4200628167
Short name T342
Test name
Test status
Simulation time 38672574358 ps
CPU time 139.99 seconds
Started Aug 02 04:53:59 PM PDT 24
Finished Aug 02 04:56:19 PM PDT 24
Peak memory 201588 kb
Host smart-b535aa79-1871-463b-9095-622bb3aeda6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200628167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.4200628167
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2692843271
Short name T861
Test name
Test status
Simulation time 6032179280 ps
CPU time 13.14 seconds
Started Aug 02 04:54:01 PM PDT 24
Finished Aug 02 04:54:15 PM PDT 24
Peak memory 201456 kb
Host smart-74648d5f-b9f6-40f2-8d3b-fc38c818d55c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692843271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.2692843271
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3900451877
Short name T26
Test name
Test status
Simulation time 2039760498 ps
CPU time 5.98 seconds
Started Aug 02 04:54:21 PM PDT 24
Finished Aug 02 04:54:27 PM PDT 24
Peak memory 201568 kb
Host smart-24a892a6-3d75-46bf-94b8-f13128cf14df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900451877 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3900451877
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1494478426
Short name T291
Test name
Test status
Simulation time 2052364611 ps
CPU time 5.98 seconds
Started Aug 02 04:54:00 PM PDT 24
Finished Aug 02 04:54:07 PM PDT 24
Peak memory 201484 kb
Host smart-ea263c83-5f5d-447f-bdd6-634e225c2905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494478426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1494478426
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1633933796
Short name T873
Test name
Test status
Simulation time 2011326058 ps
CPU time 6.03 seconds
Started Aug 02 04:54:05 PM PDT 24
Finished Aug 02 04:54:11 PM PDT 24
Peak memory 201324 kb
Host smart-b58f7927-7ea3-4a12-a56c-63ff5b0113cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633933796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.1633933796
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.796021900
Short name T889
Test name
Test status
Simulation time 5294874841 ps
CPU time 21.06 seconds
Started Aug 02 04:54:07 PM PDT 24
Finished Aug 02 04:54:28 PM PDT 24
Peak memory 201648 kb
Host smart-bd18b82b-5100-466c-b723-7e7bc9fd8484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796021900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.796021900
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2119710516
Short name T844
Test name
Test status
Simulation time 42799415182 ps
CPU time 30.11 seconds
Started Aug 02 04:54:06 PM PDT 24
Finished Aug 02 04:54:36 PM PDT 24
Peak memory 201580 kb
Host smart-b743c48a-4df6-4f7f-8e98-7de1d8d9271f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119710516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.2119710516
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.346065416
Short name T303
Test name
Test status
Simulation time 2527914074 ps
CPU time 3.81 seconds
Started Aug 02 04:55:21 PM PDT 24
Finished Aug 02 04:55:25 PM PDT 24
Peak memory 201480 kb
Host smart-f04f644a-f358-4dfd-b2ee-2f37224d7dea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346065416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_aliasing.346065416
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.43866076
Short name T882
Test name
Test status
Simulation time 6084009280 ps
CPU time 4 seconds
Started Aug 02 04:54:05 PM PDT 24
Finished Aug 02 04:54:09 PM PDT 24
Peak memory 201364 kb
Host smart-ce161693-cf51-4b1e-9dce-b74588d71808
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43866076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_c
sr_hw_reset.43866076
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1816409000
Short name T814
Test name
Test status
Simulation time 2341265497 ps
CPU time 2.23 seconds
Started Aug 02 04:54:13 PM PDT 24
Finished Aug 02 04:54:15 PM PDT 24
Peak memory 218104 kb
Host smart-639fc8a6-a3a2-48f8-a5bb-41d329978d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816409000 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1816409000
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1937910381
Short name T816
Test name
Test status
Simulation time 2047151512 ps
CPU time 3.51 seconds
Started Aug 02 04:54:10 PM PDT 24
Finished Aug 02 04:54:14 PM PDT 24
Peak memory 201380 kb
Host smart-31f15a1f-6e95-43c3-a3bf-b037ceff5c0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937910381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.1937910381
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1023638172
Short name T877
Test name
Test status
Simulation time 2012001623 ps
CPU time 6.18 seconds
Started Aug 02 04:54:16 PM PDT 24
Finished Aug 02 04:54:22 PM PDT 24
Peak memory 201228 kb
Host smart-e22e4f29-6fed-4191-bc0f-7f74f984800d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023638172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1023638172
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.249074188
Short name T825
Test name
Test status
Simulation time 5541838192 ps
CPU time 4.81 seconds
Started Aug 02 04:54:05 PM PDT 24
Finished Aug 02 04:54:10 PM PDT 24
Peak memory 201532 kb
Host smart-da2c2641-d709-44b1-9201-d9684216f3ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249074188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
sysrst_ctrl_same_csr_outstanding.249074188
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3611760245
Short name T890
Test name
Test status
Simulation time 2079516899 ps
CPU time 3.62 seconds
Started Aug 02 04:54:04 PM PDT 24
Finished Aug 02 04:54:08 PM PDT 24
Peak memory 201576 kb
Host smart-934544eb-deb1-4d54-ae29-77f5c527debf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611760245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.3611760245
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3385071780
Short name T872
Test name
Test status
Simulation time 22270314343 ps
CPU time 17.84 seconds
Started Aug 02 04:54:07 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201696 kb
Host smart-0a09f66b-4ad8-4a4d-b510-e174d5a081f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385071780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.3385071780
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2943308162
Short name T869
Test name
Test status
Simulation time 2070680668 ps
CPU time 5.21 seconds
Started Aug 02 04:54:16 PM PDT 24
Finished Aug 02 04:54:21 PM PDT 24
Peak memory 201316 kb
Host smart-d493e4bf-87c3-4785-b31f-110e292dd096
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943308162 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2943308162
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1142641808
Short name T897
Test name
Test status
Simulation time 2075689705 ps
CPU time 2.06 seconds
Started Aug 02 04:54:12 PM PDT 24
Finished Aug 02 04:54:14 PM PDT 24
Peak memory 201396 kb
Host smart-1d267dfe-07e2-4992-968a-dde0017e8cd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142641808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.1142641808
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3107021866
Short name T834
Test name
Test status
Simulation time 2014855028 ps
CPU time 5.93 seconds
Started Aug 02 04:54:15 PM PDT 24
Finished Aug 02 04:54:21 PM PDT 24
Peak memory 201376 kb
Host smart-86a1db72-b67f-4463-8e46-8a7a05e56ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107021866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.3107021866
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.863551629
Short name T254
Test name
Test status
Simulation time 2078569353 ps
CPU time 2.42 seconds
Started Aug 02 04:54:15 PM PDT 24
Finished Aug 02 04:54:18 PM PDT 24
Peak memory 201712 kb
Host smart-694f4d31-7cfb-4791-8b97-a1914cda9e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863551629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.863551629
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3057421471
Short name T831
Test name
Test status
Simulation time 2061314769 ps
CPU time 3.51 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:17 PM PDT 24
Peak memory 201416 kb
Host smart-f5987073-f3da-481f-9624-ed2ba99fcb5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057421471 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3057421471
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1675954495
Short name T875
Test name
Test status
Simulation time 2062940379 ps
CPU time 6.14 seconds
Started Aug 02 04:54:12 PM PDT 24
Finished Aug 02 04:54:18 PM PDT 24
Peak memory 201300 kb
Host smart-189b8c3d-41c9-4767-aa5b-2f624fec1862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675954495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.1675954495
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1129761375
Short name T838
Test name
Test status
Simulation time 2030462684 ps
CPU time 3.04 seconds
Started Aug 02 04:54:15 PM PDT 24
Finished Aug 02 04:54:18 PM PDT 24
Peak memory 201216 kb
Host smart-06351c55-9600-4d1a-90da-be52f68e7c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129761375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.1129761375
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2342543226
Short name T905
Test name
Test status
Simulation time 7091745580 ps
CPU time 8.23 seconds
Started Aug 02 04:54:13 PM PDT 24
Finished Aug 02 04:54:22 PM PDT 24
Peak memory 201572 kb
Host smart-7c9fb0e8-3ba5-420e-8d9c-2148166a6c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342543226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.2342543226
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1947924502
Short name T863
Test name
Test status
Simulation time 2039869486 ps
CPU time 6.38 seconds
Started Aug 02 04:54:21 PM PDT 24
Finished Aug 02 04:54:27 PM PDT 24
Peak memory 201464 kb
Host smart-4e5a44e1-c358-4133-8298-cfe0d6d504e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947924502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.1947924502
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1203475557
Short name T250
Test name
Test status
Simulation time 42512361641 ps
CPU time 28.79 seconds
Started Aug 02 04:54:16 PM PDT 24
Finished Aug 02 04:54:45 PM PDT 24
Peak memory 201524 kb
Host smart-e921d314-3093-4dca-9842-a4adf415d3b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203475557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.1203475557
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2336644218
Short name T856
Test name
Test status
Simulation time 2405498554 ps
CPU time 1.69 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:28 PM PDT 24
Peak memory 209800 kb
Host smart-82adedc1-1be8-4e22-b820-ac8fb9fc298e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336644218 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2336644218
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1853791241
Short name T862
Test name
Test status
Simulation time 2047088525 ps
CPU time 6.31 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 201480 kb
Host smart-32717939-9404-4937-ac80-f6844cab8bf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853791241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.1853791241
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2685683848
Short name T810
Test name
Test status
Simulation time 2014835303 ps
CPU time 5.98 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:32 PM PDT 24
Peak memory 201172 kb
Host smart-1feeede6-2325-44ea-bd25-372b3edb8a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685683848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2685683848
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2893404845
Short name T855
Test name
Test status
Simulation time 8599591423 ps
CPU time 31.31 seconds
Started Aug 02 04:54:20 PM PDT 24
Finished Aug 02 04:54:52 PM PDT 24
Peak memory 201636 kb
Host smart-ae0f034c-5e52-4961-8c47-2f5bffd2452d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893404845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.2893404845
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2889970933
Short name T836
Test name
Test status
Simulation time 2047288376 ps
CPU time 7.56 seconds
Started Aug 02 04:54:15 PM PDT 24
Finished Aug 02 04:54:23 PM PDT 24
Peak memory 201540 kb
Host smart-ecc091b6-cdbb-4694-91b0-6f1b615be41f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889970933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.2889970933
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1831019370
Short name T858
Test name
Test status
Simulation time 42383585240 ps
CPU time 108.54 seconds
Started Aug 02 04:54:20 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 201592 kb
Host smart-deaedc60-34d8-46d5-8684-55b495cf03cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831019370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.1831019370
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1702513134
Short name T802
Test name
Test status
Simulation time 2051403641 ps
CPU time 3.59 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201332 kb
Host smart-4717757b-9b40-4187-9a67-b352ce8c187c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702513134 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1702513134
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1014323589
Short name T909
Test name
Test status
Simulation time 2030455210 ps
CPU time 5.76 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:32 PM PDT 24
Peak memory 201312 kb
Host smart-be34dc16-9ed0-4873-b8a2-99f11673c93d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014323589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.1014323589
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2637783420
Short name T837
Test name
Test status
Simulation time 2028915047 ps
CPU time 3.09 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:54:28 PM PDT 24
Peak memory 201160 kb
Host smart-08935e75-9481-40cc-bd49-0a2129928ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637783420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.2637783420
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1149732653
Short name T881
Test name
Test status
Simulation time 5320945841 ps
CPU time 4.25 seconds
Started Aug 02 04:54:23 PM PDT 24
Finished Aug 02 04:54:28 PM PDT 24
Peak memory 201532 kb
Host smart-7d75e1c3-81b9-43b1-8849-edcf0c1adb58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149732653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.1149732653
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.930784943
Short name T832
Test name
Test status
Simulation time 2312673735 ps
CPU time 2.39 seconds
Started Aug 02 04:54:20 PM PDT 24
Finished Aug 02 04:54:23 PM PDT 24
Peak memory 201804 kb
Host smart-f63c2068-2575-4063-84c7-d69a9ded7c9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930784943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.930784943
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2508870180
Short name T833
Test name
Test status
Simulation time 42913903467 ps
CPU time 27.91 seconds
Started Aug 02 04:54:22 PM PDT 24
Finished Aug 02 04:54:50 PM PDT 24
Peak memory 201604 kb
Host smart-579d6660-e436-47fb-9dd0-6e771b9be1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508870180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.2508870180
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1372826348
Short name T853
Test name
Test status
Simulation time 2202120981 ps
CPU time 1.59 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:54:27 PM PDT 24
Peak memory 201488 kb
Host smart-d57138a1-32bd-4cd0-8640-dc0fe0358969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372826348 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1372826348
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.385098603
Short name T891
Test name
Test status
Simulation time 2097585135 ps
CPU time 2.79 seconds
Started Aug 02 04:54:20 PM PDT 24
Finished Aug 02 04:54:23 PM PDT 24
Peak memory 201324 kb
Host smart-02c73bed-d199-4b12-b875-351fc898c711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385098603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.385098603
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1849706991
Short name T805
Test name
Test status
Simulation time 2041068090 ps
CPU time 1.3 seconds
Started Aug 02 04:54:23 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201072 kb
Host smart-2f9e3d86-3d8d-4392-9432-3d87837a5ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849706991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1849706991
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.688608369
Short name T850
Test name
Test status
Simulation time 10314342431 ps
CPU time 25.53 seconds
Started Aug 02 04:54:24 PM PDT 24
Finished Aug 02 04:54:50 PM PDT 24
Peak memory 201744 kb
Host smart-f8c50fba-e665-4dab-a214-0e99afe9fac3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688608369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_same_csr_outstanding.688608369
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2910013816
Short name T859
Test name
Test status
Simulation time 2312364611 ps
CPU time 3.09 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201736 kb
Host smart-ab1ba61c-1920-457b-8a48-5aac7535bea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910013816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2910013816
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2674199059
Short name T911
Test name
Test status
Simulation time 42791941887 ps
CPU time 30.66 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:56 PM PDT 24
Peak memory 201524 kb
Host smart-ec052541-dc20-47de-a5d1-175e2636fd17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674199059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.2674199059
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1329654762
Short name T255
Test name
Test status
Simulation time 2115374094 ps
CPU time 2.27 seconds
Started Aug 02 04:54:20 PM PDT 24
Finished Aug 02 04:54:22 PM PDT 24
Peak memory 201508 kb
Host smart-64cfeb26-c771-4a68-bc8a-31fa0b840843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329654762 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1329654762
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1826622957
Short name T300
Test name
Test status
Simulation time 2061562324 ps
CPU time 2.55 seconds
Started Aug 02 04:54:21 PM PDT 24
Finished Aug 02 04:54:24 PM PDT 24
Peak memory 201504 kb
Host smart-26abf27c-5ec1-44a6-bee2-c518e097391c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826622957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1826622957
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3584398778
Short name T812
Test name
Test status
Simulation time 2056575802 ps
CPU time 1.54 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:54:26 PM PDT 24
Peak memory 201156 kb
Host smart-39153f86-ac52-4ecd-86f7-d366081cb609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584398778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.3584398778
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.231714888
Short name T20
Test name
Test status
Simulation time 10052253449 ps
CPU time 4.04 seconds
Started Aug 02 04:54:21 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201776 kb
Host smart-0f8ae32e-b108-4fca-ae04-bab04df5895a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231714888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.sysrst_ctrl_same_csr_outstanding.231714888
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2376791911
Short name T257
Test name
Test status
Simulation time 2041006502 ps
CPU time 7.77 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 201540 kb
Host smart-d3f38f67-f741-4e9c-8c63-cfd63d81c924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376791911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.2376791911
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4222015203
Short name T820
Test name
Test status
Simulation time 2108894917 ps
CPU time 3.83 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:32 PM PDT 24
Peak memory 201496 kb
Host smart-ec45977d-60c7-4f47-a820-43382362df9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222015203 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4222015203
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1893152192
Short name T288
Test name
Test status
Simulation time 2030899005 ps
CPU time 6.02 seconds
Started Aug 02 04:54:23 PM PDT 24
Finished Aug 02 04:54:29 PM PDT 24
Peak memory 201280 kb
Host smart-82baeba9-bc96-4b97-a506-1236fb88634a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893152192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.1893152192
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1278220480
Short name T801
Test name
Test status
Simulation time 2049492034 ps
CPU time 1.45 seconds
Started Aug 02 04:54:18 PM PDT 24
Finished Aug 02 04:54:20 PM PDT 24
Peak memory 201072 kb
Host smart-90f8c922-31ef-46c4-bb3a-62c95c073dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278220480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.1278220480
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2038562867
Short name T860
Test name
Test status
Simulation time 4524737188 ps
CPU time 8.78 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 201524 kb
Host smart-9ce7d2d4-bd98-4a1f-ae0d-64b9b3baa154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038562867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2038562867
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3488342674
Short name T841
Test name
Test status
Simulation time 2545935049 ps
CPU time 4.1 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201740 kb
Host smart-63da2432-94cc-4350-a134-eeffe3b55de5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488342674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.3488342674
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2914542314
Short name T260
Test name
Test status
Simulation time 22232684047 ps
CPU time 57.93 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:55:26 PM PDT 24
Peak memory 201648 kb
Host smart-f8e3a49a-1464-4b88-8f0d-b38f71229cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914542314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.2914542314
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1140959375
Short name T821
Test name
Test status
Simulation time 2076064551 ps
CPU time 6.53 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:33 PM PDT 24
Peak memory 201404 kb
Host smart-644f6e48-2056-4454-80ba-39192f9fc35e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140959375 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1140959375
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.835810918
Short name T302
Test name
Test status
Simulation time 2036535302 ps
CPU time 5.95 seconds
Started Aug 02 04:54:19 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201312 kb
Host smart-75714f2c-8e11-4618-865a-25f7fc69545c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835810918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_r
w.835810918
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.568895801
Short name T806
Test name
Test status
Simulation time 2015193431 ps
CPU time 5.52 seconds
Started Aug 02 04:54:20 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201020 kb
Host smart-87ac7a43-bb9f-43d8-b60e-526bab4a4312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568895801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_tes
t.568895801
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2455190183
Short name T874
Test name
Test status
Simulation time 4486227445 ps
CPU time 11.69 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 201476 kb
Host smart-caa37d6a-01b4-4fd8-8e4f-a86c27bf37c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455190183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.2455190183
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2596778758
Short name T907
Test name
Test status
Simulation time 2081780914 ps
CPU time 5.36 seconds
Started Aug 02 04:54:22 PM PDT 24
Finished Aug 02 04:54:27 PM PDT 24
Peak memory 201580 kb
Host smart-521daa38-d093-4a0f-8235-e68ee4885025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596778758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.2596778758
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.806344580
Short name T885
Test name
Test status
Simulation time 22240215059 ps
CPU time 43.31 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:55:09 PM PDT 24
Peak memory 201548 kb
Host smart-82492c13-b550-43cc-b73d-d37433a7f118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806344580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.806344580
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2874516681
Short name T904
Test name
Test status
Simulation time 2097591170 ps
CPU time 2.46 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:28 PM PDT 24
Peak memory 201412 kb
Host smart-3e906b2f-f61e-4688-ae2c-061bf8c74d1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874516681 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2874516681
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2277731552
Short name T895
Test name
Test status
Simulation time 2115603899 ps
CPU time 2.3 seconds
Started Aug 02 04:54:21 PM PDT 24
Finished Aug 02 04:54:24 PM PDT 24
Peak memory 201504 kb
Host smart-1a122dbb-b38d-4241-be2b-95ecbdd023e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277731552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.2277731552
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1495760604
Short name T824
Test name
Test status
Simulation time 2007949428 ps
CPU time 5.81 seconds
Started Aug 02 04:54:24 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201376 kb
Host smart-9bb05905-e5df-43e2-a4f9-51916cef57a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495760604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.1495760604
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3195528312
Short name T845
Test name
Test status
Simulation time 8211704391 ps
CPU time 8.43 seconds
Started Aug 02 04:54:19 PM PDT 24
Finished Aug 02 04:54:27 PM PDT 24
Peak memory 201620 kb
Host smart-7dfa8a80-6031-427d-bdeb-350e0681e346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195528312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.3195528312
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.60579959
Short name T259
Test name
Test status
Simulation time 2087459426 ps
CPU time 5.01 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201604 kb
Host smart-22ec5ec2-4550-443b-b654-1370ab7475b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60579959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors
.60579959
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.19057790
Short name T339
Test name
Test status
Simulation time 22188293065 ps
CPU time 55.59 seconds
Started Aug 02 04:54:20 PM PDT 24
Finished Aug 02 04:55:16 PM PDT 24
Peak memory 201644 kb
Host smart-5b0b5301-5047-4fd7-84ae-e4dc23da1133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19057790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_tl_intg_err.19057790
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3093754104
Short name T843
Test name
Test status
Simulation time 2042537107 ps
CPU time 6.39 seconds
Started Aug 02 04:54:19 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201496 kb
Host smart-94d9d981-64e3-4256-9cd5-9bd90e1e2940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093754104 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3093754104
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2057261055
Short name T294
Test name
Test status
Simulation time 2025478753 ps
CPU time 5.45 seconds
Started Aug 02 04:54:19 PM PDT 24
Finished Aug 02 04:54:24 PM PDT 24
Peak memory 201316 kb
Host smart-bc9cc340-a178-4145-9e52-d4b2062f8188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057261055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2057261055
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2146667185
Short name T903
Test name
Test status
Simulation time 2017518734 ps
CPU time 5.56 seconds
Started Aug 02 04:54:19 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201024 kb
Host smart-f36702ba-bd48-4e1c-9dcd-bba0a31dd598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146667185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.2146667185
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2688621020
Short name T913
Test name
Test status
Simulation time 7525752313 ps
CPU time 36.69 seconds
Started Aug 02 04:54:20 PM PDT 24
Finished Aug 02 04:54:57 PM PDT 24
Peak memory 201564 kb
Host smart-9fbd4dce-33d9-425c-9367-c0f992726113
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688621020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.2688621020
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2404304152
Short name T868
Test name
Test status
Simulation time 2255189251 ps
CPU time 3.05 seconds
Started Aug 02 04:54:22 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201648 kb
Host smart-6f595cf8-b1a9-4e1c-9d80-8a59707b6f67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404304152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.2404304152
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.545558856
Short name T338
Test name
Test status
Simulation time 22234825181 ps
CPU time 59.4 seconds
Started Aug 02 04:54:29 PM PDT 24
Finished Aug 02 04:55:28 PM PDT 24
Peak memory 201636 kb
Host smart-14290bc5-fc9c-4d86-b178-5d18cc8b2450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545558856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_tl_intg_err.545558856
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3535824267
Short name T299
Test name
Test status
Simulation time 3093164974 ps
CPU time 4.37 seconds
Started Aug 02 04:55:21 PM PDT 24
Finished Aug 02 04:55:25 PM PDT 24
Peak memory 201472 kb
Host smart-8383b5fc-316c-4f1e-a2eb-f7b15f10ae85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535824267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3535824267
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2900426730
Short name T842
Test name
Test status
Simulation time 40642564797 ps
CPU time 99.91 seconds
Started Aug 02 04:55:23 PM PDT 24
Finished Aug 02 04:57:03 PM PDT 24
Peak memory 201476 kb
Host smart-f90fe041-3ebd-4f62-a9c0-a7e228e4c4fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900426730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.2900426730
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3935345487
Short name T298
Test name
Test status
Simulation time 6045680518 ps
CPU time 4.53 seconds
Started Aug 02 04:54:08 PM PDT 24
Finished Aug 02 04:54:13 PM PDT 24
Peak memory 201360 kb
Host smart-2a2164cb-63f5-42a7-9c85-6c474a2f1f0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935345487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.3935345487
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1619591422
Short name T798
Test name
Test status
Simulation time 2045770517 ps
CPU time 5.9 seconds
Started Aug 02 04:54:07 PM PDT 24
Finished Aug 02 04:54:14 PM PDT 24
Peak memory 201408 kb
Host smart-c3985df5-833b-4808-9c68-e277111c6041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619591422 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1619591422
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3342895387
Short name T297
Test name
Test status
Simulation time 2057602756 ps
CPU time 5.7 seconds
Started Aug 02 04:54:10 PM PDT 24
Finished Aug 02 04:54:16 PM PDT 24
Peak memory 201256 kb
Host smart-012861dc-d738-46d4-bbeb-2ac754b17821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342895387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3342895387
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1929460744
Short name T876
Test name
Test status
Simulation time 2010996803 ps
CPU time 5.65 seconds
Started Aug 02 04:54:09 PM PDT 24
Finished Aug 02 04:54:14 PM PDT 24
Peak memory 201084 kb
Host smart-0d0b7490-eeeb-479c-80d6-d2c972000f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929460744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.1929460744
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1100572587
Short name T803
Test name
Test status
Simulation time 4802458084 ps
CPU time 13.71 seconds
Started Aug 02 04:54:08 PM PDT 24
Finished Aug 02 04:54:22 PM PDT 24
Peak memory 201504 kb
Host smart-555b5700-7f99-4a69-a9c0-a414bce89d7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100572587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.1100572587
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2069002057
Short name T251
Test name
Test status
Simulation time 2148092840 ps
CPU time 7.4 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:54:33 PM PDT 24
Peak memory 201876 kb
Host smart-16a0e9bf-fb4a-4342-ac7b-9d94402ffd70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069002057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.2069002057
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2450982533
Short name T822
Test name
Test status
Simulation time 2022463099 ps
CPU time 2.58 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201124 kb
Host smart-b1ca7058-534f-4e48-86bd-0fb861236e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450982533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2450982533
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3215706457
Short name T887
Test name
Test status
Simulation time 2015170612 ps
CPU time 5.58 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:33 PM PDT 24
Peak memory 201212 kb
Host smart-3fdfc5e9-ec99-4f44-908c-9ef7836eb2aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215706457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.3215706457
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4126113794
Short name T901
Test name
Test status
Simulation time 2010440160 ps
CPU time 5.92 seconds
Started Aug 02 04:54:22 PM PDT 24
Finished Aug 02 04:54:28 PM PDT 24
Peak memory 201224 kb
Host smart-57b90983-3c1e-497b-b65f-8e34535ae46a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126113794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.4126113794
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1043185212
Short name T906
Test name
Test status
Simulation time 2027190820 ps
CPU time 3.32 seconds
Started Aug 02 04:54:21 PM PDT 24
Finished Aug 02 04:54:25 PM PDT 24
Peak memory 201268 kb
Host smart-f7b40211-1b21-4742-b172-f30d1d26d66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043185212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.1043185212
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2836881351
Short name T797
Test name
Test status
Simulation time 2011817867 ps
CPU time 6.34 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 201128 kb
Host smart-b4c8513a-03c5-4365-aba7-c3f7eb06a38b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836881351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.2836881351
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2953512362
Short name T892
Test name
Test status
Simulation time 2024906446 ps
CPU time 1.89 seconds
Started Aug 02 04:54:36 PM PDT 24
Finished Aug 02 04:54:38 PM PDT 24
Peak memory 201188 kb
Host smart-92942ffa-adb8-4bbc-84ec-aa8bbafa7bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953512362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.2953512362
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3638496919
Short name T866
Test name
Test status
Simulation time 2029547998 ps
CPU time 2.51 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:31 PM PDT 24
Peak memory 201228 kb
Host smart-a7d30716-e8f3-40a5-bc09-85e6be448a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638496919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3638496919
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1461740352
Short name T900
Test name
Test status
Simulation time 2021143829 ps
CPU time 3.35 seconds
Started Aug 02 04:54:34 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 201044 kb
Host smart-7049b306-81b2-41dc-9c7e-39760896f716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461740352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.1461740352
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3556837578
Short name T880
Test name
Test status
Simulation time 2027905810 ps
CPU time 2.03 seconds
Started Aug 02 04:54:31 PM PDT 24
Finished Aug 02 04:54:33 PM PDT 24
Peak memory 201240 kb
Host smart-2d438a23-7032-4e3b-b272-27abe06a1dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556837578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.3556837578
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4265142742
Short name T808
Test name
Test status
Simulation time 2017218483 ps
CPU time 4.27 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:32 PM PDT 24
Peak memory 201164 kb
Host smart-74d1de79-1c4d-4c16-a537-ff0fe20744a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265142742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.4265142742
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.66123388
Short name T912
Test name
Test status
Simulation time 2676424259 ps
CPU time 5.04 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:19 PM PDT 24
Peak memory 201812 kb
Host smart-4d8e333a-a543-413c-9dff-c9564cf3a120
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66123388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_c
sr_aliasing.66123388
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.263526013
Short name T293
Test name
Test status
Simulation time 58581456886 ps
CPU time 29.62 seconds
Started Aug 02 04:54:04 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 201620 kb
Host smart-b8abda7c-8783-44d4-a092-c038c2ecd5fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263526013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_bit_bash.263526013
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3400558924
Short name T296
Test name
Test status
Simulation time 6048707110 ps
CPU time 8.84 seconds
Started Aug 02 04:54:07 PM PDT 24
Finished Aug 02 04:54:16 PM PDT 24
Peak memory 201496 kb
Host smart-42816bde-7edb-4237-be7d-c57660080b26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400558924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.3400558924
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2969234217
Short name T886
Test name
Test status
Simulation time 2073586301 ps
CPU time 6.68 seconds
Started Aug 02 04:54:06 PM PDT 24
Finished Aug 02 04:54:13 PM PDT 24
Peak memory 201628 kb
Host smart-b566a602-9f15-43e9-be91-378011181118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969234217 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2969234217
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3858961504
Short name T290
Test name
Test status
Simulation time 2139613635 ps
CPU time 1.39 seconds
Started Aug 02 04:54:07 PM PDT 24
Finished Aug 02 04:54:09 PM PDT 24
Peak memory 201364 kb
Host smart-78b0648d-a7bc-492a-94d3-8eba7951c991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858961504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.3858961504
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1912117904
Short name T796
Test name
Test status
Simulation time 2041050316 ps
CPU time 1.8 seconds
Started Aug 02 04:54:05 PM PDT 24
Finished Aug 02 04:54:07 PM PDT 24
Peak memory 201208 kb
Host smart-cd68869d-c301-45a3-957d-e8f39c0ea869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912117904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1912117904
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1142781385
Short name T857
Test name
Test status
Simulation time 7487851630 ps
CPU time 10.11 seconds
Started Aug 02 04:54:08 PM PDT 24
Finished Aug 02 04:54:18 PM PDT 24
Peak memory 201760 kb
Host smart-d4d9a27b-3576-4675-81c5-ea4dc049d0fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142781385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.1142781385
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3743002731
Short name T337
Test name
Test status
Simulation time 22454898592 ps
CPU time 14.83 seconds
Started Aug 02 04:54:16 PM PDT 24
Finished Aug 02 04:54:31 PM PDT 24
Peak memory 201796 kb
Host smart-f8baaf55-6eb9-4a33-9364-076b2cda5579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743002731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3743002731
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.475044943
Short name T828
Test name
Test status
Simulation time 2050863354 ps
CPU time 1.89 seconds
Started Aug 02 04:54:34 PM PDT 24
Finished Aug 02 04:54:36 PM PDT 24
Peak memory 201156 kb
Host smart-443aad68-7855-47cd-ab4b-4a8344083270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475044943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_tes
t.475044943
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3449697491
Short name T811
Test name
Test status
Simulation time 2044458008 ps
CPU time 1.95 seconds
Started Aug 02 04:54:32 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 201168 kb
Host smart-95159fc9-bc28-450e-bca9-2be727d2832c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449697491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.3449697491
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2825651159
Short name T826
Test name
Test status
Simulation time 2015318197 ps
CPU time 5.36 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 201132 kb
Host smart-04696e1c-f5f4-483f-a537-84fdef37cb3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825651159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.2825651159
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2579178453
Short name T840
Test name
Test status
Simulation time 2082687556 ps
CPU time 1.12 seconds
Started Aug 02 04:54:36 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 201104 kb
Host smart-474b4628-369b-491d-a25b-ed4031dd39e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579178453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2579178453
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.889909312
Short name T846
Test name
Test status
Simulation time 2012990791 ps
CPU time 5.58 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:32 PM PDT 24
Peak memory 201020 kb
Host smart-90f1f04f-5ad7-451e-a978-70b8d9d27d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889909312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_tes
t.889909312
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.133452538
Short name T902
Test name
Test status
Simulation time 2040109836 ps
CPU time 2 seconds
Started Aug 02 04:54:29 PM PDT 24
Finished Aug 02 04:54:31 PM PDT 24
Peak memory 201324 kb
Host smart-cd5b083c-4ca5-405f-a9ac-22d6813bd7f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133452538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_tes
t.133452538
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.771902720
Short name T893
Test name
Test status
Simulation time 2024620595 ps
CPU time 3.09 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:29 PM PDT 24
Peak memory 201212 kb
Host smart-6fb64f62-9b42-4045-95fb-3f990cec3b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771902720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_tes
t.771902720
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.4139495266
Short name T819
Test name
Test status
Simulation time 2023387324 ps
CPU time 3.22 seconds
Started Aug 02 04:54:33 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 201336 kb
Host smart-8fb44bdc-4bd4-4741-8420-aed6c2d7d491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139495266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.4139495266
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2162650025
Short name T799
Test name
Test status
Simulation time 2021355240 ps
CPU time 3.28 seconds
Started Aug 02 04:54:29 PM PDT 24
Finished Aug 02 04:54:33 PM PDT 24
Peak memory 201256 kb
Host smart-b4867a6a-83ca-4ec5-a164-14874bca6910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162650025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.2162650025
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.111492888
Short name T794
Test name
Test status
Simulation time 2010910501 ps
CPU time 5.95 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:32 PM PDT 24
Peak memory 201080 kb
Host smart-0906a0fd-d0b0-46c7-8821-6f0bd4cb9bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111492888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_tes
t.111492888
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1131265874
Short name T813
Test name
Test status
Simulation time 2679137740 ps
CPU time 9.28 seconds
Started Aug 02 04:54:05 PM PDT 24
Finished Aug 02 04:54:15 PM PDT 24
Peak memory 201692 kb
Host smart-c7e25338-48d2-41ad-96bc-32c48c769af1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131265874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.1131265874
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1059178110
Short name T292
Test name
Test status
Simulation time 40516911223 ps
CPU time 150.87 seconds
Started Aug 02 04:54:09 PM PDT 24
Finished Aug 02 04:56:40 PM PDT 24
Peak memory 201616 kb
Host smart-4911bf43-be5e-4d56-96e2-abf32f5c6b59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059178110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.1059178110
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.370832045
Short name T908
Test name
Test status
Simulation time 4013598736 ps
CPU time 10.93 seconds
Started Aug 02 04:54:05 PM PDT 24
Finished Aug 02 04:54:16 PM PDT 24
Peak memory 201400 kb
Host smart-e40a1ff3-cb41-41c1-b7ba-919277bf544e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370832045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.370832045
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2682455137
Short name T854
Test name
Test status
Simulation time 2044443045 ps
CPU time 6.12 seconds
Started Aug 02 04:54:12 PM PDT 24
Finished Aug 02 04:54:18 PM PDT 24
Peak memory 201428 kb
Host smart-2309bf1d-14a9-4038-9f26-77aa154d4053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682455137 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2682455137
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2577155514
Short name T295
Test name
Test status
Simulation time 2095757415 ps
CPU time 1.41 seconds
Started Aug 02 04:54:07 PM PDT 24
Finished Aug 02 04:54:09 PM PDT 24
Peak memory 201436 kb
Host smart-091dec9b-64cd-4ec4-b320-341af800e7c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577155514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.2577155514
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1381552529
Short name T910
Test name
Test status
Simulation time 2013245266 ps
CPU time 5.98 seconds
Started Aug 02 04:54:07 PM PDT 24
Finished Aug 02 04:54:13 PM PDT 24
Peak memory 201048 kb
Host smart-67a6dc69-0fb7-4a78-ba0a-9d13858838c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381552529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.1381552529
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.739322357
Short name T21
Test name
Test status
Simulation time 7575109413 ps
CPU time 12.93 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:27 PM PDT 24
Peak memory 201748 kb
Host smart-7e72bba1-4730-4c7a-a584-4f9fe8b7140d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739322357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
sysrst_ctrl_same_csr_outstanding.739322357
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2118787029
Short name T261
Test name
Test status
Simulation time 2727475272 ps
CPU time 2.86 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:17 PM PDT 24
Peak memory 201876 kb
Host smart-436dbca7-59a5-4137-bf03-f698e1d132da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118787029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.2118787029
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.442317278
Short name T916
Test name
Test status
Simulation time 22311371395 ps
CPU time 11.24 seconds
Started Aug 02 04:55:17 PM PDT 24
Finished Aug 02 04:55:29 PM PDT 24
Peak memory 201500 kb
Host smart-f2fa5aa3-6b1c-42a6-bf17-fb0ea0866144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442317278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_tl_intg_err.442317278
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1732840439
Short name T817
Test name
Test status
Simulation time 2032006406 ps
CPU time 1.83 seconds
Started Aug 02 04:54:26 PM PDT 24
Finished Aug 02 04:54:28 PM PDT 24
Peak memory 201020 kb
Host smart-6b9c6579-b9e5-47c2-a442-7b691b569ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732840439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1732840439
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3906420941
Short name T851
Test name
Test status
Simulation time 2014224523 ps
CPU time 6.12 seconds
Started Aug 02 04:54:32 PM PDT 24
Finished Aug 02 04:54:38 PM PDT 24
Peak memory 201216 kb
Host smart-7b2fa826-588f-4e64-a554-115de884e500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906420941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3906420941
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2170530399
Short name T800
Test name
Test status
Simulation time 2018140325 ps
CPU time 2.99 seconds
Started Aug 02 04:54:34 PM PDT 24
Finished Aug 02 04:54:37 PM PDT 24
Peak memory 201092 kb
Host smart-0d16828f-69b2-4904-8acd-bc4d4a5c5611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170530399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.2170530399
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3794134902
Short name T795
Test name
Test status
Simulation time 2012470856 ps
CPU time 5.27 seconds
Started Aug 02 04:54:29 PM PDT 24
Finished Aug 02 04:54:34 PM PDT 24
Peak memory 200956 kb
Host smart-dccfb50c-2c8a-4239-bf27-1c8d06711630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794134902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.3794134902
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1888468331
Short name T848
Test name
Test status
Simulation time 2014259754 ps
CPU time 5.85 seconds
Started Aug 02 04:54:29 PM PDT 24
Finished Aug 02 04:54:35 PM PDT 24
Peak memory 201376 kb
Host smart-19911dd7-650d-46b2-8a2e-cb44360de94e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888468331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.1888468331
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2610904003
Short name T914
Test name
Test status
Simulation time 2044959362 ps
CPU time 1.97 seconds
Started Aug 02 04:54:25 PM PDT 24
Finished Aug 02 04:54:27 PM PDT 24
Peak memory 201212 kb
Host smart-61e69c3c-8924-4355-8db9-acb047ca4709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610904003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.2610904003
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.155030783
Short name T815
Test name
Test status
Simulation time 2015006391 ps
CPU time 3.26 seconds
Started Aug 02 04:54:27 PM PDT 24
Finished Aug 02 04:54:31 PM PDT 24
Peak memory 201184 kb
Host smart-3386ed14-95e8-441b-888e-78862bbac740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155030783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_tes
t.155030783
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2326506740
Short name T847
Test name
Test status
Simulation time 2046161275 ps
CPU time 1.56 seconds
Started Aug 02 04:54:28 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201012 kb
Host smart-9462c5d4-0bf3-4f5a-9413-bfd774c294ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326506740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.2326506740
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2111603202
Short name T870
Test name
Test status
Simulation time 2046418616 ps
CPU time 1.51 seconds
Started Aug 02 04:54:34 PM PDT 24
Finished Aug 02 04:54:36 PM PDT 24
Peak memory 201208 kb
Host smart-f3443a82-32ef-4291-a6c4-6ddddc14b74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111603202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.2111603202
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3572912448
Short name T899
Test name
Test status
Simulation time 2126384763 ps
CPU time 0.95 seconds
Started Aug 02 04:54:29 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201040 kb
Host smart-72fbca03-f7f6-40fc-9d34-4ccc469b8b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572912448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.3572912448
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3795368825
Short name T864
Test name
Test status
Simulation time 2243970181 ps
CPU time 1.54 seconds
Started Aug 02 04:54:15 PM PDT 24
Finished Aug 02 04:54:17 PM PDT 24
Peak memory 201692 kb
Host smart-9b7b5cb1-c865-4adb-b587-e3fe8c97b163
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795368825 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3795368825
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.734478677
Short name T827
Test name
Test status
Simulation time 2031043379 ps
CPU time 5.56 seconds
Started Aug 02 04:54:13 PM PDT 24
Finished Aug 02 04:54:19 PM PDT 24
Peak memory 201324 kb
Host smart-bf86b6a8-5333-471d-a00c-1a141e1221e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734478677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw
.734478677
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.873221076
Short name T835
Test name
Test status
Simulation time 2007314404 ps
CPU time 5.67 seconds
Started Aug 02 04:54:13 PM PDT 24
Finished Aug 02 04:54:19 PM PDT 24
Peak memory 201004 kb
Host smart-4d948e4d-7c93-4602-9805-711d8b13c808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873221076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.873221076
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.805787021
Short name T865
Test name
Test status
Simulation time 5169381546 ps
CPU time 3.97 seconds
Started Aug 02 04:54:11 PM PDT 24
Finished Aug 02 04:54:16 PM PDT 24
Peak memory 201524 kb
Host smart-051cdc9a-112e-4052-a6ed-02b4c26e32d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805787021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
sysrst_ctrl_same_csr_outstanding.805787021
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1732440585
Short name T852
Test name
Test status
Simulation time 2089675881 ps
CPU time 7.04 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:21 PM PDT 24
Peak memory 201608 kb
Host smart-2593c063-2d05-4962-8750-cd619f905ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732440585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.1732440585
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3267114367
Short name T878
Test name
Test status
Simulation time 42366654211 ps
CPU time 60.27 seconds
Started Aug 02 04:54:24 PM PDT 24
Finished Aug 02 04:55:24 PM PDT 24
Peak memory 201608 kb
Host smart-95f051e6-9121-4e2a-baa4-07de58c37c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267114367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3267114367
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2071045960
Short name T829
Test name
Test status
Simulation time 2108504872 ps
CPU time 3.81 seconds
Started Aug 02 04:54:17 PM PDT 24
Finished Aug 02 04:54:21 PM PDT 24
Peak memory 201324 kb
Host smart-4608f3d9-a788-4965-9f1f-53316780c895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071045960 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2071045960
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.748009002
Short name T823
Test name
Test status
Simulation time 2122523205 ps
CPU time 2.11 seconds
Started Aug 02 04:54:15 PM PDT 24
Finished Aug 02 04:54:18 PM PDT 24
Peak memory 201352 kb
Host smart-9581b9bd-50d3-4f58-9ed2-59636aa69d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748009002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw
.748009002
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.813466075
Short name T839
Test name
Test status
Simulation time 2017862696 ps
CPU time 5.91 seconds
Started Aug 02 04:54:13 PM PDT 24
Finished Aug 02 04:54:19 PM PDT 24
Peak memory 201248 kb
Host smart-636e31fc-d8fb-4ddd-9dc6-64d49616e6a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813466075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test
.813466075
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1694944538
Short name T849
Test name
Test status
Simulation time 9728212081 ps
CPU time 24.25 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:39 PM PDT 24
Peak memory 201736 kb
Host smart-a782ac8a-4c1c-4fe8-98d6-54a53072d708
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694944538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.1694944538
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3405661397
Short name T894
Test name
Test status
Simulation time 2046435196 ps
CPU time 7.54 seconds
Started Aug 02 04:54:21 PM PDT 24
Finished Aug 02 04:54:29 PM PDT 24
Peak memory 201760 kb
Host smart-93ab3ad9-ffea-4ffe-966e-624c5a990826
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405661397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.3405661397
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3781305060
Short name T884
Test name
Test status
Simulation time 22447640336 ps
CPU time 14.6 seconds
Started Aug 02 04:54:15 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201696 kb
Host smart-37beb6b1-2e0a-45fd-8ce2-6233393823b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781305060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3781305060
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2078403997
Short name T818
Test name
Test status
Simulation time 2109143797 ps
CPU time 2.11 seconds
Started Aug 02 04:54:13 PM PDT 24
Finished Aug 02 04:54:15 PM PDT 24
Peak memory 201424 kb
Host smart-55d3ed87-a57d-4a7e-84c9-554db9ba4934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078403997 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2078403997
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2008573154
Short name T289
Test name
Test status
Simulation time 2131814691 ps
CPU time 2.24 seconds
Started Aug 02 04:54:21 PM PDT 24
Finished Aug 02 04:54:23 PM PDT 24
Peak memory 201296 kb
Host smart-7b3c1da4-dece-46bd-bd94-6d09ce2e445a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008573154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.2008573154
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2760506317
Short name T830
Test name
Test status
Simulation time 2044954745 ps
CPU time 1.98 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:16 PM PDT 24
Peak memory 201140 kb
Host smart-7614db46-f628-4685-9eec-728de287e374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760506317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.2760506317
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1646660289
Short name T871
Test name
Test status
Simulation time 9529791796 ps
CPU time 8.46 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:23 PM PDT 24
Peak memory 201608 kb
Host smart-49cfbdf3-58bd-4ed3-8ff9-94dfa8071cf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646660289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.1646660289
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1611044912
Short name T867
Test name
Test status
Simulation time 2304742129 ps
CPU time 3.23 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:18 PM PDT 24
Peak memory 201668 kb
Host smart-5237820f-be10-4357-ac00-43e7b5d15d99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611044912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1611044912
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.380210782
Short name T341
Test name
Test status
Simulation time 22203203680 ps
CPU time 55.28 seconds
Started Aug 02 04:54:16 PM PDT 24
Finished Aug 02 04:55:12 PM PDT 24
Peak memory 201588 kb
Host smart-f866ed7c-f6d3-48ee-9556-ed8971e82a64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380210782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_tl_intg_err.380210782
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2057884563
Short name T915
Test name
Test status
Simulation time 2115786238 ps
CPU time 2.53 seconds
Started Aug 02 04:54:13 PM PDT 24
Finished Aug 02 04:54:16 PM PDT 24
Peak memory 209796 kb
Host smart-133819e2-a8d0-4bf6-ac07-1e1ab03b0619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057884563 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2057884563
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1924057216
Short name T27
Test name
Test status
Simulation time 2060976229 ps
CPU time 2.16 seconds
Started Aug 02 04:54:16 PM PDT 24
Finished Aug 02 04:54:18 PM PDT 24
Peak memory 201208 kb
Host smart-c72ccca0-e916-450e-b52e-fa576787c2c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924057216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.1924057216
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.737389160
Short name T883
Test name
Test status
Simulation time 2014016346 ps
CPU time 5.92 seconds
Started Aug 02 04:54:15 PM PDT 24
Finished Aug 02 04:54:21 PM PDT 24
Peak memory 201228 kb
Host smart-faf4c3de-7f7a-4034-90bc-626f743b2015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737389160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test
.737389160
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.4008290681
Short name T22
Test name
Test status
Simulation time 4409417691 ps
CPU time 17.67 seconds
Started Aug 02 04:54:12 PM PDT 24
Finished Aug 02 04:54:30 PM PDT 24
Peak memory 201540 kb
Host smart-6ece981d-cd57-4806-bde4-108beaf47609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008290681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.4008290681
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1853672230
Short name T256
Test name
Test status
Simulation time 2409571739 ps
CPU time 4.36 seconds
Started Aug 02 04:54:16 PM PDT 24
Finished Aug 02 04:54:20 PM PDT 24
Peak memory 201544 kb
Host smart-73175b80-63e0-4aa6-b1c1-bff9541d212d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853672230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.1853672230
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1619316657
Short name T28
Test name
Test status
Simulation time 42791911400 ps
CPU time 33.21 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:47 PM PDT 24
Peak memory 201640 kb
Host smart-670d876c-98d3-4a91-8ed9-7ffd932dcc85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619316657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1619316657
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2062313682
Short name T896
Test name
Test status
Simulation time 2117861902 ps
CPU time 2.1 seconds
Started Aug 02 04:54:17 PM PDT 24
Finished Aug 02 04:54:19 PM PDT 24
Peak memory 201512 kb
Host smart-43eacc03-6e95-49f7-b537-7e0b9ebd9a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062313682 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2062313682
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.75249114
Short name T252
Test name
Test status
Simulation time 2043817096 ps
CPU time 2.84 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:54:17 PM PDT 24
Peak memory 201308 kb
Host smart-032cdf3f-f6bb-4fe8-bcfb-3cbd748155f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75249114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.75249114
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3032021601
Short name T807
Test name
Test status
Simulation time 2054010538 ps
CPU time 1.36 seconds
Started Aug 02 04:54:12 PM PDT 24
Finished Aug 02 04:54:14 PM PDT 24
Peak memory 201092 kb
Host smart-ffaa9e25-cee3-45aa-9c9b-3b80ada7bf19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032021601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.3032021601
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3083272703
Short name T804
Test name
Test status
Simulation time 10649921581 ps
CPU time 26.32 seconds
Started Aug 02 04:54:12 PM PDT 24
Finished Aug 02 04:54:39 PM PDT 24
Peak memory 201588 kb
Host smart-9150aaae-7b20-4c72-9a94-054d63f07406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083272703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.3083272703
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4289260140
Short name T879
Test name
Test status
Simulation time 2136042327 ps
CPU time 2.83 seconds
Started Aug 02 04:54:17 PM PDT 24
Finished Aug 02 04:54:20 PM PDT 24
Peak memory 201492 kb
Host smart-94d53bb4-146b-48a0-8cf1-79a2d7a7a7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289260140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.4289260140
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.532903191
Short name T888
Test name
Test status
Simulation time 22253823176 ps
CPU time 58.37 seconds
Started Aug 02 04:54:14 PM PDT 24
Finished Aug 02 04:55:13 PM PDT 24
Peak memory 201680 kb
Host smart-21902e67-06c8-4ee4-8ecd-71d6b66739e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532903191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_tl_intg_err.532903191
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.3344762583
Short name T280
Test name
Test status
Simulation time 2018529011 ps
CPU time 3.29 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 200720 kb
Host smart-3cdd4192-9d37-4451-ae3d-38e4ea539328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344762583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.3344762583
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.688226728
Short name T375
Test name
Test status
Simulation time 3799940524 ps
CPU time 2.98 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:55:48 PM PDT 24
Peak memory 200904 kb
Host smart-0ce09bbd-67bb-4334-9900-06ef254fb6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688226728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.688226728
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2154293774
Short name T98
Test name
Test status
Simulation time 51221391906 ps
CPU time 23.4 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 201072 kb
Host smart-1d99a5f3-5088-4169-b75b-efb3c3f08659
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154293774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.2154293774
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2656300273
Short name T205
Test name
Test status
Simulation time 2240225468 ps
CPU time 1.79 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:55:47 PM PDT 24
Peak memory 200848 kb
Host smart-84daac10-0409-4b1c-8ff9-e08c7c3afadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656300273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2656300273
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3423420534
Short name T659
Test name
Test status
Simulation time 2542440643 ps
CPU time 3.69 seconds
Started Aug 02 04:55:48 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 200720 kb
Host smart-5ad9e1a3-d73e-484c-884f-e26498e49ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423420534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3423420534
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1360373976
Short name T137
Test name
Test status
Simulation time 48430751549 ps
CPU time 11.95 seconds
Started Aug 02 04:55:43 PM PDT 24
Finished Aug 02 04:55:55 PM PDT 24
Peak memory 201148 kb
Host smart-bb466a78-c57f-4188-abd4-69d8dfaf0ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360373976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1360373976
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.198036976
Short name T507
Test name
Test status
Simulation time 4449450054 ps
CPU time 12.05 seconds
Started Aug 02 04:55:43 PM PDT 24
Finished Aug 02 04:55:55 PM PDT 24
Peak memory 200732 kb
Host smart-a313356f-e527-432a-b7c7-0446afc3f0b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198036976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ec_pwr_on_rst.198036976
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2460781654
Short name T465
Test name
Test status
Simulation time 3381034672 ps
CPU time 2.2 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 200816 kb
Host smart-fd94e8b5-b602-4663-a2f7-eb9a7e3d5feb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460781654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.2460781654
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2346256921
Short name T474
Test name
Test status
Simulation time 2615867402 ps
CPU time 3.63 seconds
Started Aug 02 04:55:43 PM PDT 24
Finished Aug 02 04:55:46 PM PDT 24
Peak memory 200652 kb
Host smart-649fbead-3a1f-47ba-a77f-3545ef70e74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346256921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.2346256921
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2524259149
Short name T438
Test name
Test status
Simulation time 2451401147 ps
CPU time 3.8 seconds
Started Aug 02 04:55:53 PM PDT 24
Finished Aug 02 04:55:56 PM PDT 24
Peak memory 200736 kb
Host smart-8831c6dd-7d7f-4d42-b014-aa12d98c7326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524259149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2524259149
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1628229299
Short name T377
Test name
Test status
Simulation time 2243271574 ps
CPU time 6.71 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 200752 kb
Host smart-90cbb9d0-ba39-4ef5-b7ed-d4d4b51437a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628229299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1628229299
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.986407074
Short name T601
Test name
Test status
Simulation time 2521020515 ps
CPU time 3.19 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:55:55 PM PDT 24
Peak memory 200848 kb
Host smart-5a3caaa4-75c5-49c3-95f4-5ac49bf18c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986407074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.986407074
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1822896914
Short name T247
Test name
Test status
Simulation time 22018706764 ps
CPU time 29.99 seconds
Started Aug 02 04:55:53 PM PDT 24
Finished Aug 02 04:56:23 PM PDT 24
Peak memory 220556 kb
Host smart-f6e28202-cd57-4f9f-b86b-71a39aad74c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822896914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1822896914
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2129855333
Short name T48
Test name
Test status
Simulation time 2112296434 ps
CPU time 5.76 seconds
Started Aug 02 04:55:45 PM PDT 24
Finished Aug 02 04:55:51 PM PDT 24
Peak memory 200776 kb
Host smart-c12a709b-44c3-4694-9b35-805ed958edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129855333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2129855333
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.3336200742
Short name T184
Test name
Test status
Simulation time 13257947217 ps
CPU time 21.42 seconds
Started Aug 02 04:55:48 PM PDT 24
Finished Aug 02 04:56:10 PM PDT 24
Peak memory 200820 kb
Host smart-ff6bded1-de65-40b5-993a-a724ea1d28fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336200742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.3336200742
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.668463987
Short name T112
Test name
Test status
Simulation time 3661819065 ps
CPU time 2.51 seconds
Started Aug 02 04:55:42 PM PDT 24
Finished Aug 02 04:55:45 PM PDT 24
Peak memory 200836 kb
Host smart-c2f31f29-c264-40bc-bf91-63161267483f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668463987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ultra_low_pwr.668463987
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.2013965520
Short name T461
Test name
Test status
Simulation time 2010865004 ps
CPU time 5.9 seconds
Started Aug 02 04:56:00 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 200712 kb
Host smart-492a5e11-1cca-4bae-b11a-919adba5f0d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013965520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.2013965520
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.39032493
Short name T136
Test name
Test status
Simulation time 3205704017 ps
CPU time 6.32 seconds
Started Aug 02 04:55:53 PM PDT 24
Finished Aug 02 04:56:00 PM PDT 24
Peak memory 200884 kb
Host smart-dc3e14b4-cbfe-4ae8-a95e-944d3c408af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39032493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.39032493
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2554310378
Short name T735
Test name
Test status
Simulation time 104287308525 ps
CPU time 36.09 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:56:26 PM PDT 24
Peak memory 201024 kb
Host smart-66fddb3a-92f0-47e6-af20-6dc00ae90ebe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554310378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.2554310378
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2220110019
Short name T681
Test name
Test status
Simulation time 2236274081 ps
CPU time 2.37 seconds
Started Aug 02 04:55:55 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 200776 kb
Host smart-b5782a6f-065a-4bb6-9059-0f5e33689635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220110019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2220110019
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.953332977
Short name T535
Test name
Test status
Simulation time 2499066052 ps
CPU time 6.38 seconds
Started Aug 02 04:55:53 PM PDT 24
Finished Aug 02 04:56:00 PM PDT 24
Peak memory 200704 kb
Host smart-bd11587a-7e2b-4706-91b5-a7f575dc5af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953332977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.953332977
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.68323751
Short name T382
Test name
Test status
Simulation time 2699332262 ps
CPU time 6.98 seconds
Started Aug 02 04:55:51 PM PDT 24
Finished Aug 02 04:55:58 PM PDT 24
Peak memory 200804 kb
Host smart-ab4ce4a4-6a39-4871-a777-d2f92c947924
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68323751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_ec_pwr_on_rst.68323751
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.312422612
Short name T135
Test name
Test status
Simulation time 5202904713 ps
CPU time 7.83 seconds
Started Aug 02 04:55:56 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 200740 kb
Host smart-03b16b5f-68a0-44d4-9495-7a269a26e601
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312422612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_edge_detect.312422612
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1407783750
Short name T597
Test name
Test status
Simulation time 2616863858 ps
CPU time 4 seconds
Started Aug 02 04:56:00 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 200708 kb
Host smart-4d0a40a5-4c71-4a7e-a9cd-6531f77127a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407783750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.1407783750
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3284276741
Short name T770
Test name
Test status
Simulation time 2463479540 ps
CPU time 2.1 seconds
Started Aug 02 04:55:49 PM PDT 24
Finished Aug 02 04:55:51 PM PDT 24
Peak memory 200808 kb
Host smart-8f4e237d-39f1-471c-b93a-970f592860ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284276741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3284276741
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1795899413
Short name T490
Test name
Test status
Simulation time 2123531853 ps
CPU time 1.97 seconds
Started Aug 02 04:55:49 PM PDT 24
Finished Aug 02 04:55:51 PM PDT 24
Peak memory 200684 kb
Host smart-687feecc-e1c7-4139-830d-adcddcb545ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795899413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1795899413
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1956603308
Short name T486
Test name
Test status
Simulation time 2527051082 ps
CPU time 2.24 seconds
Started Aug 02 04:55:53 PM PDT 24
Finished Aug 02 04:55:56 PM PDT 24
Peak memory 200836 kb
Host smart-fc40d15e-fc49-46f7-865c-faa8aa74c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956603308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1956603308
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3384384975
Short name T263
Test name
Test status
Simulation time 42024949498 ps
CPU time 54.79 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:58 PM PDT 24
Peak memory 220196 kb
Host smart-7452824b-4a37-4d65-afec-a844b8fffea0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384384975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.3384384975
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.3427954577
Short name T442
Test name
Test status
Simulation time 2111942627 ps
CPU time 5.4 seconds
Started Aug 02 04:56:00 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 200636 kb
Host smart-eaef09ea-96cc-4879-824c-bc093a20be9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427954577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.3427954577
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.3940246109
Short name T36
Test name
Test status
Simulation time 142959486929 ps
CPU time 87.43 seconds
Started Aug 02 04:55:51 PM PDT 24
Finished Aug 02 04:57:19 PM PDT 24
Peak memory 200808 kb
Host smart-551d5d96-9d31-4aad-ab5f-3ed04b3713a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940246109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.3940246109
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.4144433020
Short name T207
Test name
Test status
Simulation time 48223822966 ps
CPU time 26.99 seconds
Started Aug 02 04:56:01 PM PDT 24
Finished Aug 02 04:56:28 PM PDT 24
Peak memory 209440 kb
Host smart-2642d3ba-da74-4133-8572-4eed7dd08b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144433020 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.4144433020
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3604209785
Short name T580
Test name
Test status
Simulation time 2660926202 ps
CPU time 1.54 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:55:54 PM PDT 24
Peak memory 200868 kb
Host smart-384ea241-4049-4f6f-8374-4fce776d80d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604209785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.3604209785
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.3973715487
Short name T159
Test name
Test status
Simulation time 2031682377 ps
CPU time 1.88 seconds
Started Aug 02 04:56:17 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200764 kb
Host smart-8968aed5-ea6a-4766-834e-dd25d3e12297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973715487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.3973715487
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.162476603
Short name T634
Test name
Test status
Simulation time 3196293624 ps
CPU time 4.68 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:16 PM PDT 24
Peak memory 200828 kb
Host smart-32b46697-eed6-494b-9021-ddb135926dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162476603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.162476603
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.2562841219
Short name T104
Test name
Test status
Simulation time 118974633417 ps
CPU time 62.51 seconds
Started Aug 02 04:56:14 PM PDT 24
Finished Aug 02 04:57:17 PM PDT 24
Peak memory 201044 kb
Host smart-95e938bc-d025-4a6b-a059-d0f8ae404367
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562841219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.2562841219
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2680208807
Short name T324
Test name
Test status
Simulation time 132299764194 ps
CPU time 64.41 seconds
Started Aug 02 04:56:10 PM PDT 24
Finished Aug 02 04:57:15 PM PDT 24
Peak memory 201164 kb
Host smart-7ee97be5-3592-4431-95b9-3370e93c9d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680208807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.2680208807
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2917338543
Short name T532
Test name
Test status
Simulation time 4807034372 ps
CPU time 12.48 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:24 PM PDT 24
Peak memory 200776 kb
Host smart-410b3545-ab92-4ad4-a947-942eeedebf8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917338543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.2917338543
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.838821780
Short name T758
Test name
Test status
Simulation time 2525925731 ps
CPU time 2.02 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 200864 kb
Host smart-885ee171-cf8d-4217-9b80-488b355b8b1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838821780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctr
l_edge_detect.838821780
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3274155314
Short name T283
Test name
Test status
Simulation time 2612693073 ps
CPU time 4.07 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:16 PM PDT 24
Peak memory 200696 kb
Host smart-e08c613f-3e8a-427e-bb19-e776851a5d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274155314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.3274155314
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3493029287
Short name T273
Test name
Test status
Simulation time 2470408580 ps
CPU time 6.95 seconds
Started Aug 02 04:56:13 PM PDT 24
Finished Aug 02 04:56:20 PM PDT 24
Peak memory 200772 kb
Host smart-e1678743-886c-494f-ada8-73855b1d3b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493029287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.3493029287
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3162100253
Short name T286
Test name
Test status
Simulation time 2144136895 ps
CPU time 6.23 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:17 PM PDT 24
Peak memory 200672 kb
Host smart-90ad1a87-a6ed-4019-91d5-a8c1b12acb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162100253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3162100253
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2941260807
Short name T566
Test name
Test status
Simulation time 2511958472 ps
CPU time 6.95 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200716 kb
Host smart-7d9a0ae9-2bbd-4cf1-a6c5-2d69a81698ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941260807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.2941260807
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.222610361
Short name T187
Test name
Test status
Simulation time 2127137158 ps
CPU time 1.97 seconds
Started Aug 02 04:56:13 PM PDT 24
Finished Aug 02 04:56:15 PM PDT 24
Peak memory 200724 kb
Host smart-043d4435-f9e2-4464-aa09-802895e4ec95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222610361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.222610361
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.3098201266
Short name T716
Test name
Test status
Simulation time 106962678393 ps
CPU time 253.95 seconds
Started Aug 02 04:56:14 PM PDT 24
Finished Aug 02 05:00:29 PM PDT 24
Peak memory 200812 kb
Host smart-d45c5c06-9cac-490a-8bcf-c7f86e6d3ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098201266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.3098201266
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3480518411
Short name T185
Test name
Test status
Simulation time 39242952189 ps
CPU time 17.73 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:29 PM PDT 24
Peak memory 209368 kb
Host smart-6e9d2a6b-c658-479e-bcaa-261eda728b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480518411 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.3480518411
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.2615311667
Short name T663
Test name
Test status
Simulation time 2012149409 ps
CPU time 5.74 seconds
Started Aug 02 04:56:20 PM PDT 24
Finished Aug 02 04:56:25 PM PDT 24
Peak memory 200816 kb
Host smart-0f2d75f3-efec-4041-9a11-686aa73c1a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615311667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.2615311667
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.389738584
Short name T762
Test name
Test status
Simulation time 3427608540 ps
CPU time 5.07 seconds
Started Aug 02 04:56:21 PM PDT 24
Finished Aug 02 04:56:27 PM PDT 24
Peak memory 200872 kb
Host smart-5f411a06-2c67-4582-abf6-4083bdbcf358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389738584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.389738584
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.663374043
Short name T158
Test name
Test status
Simulation time 177980424643 ps
CPU time 471.41 seconds
Started Aug 02 04:56:20 PM PDT 24
Finished Aug 02 05:04:11 PM PDT 24
Peak memory 201072 kb
Host smart-605bcda1-d71f-4bbf-831b-6789f47f6c4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663374043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_combo_detect.663374043
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.487779722
Short name T330
Test name
Test status
Simulation time 128595651896 ps
CPU time 348.3 seconds
Started Aug 02 04:56:18 PM PDT 24
Finished Aug 02 05:02:06 PM PDT 24
Peak memory 201052 kb
Host smart-9864170e-1aa5-40b0-a624-e528ed9592b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487779722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_wi
th_pre_cond.487779722
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2721432208
Short name T358
Test name
Test status
Simulation time 4366850109 ps
CPU time 3.13 seconds
Started Aug 02 04:56:18 PM PDT 24
Finished Aug 02 04:56:21 PM PDT 24
Peak memory 200836 kb
Host smart-96e74a7d-11e8-4708-81d9-b1c808dd2e86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721432208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.2721432208
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.2950862101
Short name T34
Test name
Test status
Simulation time 3086718789 ps
CPU time 2.16 seconds
Started Aug 02 04:56:21 PM PDT 24
Finished Aug 02 04:56:23 PM PDT 24
Peak memory 200844 kb
Host smart-47788ebc-c3f9-46a1-9d5e-a0fc4ce952ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950862101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.2950862101
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1260698418
Short name T779
Test name
Test status
Simulation time 2670589453 ps
CPU time 1.25 seconds
Started Aug 02 04:56:15 PM PDT 24
Finished Aug 02 04:56:17 PM PDT 24
Peak memory 200840 kb
Host smart-304b908c-2a91-4454-93d4-664adc093644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260698418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1260698418
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1830954872
Short name T466
Test name
Test status
Simulation time 2452020875 ps
CPU time 5.14 seconds
Started Aug 02 04:56:17 PM PDT 24
Finished Aug 02 04:56:23 PM PDT 24
Peak memory 200704 kb
Host smart-cbbf130d-7f21-464b-9c46-7a4bc30d7afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830954872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1830954872
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.4054802289
Short name T765
Test name
Test status
Simulation time 2031899448 ps
CPU time 3.12 seconds
Started Aug 02 04:56:18 PM PDT 24
Finished Aug 02 04:56:22 PM PDT 24
Peak memory 200728 kb
Host smart-648b0d38-b8b5-461a-ad11-6863aeca69ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054802289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.4054802289
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2894318650
Short name T414
Test name
Test status
Simulation time 2548800989 ps
CPU time 1.56 seconds
Started Aug 02 04:56:17 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200748 kb
Host smart-0deb281f-0b44-47d6-b0ea-8e5d92a3650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894318650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2894318650
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.2814905445
Short name T701
Test name
Test status
Simulation time 2111931764 ps
CPU time 5.79 seconds
Started Aug 02 04:56:20 PM PDT 24
Finished Aug 02 04:56:26 PM PDT 24
Peak memory 200764 kb
Host smart-3f2f3213-30ae-44c1-8469-9e16031cf23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814905445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2814905445
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.2839013562
Short name T80
Test name
Test status
Simulation time 4059066972 ps
CPU time 6.07 seconds
Started Aug 02 04:56:18 PM PDT 24
Finished Aug 02 04:56:24 PM PDT 24
Peak memory 200868 kb
Host smart-9094ef86-ae10-4d6e-bbc8-d25e25a0387c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839013562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.2839013562
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.4139994154
Short name T781
Test name
Test status
Simulation time 2033958533 ps
CPU time 1.93 seconds
Started Aug 02 04:56:18 PM PDT 24
Finished Aug 02 04:56:20 PM PDT 24
Peak memory 200840 kb
Host smart-7257ec63-a592-4181-aab5-c87e30fc6640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139994154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.4139994154
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3219228705
Short name T264
Test name
Test status
Simulation time 3665039785 ps
CPU time 10.37 seconds
Started Aug 02 04:56:18 PM PDT 24
Finished Aug 02 04:56:29 PM PDT 24
Peak memory 200772 kb
Host smart-010404b9-bbfb-4fd5-8498-a57e002e6893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219228705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3
219228705
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.823974754
Short name T713
Test name
Test status
Simulation time 132189534650 ps
CPU time 83.81 seconds
Started Aug 02 04:56:22 PM PDT 24
Finished Aug 02 04:57:46 PM PDT 24
Peak memory 201000 kb
Host smart-62ac6862-cb85-42c3-9421-0a46caf785a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823974754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_combo_detect.823974754
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.289349825
Short name T143
Test name
Test status
Simulation time 3810612671 ps
CPU time 10.03 seconds
Started Aug 02 04:56:16 PM PDT 24
Finished Aug 02 04:56:27 PM PDT 24
Peak memory 200656 kb
Host smart-e6341b4b-717a-48b1-bd8d-b9623bed985d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289349825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ec_pwr_on_rst.289349825
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.966778992
Short name T108
Test name
Test status
Simulation time 223237325862 ps
CPU time 5.14 seconds
Started Aug 02 04:56:17 PM PDT 24
Finished Aug 02 04:56:22 PM PDT 24
Peak memory 200788 kb
Host smart-1e803d0f-94c4-4908-9507-9892c76b9e2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966778992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctr
l_edge_detect.966778992
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.948972661
Short name T376
Test name
Test status
Simulation time 2614400419 ps
CPU time 6.85 seconds
Started Aug 02 04:56:17 PM PDT 24
Finished Aug 02 04:56:24 PM PDT 24
Peak memory 200768 kb
Host smart-1fbf4cc1-0671-46e2-85bd-8ef17d5174cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948972661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.948972661
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2436470474
Short name T699
Test name
Test status
Simulation time 2470082415 ps
CPU time 7.51 seconds
Started Aug 02 04:56:18 PM PDT 24
Finished Aug 02 04:56:25 PM PDT 24
Peak memory 200804 kb
Host smart-13fe486f-52a2-49b8-a722-f05edc4155b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436470474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2436470474
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.570692302
Short name T518
Test name
Test status
Simulation time 2219136876 ps
CPU time 5.31 seconds
Started Aug 02 04:56:20 PM PDT 24
Finished Aug 02 04:56:25 PM PDT 24
Peak memory 200816 kb
Host smart-77917412-0c63-4cd8-a230-ebdf86fcb421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570692302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.570692302
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1889107369
Short name T453
Test name
Test status
Simulation time 2516682438 ps
CPU time 3.92 seconds
Started Aug 02 04:56:20 PM PDT 24
Finished Aug 02 04:56:24 PM PDT 24
Peak memory 200780 kb
Host smart-e66c2dd9-aab0-4930-bbc1-76eb2e8b6923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889107369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1889107369
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.3230334209
Short name T767
Test name
Test status
Simulation time 2113106821 ps
CPU time 5.75 seconds
Started Aug 02 04:56:19 PM PDT 24
Finished Aug 02 04:56:25 PM PDT 24
Peak memory 200768 kb
Host smart-d81328e5-9346-40e3-8c83-38fe1a349775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230334209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.3230334209
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3938980803
Short name T123
Test name
Test status
Simulation time 65650936447 ps
CPU time 43.57 seconds
Started Aug 02 04:56:16 PM PDT 24
Finished Aug 02 04:57:00 PM PDT 24
Peak memory 209284 kb
Host smart-87b5a55b-df34-48ff-b428-4df6a8ac6163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938980803 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3938980803
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2856586596
Short name T685
Test name
Test status
Simulation time 5923876739 ps
CPU time 2.1 seconds
Started Aug 02 04:56:18 PM PDT 24
Finished Aug 02 04:56:20 PM PDT 24
Peak memory 200948 kb
Host smart-b8bff092-9436-43ed-a058-046b174edb68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856586596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.2856586596
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.1574816866
Short name T527
Test name
Test status
Simulation time 2013960824 ps
CPU time 5.49 seconds
Started Aug 02 04:56:24 PM PDT 24
Finished Aug 02 04:56:30 PM PDT 24
Peak memory 200732 kb
Host smart-7de973e7-6973-44cb-be2d-a49dd1c3ac2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574816866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.1574816866
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1174102321
Short name T285
Test name
Test status
Simulation time 3571029602 ps
CPU time 3.02 seconds
Started Aug 02 04:56:26 PM PDT 24
Finished Aug 02 04:56:29 PM PDT 24
Peak memory 200840 kb
Host smart-1da74008-0c1a-4055-9db4-6dbc56ccd4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174102321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1
174102321
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3056736545
Short name T727
Test name
Test status
Simulation time 36840417671 ps
CPU time 25.27 seconds
Started Aug 02 04:56:25 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 200948 kb
Host smart-6921e40d-db43-43df-bfb0-bd66b23dd392
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056736545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.3056736545
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1360307037
Short name T389
Test name
Test status
Simulation time 4279568744 ps
CPU time 3.33 seconds
Started Aug 02 04:56:26 PM PDT 24
Finished Aug 02 04:56:30 PM PDT 24
Peak memory 200764 kb
Host smart-e1262690-1b4e-4e3f-9cdf-b6d12364e100
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360307037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1360307037
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3758800276
Short name T578
Test name
Test status
Simulation time 2627270013 ps
CPU time 2.3 seconds
Started Aug 02 04:56:28 PM PDT 24
Finished Aug 02 04:56:30 PM PDT 24
Peak memory 200752 kb
Host smart-894a3692-e0ca-4f8c-ba12-a5f5b6362f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758800276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.3758800276
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.4130646719
Short name T203
Test name
Test status
Simulation time 2478171570 ps
CPU time 2.36 seconds
Started Aug 02 04:56:17 PM PDT 24
Finished Aug 02 04:56:20 PM PDT 24
Peak memory 200708 kb
Host smart-c057bddc-c15a-459a-87a9-4383c4a68e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130646719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.4130646719
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.482366285
Short name T372
Test name
Test status
Simulation time 2213589957 ps
CPU time 6.16 seconds
Started Aug 02 04:56:23 PM PDT 24
Finished Aug 02 04:56:30 PM PDT 24
Peak memory 200680 kb
Host smart-22a0df70-76f9-427c-9de4-66af7a9a77ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482366285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.482366285
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.2744804866
Short name T528
Test name
Test status
Simulation time 2541133990 ps
CPU time 1.98 seconds
Started Aug 02 04:56:24 PM PDT 24
Finished Aug 02 04:56:26 PM PDT 24
Peak memory 200684 kb
Host smart-ce6591e7-6856-4912-a38e-e08b11c1b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744804866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.2744804866
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.333366606
Short name T449
Test name
Test status
Simulation time 2117527901 ps
CPU time 3.49 seconds
Started Aug 02 04:56:20 PM PDT 24
Finished Aug 02 04:56:24 PM PDT 24
Peak memory 200624 kb
Host smart-579df5e3-377d-40ee-a964-c3913a9d37d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333366606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.333366606
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2312305965
Short name T267
Test name
Test status
Simulation time 20081800754 ps
CPU time 41.96 seconds
Started Aug 02 04:56:28 PM PDT 24
Finished Aug 02 04:57:10 PM PDT 24
Peak memory 210384 kb
Host smart-941816f8-ec13-438f-b3b2-b5953fdecd7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312305965 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.2312305965
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1026635288
Short name T744
Test name
Test status
Simulation time 3007837444 ps
CPU time 4.23 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:31 PM PDT 24
Peak memory 200772 kb
Host smart-bcb3dd91-c22a-4dc8-a115-15c783a67c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026635288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
026635288
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.468449460
Short name T615
Test name
Test status
Simulation time 119691749760 ps
CPU time 18.93 seconds
Started Aug 02 04:56:23 PM PDT 24
Finished Aug 02 04:56:43 PM PDT 24
Peak memory 201052 kb
Host smart-bdd2767a-7d1e-4b1c-9b56-e736392f08f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468449460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_combo_detect.468449460
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1909724895
Short name T444
Test name
Test status
Simulation time 2797485145 ps
CPU time 2.67 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:30 PM PDT 24
Peak memory 200780 kb
Host smart-3b98f221-cdcf-4040-9b58-b1d6f3f894df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909724895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.1909724895
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.4012092407
Short name T635
Test name
Test status
Simulation time 2765991690 ps
CPU time 1.05 seconds
Started Aug 02 04:56:25 PM PDT 24
Finished Aug 02 04:56:26 PM PDT 24
Peak memory 200652 kb
Host smart-bd3e84c3-5ab1-4054-93a9-b2f936cce034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012092407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.4012092407
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3376768366
Short name T456
Test name
Test status
Simulation time 2463556733 ps
CPU time 7.51 seconds
Started Aug 02 04:56:25 PM PDT 24
Finished Aug 02 04:56:33 PM PDT 24
Peak memory 200812 kb
Host smart-b69cee24-d47c-4f94-b80e-3b618d678559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376768366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3376768366
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.1478973026
Short name T426
Test name
Test status
Simulation time 2233702014 ps
CPU time 5.89 seconds
Started Aug 02 04:56:24 PM PDT 24
Finished Aug 02 04:56:30 PM PDT 24
Peak memory 200756 kb
Host smart-3c8b2ac3-b349-4b1b-9e92-e93c7dc60706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478973026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.1478973026
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.3834734866
Short name T480
Test name
Test status
Simulation time 2528320636 ps
CPU time 2.29 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:29 PM PDT 24
Peak memory 200788 kb
Host smart-7b48e03e-6fbf-497f-98dc-296fc344cdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834734866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.3834734866
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.348182420
Short name T647
Test name
Test status
Simulation time 2113284065 ps
CPU time 6.15 seconds
Started Aug 02 04:56:25 PM PDT 24
Finished Aug 02 04:56:31 PM PDT 24
Peak memory 200636 kb
Host smart-1892267c-a685-4775-b628-6c8047fa5565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348182420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.348182420
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.3279321653
Short name T32
Test name
Test status
Simulation time 153475210517 ps
CPU time 96.03 seconds
Started Aug 02 04:56:23 PM PDT 24
Finished Aug 02 04:58:00 PM PDT 24
Peak memory 200964 kb
Host smart-999efd00-e4fb-4649-ae47-829c3a60a2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279321653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.3279321653
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1565578397
Short name T117
Test name
Test status
Simulation time 78445679421 ps
CPU time 46.62 seconds
Started Aug 02 04:56:25 PM PDT 24
Finished Aug 02 04:57:11 PM PDT 24
Peak memory 209404 kb
Host smart-92713029-297d-4598-b4a3-ad972a03416a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565578397 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1565578397
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3770807691
Short name T126
Test name
Test status
Simulation time 3637754660 ps
CPU time 6.73 seconds
Started Aug 02 04:56:25 PM PDT 24
Finished Aug 02 04:56:32 PM PDT 24
Peak memory 200776 kb
Host smart-ae6ac701-e18e-44f1-9cfc-bd377b07be94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770807691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.3770807691
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.3921884200
Short name T624
Test name
Test status
Simulation time 2018434799 ps
CPU time 2.92 seconds
Started Aug 02 04:56:24 PM PDT 24
Finished Aug 02 04:56:27 PM PDT 24
Peak memory 200804 kb
Host smart-bb15add9-d80a-433c-a5c3-cfbbccd6f8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921884200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.3921884200
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1597452784
Short name T529
Test name
Test status
Simulation time 3393140029 ps
CPU time 2.69 seconds
Started Aug 02 04:56:26 PM PDT 24
Finished Aug 02 04:56:29 PM PDT 24
Peak memory 200920 kb
Host smart-27afdf00-d8d4-4ff3-82b6-5392579dfc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597452784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.1
597452784
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.923472770
Short name T232
Test name
Test status
Simulation time 104366025545 ps
CPU time 273.65 seconds
Started Aug 02 04:56:23 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 201096 kb
Host smart-0eb0e7de-a295-4b0c-abbb-baa8e0f55222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923472770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_combo_detect.923472770
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3215896140
Short name T639
Test name
Test status
Simulation time 2639940705 ps
CPU time 4.18 seconds
Started Aug 02 04:56:26 PM PDT 24
Finished Aug 02 04:56:31 PM PDT 24
Peak memory 200708 kb
Host smart-eb949f96-cc9e-4e4a-92e3-4c0af8441727
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215896140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.3215896140
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3320084821
Short name T271
Test name
Test status
Simulation time 6007475243 ps
CPU time 2.59 seconds
Started Aug 02 04:56:23 PM PDT 24
Finished Aug 02 04:56:26 PM PDT 24
Peak memory 200868 kb
Host smart-d1b0bc24-a244-4527-b6fe-fb4765b73ef0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320084821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.3320084821
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3832118857
Short name T678
Test name
Test status
Simulation time 2609836605 ps
CPU time 6.98 seconds
Started Aug 02 04:56:28 PM PDT 24
Finished Aug 02 04:56:35 PM PDT 24
Peak memory 200752 kb
Host smart-c955febc-2771-42f6-87f5-c9d2f7534a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832118857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.3832118857
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2125536374
Short name T583
Test name
Test status
Simulation time 2466980682 ps
CPU time 5.1 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:33 PM PDT 24
Peak memory 200752 kb
Host smart-512478e5-a7c1-4c6e-a188-bfb0842a7836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125536374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2125536374
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3057802312
Short name T610
Test name
Test status
Simulation time 2125325236 ps
CPU time 6.06 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:33 PM PDT 24
Peak memory 200676 kb
Host smart-bd2f8aaa-fac0-46f4-a613-043470918098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057802312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3057802312
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2720653141
Short name T683
Test name
Test status
Simulation time 2512408187 ps
CPU time 6.63 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:34 PM PDT 24
Peak memory 200876 kb
Host smart-24a43f87-5ae1-4dfe-a322-910d489e4a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720653141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2720653141
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.532821692
Short name T138
Test name
Test status
Simulation time 2113179423 ps
CPU time 6.18 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:33 PM PDT 24
Peak memory 200740 kb
Host smart-293cdcfd-20b6-4709-b04f-7f5754b1888f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532821692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.532821692
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2724061044
Short name T268
Test name
Test status
Simulation time 47227276565 ps
CPU time 119.29 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:58:27 PM PDT 24
Peak memory 209408 kb
Host smart-92a9695e-9e25-4fd2-ba4a-2eb7960d58f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724061044 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2724061044
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.164647522
Short name T777
Test name
Test status
Simulation time 265609443548 ps
CPU time 90.31 seconds
Started Aug 02 04:56:28 PM PDT 24
Finished Aug 02 04:57:59 PM PDT 24
Peak memory 200836 kb
Host smart-7e8c2ba8-102d-45b9-af81-81e6a453872b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164647522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ultra_low_pwr.164647522
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.4129569646
Short name T696
Test name
Test status
Simulation time 2014525311 ps
CPU time 5.86 seconds
Started Aug 02 04:56:39 PM PDT 24
Finished Aug 02 04:56:45 PM PDT 24
Peak memory 200708 kb
Host smart-c0079c00-fc12-4f52-99f3-7bf0df1d7965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129569646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.4129569646
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2576332862
Short name T423
Test name
Test status
Simulation time 3228086345 ps
CPU time 2.35 seconds
Started Aug 02 04:56:33 PM PDT 24
Finished Aug 02 04:56:36 PM PDT 24
Peak memory 200808 kb
Host smart-e0142f05-fa27-4713-9496-e6b4740e09bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576332862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.2
576332862
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.253171123
Short name T204
Test name
Test status
Simulation time 99862624213 ps
CPU time 243.9 seconds
Started Aug 02 04:56:38 PM PDT 24
Finished Aug 02 05:00:42 PM PDT 24
Peak memory 201040 kb
Host smart-ddb0ef5b-20b9-42a8-8938-1a1149bf1911
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253171123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_combo_detect.253171123
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3270196196
Short name T47
Test name
Test status
Simulation time 3211349470 ps
CPU time 2.05 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:37 PM PDT 24
Peak memory 200704 kb
Host smart-bcd89c49-d82f-4791-961c-0ea0b0d68217
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270196196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.3270196196
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.2222943492
Short name T164
Test name
Test status
Simulation time 3463257721 ps
CPU time 4.06 seconds
Started Aug 02 04:56:33 PM PDT 24
Finished Aug 02 04:56:37 PM PDT 24
Peak memory 200904 kb
Host smart-79d9d35f-e622-41ac-9633-e2b5506e1138
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222943492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.2222943492
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.423048631
Short name T702
Test name
Test status
Simulation time 2613860471 ps
CPU time 6.26 seconds
Started Aug 02 04:56:33 PM PDT 24
Finished Aug 02 04:56:39 PM PDT 24
Peak memory 200752 kb
Host smart-798f666f-ae89-494b-b74f-b11df3ef9a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423048631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.423048631
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.4100949821
Short name T515
Test name
Test status
Simulation time 2453734103 ps
CPU time 6.81 seconds
Started Aug 02 04:56:27 PM PDT 24
Finished Aug 02 04:56:34 PM PDT 24
Peak memory 200876 kb
Host smart-297cd90d-4acf-47e1-bd40-481a883e1bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100949821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.4100949821
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2071967681
Short name T211
Test name
Test status
Simulation time 2044987854 ps
CPU time 1.41 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:35 PM PDT 24
Peak memory 200740 kb
Host smart-8135e776-2eff-47a3-b1bb-11a582dd87f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071967681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.2071967681
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2909225754
Short name T775
Test name
Test status
Simulation time 2520702902 ps
CPU time 3.88 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:39 PM PDT 24
Peak memory 200876 kb
Host smart-8919dc96-ab2e-45d6-a142-75c5de572415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909225754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2909225754
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.4172427902
Short name T391
Test name
Test status
Simulation time 2256258085 ps
CPU time 0.88 seconds
Started Aug 02 04:56:25 PM PDT 24
Finished Aug 02 04:56:26 PM PDT 24
Peak memory 200696 kb
Host smart-e1726a64-c0d4-4f78-b41f-67e36febc323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172427902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.4172427902
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.3951238094
Short name T6
Test name
Test status
Simulation time 11545125541 ps
CPU time 28.43 seconds
Started Aug 02 04:56:33 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200788 kb
Host smart-23b4e1c0-8813-4a12-88aa-29bd76cc3518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951238094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.3951238094
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.387669146
Short name T99
Test name
Test status
Simulation time 48940094535 ps
CPU time 121.3 seconds
Started Aug 02 04:56:36 PM PDT 24
Finished Aug 02 04:58:37 PM PDT 24
Peak memory 209464 kb
Host smart-e701121f-529f-41a8-99e1-89b9fb235d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387669146 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.387669146
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1798830771
Short name T617
Test name
Test status
Simulation time 7003972569 ps
CPU time 2.38 seconds
Started Aug 02 04:56:37 PM PDT 24
Finished Aug 02 04:56:40 PM PDT 24
Peak memory 200828 kb
Host smart-7a05710e-7a00-4054-8d50-afbf65aece85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798830771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.1798830771
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.2565654063
Short name T373
Test name
Test status
Simulation time 2109697105 ps
CPU time 0.85 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:36 PM PDT 24
Peak memory 200688 kb
Host smart-e047ad36-9fa9-490e-8d62-fb95b41f737f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565654063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.2565654063
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.3197465497
Short name T239
Test name
Test status
Simulation time 43595628669 ps
CPU time 26.56 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:57:01 PM PDT 24
Peak memory 201080 kb
Host smart-6193d075-9a00-4a3b-85d6-40ea68742b4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197465497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.3197465497
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.491458987
Short name T722
Test name
Test status
Simulation time 27849548731 ps
CPU time 18.05 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:52 PM PDT 24
Peak memory 201152 kb
Host smart-5132f66d-07f2-44c0-9cab-a5f913538018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491458987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_wi
th_pre_cond.491458987
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1014675954
Short name T501
Test name
Test status
Simulation time 4431521690 ps
CPU time 1.14 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:36 PM PDT 24
Peak memory 200836 kb
Host smart-b7ff4754-4ece-455a-b90c-ce9452d22ae3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014675954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.1014675954
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.2184565883
Short name T151
Test name
Test status
Simulation time 2976483186 ps
CPU time 3.8 seconds
Started Aug 02 04:56:39 PM PDT 24
Finished Aug 02 04:56:43 PM PDT 24
Peak memory 200788 kb
Host smart-2410289a-cc8f-4b6f-8ff9-f16708e64249
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184565883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.2184565883
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2069768799
Short name T724
Test name
Test status
Simulation time 2615955210 ps
CPU time 4.04 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:38 PM PDT 24
Peak memory 200836 kb
Host smart-b3868431-36c2-4d13-b477-04c7a47d59c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069768799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.2069768799
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.725490890
Short name T590
Test name
Test status
Simulation time 2465845763 ps
CPU time 6.59 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:40 PM PDT 24
Peak memory 200708 kb
Host smart-ffbd2433-00d2-4ad3-a39a-b140f8654ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725490890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.725490890
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3375498235
Short name T732
Test name
Test status
Simulation time 2156124747 ps
CPU time 2.86 seconds
Started Aug 02 04:56:36 PM PDT 24
Finished Aug 02 04:56:39 PM PDT 24
Peak memory 200736 kb
Host smart-26dc8f89-1e64-47e3-97de-7d1e08e704e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375498235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3375498235
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2023385124
Short name T475
Test name
Test status
Simulation time 2512172642 ps
CPU time 6.66 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:42 PM PDT 24
Peak memory 200804 kb
Host smart-29cff99b-0da2-42d5-8418-fd8dee452718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023385124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2023385124
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.4251135693
Short name T674
Test name
Test status
Simulation time 2130157041 ps
CPU time 1.95 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:37 PM PDT 24
Peak memory 200728 kb
Host smart-f4b42f76-b447-4eb2-bbea-243b16f7eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251135693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.4251135693
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.379092656
Short name T154
Test name
Test status
Simulation time 14931785006 ps
CPU time 38.31 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:57:13 PM PDT 24
Peak memory 200852 kb
Host smart-e7751eeb-4fee-4fb5-b405-f921d1ddf08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379092656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_st
ress_all.379092656
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.830879432
Short name T148
Test name
Test status
Simulation time 37457380023 ps
CPU time 82.29 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:57:57 PM PDT 24
Peak memory 209496 kb
Host smart-83dd42eb-be43-47f0-b053-04c2a94dad7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830879432 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.830879432
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3330979740
Short name T704
Test name
Test status
Simulation time 1244569272534 ps
CPU time 98.51 seconds
Started Aug 02 04:56:36 PM PDT 24
Finished Aug 02 04:58:15 PM PDT 24
Peak memory 200788 kb
Host smart-f1046fc9-a8cf-4ae1-b63d-7b4e080d8877
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330979740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.3330979740
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.228310842
Short name T694
Test name
Test status
Simulation time 2035846419 ps
CPU time 1.95 seconds
Started Aug 02 04:56:37 PM PDT 24
Finished Aug 02 04:56:39 PM PDT 24
Peak memory 200708 kb
Host smart-10651274-6add-4b2b-aa3e-1d30f0c2f0ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228310842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_tes
t.228310842
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1514107675
Short name T363
Test name
Test status
Simulation time 3640791731 ps
CPU time 1.29 seconds
Started Aug 02 04:56:33 PM PDT 24
Finished Aug 02 04:56:34 PM PDT 24
Peak memory 200880 kb
Host smart-72e92fbb-b298-440b-9509-aa96ac213c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514107675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
514107675
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1640231816
Short name T347
Test name
Test status
Simulation time 130511694980 ps
CPU time 338.62 seconds
Started Aug 02 04:56:38 PM PDT 24
Finished Aug 02 05:02:17 PM PDT 24
Peak memory 200992 kb
Host smart-8de7568d-1113-4ecb-95b3-b6b3ea05afa7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640231816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.1640231816
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.680639050
Short name T309
Test name
Test status
Simulation time 65319170220 ps
CPU time 39.72 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:57:15 PM PDT 24
Peak memory 201168 kb
Host smart-da16038a-35a5-440f-aa0b-fd327907bf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680639050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.680639050
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2993120869
Short name T390
Test name
Test status
Simulation time 4420003912 ps
CPU time 3.25 seconds
Started Aug 02 04:56:38 PM PDT 24
Finished Aug 02 04:56:41 PM PDT 24
Peak memory 200764 kb
Host smart-6ea8ef28-6bab-44e5-9667-efe166ae2581
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993120869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.2993120869
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2221664021
Short name T210
Test name
Test status
Simulation time 2619835297 ps
CPU time 3.82 seconds
Started Aug 02 04:56:37 PM PDT 24
Finished Aug 02 04:56:41 PM PDT 24
Peak memory 200836 kb
Host smart-608bc007-5e70-4e52-beaf-0d84a0e1f414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221664021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.2221664021
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.861782078
Short name T157
Test name
Test status
Simulation time 2459100273 ps
CPU time 7.1 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:41 PM PDT 24
Peak memory 200708 kb
Host smart-b44414d9-286d-48a1-8cab-652607c1c741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861782078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.861782078
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2271027454
Short name T697
Test name
Test status
Simulation time 2092168970 ps
CPU time 5.79 seconds
Started Aug 02 04:56:33 PM PDT 24
Finished Aug 02 04:56:39 PM PDT 24
Peak memory 200704 kb
Host smart-48f228f8-e896-43d7-9104-814d82ea46aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271027454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.2271027454
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3517572632
Short name T384
Test name
Test status
Simulation time 2523988555 ps
CPU time 2.35 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:37 PM PDT 24
Peak memory 200844 kb
Host smart-b47c2182-9019-4ab0-9530-ee8323956530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517572632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3517572632
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.2095145450
Short name T380
Test name
Test status
Simulation time 2135860935 ps
CPU time 1.82 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:37 PM PDT 24
Peak memory 200788 kb
Host smart-b67e8743-af90-4e38-8c20-543b6843eab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095145450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2095145450
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.954382279
Short name T430
Test name
Test status
Simulation time 7907481238 ps
CPU time 19.81 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:56 PM PDT 24
Peak memory 200800 kb
Host smart-ede50a17-8fa8-4661-8b07-23c04bd28703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954382279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_st
ress_all.954382279
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.4057445164
Short name T3
Test name
Test status
Simulation time 3409051925 ps
CPU time 2.21 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:37 PM PDT 24
Peak memory 200896 kb
Host smart-f6151c13-bc8d-4b8c-8d11-0b04aacc7880
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057445164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.4057445164
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.358421079
Short name T369
Test name
Test status
Simulation time 2011941857 ps
CPU time 5.68 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:40 PM PDT 24
Peak memory 200784 kb
Host smart-e0dcde5e-5c20-4d02-a489-c4dbd9d7cd9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358421079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_tes
t.358421079
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2155384939
Short name T196
Test name
Test status
Simulation time 3643913089 ps
CPU time 1.89 seconds
Started Aug 02 04:56:36 PM PDT 24
Finished Aug 02 04:56:38 PM PDT 24
Peak memory 200860 kb
Host smart-118b19ad-a68f-444d-a394-5df12ee55907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155384939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.2
155384939
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1425518826
Short name T9
Test name
Test status
Simulation time 25595539223 ps
CPU time 64.12 seconds
Started Aug 02 04:56:36 PM PDT 24
Finished Aug 02 04:57:41 PM PDT 24
Peak memory 201092 kb
Host smart-0c3cafcc-3fd8-4028-96a7-b6a3dece08ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425518826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.1425518826
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.859446909
Short name T627
Test name
Test status
Simulation time 4105225931 ps
CPU time 5.81 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:42 PM PDT 24
Peak memory 200784 kb
Host smart-93313d01-298b-4321-9821-2c4f4ac9bc4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859446909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.859446909
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.580428694
Short name T648
Test name
Test status
Simulation time 3881384494 ps
CPU time 8.26 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:43 PM PDT 24
Peak memory 200864 kb
Host smart-0df5e89d-ff98-4c9d-9ed1-931a3f715f2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580428694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctr
l_edge_detect.580428694
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2246882747
Short name T387
Test name
Test status
Simulation time 2647042191 ps
CPU time 1.41 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:36 PM PDT 24
Peak memory 200680 kb
Host smart-6c78fbff-4a8d-49fd-bbb4-523be78f8e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246882747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2246882747
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.4233795500
Short name T651
Test name
Test status
Simulation time 2605733443 ps
CPU time 0.99 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:36 PM PDT 24
Peak memory 200788 kb
Host smart-4b081755-9b38-4227-b40c-049e20c9bc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233795500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.4233795500
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.767049453
Short name T393
Test name
Test status
Simulation time 2058967594 ps
CPU time 2.48 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:37 PM PDT 24
Peak memory 200784 kb
Host smart-2635050d-95e2-40d6-a692-537cb0b3ef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767049453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.767049453
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.287343199
Short name T548
Test name
Test status
Simulation time 2529979403 ps
CPU time 2.37 seconds
Started Aug 02 04:56:35 PM PDT 24
Finished Aug 02 04:56:38 PM PDT 24
Peak memory 200764 kb
Host smart-eec0411b-7d84-4749-b8e0-4e9247a3d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287343199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.287343199
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.2815136688
Short name T574
Test name
Test status
Simulation time 2156691503 ps
CPU time 1.28 seconds
Started Aug 02 04:56:34 PM PDT 24
Finished Aug 02 04:56:36 PM PDT 24
Peak memory 200696 kb
Host smart-57da7c1d-df2f-44eb-b9c6-93ef8297df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815136688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2815136688
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.2685557982
Short name T510
Test name
Test status
Simulation time 16333511461 ps
CPU time 6.24 seconds
Started Aug 02 04:56:33 PM PDT 24
Finished Aug 02 04:56:39 PM PDT 24
Peak memory 200848 kb
Host smart-400b2df0-bfb5-4465-8fe8-b05032e874d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685557982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.2685557982
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.542112807
Short name T738
Test name
Test status
Simulation time 59670245126 ps
CPU time 153.2 seconds
Started Aug 02 04:56:36 PM PDT 24
Finished Aug 02 04:59:10 PM PDT 24
Peak memory 209308 kb
Host smart-ac1aa8be-5333-4fed-8690-44df51b1ffa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542112807 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.542112807
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.474061898
Short name T119
Test name
Test status
Simulation time 40266697155 ps
CPU time 4.29 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:56:57 PM PDT 24
Peak memory 200832 kb
Host smart-b2609342-107c-4cd4-83d4-f56467761baa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474061898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ultra_low_pwr.474061898
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.2026486320
Short name T361
Test name
Test status
Simulation time 2044043544 ps
CPU time 1.57 seconds
Started Aug 02 04:55:54 PM PDT 24
Finished Aug 02 04:55:55 PM PDT 24
Peak memory 200708 kb
Host smart-7a6687f7-89f7-42d3-9d48-11a3d1e0bc3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026486320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.2026486320
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3350825975
Short name T725
Test name
Test status
Simulation time 3411411616 ps
CPU time 2.68 seconds
Started Aug 02 04:55:55 PM PDT 24
Finished Aug 02 04:55:58 PM PDT 24
Peak memory 200820 kb
Host smart-006d6003-f39e-4afb-8952-c49e8b475230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350825975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.3350825975
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.4074685871
Short name T94
Test name
Test status
Simulation time 37457275043 ps
CPU time 7.65 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:58 PM PDT 24
Peak memory 201032 kb
Host smart-853a182a-c43b-4d28-bd5e-6c6722acb0eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074685871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.4074685871
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3321839838
Short name T82
Test name
Test status
Simulation time 2444246237 ps
CPU time 2.12 seconds
Started Aug 02 04:55:51 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 200828 kb
Host smart-ac2ede8b-e28f-4019-802d-8f450a2b1776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321839838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3321839838
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2684698608
Short name T782
Test name
Test status
Simulation time 2307846797 ps
CPU time 2.03 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 200708 kb
Host smart-eeb974bc-605e-4647-bb82-6e3d8b09ac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684698608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2684698608
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1420219972
Short name T223
Test name
Test status
Simulation time 27079247856 ps
CPU time 73.01 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:57:05 PM PDT 24
Peak memory 201120 kb
Host smart-c1d477c9-1a98-44c4-9854-19af55e25075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420219972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.1420219972
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2318093155
Short name T712
Test name
Test status
Simulation time 607031620116 ps
CPU time 370.63 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 05:02:01 PM PDT 24
Peak memory 200700 kb
Host smart-96071e3f-a807-4f23-930d-4d8875876948
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318093155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.2318093155
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1982869821
Short name T637
Test name
Test status
Simulation time 4557222904 ps
CPU time 3.81 seconds
Started Aug 02 04:55:55 PM PDT 24
Finished Aug 02 04:55:59 PM PDT 24
Peak memory 200796 kb
Host smart-b8e73346-30c1-449a-a870-1fe782f19696
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982869821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.1982869821
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1785419355
Short name T776
Test name
Test status
Simulation time 2623090527 ps
CPU time 4.04 seconds
Started Aug 02 04:55:53 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 200836 kb
Host smart-793c89d2-593a-4ff1-99a7-c8ab3540f0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785419355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1785419355
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.763572421
Short name T757
Test name
Test status
Simulation time 2480117717 ps
CPU time 1.68 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:51 PM PDT 24
Peak memory 200776 kb
Host smart-9cbf2201-8341-455b-aa73-1c3bf995248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763572421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.763572421
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.4271177015
Short name T585
Test name
Test status
Simulation time 2230632165 ps
CPU time 6.17 seconds
Started Aug 02 04:55:55 PM PDT 24
Finished Aug 02 04:56:01 PM PDT 24
Peak memory 200780 kb
Host smart-608907f1-5426-4953-b0d2-a6d382999f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271177015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.4271177015
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.301643726
Short name T613
Test name
Test status
Simulation time 2607232718 ps
CPU time 1.23 seconds
Started Aug 02 04:55:48 PM PDT 24
Finished Aug 02 04:55:50 PM PDT 24
Peak memory 200744 kb
Host smart-037ca33d-02a8-406b-b67d-8435fbc6a176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301643726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.301643726
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.3194139091
Short name T248
Test name
Test status
Simulation time 42079195492 ps
CPU time 31.98 seconds
Started Aug 02 04:55:49 PM PDT 24
Finished Aug 02 04:56:22 PM PDT 24
Peak memory 220476 kb
Host smart-04cd1f1f-4778-454c-aab1-a589568b2787
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194139091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.3194139091
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.3020321391
Short name T476
Test name
Test status
Simulation time 2235206660 ps
CPU time 0.98 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 200816 kb
Host smart-0c601d95-808e-4538-8ae9-8d10852a4bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020321391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3020321391
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.2344698702
Short name T182
Test name
Test status
Simulation time 9839714095 ps
CPU time 3.78 seconds
Started Aug 02 04:55:54 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 200760 kb
Host smart-57daaa0f-2b49-44e5-aca0-0aaa39fb1af4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344698702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.2344698702
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1890194200
Short name T215
Test name
Test status
Simulation time 385163828902 ps
CPU time 156.28 seconds
Started Aug 02 04:55:51 PM PDT 24
Finished Aug 02 04:58:27 PM PDT 24
Peak memory 212804 kb
Host smart-786e0da9-6052-4ee1-9bb9-1d6a3adeafc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890194200 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1890194200
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1981856981
Short name T277
Test name
Test status
Simulation time 5520511524 ps
CPU time 1.77 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:55:54 PM PDT 24
Peak memory 200876 kb
Host smart-333de840-1ceb-432a-8e71-54b1752981d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981856981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.1981856981
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.4187455223
Short name T374
Test name
Test status
Simulation time 2025190332 ps
CPU time 1.97 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 200764 kb
Host smart-2256fc8b-4865-4447-bc2e-5956a00d2f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187455223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.4187455223
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3216220277
Short name T83
Test name
Test status
Simulation time 3210241889 ps
CPU time 4.84 seconds
Started Aug 02 04:56:44 PM PDT 24
Finished Aug 02 04:56:49 PM PDT 24
Peak memory 200804 kb
Host smart-08bd7cd1-2c13-4b80-ba40-a8b1ab6ca0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216220277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3
216220277
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.1083911656
Short name T731
Test name
Test status
Simulation time 25408702530 ps
CPU time 5.92 seconds
Started Aug 02 04:56:43 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 201112 kb
Host smart-2a90d136-5cde-4600-ac38-3e6f2dae4d47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083911656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.1083911656
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1112940467
Short name T141
Test name
Test status
Simulation time 30195537392 ps
CPU time 9.52 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:58 PM PDT 24
Peak memory 201116 kb
Host smart-dce2d208-7038-4e97-a75e-c42b6a878471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112940467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.1112940467
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2479334496
Short name T582
Test name
Test status
Simulation time 2763156271 ps
CPU time 7.55 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:53 PM PDT 24
Peak memory 200704 kb
Host smart-ba78a827-b841-4356-ad5c-f10c6cedba5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479334496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.2479334496
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1956273048
Short name T774
Test name
Test status
Simulation time 3298936928 ps
CPU time 1.39 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 200820 kb
Host smart-e3d377eb-429e-4b7b-a0d4-46b9627a5dc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956273048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.1956273048
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2342885788
Short name T526
Test name
Test status
Simulation time 2609885091 ps
CPU time 7.05 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:56:53 PM PDT 24
Peak memory 200760 kb
Host smart-12c6fccb-6cf3-44ca-85e8-3b503eacc806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342885788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.2342885788
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.394358992
Short name T546
Test name
Test status
Simulation time 2450780577 ps
CPU time 2.82 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:56:49 PM PDT 24
Peak memory 200844 kb
Host smart-6267ad91-993c-427c-8973-4d45b4c45688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394358992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.394358992
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3737273092
Short name T443
Test name
Test status
Simulation time 2123232177 ps
CPU time 1.14 seconds
Started Aug 02 04:56:43 PM PDT 24
Finished Aug 02 04:56:44 PM PDT 24
Peak memory 200676 kb
Host smart-c1a5a293-ea23-45f8-9555-d92bcdbdf711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737273092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3737273092
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.470135480
Short name T576
Test name
Test status
Simulation time 2512618125 ps
CPU time 6.76 seconds
Started Aug 02 04:56:44 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 200816 kb
Host smart-baef29ad-3ae8-468d-9f6a-ad4fec44e3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470135480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.470135480
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.548713383
Short name T439
Test name
Test status
Simulation time 2111170352 ps
CPU time 5.94 seconds
Started Aug 02 04:56:44 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 200680 kb
Host smart-3d9426b2-c0c0-4461-9984-7f1b6e8db72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548713383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.548713383
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.2890989598
Short name T176
Test name
Test status
Simulation time 15607178590 ps
CPU time 40.62 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:57:31 PM PDT 24
Peak memory 200796 kb
Host smart-b8f365a4-58d3-4192-baaf-63b4702c8bb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890989598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.2890989598
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1093163965
Short name T206
Test name
Test status
Simulation time 4580747059 ps
CPU time 6.19 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:56:52 PM PDT 24
Peak memory 200768 kb
Host smart-ed31a2e2-d847-4696-a411-b0a379a64ea8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093163965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.1093163965
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.3065422801
Short name T499
Test name
Test status
Simulation time 2011616553 ps
CPU time 5.45 seconds
Started Aug 02 04:56:47 PM PDT 24
Finished Aug 02 04:56:52 PM PDT 24
Peak memory 200828 kb
Host smart-48045f1c-b19a-4b62-ac34-eceb1087acae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065422801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.3065422801
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.522595445
Short name T589
Test name
Test status
Simulation time 3471760087 ps
CPU time 4.69 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:53 PM PDT 24
Peak memory 200624 kb
Host smart-6a25a2ef-da7b-46a9-b317-6ace535039f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522595445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.522595445
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3266735319
Short name T305
Test name
Test status
Simulation time 138759499211 ps
CPU time 370.67 seconds
Started Aug 02 04:56:43 PM PDT 24
Finished Aug 02 05:02:54 PM PDT 24
Peak memory 200952 kb
Host smart-5f71b7ef-91df-4215-b831-1d8ecbdb5db5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266735319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3266735319
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3382806766
Short name T587
Test name
Test status
Simulation time 26602547181 ps
CPU time 18.92 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:57:07 PM PDT 24
Peak memory 201188 kb
Host smart-0581cf76-51d3-41f3-bc43-b6f145dd6626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382806766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.3382806766
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3233951257
Short name T101
Test name
Test status
Simulation time 3229743847 ps
CPU time 8.39 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:54 PM PDT 24
Peak memory 200808 kb
Host smart-921433b5-9030-4a82-ab60-59fd071e6ef4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233951257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.3233951257
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3910491742
Short name T10
Test name
Test status
Simulation time 3366890364 ps
CPU time 1.81 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:46 PM PDT 24
Peak memory 200848 kb
Host smart-be662d69-a8c9-4431-b5aa-b35dbe9f7c6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910491742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.3910491742
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.2108631037
Short name T59
Test name
Test status
Simulation time 2610170883 ps
CPU time 5.78 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:54 PM PDT 24
Peak memory 200708 kb
Host smart-61e3b8df-1009-4105-9569-e46d6a0b5997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108631037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.2108631037
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2007611931
Short name T274
Test name
Test status
Simulation time 2462665404 ps
CPU time 5.51 seconds
Started Aug 02 04:56:43 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 200836 kb
Host smart-56b76c34-5788-4488-8604-1d659a7e705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007611931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2007611931
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.947348473
Short name T455
Test name
Test status
Simulation time 2057912948 ps
CPU time 5.66 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 200700 kb
Host smart-d3e21b92-7f85-414d-8aa8-72cfd7eef882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947348473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.947348473
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.4160995119
Short name T778
Test name
Test status
Simulation time 2539756858 ps
CPU time 2.17 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 200744 kb
Host smart-42c00346-bddf-4826-b3ab-b270dd59cdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160995119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.4160995119
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.2737596508
Short name T139
Test name
Test status
Simulation time 2118270220 ps
CPU time 3.28 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:49 PM PDT 24
Peak memory 200744 kb
Host smart-9675bd55-0368-434e-92e6-3d8c5760d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737596508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2737596508
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.2823364514
Short name T448
Test name
Test status
Simulation time 13180912207 ps
CPU time 27.19 seconds
Started Aug 02 04:56:44 PM PDT 24
Finished Aug 02 04:57:11 PM PDT 24
Peak memory 200796 kb
Host smart-b1a0350c-cb52-4136-b076-879ca9332b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823364514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.2823364514
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3907251330
Short name T278
Test name
Test status
Simulation time 31620253786 ps
CPU time 72.14 seconds
Started Aug 02 04:56:47 PM PDT 24
Finished Aug 02 04:58:00 PM PDT 24
Peak memory 209364 kb
Host smart-b9e09eb5-c69e-42e2-9885-de4dda429859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907251330 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3907251330
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2300361795
Short name T124
Test name
Test status
Simulation time 8215750342 ps
CPU time 4.58 seconds
Started Aug 02 04:56:47 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 200856 kb
Host smart-e78ad4cf-624b-4fc3-ac83-81d53138882f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300361795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.2300361795
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.3280753767
Short name T397
Test name
Test status
Simulation time 2028212378 ps
CPU time 1.9 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 200764 kb
Host smart-07027619-3a84-4e35-904f-500e755f757a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280753767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.3280753767
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.4224138584
Short name T422
Test name
Test status
Simulation time 3457450890 ps
CPU time 9.49 seconds
Started Aug 02 04:56:47 PM PDT 24
Finished Aug 02 04:56:57 PM PDT 24
Peak memory 200896 kb
Host smart-501794bf-f835-4cb8-83d6-fa53cb711d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224138584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.4
224138584
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3010840769
Short name T69
Test name
Test status
Simulation time 43739236662 ps
CPU time 31.72 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:57:19 PM PDT 24
Peak memory 201128 kb
Host smart-094800e8-95e1-4ad9-ae67-c06e9395aca7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010840769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.3010840769
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.773725266
Short name T321
Test name
Test status
Simulation time 63318447723 ps
CPU time 42.42 seconds
Started Aug 02 04:56:44 PM PDT 24
Finished Aug 02 04:57:27 PM PDT 24
Peak memory 201016 kb
Host smart-0690ebb5-1b30-4f3c-9a06-cffd05ff340e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773725266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_wi
th_pre_cond.773725266
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1480514665
Short name T471
Test name
Test status
Simulation time 2977897084 ps
CPU time 1.14 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:47 PM PDT 24
Peak memory 200680 kb
Host smart-566a3418-1bc9-46b4-a404-1cf51199ff74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480514665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.1480514665
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.4252785440
Short name T202
Test name
Test status
Simulation time 2581322317 ps
CPU time 1.88 seconds
Started Aug 02 04:56:44 PM PDT 24
Finished Aug 02 04:56:46 PM PDT 24
Peak memory 200820 kb
Host smart-23777f12-bed3-4dad-870b-54ba7494f655
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252785440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.4252785440
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1372591479
Short name T710
Test name
Test status
Simulation time 2614557548 ps
CPU time 7.91 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:53 PM PDT 24
Peak memory 200648 kb
Host smart-1c26e00e-7c8c-463c-9efb-12bf7e60a642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372591479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.1372591479
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2960385087
Short name T720
Test name
Test status
Simulation time 2474347758 ps
CPU time 3.89 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:52 PM PDT 24
Peak memory 200452 kb
Host smart-e41e8df4-b1e1-49c6-af93-6080ae2bdee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960385087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2960385087
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.373175337
Short name T760
Test name
Test status
Simulation time 2091072647 ps
CPU time 3.62 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 200684 kb
Host smart-cd83e33c-c2b4-4341-ad8f-723a14caf6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373175337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.373175337
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.988953163
Short name T784
Test name
Test status
Simulation time 2541793618 ps
CPU time 1.93 seconds
Started Aug 02 04:56:43 PM PDT 24
Finished Aug 02 04:56:45 PM PDT 24
Peak memory 200772 kb
Host smart-812cc28e-4a2b-4105-8acd-d7a9a083be8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988953163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.988953163
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.2399343514
Short name T458
Test name
Test status
Simulation time 2109578385 ps
CPU time 6.25 seconds
Started Aug 02 04:56:44 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 200624 kb
Host smart-0fc55e09-c350-4e8f-9b8d-53ea4be8a685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399343514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2399343514
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.314879307
Short name T588
Test name
Test status
Simulation time 6452688760 ps
CPU time 8.24 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:56:54 PM PDT 24
Peak memory 200856 kb
Host smart-81c2cfdf-1a5b-484f-b00a-aefe82261829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314879307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.314879307
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3997929825
Short name T155
Test name
Test status
Simulation time 181867850408 ps
CPU time 62.05 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:57:48 PM PDT 24
Peak memory 209452 kb
Host smart-e9fc99ad-abd7-4dd4-923e-9bef9919ba51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997929825 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.3997929825
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3709544677
Short name T125
Test name
Test status
Simulation time 7449850388 ps
CPU time 2.55 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 200872 kb
Host smart-d26a397c-bf51-4283-93eb-d38faab1ccd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709544677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3709544677
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.1249651600
Short name T436
Test name
Test status
Simulation time 2011303273 ps
CPU time 5.85 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:56:52 PM PDT 24
Peak memory 200768 kb
Host smart-8625073f-2943-44aa-9725-fe755f51d910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249651600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.1249651600
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.4196159583
Short name T537
Test name
Test status
Simulation time 3302606576 ps
CPU time 1.59 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 200904 kb
Host smart-7185a58c-c204-4144-af89-e1b930771072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196159583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.4
196159583
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.4102394369
Short name T605
Test name
Test status
Simulation time 96606676534 ps
CPU time 79.07 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:58:07 PM PDT 24
Peak memory 201088 kb
Host smart-8a126566-616a-4450-b694-e8811ed9689f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102394369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.4102394369
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3332521524
Short name T792
Test name
Test status
Simulation time 179560772774 ps
CPU time 278.72 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 05:01:25 PM PDT 24
Peak memory 201200 kb
Host smart-23006e97-4bb3-4a05-aa07-b7694ad92ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332521524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.3332521524
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.733379723
Short name T110
Test name
Test status
Simulation time 2729137087 ps
CPU time 2.08 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:47 PM PDT 24
Peak memory 200716 kb
Host smart-285d1e50-2545-443c-b5d6-7d67e38d61f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733379723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ec_pwr_on_rst.733379723
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2879843115
Short name T58
Test name
Test status
Simulation time 2615498452 ps
CPU time 4.6 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:49 PM PDT 24
Peak memory 200788 kb
Host smart-f732d810-73be-4bc3-97fb-d971f711f1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879843115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2879843115
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.715720973
Short name T447
Test name
Test status
Simulation time 2475378763 ps
CPU time 3.75 seconds
Started Aug 02 04:56:47 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 200804 kb
Host smart-fbf89079-5480-42c6-adf7-389519e4a734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715720973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.715720973
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.994455226
Short name T201
Test name
Test status
Simulation time 2134487149 ps
CPU time 3.51 seconds
Started Aug 02 04:56:42 PM PDT 24
Finished Aug 02 04:56:46 PM PDT 24
Peak memory 200672 kb
Host smart-591ee3a8-5def-4fd9-9c76-2b91432c08f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994455226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.994455226
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.772028845
Short name T275
Test name
Test status
Simulation time 2590299239 ps
CPU time 1.28 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 200716 kb
Host smart-ee3968e9-c1dd-444c-99ed-06654e206161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772028845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.772028845
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.548456550
Short name T695
Test name
Test status
Simulation time 2116565536 ps
CPU time 3.05 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:49 PM PDT 24
Peak memory 200704 kb
Host smart-914f33fe-cd4e-46df-9034-910caf812856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548456550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.548456550
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.4293438414
Short name T385
Test name
Test status
Simulation time 13579343519 ps
CPU time 26.53 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:57:12 PM PDT 24
Peak memory 200740 kb
Host smart-bfc9f7f5-56fb-459f-a517-95830952b6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293438414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.4293438414
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2924415298
Short name T462
Test name
Test status
Simulation time 48879279757 ps
CPU time 56.29 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:57:46 PM PDT 24
Peak memory 209340 kb
Host smart-d37b7423-bb4c-4f36-9719-df67950b6e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924415298 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.2924415298
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2783116541
Short name T408
Test name
Test status
Simulation time 3886596808 ps
CPU time 3.02 seconds
Started Aug 02 04:56:45 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 200956 kb
Host smart-c6eb671e-0d2e-4c18-9fdd-930c04f1e9bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783116541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.2783116541
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.145288750
Short name T665
Test name
Test status
Simulation time 2036323398 ps
CPU time 1.48 seconds
Started Aug 02 04:57:05 PM PDT 24
Finished Aug 02 04:57:07 PM PDT 24
Peak memory 200752 kb
Host smart-b91037ca-d500-4a86-91fc-348fed541ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145288750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_tes
t.145288750
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.842283207
Short name T533
Test name
Test status
Simulation time 3520444828 ps
CPU time 7.29 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:56:57 PM PDT 24
Peak memory 200776 kb
Host smart-114b8dc3-d542-4256-8cef-769d8baf2803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842283207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.842283207
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.3269169604
Short name T173
Test name
Test status
Simulation time 149861615716 ps
CPU time 82.15 seconds
Started Aug 02 04:56:51 PM PDT 24
Finished Aug 02 04:58:13 PM PDT 24
Peak memory 201032 kb
Host smart-7fecc49a-e6c8-4977-bf7b-ae933c768722
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269169604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.3269169604
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2348692091
Short name T752
Test name
Test status
Simulation time 3025762083 ps
CPU time 8.39 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:56:58 PM PDT 24
Peak memory 200672 kb
Host smart-44a15510-53e9-48ad-9584-4a6d8de55c27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348692091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.2348692091
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1628794790
Short name T212
Test name
Test status
Simulation time 4736920745 ps
CPU time 2.82 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:56:53 PM PDT 24
Peak memory 200756 kb
Host smart-0018bf76-85fb-47b3-a729-80937f37ba07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628794790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.1628794790
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1523636535
Short name T433
Test name
Test status
Simulation time 2620982984 ps
CPU time 3.63 seconds
Started Aug 02 04:56:51 PM PDT 24
Finished Aug 02 04:56:55 PM PDT 24
Peak memory 200712 kb
Host smart-cb539f63-16fc-4e78-9c5a-02a8df31c256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523636535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.1523636535
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3707541778
Short name T658
Test name
Test status
Simulation time 2476326861 ps
CPU time 1.9 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 200840 kb
Host smart-c69888ef-5521-443d-ad6e-97c5be50e2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707541778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3707541778
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.508257237
Short name T671
Test name
Test status
Simulation time 2181420153 ps
CPU time 5.97 seconds
Started Aug 02 04:56:47 PM PDT 24
Finished Aug 02 04:56:53 PM PDT 24
Peak memory 200800 kb
Host smart-459ee73b-a5d8-4234-b601-7e3434a2a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508257237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.508257237
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.244544534
Short name T709
Test name
Test status
Simulation time 2525313223 ps
CPU time 2.26 seconds
Started Aug 02 04:56:48 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 200736 kb
Host smart-0b7998c9-5648-465d-bca6-c72e7f75081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244544534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.244544534
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.3310817151
Short name T171
Test name
Test status
Simulation time 2136308254 ps
CPU time 2.03 seconds
Started Aug 02 04:56:46 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 200700 kb
Host smart-128ff581-76fe-4c35-939c-a891c4661886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310817151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.3310817151
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.1729558859
Short name T630
Test name
Test status
Simulation time 13062643196 ps
CPU time 33.07 seconds
Started Aug 02 04:56:51 PM PDT 24
Finished Aug 02 04:57:24 PM PDT 24
Peak memory 200892 kb
Host smart-ada40b1f-5a19-4554-87d3-e61b639d3a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729558859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.1729558859
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.121393916
Short name T790
Test name
Test status
Simulation time 7043857379 ps
CPU time 2.1 seconds
Started Aug 02 04:56:51 PM PDT 24
Finished Aug 02 04:56:53 PM PDT 24
Peak memory 200880 kb
Host smart-446ffe40-837e-4147-8bea-1058e5b64068
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121393916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ultra_low_pwr.121393916
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.1052339664
Short name T631
Test name
Test status
Simulation time 2018959023 ps
CPU time 3.19 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:56:56 PM PDT 24
Peak memory 200740 kb
Host smart-1e12fa9f-7f8c-4798-a010-fb99261c3a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052339664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.1052339664
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1810796388
Short name T399
Test name
Test status
Simulation time 3532788373 ps
CPU time 3.12 seconds
Started Aug 02 04:56:51 PM PDT 24
Finished Aug 02 04:56:54 PM PDT 24
Peak memory 200836 kb
Host smart-4e89b840-b85e-4ba1-af95-c6e8c0cfb79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810796388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1
810796388
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2411114632
Short name T306
Test name
Test status
Simulation time 162696900204 ps
CPU time 219.4 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 05:00:32 PM PDT 24
Peak memory 201040 kb
Host smart-01c42f84-092a-4f1c-80e5-a98fe9da93ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411114632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.2411114632
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.153298279
Short name T472
Test name
Test status
Simulation time 3799913085 ps
CPU time 9.82 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200704 kb
Host smart-aff88130-eb21-40d3-b776-427306659a76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153298279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ec_pwr_on_rst.153298279
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3634950304
Short name T545
Test name
Test status
Simulation time 2611152804 ps
CPU time 7.57 seconds
Started Aug 02 04:57:05 PM PDT 24
Finished Aug 02 04:57:13 PM PDT 24
Peak memory 200752 kb
Host smart-5789d17e-2865-43a6-9925-31693e75a5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634950304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3634950304
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1548478602
Short name T593
Test name
Test status
Simulation time 2458388462 ps
CPU time 5.92 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:56:57 PM PDT 24
Peak memory 200780 kb
Host smart-c9426019-caac-4b00-ad88-91ff0235fbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548478602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1548478602
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2420680344
Short name T370
Test name
Test status
Simulation time 2162451289 ps
CPU time 5.76 seconds
Started Aug 02 04:57:03 PM PDT 24
Finished Aug 02 04:57:09 PM PDT 24
Peak memory 200228 kb
Host smart-cda73078-157a-4aa2-942b-26b4da564663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420680344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2420680344
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1680731998
Short name T174
Test name
Test status
Simulation time 2511120896 ps
CPU time 7.31 seconds
Started Aug 02 04:57:03 PM PDT 24
Finished Aug 02 04:57:10 PM PDT 24
Peak memory 200176 kb
Host smart-a4c2fc8c-6c7a-430c-9e29-62caf807efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680731998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1680731998
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2030657931
Short name T160
Test name
Test status
Simulation time 2112093995 ps
CPU time 3.31 seconds
Started Aug 02 04:56:54 PM PDT 24
Finished Aug 02 04:56:57 PM PDT 24
Peak memory 200352 kb
Host smart-7e2c0766-dbaf-4ae5-a5d5-9b5e1fe20b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030657931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2030657931
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.2337301710
Short name T622
Test name
Test status
Simulation time 7063094169 ps
CPU time 17.99 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 04:57:12 PM PDT 24
Peak memory 200800 kb
Host smart-eed674c5-665c-46a5-a9b9-71360230faf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337301710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.2337301710
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2236817233
Short name T266
Test name
Test status
Simulation time 33923318627 ps
CPU time 87.74 seconds
Started Aug 02 04:56:49 PM PDT 24
Finished Aug 02 04:58:17 PM PDT 24
Peak memory 209460 kb
Host smart-6d866522-2717-4661-ad71-35aedb062d5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236817233 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2236817233
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2492415897
Short name T120
Test name
Test status
Simulation time 8315745052 ps
CPU time 8.41 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:57:01 PM PDT 24
Peak memory 200836 kb
Host smart-4096058e-f874-4632-a612-86b36aaf40a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492415897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.2492415897
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.2845044797
Short name T525
Test name
Test status
Simulation time 2018949945 ps
CPU time 3.2 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:56:54 PM PDT 24
Peak memory 200804 kb
Host smart-deae9df6-e07a-43d9-9c7d-02ad811abe2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845044797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.2845044797
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1248475908
Short name T467
Test name
Test status
Simulation time 3584446797 ps
CPU time 5.42 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:56:58 PM PDT 24
Peak memory 200804 kb
Host smart-e6e21699-8e61-4526-9aac-a90e092449fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248475908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.1
248475908
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3302239550
Short name T93
Test name
Test status
Simulation time 182334147311 ps
CPU time 496.86 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 05:05:10 PM PDT 24
Peak memory 201004 kb
Host smart-137919a4-3926-47d3-9f30-a422d1900d75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302239550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.3302239550
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4164853312
Short name T326
Test name
Test status
Simulation time 103229672127 ps
CPU time 141.26 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 04:59:15 PM PDT 24
Peak memory 201044 kb
Host smart-bc8fc677-27a6-45f7-9f05-8ff089a8160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164853312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.4164853312
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1457381120
Short name T362
Test name
Test status
Simulation time 3047398526 ps
CPU time 8.11 seconds
Started Aug 02 04:56:54 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200764 kb
Host smart-ebe90148-b991-49f6-8fb5-dbf99b831f65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457381120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.1457381120
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.391865225
Short name T165
Test name
Test status
Simulation time 4508653554 ps
CPU time 7.14 seconds
Started Aug 02 04:56:55 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200764 kb
Host smart-feb7eade-a166-4649-8c95-5aad3e34858c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391865225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctr
l_edge_detect.391865225
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3654169105
Short name T626
Test name
Test status
Simulation time 2611285268 ps
CPU time 5.22 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:56:58 PM PDT 24
Peak memory 200780 kb
Host smart-5cbdf942-914e-46f5-b174-4e59375919fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654169105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3654169105
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1196619200
Short name T554
Test name
Test status
Simulation time 2459691016 ps
CPU time 6.55 seconds
Started Aug 02 04:56:56 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200704 kb
Host smart-c28c4793-b91d-41a6-b893-fb41512d95f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196619200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1196619200
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.392422219
Short name T401
Test name
Test status
Simulation time 2173009055 ps
CPU time 3.31 seconds
Started Aug 02 04:56:56 PM PDT 24
Finished Aug 02 04:56:59 PM PDT 24
Peak memory 200696 kb
Host smart-6772c371-d7f0-4a5c-9731-deede03ffd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392422219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.392422219
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.2834876066
Short name T619
Test name
Test status
Simulation time 2529604880 ps
CPU time 2.66 seconds
Started Aug 02 04:56:54 PM PDT 24
Finished Aug 02 04:56:57 PM PDT 24
Peak memory 200380 kb
Host smart-8eedb4eb-4f48-467e-9681-a2728c33030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834876066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.2834876066
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.3242045519
Short name T572
Test name
Test status
Simulation time 2151688700 ps
CPU time 1.58 seconds
Started Aug 02 04:56:54 PM PDT 24
Finished Aug 02 04:56:55 PM PDT 24
Peak memory 200800 kb
Host smart-017c3dec-d112-449b-b151-5e9dc2f96707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242045519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3242045519
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2691870400
Short name T77
Test name
Test status
Simulation time 992015866923 ps
CPU time 2611.12 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 05:40:24 PM PDT 24
Peak memory 200752 kb
Host smart-ceb11e03-b963-42e2-a268-d05185170f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691870400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2691870400
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1497359040
Short name T666
Test name
Test status
Simulation time 6272417880 ps
CPU time 6.95 seconds
Started Aug 02 04:56:56 PM PDT 24
Finished Aug 02 04:57:03 PM PDT 24
Peak memory 200796 kb
Host smart-f381ab0e-f446-418d-9016-448fc7c2a152
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497359040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.1497359040
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.3426407376
Short name T50
Test name
Test status
Simulation time 2010552115 ps
CPU time 5.37 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:56:58 PM PDT 24
Peak memory 200732 kb
Host smart-9e328813-de22-433e-b482-9bca4d18fa57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426407376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.3426407376
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3316053210
Short name T478
Test name
Test status
Simulation time 3591596423 ps
CPU time 2.95 seconds
Started Aug 02 04:56:51 PM PDT 24
Finished Aug 02 04:56:54 PM PDT 24
Peak memory 200836 kb
Host smart-c85ef1be-972a-43e9-b959-4efcd9cc3725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316053210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3
316053210
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1788925335
Short name T230
Test name
Test status
Simulation time 128800556607 ps
CPU time 152.34 seconds
Started Aug 02 04:56:55 PM PDT 24
Finished Aug 02 04:59:28 PM PDT 24
Peak memory 201016 kb
Host smart-50ba99bd-b8bc-495f-913c-67bd3c792e12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788925335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1788925335
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.4087494623
Short name T531
Test name
Test status
Simulation time 83170960304 ps
CPU time 24.78 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 04:57:18 PM PDT 24
Peak memory 201100 kb
Host smart-720d29b5-7485-4504-8a21-83cb6f02e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087494623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.4087494623
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3660109875
Short name T607
Test name
Test status
Simulation time 4771576328 ps
CPU time 2.66 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:56:55 PM PDT 24
Peak memory 200768 kb
Host smart-9e42e4aa-1cff-433f-9e1a-bb1da0188026
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660109875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.3660109875
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.3609581664
Short name T63
Test name
Test status
Simulation time 2457739076 ps
CPU time 2.08 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 04:56:56 PM PDT 24
Peak memory 200876 kb
Host smart-44aea17a-4a18-4caa-97c4-f076401817e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609581664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.3609581664
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.45832655
Short name T641
Test name
Test status
Simulation time 2639899408 ps
CPU time 2.31 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:56:52 PM PDT 24
Peak memory 200776 kb
Host smart-064ef7f1-74c0-48bb-9bf6-ef70564511e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45832655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.45832655
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.944036802
Short name T677
Test name
Test status
Simulation time 2463348909 ps
CPU time 7.18 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 04:57:00 PM PDT 24
Peak memory 200808 kb
Host smart-c52baf67-55b5-418c-923a-fd35e0fffe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944036802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.944036802
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3955465959
Short name T357
Test name
Test status
Simulation time 2304246685 ps
CPU time 1.18 seconds
Started Aug 02 04:56:56 PM PDT 24
Finished Aug 02 04:56:57 PM PDT 24
Peak memory 200776 kb
Host smart-aa4753d3-e807-488a-89a9-e5ad86e814fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955465959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.3955465959
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1240268365
Short name T142
Test name
Test status
Simulation time 2544331182 ps
CPU time 1.8 seconds
Started Aug 02 04:56:54 PM PDT 24
Finished Aug 02 04:56:56 PM PDT 24
Peak memory 200744 kb
Host smart-b9a11b35-a821-4136-8f1a-5a4bf65ebb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240268365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1240268365
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.2910952555
Short name T682
Test name
Test status
Simulation time 2112075979 ps
CPU time 5.98 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:56:59 PM PDT 24
Peak memory 200812 kb
Host smart-978869be-a4f1-4761-8cb0-afac179a93fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910952555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2910952555
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1726911983
Short name T652
Test name
Test status
Simulation time 8265015529 ps
CPU time 6.24 seconds
Started Aug 02 04:56:53 PM PDT 24
Finished Aug 02 04:56:59 PM PDT 24
Peak memory 200764 kb
Host smart-9e72cd67-5c5e-4973-b6bc-657e2f8051ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726911983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1726911983
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3100269201
Short name T279
Test name
Test status
Simulation time 15391129794 ps
CPU time 41.22 seconds
Started Aug 02 04:56:56 PM PDT 24
Finished Aug 02 04:57:37 PM PDT 24
Peak memory 201220 kb
Host smart-4a7f3f63-51e1-4984-adfe-3f1e5143d360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100269201 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.3100269201
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.4150857869
Short name T493
Test name
Test status
Simulation time 6576646860 ps
CPU time 2.29 seconds
Started Aug 02 04:56:52 PM PDT 24
Finished Aug 02 04:56:55 PM PDT 24
Peak memory 200868 kb
Host smart-715c34be-3772-472d-bb38-baecadb93d8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150857869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.4150857869
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.2750261020
Short name T410
Test name
Test status
Simulation time 2030363494 ps
CPU time 2 seconds
Started Aug 02 04:56:57 PM PDT 24
Finished Aug 02 04:56:59 PM PDT 24
Peak memory 200724 kb
Host smart-dc02d1c7-57e3-4076-b316-5c737ce6275b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750261020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.2750261020
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2591942946
Short name T366
Test name
Test status
Simulation time 76125973677 ps
CPU time 58.56 seconds
Started Aug 02 04:57:01 PM PDT 24
Finished Aug 02 04:58:00 PM PDT 24
Peak memory 200876 kb
Host smart-233ec331-c19a-4363-acfb-7de4d821d432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591942946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2
591942946
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.1465469621
Short name T333
Test name
Test status
Simulation time 129773160545 ps
CPU time 310.24 seconds
Started Aug 02 04:57:05 PM PDT 24
Finished Aug 02 05:02:15 PM PDT 24
Peak memory 200968 kb
Host smart-7ac23824-1e61-412e-9c89-cb25d545c006
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465469621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.1465469621
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1803090386
Short name T405
Test name
Test status
Simulation time 2918625109 ps
CPU time 3.99 seconds
Started Aug 02 04:56:57 PM PDT 24
Finished Aug 02 04:57:01 PM PDT 24
Peak memory 200712 kb
Host smart-2fad3b45-d0ba-4fb7-9404-5f62e1b17c6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803090386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.1803090386
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3350228847
Short name T571
Test name
Test status
Simulation time 3697748512 ps
CPU time 9 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:57:23 PM PDT 24
Peak memory 200884 kb
Host smart-f7c38a00-96e8-40ca-a17a-14ccccba4ff1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350228847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.3350228847
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2756717801
Short name T717
Test name
Test status
Simulation time 2611379724 ps
CPU time 7.49 seconds
Started Aug 02 04:57:01 PM PDT 24
Finished Aug 02 04:57:09 PM PDT 24
Peak memory 200804 kb
Host smart-9a33dc58-9706-4deb-bdf3-9e092cf313f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756717801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2756717801
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.2093635578
Short name T763
Test name
Test status
Simulation time 2456609223 ps
CPU time 6.59 seconds
Started Aug 02 04:56:57 PM PDT 24
Finished Aug 02 04:57:04 PM PDT 24
Peak memory 200720 kb
Host smart-fde4ec84-b087-4cd2-a958-9cb71a1a1088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093635578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2093635578
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.3485735809
Short name T514
Test name
Test status
Simulation time 2216801553 ps
CPU time 6.31 seconds
Started Aug 02 04:56:54 PM PDT 24
Finished Aug 02 04:57:00 PM PDT 24
Peak memory 200788 kb
Host smart-10919605-1883-4671-8400-768c13caefa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485735809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.3485735809
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.3563902052
Short name T111
Test name
Test status
Simulation time 2511596498 ps
CPU time 6.35 seconds
Started Aug 02 04:57:01 PM PDT 24
Finished Aug 02 04:57:08 PM PDT 24
Peak memory 200808 kb
Host smart-48d04077-93b4-4061-ad25-c6dfd4249134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563902052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.3563902052
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.827195077
Short name T595
Test name
Test status
Simulation time 2194367169 ps
CPU time 1.03 seconds
Started Aug 02 04:56:50 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 200748 kb
Host smart-cf080182-0d42-4657-ac8e-a09bacaa0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827195077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.827195077
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.2859688731
Short name T620
Test name
Test status
Simulation time 8007182159 ps
CPU time 20.06 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:18 PM PDT 24
Peak memory 200896 kb
Host smart-26742fc2-437d-4d27-94bb-87240679965e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859688731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.2859688731
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2558630660
Short name T42
Test name
Test status
Simulation time 41675896842 ps
CPU time 65.67 seconds
Started Aug 02 04:56:56 PM PDT 24
Finished Aug 02 04:58:02 PM PDT 24
Peak memory 217552 kb
Host smart-e59efd2a-1fdb-4a9e-8a29-d2c82c27ac9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558630660 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2558630660
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.174834494
Short name T419
Test name
Test status
Simulation time 10092379731 ps
CPU time 2.07 seconds
Started Aug 02 04:56:57 PM PDT 24
Finished Aug 02 04:56:59 PM PDT 24
Peak memory 200776 kb
Host smart-ce1757cb-af33-448b-a50b-2856b8065a61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174834494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ultra_low_pwr.174834494
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.1821274622
Short name T163
Test name
Test status
Simulation time 2030343106 ps
CPU time 1.82 seconds
Started Aug 02 04:57:03 PM PDT 24
Finished Aug 02 04:57:05 PM PDT 24
Peak memory 200864 kb
Host smart-93d998cd-e2c5-41ac-b00d-ed3025dab78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821274622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.1821274622
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2582502591
Short name T41
Test name
Test status
Simulation time 3070166088 ps
CPU time 8.15 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:06 PM PDT 24
Peak memory 200820 kb
Host smart-4834a287-0c4d-4a93-80b4-f294f9405543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582502591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.2
582502591
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1826339655
Short name T687
Test name
Test status
Simulation time 177028649667 ps
CPU time 116.73 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:58:55 PM PDT 24
Peak memory 201088 kb
Host smart-2dbc06fe-f635-4c56-9984-c7cf6d74f0dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826339655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.1826339655
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.4166397414
Short name T244
Test name
Test status
Simulation time 28846961500 ps
CPU time 16.68 seconds
Started Aug 02 04:57:00 PM PDT 24
Finished Aug 02 04:57:17 PM PDT 24
Peak memory 201088 kb
Host smart-2df6d8e3-5ad7-4951-a913-2907e02b2fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166397414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.4166397414
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.4277703137
Short name T530
Test name
Test status
Simulation time 4188551405 ps
CPU time 1.72 seconds
Started Aug 02 04:56:54 PM PDT 24
Finished Aug 02 04:56:56 PM PDT 24
Peak memory 200800 kb
Host smart-c1650322-20f8-4a17-aa0c-cb4a8e4a2978
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277703137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.4277703137
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.3698130049
Short name T181
Test name
Test status
Simulation time 2965839991 ps
CPU time 3.04 seconds
Started Aug 02 04:57:07 PM PDT 24
Finished Aug 02 04:57:10 PM PDT 24
Peak memory 200820 kb
Host smart-95012c0a-6b82-4010-95cf-d33befca525c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698130049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.3698130049
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3142558700
Short name T632
Test name
Test status
Simulation time 2615014975 ps
CPU time 7.4 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:05 PM PDT 24
Peak memory 200840 kb
Host smart-68e3aedc-d05d-4e87-8262-fcda88704104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142558700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3142558700
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.4041613713
Short name T272
Test name
Test status
Simulation time 2458632984 ps
CPU time 7.4 seconds
Started Aug 02 04:57:01 PM PDT 24
Finished Aug 02 04:57:09 PM PDT 24
Peak memory 200808 kb
Host smart-14760003-143a-4440-9fcd-1b05b6c16e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041613713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.4041613713
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3642791665
Short name T386
Test name
Test status
Simulation time 2148734840 ps
CPU time 3.26 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:01 PM PDT 24
Peak memory 200836 kb
Host smart-d58438ec-298b-4cb7-8cc9-7e0fd0a0e3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642791665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.3642791665
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3984429447
Short name T460
Test name
Test status
Simulation time 2510951684 ps
CPU time 6.75 seconds
Started Aug 02 04:57:01 PM PDT 24
Finished Aug 02 04:57:08 PM PDT 24
Peak memory 200808 kb
Host smart-040cf787-716b-4fcf-8648-ba171bfb638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984429447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3984429447
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.2676271092
Short name T517
Test name
Test status
Simulation time 2125343364 ps
CPU time 2.18 seconds
Started Aug 02 04:57:01 PM PDT 24
Finished Aug 02 04:57:04 PM PDT 24
Peak memory 200740 kb
Host smart-68110f8e-da99-41d4-b3fb-ace5ef463397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676271092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.2676271092
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3277443064
Short name T167
Test name
Test status
Simulation time 314425921073 ps
CPU time 5.68 seconds
Started Aug 02 04:57:00 PM PDT 24
Finished Aug 02 04:57:06 PM PDT 24
Peak memory 200764 kb
Host smart-39c0be01-190e-4e0c-9251-917b6a00640a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277443064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3277443064
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2938522915
Short name T33
Test name
Test status
Simulation time 1147259296050 ps
CPU time 81.27 seconds
Started Aug 02 04:57:00 PM PDT 24
Finished Aug 02 04:58:21 PM PDT 24
Peak memory 209436 kb
Host smart-0ac93ccd-7eed-42e8-9b90-8341f69b052a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938522915 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2938522915
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2241791634
Short name T451
Test name
Test status
Simulation time 3027486594 ps
CPU time 3.57 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:03 PM PDT 24
Peak memory 200744 kb
Host smart-94ae5540-5302-4255-a9b1-acd0d685e54e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241791634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2241791634
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.350993114
Short name T175
Test name
Test status
Simulation time 2011978352 ps
CPU time 5.74 seconds
Started Aug 02 04:55:55 PM PDT 24
Finished Aug 02 04:56:01 PM PDT 24
Peak memory 200736 kb
Host smart-afddd9da-fef8-4f60-9fe6-ed9259b884e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350993114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test
.350993114
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.879302116
Short name T522
Test name
Test status
Simulation time 3610137636 ps
CPU time 2.97 seconds
Started Aug 02 04:55:54 PM PDT 24
Finished Aug 02 04:55:58 PM PDT 24
Peak memory 200864 kb
Host smart-edd060a7-7286-4dc9-95aa-f72ed425874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879302116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.879302116
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.2240007491
Short name T346
Test name
Test status
Simulation time 140850912630 ps
CPU time 40.44 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:56:33 PM PDT 24
Peak memory 201016 kb
Host smart-165e2818-86cf-4033-b5d5-087aa7ee178c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240007491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.2240007491
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.777565971
Short name T621
Test name
Test status
Simulation time 2407364456 ps
CPU time 2.12 seconds
Started Aug 02 04:55:51 PM PDT 24
Finished Aug 02 04:55:53 PM PDT 24
Peak memory 200776 kb
Host smart-59fb3796-5002-4b58-95c0-96c552cce49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777565971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.777565971
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1987837303
Short name T40
Test name
Test status
Simulation time 2332787154 ps
CPU time 2.1 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:14 PM PDT 24
Peak memory 200812 kb
Host smart-f3c47a22-346b-4c84-9dca-ef59cc51ab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987837303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1987837303
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2322282275
Short name T416
Test name
Test status
Simulation time 4155280545 ps
CPU time 10.97 seconds
Started Aug 02 04:55:53 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 200692 kb
Host smart-8d7ce462-dec0-449d-b2cd-538d0f79cb2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322282275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.2322282275
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.1048921370
Short name T561
Test name
Test status
Simulation time 4789047077 ps
CPU time 2.94 seconds
Started Aug 02 04:55:55 PM PDT 24
Finished Aug 02 04:55:58 PM PDT 24
Peak memory 200796 kb
Host smart-0a21c09d-c78b-4d35-935a-5207a5f298f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048921370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.1048921370
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3566978942
Short name T714
Test name
Test status
Simulation time 2611396852 ps
CPU time 7.24 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:55:59 PM PDT 24
Peak memory 200788 kb
Host smart-f81a8e5d-8eef-41ef-9519-ccd2a29bd4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566978942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3566978942
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.2125871286
Short name T676
Test name
Test status
Simulation time 2476888579 ps
CPU time 2.39 seconds
Started Aug 02 04:55:49 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 200716 kb
Host smart-e4b005ea-5643-4613-aca1-94c40afaa46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125871286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.2125871286
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1522107469
Short name T686
Test name
Test status
Simulation time 2260672363 ps
CPU time 1.62 seconds
Started Aug 02 04:55:51 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 200860 kb
Host smart-6da5f64c-5369-4275-8b17-f4b9b7b92389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522107469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.1522107469
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1114964881
Short name T618
Test name
Test status
Simulation time 2515317351 ps
CPU time 7.19 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:57 PM PDT 24
Peak memory 200728 kb
Host smart-e1272c55-9d51-429a-bf61-108cde308576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114964881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1114964881
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3657324068
Short name T262
Test name
Test status
Simulation time 22034613252 ps
CPU time 52.04 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:56:45 PM PDT 24
Peak memory 220684 kb
Host smart-18d599d2-71af-4902-b2c6-856f0800f621
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657324068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3657324068
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.4037920511
Short name T539
Test name
Test status
Simulation time 2198005591 ps
CPU time 0.88 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:52 PM PDT 24
Peak memory 200844 kb
Host smart-8d2d0c27-7329-41bb-a35f-e5342252bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037920511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.4037920511
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.3939795918
Short name T421
Test name
Test status
Simulation time 6951581159 ps
CPU time 17 seconds
Started Aug 02 04:56:00 PM PDT 24
Finished Aug 02 04:56:17 PM PDT 24
Peak memory 200760 kb
Host smart-ff2a555e-a9f2-4ed5-8137-8bcf633b8f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939795918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.3939795918
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3448598358
Short name T133
Test name
Test status
Simulation time 38359649718 ps
CPU time 24.62 seconds
Started Aug 02 04:55:53 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 214348 kb
Host smart-127ae10a-59a3-4451-badb-a47d4db7bf40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448598358 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.3448598358
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2268976790
Short name T429
Test name
Test status
Simulation time 7945735052 ps
CPU time 3.8 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:55:56 PM PDT 24
Peak memory 200780 kb
Host smart-8a7e1217-8533-40b0-a7f0-ea1009a83e40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268976790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2268976790
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.2219061539
Short name T162
Test name
Test status
Simulation time 2014746849 ps
CPU time 3.35 seconds
Started Aug 02 04:57:06 PM PDT 24
Finished Aug 02 04:57:10 PM PDT 24
Peak memory 200840 kb
Host smart-bf799a25-44bb-49fc-970d-fea2a343dcae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219061539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.2219061539
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2791698084
Short name T745
Test name
Test status
Simulation time 482200641284 ps
CPU time 292.13 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 05:01:50 PM PDT 24
Peak memory 200764 kb
Host smart-e7f882e4-d31d-4bc0-a035-181bb0bb5718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791698084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
791698084
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.735102392
Short name T102
Test name
Test status
Simulation time 49826475091 ps
CPU time 32.06 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:30 PM PDT 24
Peak memory 200952 kb
Host smart-d1bdbc94-cf7e-40ef-9734-c7660a8598d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735102392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_combo_detect.735102392
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2961204982
Short name T508
Test name
Test status
Simulation time 3132658393 ps
CPU time 7.73 seconds
Started Aug 02 04:57:00 PM PDT 24
Finished Aug 02 04:57:08 PM PDT 24
Peak memory 200836 kb
Host smart-e9314454-c69f-4421-9d26-067b0833ed8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961204982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.2961204982
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.461778666
Short name T367
Test name
Test status
Simulation time 2654897077 ps
CPU time 1.41 seconds
Started Aug 02 04:57:02 PM PDT 24
Finished Aug 02 04:57:03 PM PDT 24
Peak memory 200844 kb
Host smart-ecfabced-fc05-4b8a-b64b-8cb000e1045f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461778666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.461778666
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2770742727
Short name T378
Test name
Test status
Simulation time 2488558709 ps
CPU time 2.77 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200724 kb
Host smart-0e6ea6d2-d33b-493f-90a3-081e33d3cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770742727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.2770742727
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.1134443984
Short name T402
Test name
Test status
Simulation time 2253910325 ps
CPU time 2.82 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200752 kb
Host smart-f50a853f-8d4c-4c5e-af25-7aaec84ad2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134443984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.1134443984
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2336089064
Short name T591
Test name
Test status
Simulation time 2511504953 ps
CPU time 7.69 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:06 PM PDT 24
Peak memory 200736 kb
Host smart-1c4905a8-7201-49a3-a6f9-b5172621f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336089064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.2336089064
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.170829601
Short name T640
Test name
Test status
Simulation time 2127149393 ps
CPU time 2.01 seconds
Started Aug 02 04:57:08 PM PDT 24
Finished Aug 02 04:57:10 PM PDT 24
Peak memory 200768 kb
Host smart-2ebd6d99-ff22-47e0-b25c-3d8df19ef02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170829601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.170829601
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.1650331479
Short name T786
Test name
Test status
Simulation time 7059579103 ps
CPU time 4.36 seconds
Started Aug 02 04:57:07 PM PDT 24
Finished Aug 02 04:57:11 PM PDT 24
Peak memory 200800 kb
Host smart-da51565f-37d5-4b22-9c56-c0898c0ccbc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650331479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.1650331479
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2430451125
Short name T344
Test name
Test status
Simulation time 65819419308 ps
CPU time 58.68 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:57 PM PDT 24
Peak memory 209428 kb
Host smart-38883d0b-e509-4631-a937-417b8ade0247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430451125 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.2430451125
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1493317125
Short name T55
Test name
Test status
Simulation time 2798264144 ps
CPU time 3.09 seconds
Started Aug 02 04:56:57 PM PDT 24
Finished Aug 02 04:57:00 PM PDT 24
Peak memory 200908 kb
Host smart-7eea4d17-dda0-4bab-9417-485152119817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493317125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.1493317125
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.1691660242
Short name T611
Test name
Test status
Simulation time 2011790650 ps
CPU time 5.63 seconds
Started Aug 02 04:57:01 PM PDT 24
Finished Aug 02 04:57:06 PM PDT 24
Peak memory 200840 kb
Host smart-75e8eafb-cb9b-47d6-8ebb-f745ac205094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691660242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.1691660242
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2167283379
Short name T107
Test name
Test status
Simulation time 3688014545 ps
CPU time 3.06 seconds
Started Aug 02 04:57:00 PM PDT 24
Finished Aug 02 04:57:03 PM PDT 24
Peak memory 200800 kb
Host smart-38e55446-1411-47bf-98b2-66116e04d4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167283379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.2
167283379
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.4234248713
Short name T736
Test name
Test status
Simulation time 47307118304 ps
CPU time 117.72 seconds
Started Aug 02 04:57:12 PM PDT 24
Finished Aug 02 04:59:10 PM PDT 24
Peak memory 201016 kb
Host smart-262ca25a-aa47-429f-bccb-0be7c48f9167
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234248713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.4234248713
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2586546073
Short name T459
Test name
Test status
Simulation time 28110794338 ps
CPU time 18.77 seconds
Started Aug 02 04:57:09 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 201200 kb
Host smart-6af8f57f-a976-47c6-8359-e17cfcbdf7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586546073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2586546073
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.4127834203
Short name T431
Test name
Test status
Simulation time 3193767587 ps
CPU time 4.54 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:04 PM PDT 24
Peak memory 200780 kb
Host smart-af7c2dd1-d708-4629-bf14-d2ec4d1308de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127834203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.4127834203
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.271550195
Short name T64
Test name
Test status
Simulation time 3028254358 ps
CPU time 8.5 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:07 PM PDT 24
Peak memory 200888 kb
Host smart-8f5001ef-623f-49d9-b939-a559547ec042
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271550195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctr
l_edge_detect.271550195
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2845090983
Short name T62
Test name
Test status
Simulation time 2624548416 ps
CPU time 2.62 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200768 kb
Host smart-c1ff30b7-90db-4ce9-b420-89fe294e9d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845090983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2845090983
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.3279297774
Short name T558
Test name
Test status
Simulation time 2492454688 ps
CPU time 2.86 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:01 PM PDT 24
Peak memory 200788 kb
Host smart-f4d66835-8b4a-41e6-83fc-4902ac4d311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279297774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.3279297774
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1664947299
Short name T592
Test name
Test status
Simulation time 2182519597 ps
CPU time 2.05 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:01 PM PDT 24
Peak memory 200752 kb
Host smart-7ff409b0-a243-40c7-b106-77e99d941f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664947299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1664947299
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2059285490
Short name T596
Test name
Test status
Simulation time 2513914567 ps
CPU time 4.02 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:03 PM PDT 24
Peak memory 200772 kb
Host smart-006c2b39-fd05-4ee1-bf3d-f32a4dac8a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059285490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.2059285490
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.2849143565
Short name T538
Test name
Test status
Simulation time 2120672200 ps
CPU time 3.46 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:02 PM PDT 24
Peak memory 200772 kb
Host smart-f182f724-12dc-407b-ad1c-d8ea95d930d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849143565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.2849143565
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.3723551944
Short name T680
Test name
Test status
Simulation time 143258947553 ps
CPU time 35.2 seconds
Started Aug 02 04:56:59 PM PDT 24
Finished Aug 02 04:57:35 PM PDT 24
Peak memory 200920 kb
Host smart-7d311ee8-9372-404a-9a64-97ace297aa62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723551944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.3723551944
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3265865883
Short name T599
Test name
Test status
Simulation time 4225121762 ps
CPU time 4.92 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:03 PM PDT 24
Peak memory 200804 kb
Host smart-98895cdd-cc24-4a03-96eb-598b81950bcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265865883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.3265865883
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.4189273279
Short name T754
Test name
Test status
Simulation time 2020723337 ps
CPU time 3.16 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:57:17 PM PDT 24
Peak memory 200708 kb
Host smart-23b252ac-ac13-4190-809b-b27084f8640c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189273279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.4189273279
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2763527168
Short name T562
Test name
Test status
Simulation time 3313304106 ps
CPU time 2.82 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:24 PM PDT 24
Peak memory 200824 kb
Host smart-4c51ce45-6379-4574-89a5-53177f9026a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763527168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2
763527168
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3764375196
Short name T92
Test name
Test status
Simulation time 56984381840 ps
CPU time 63.47 seconds
Started Aug 02 04:57:16 PM PDT 24
Finished Aug 02 04:58:20 PM PDT 24
Peak memory 201068 kb
Host smart-ba0ee946-fcd2-4d58-a454-9f984e5128d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764375196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.3764375196
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.348259112
Short name T198
Test name
Test status
Simulation time 4966380563 ps
CPU time 3.03 seconds
Started Aug 02 04:57:06 PM PDT 24
Finished Aug 02 04:57:09 PM PDT 24
Peak memory 200860 kb
Host smart-8e32b66a-34d7-4166-9a31-3c59a8fa1e64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348259112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_ec_pwr_on_rst.348259112
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1972789557
Short name T190
Test name
Test status
Simulation time 3001859935 ps
CPU time 6.29 seconds
Started Aug 02 04:57:08 PM PDT 24
Finished Aug 02 04:57:14 PM PDT 24
Peak memory 200936 kb
Host smart-ee2b76f9-2d20-4824-a16a-4c579955b456
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972789557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.1972789557
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3725374484
Short name T487
Test name
Test status
Simulation time 2612496148 ps
CPU time 7.37 seconds
Started Aug 02 04:57:16 PM PDT 24
Finished Aug 02 04:57:23 PM PDT 24
Peak memory 200700 kb
Host smart-739421bd-6335-431c-b251-69d4d608bb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725374484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3725374484
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3146597780
Short name T452
Test name
Test status
Simulation time 2472829174 ps
CPU time 7.12 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:05 PM PDT 24
Peak memory 200840 kb
Host smart-f680e52f-2133-4dfd-8d1e-1d2beaf351d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146597780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3146597780
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3822481665
Short name T649
Test name
Test status
Simulation time 2193093959 ps
CPU time 5.92 seconds
Started Aug 02 04:56:58 PM PDT 24
Finished Aug 02 04:57:04 PM PDT 24
Peak memory 200760 kb
Host smart-7fb4d7e3-c737-426e-9e9d-9b4802dc113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822481665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3822481665
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.864874706
Short name T412
Test name
Test status
Simulation time 2539878370 ps
CPU time 2.12 seconds
Started Aug 02 04:57:06 PM PDT 24
Finished Aug 02 04:57:09 PM PDT 24
Peak memory 200836 kb
Host smart-03469c36-55e5-4996-a424-100059f88262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864874706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.864874706
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.2947719621
Short name T642
Test name
Test status
Simulation time 2111850801 ps
CPU time 6.4 seconds
Started Aug 02 04:57:00 PM PDT 24
Finished Aug 02 04:57:06 PM PDT 24
Peak memory 200680 kb
Host smart-260e9ad8-f377-4279-994e-3c11cb93c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947719621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2947719621
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.2278051145
Short name T772
Test name
Test status
Simulation time 72028706755 ps
CPU time 95.51 seconds
Started Aug 02 04:57:05 PM PDT 24
Finished Aug 02 04:58:41 PM PDT 24
Peak memory 201028 kb
Host smart-c10a9357-90d2-48d6-a10e-11d3178f5fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278051145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.2278051145
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.4241018580
Short name T118
Test name
Test status
Simulation time 84576694978 ps
CPU time 54.43 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:58:09 PM PDT 24
Peak memory 209356 kb
Host smart-f32b70a9-dc3d-45f4-9b95-ac2e8f7fa2be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241018580 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.4241018580
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1892608904
Short name T71
Test name
Test status
Simulation time 11255510914 ps
CPU time 1.55 seconds
Started Aug 02 04:57:10 PM PDT 24
Finished Aug 02 04:57:12 PM PDT 24
Peak memory 200916 kb
Host smart-a269d56b-a76c-48e7-a63c-d02ca50f42fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892608904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.1892608904
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.4176198663
Short name T628
Test name
Test status
Simulation time 2014492673 ps
CPU time 5.97 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:27 PM PDT 24
Peak memory 200760 kb
Host smart-0cee86ca-8363-4df8-a7ab-f1443ff1de49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176198663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.4176198663
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2594190136
Short name T457
Test name
Test status
Simulation time 297356620218 ps
CPU time 751.62 seconds
Started Aug 02 04:57:11 PM PDT 24
Finished Aug 02 05:09:43 PM PDT 24
Peak memory 200776 kb
Host smart-656a3169-ad2f-4d46-ae50-d2eef230a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594190136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2
594190136
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3738313187
Short name T334
Test name
Test status
Simulation time 62608261363 ps
CPU time 74.71 seconds
Started Aug 02 04:57:06 PM PDT 24
Finished Aug 02 04:58:21 PM PDT 24
Peak memory 201012 kb
Host smart-1bec795a-d5d9-4069-85df-8f5f0dcd8951
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738313187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.3738313187
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.224553489
Short name T222
Test name
Test status
Simulation time 40016932087 ps
CPU time 45.56 seconds
Started Aug 02 04:57:05 PM PDT 24
Finished Aug 02 04:57:51 PM PDT 24
Peak memory 201156 kb
Host smart-6a0e88c4-2422-494d-b760-2f563c4b823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224553489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_wi
th_pre_cond.224553489
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1360113844
Short name T418
Test name
Test status
Simulation time 2938885424 ps
CPU time 7.81 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:29 PM PDT 24
Peak memory 200744 kb
Host smart-a677dd2a-7009-4d4b-9407-d00a922d4ba7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360113844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.1360113844
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3258765801
Short name T188
Test name
Test status
Simulation time 3119605248 ps
CPU time 8.29 seconds
Started Aug 02 04:57:08 PM PDT 24
Finished Aug 02 04:57:17 PM PDT 24
Peak memory 200860 kb
Host smart-8408127f-bb5a-4729-b973-9fad18b4db7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258765801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3258765801
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1176646486
Short name T368
Test name
Test status
Simulation time 2642378779 ps
CPU time 1.87 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:23 PM PDT 24
Peak memory 200728 kb
Host smart-3dcfc5a1-f24e-4770-a5f6-450b7ba59de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176646486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.1176646486
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2882102654
Short name T793
Test name
Test status
Simulation time 2451361168 ps
CPU time 7.27 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 200760 kb
Host smart-9c703381-4eae-441a-af42-e232482fd9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882102654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2882102654
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3557952957
Short name T208
Test name
Test status
Simulation time 2085738222 ps
CPU time 3.43 seconds
Started Aug 02 04:57:16 PM PDT 24
Finished Aug 02 04:57:19 PM PDT 24
Peak memory 200668 kb
Host smart-4af5bbba-f78e-44f9-813e-8664f60422bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557952957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3557952957
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1076804484
Short name T276
Test name
Test status
Simulation time 2539173154 ps
CPU time 2.37 seconds
Started Aug 02 04:57:07 PM PDT 24
Finished Aug 02 04:57:09 PM PDT 24
Peak memory 200768 kb
Host smart-a87dd759-f5a7-4720-9fe5-dbdf32604da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076804484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1076804484
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.1794705264
Short name T789
Test name
Test status
Simulation time 2109951187 ps
CPU time 5.67 seconds
Started Aug 02 04:57:10 PM PDT 24
Finished Aug 02 04:57:16 PM PDT 24
Peak memory 200740 kb
Host smart-d6a608bf-08a3-49fd-9f53-71c12db14fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794705264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1794705264
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2973237839
Short name T604
Test name
Test status
Simulation time 6554567083 ps
CPU time 4.72 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:57:19 PM PDT 24
Peak memory 200812 kb
Host smart-6ca6122e-11f6-41f6-9c53-05ba2344b261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973237839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2973237839
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.300686380
Short name T481
Test name
Test status
Simulation time 15275088954 ps
CPU time 9.97 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:57:23 PM PDT 24
Peak memory 201160 kb
Host smart-04624468-8fc1-4ecb-8473-27727201cc62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300686380 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.300686380
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.954562379
Short name T113
Test name
Test status
Simulation time 3710155749 ps
CPU time 1.79 seconds
Started Aug 02 04:57:12 PM PDT 24
Finished Aug 02 04:57:14 PM PDT 24
Peak memory 200904 kb
Host smart-448b185c-292a-484e-9e07-9f252e235fb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954562379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ultra_low_pwr.954562379
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.4278563492
Short name T623
Test name
Test status
Simulation time 2026830910 ps
CPU time 1.91 seconds
Started Aug 02 04:57:15 PM PDT 24
Finished Aug 02 04:57:17 PM PDT 24
Peak memory 200728 kb
Host smart-bfc8f41c-4d10-4178-af29-d7dc3e55ba66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278563492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.4278563492
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2933063464
Short name T197
Test name
Test status
Simulation time 96976788016 ps
CPU time 233.73 seconds
Started Aug 02 04:57:12 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 200904 kb
Host smart-36bd24b3-afaf-496a-b349-b82f695430b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933063464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2
933063464
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1153515148
Short name T335
Test name
Test status
Simulation time 151035672389 ps
CPU time 100.5 seconds
Started Aug 02 04:57:10 PM PDT 24
Finished Aug 02 04:58:51 PM PDT 24
Peak memory 201016 kb
Host smart-d7d8daf5-4033-475d-b36d-2d5924192281
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153515148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.1153515148
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1200830216
Short name T74
Test name
Test status
Simulation time 75591576418 ps
CPU time 49.27 seconds
Started Aug 02 04:57:16 PM PDT 24
Finished Aug 02 04:58:05 PM PDT 24
Peak memory 201180 kb
Host smart-7d24da36-1435-4b5e-ba3a-fa91b6cb174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200830216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.1200830216
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1065735969
Short name T396
Test name
Test status
Simulation time 2824840906 ps
CPU time 8.12 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:57:22 PM PDT 24
Peak memory 200704 kb
Host smart-584c6f81-5df3-45a5-9d6d-3f1d1cd4dfd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065735969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.1065735969
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.3633054240
Short name T146
Test name
Test status
Simulation time 3794194690 ps
CPU time 1.33 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:23 PM PDT 24
Peak memory 200852 kb
Host smart-720bcc5b-7684-4813-a18b-5ee232d24102
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633054240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.3633054240
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1436556237
Short name T464
Test name
Test status
Simulation time 2633329851 ps
CPU time 2.29 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:24 PM PDT 24
Peak memory 200760 kb
Host smart-dac4819a-4c7c-4b95-8769-dcd213910025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436556237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1436556237
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3757959031
Short name T424
Test name
Test status
Simulation time 2464754593 ps
CPU time 6.84 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:57:21 PM PDT 24
Peak memory 200808 kb
Host smart-fc34f654-0995-42e9-b044-f200e17f11fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757959031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.3757959031
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.3158442547
Short name T473
Test name
Test status
Simulation time 2034252987 ps
CPU time 5.59 seconds
Started Aug 02 04:57:10 PM PDT 24
Finished Aug 02 04:57:16 PM PDT 24
Peak memory 200740 kb
Host smart-578a6e5e-9416-419a-8307-b1b2eb2feea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158442547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.3158442547
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.3838296944
Short name T746
Test name
Test status
Simulation time 2557509009 ps
CPU time 1.27 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:57:14 PM PDT 24
Peak memory 200708 kb
Host smart-8dda5523-6d01-4399-84ca-030a57ebb686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838296944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3838296944
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.1605540304
Short name T116
Test name
Test status
Simulation time 2108975434 ps
CPU time 5.69 seconds
Started Aug 02 04:57:11 PM PDT 24
Finished Aug 02 04:57:16 PM PDT 24
Peak memory 200636 kb
Host smart-2b4f355e-7297-4735-b93f-9f5293e9517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605540304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.1605540304
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.685649198
Short name T43
Test name
Test status
Simulation time 283819215482 ps
CPU time 154.02 seconds
Started Aug 02 04:57:09 PM PDT 24
Finished Aug 02 04:59:43 PM PDT 24
Peak memory 200960 kb
Host smart-724c779c-cde5-483e-b64d-80dcbd95b899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685649198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_st
ress_all.685649198
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2933430663
Short name T78
Test name
Test status
Simulation time 4753595402 ps
CPU time 3.72 seconds
Started Aug 02 04:57:07 PM PDT 24
Finished Aug 02 04:57:11 PM PDT 24
Peak memory 200800 kb
Host smart-5216e509-6cc8-47de-a4af-1dda8fbd6419
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933430663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2933430663
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3270526419
Short name T355
Test name
Test status
Simulation time 2012368721 ps
CPU time 5.76 seconds
Started Aug 02 04:57:22 PM PDT 24
Finished Aug 02 04:57:33 PM PDT 24
Peak memory 200728 kb
Host smart-f5b8e585-f774-4f48-8f9e-9c38d565afee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270526419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3270526419
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1453901030
Short name T265
Test name
Test status
Simulation time 26727475637 ps
CPU time 66.63 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:58:20 PM PDT 24
Peak memory 200876 kb
Host smart-dd4f6396-cfb3-4006-a163-730220c6a5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453901030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1
453901030
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.127471341
Short name T246
Test name
Test status
Simulation time 96898120875 ps
CPU time 121.26 seconds
Started Aug 02 04:57:12 PM PDT 24
Finished Aug 02 04:59:13 PM PDT 24
Peak memory 201024 kb
Host smart-d49f3bc8-4f81-45ba-875f-d22f3b45906f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127471341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.127471341
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.215314439
Short name T91
Test name
Test status
Simulation time 32665301934 ps
CPU time 81.95 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:58:36 PM PDT 24
Peak memory 201064 kb
Host smart-8320fc94-bb23-4493-9a93-26aac9150be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215314439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wi
th_pre_cond.215314439
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2260413632
Short name T365
Test name
Test status
Simulation time 4412310729 ps
CPU time 11.81 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:33 PM PDT 24
Peak memory 200756 kb
Host smart-f247f1b5-99a0-4d87-80db-5e7cf146014d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260413632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.2260413632
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.3452415912
Short name T178
Test name
Test status
Simulation time 5482218662 ps
CPU time 3.83 seconds
Started Aug 02 04:57:16 PM PDT 24
Finished Aug 02 04:57:20 PM PDT 24
Peak memory 200836 kb
Host smart-b48eaa11-4f5d-4717-93f1-893c36cca845
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452415912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.3452415912
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.359329579
Short name T608
Test name
Test status
Simulation time 2632469005 ps
CPU time 2.18 seconds
Started Aug 02 04:57:07 PM PDT 24
Finished Aug 02 04:57:09 PM PDT 24
Peak memory 200772 kb
Host smart-cc532cfa-1a11-4f5e-a9f5-31ed99b911aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359329579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.359329579
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.657273738
Short name T403
Test name
Test status
Simulation time 2494370646 ps
CPU time 7.18 seconds
Started Aug 02 04:57:09 PM PDT 24
Finished Aug 02 04:57:16 PM PDT 24
Peak memory 200784 kb
Host smart-327349a1-0de5-4352-b1e2-a7209ae09156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657273738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.657273738
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2946757650
Short name T492
Test name
Test status
Simulation time 2030503842 ps
CPU time 5.75 seconds
Started Aug 02 04:57:05 PM PDT 24
Finished Aug 02 04:57:11 PM PDT 24
Peak memory 200768 kb
Host smart-a74e04ee-04b6-4ba3-86f9-aa95290ba6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946757650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2946757650
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2608195351
Short name T100
Test name
Test status
Simulation time 2516501238 ps
CPU time 3.9 seconds
Started Aug 02 04:57:11 PM PDT 24
Finished Aug 02 04:57:15 PM PDT 24
Peak memory 200844 kb
Host smart-a460e535-08f5-4fac-9315-6a0bb8bdd5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608195351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2608195351
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.3568542650
Short name T231
Test name
Test status
Simulation time 2111081007 ps
CPU time 6.15 seconds
Started Aug 02 04:57:15 PM PDT 24
Finished Aug 02 04:57:21 PM PDT 24
Peak memory 200764 kb
Host smart-e896ccde-b2fe-43d5-8078-b842f3fe814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568542650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3568542650
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.543466866
Short name T661
Test name
Test status
Simulation time 17062832991 ps
CPU time 34.4 seconds
Started Aug 02 04:57:15 PM PDT 24
Finished Aug 02 04:57:49 PM PDT 24
Peak memory 200720 kb
Host smart-bbcf60ac-0f3e-4f12-8ae7-55b52b656d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543466866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_st
ress_all.543466866
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.603463299
Short name T131
Test name
Test status
Simulation time 24474350353 ps
CPU time 57.18 seconds
Started Aug 02 04:57:15 PM PDT 24
Finished Aug 02 04:58:13 PM PDT 24
Peak memory 217508 kb
Host smart-87c2141b-2aa8-4a7f-99a0-eea74f80f8dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603463299 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.603463299
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2462276132
Short name T128
Test name
Test status
Simulation time 9319345825 ps
CPU time 2.66 seconds
Started Aug 02 04:57:17 PM PDT 24
Finished Aug 02 04:57:20 PM PDT 24
Peak memory 200876 kb
Host smart-9f6804c2-83cc-47d7-865c-104d038fc18b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462276132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.2462276132
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.706579789
Short name T662
Test name
Test status
Simulation time 2015328685 ps
CPU time 5.11 seconds
Started Aug 02 04:57:16 PM PDT 24
Finished Aug 02 04:57:21 PM PDT 24
Peak memory 200840 kb
Host smart-49000f33-f5a8-4448-8440-905885d2df86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706579789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_tes
t.706579789
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3955495864
Short name T540
Test name
Test status
Simulation time 60075062879 ps
CPU time 33.28 seconds
Started Aug 02 04:57:15 PM PDT 24
Finished Aug 02 04:57:49 PM PDT 24
Peak memory 200772 kb
Host smart-fb188184-47bf-434e-9574-c043f18bc547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955495864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3
955495864
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.746264057
Short name T235
Test name
Test status
Simulation time 194168414429 ps
CPU time 246.89 seconds
Started Aug 02 04:57:18 PM PDT 24
Finished Aug 02 05:01:25 PM PDT 24
Peak memory 201000 kb
Host smart-94bee3d0-75b7-4ed5-aa5b-8b564be1f6b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746264057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.746264057
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2769344199
Short name T308
Test name
Test status
Simulation time 55301669389 ps
CPU time 10.12 seconds
Started Aug 02 04:57:20 PM PDT 24
Finished Aug 02 04:57:31 PM PDT 24
Peak memory 201080 kb
Host smart-76bb4f1d-6166-4f5e-9091-8bc2a410342c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769344199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.2769344199
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.702886593
Short name T371
Test name
Test status
Simulation time 3152946563 ps
CPU time 1.65 seconds
Started Aug 02 04:57:22 PM PDT 24
Finished Aug 02 04:57:24 PM PDT 24
Peak memory 200708 kb
Host smart-f8dc8781-36a7-4af6-80be-bb5269ee5090
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702886593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ec_pwr_on_rst.702886593
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.770804067
Short name T351
Test name
Test status
Simulation time 165273547595 ps
CPU time 11.77 seconds
Started Aug 02 04:57:17 PM PDT 24
Finished Aug 02 04:57:29 PM PDT 24
Peak memory 200868 kb
Host smart-9a867e34-8224-41fb-a527-def86c6ccbd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770804067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctr
l_edge_detect.770804067
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1691150912
Short name T668
Test name
Test status
Simulation time 2628545888 ps
CPU time 2.37 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:57:16 PM PDT 24
Peak memory 200808 kb
Host smart-89b3b419-513a-4d69-a8e4-96ecb959f019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691150912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1691150912
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3671223362
Short name T708
Test name
Test status
Simulation time 2446345797 ps
CPU time 6.84 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:57:20 PM PDT 24
Peak memory 200712 kb
Host smart-4268a7e0-43ca-42ea-bcaf-8c0bb064e760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671223362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3671223362
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1158093814
Short name T400
Test name
Test status
Simulation time 2056438025 ps
CPU time 5.3 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:57:19 PM PDT 24
Peak memory 200700 kb
Host smart-3109a717-356f-4fff-9351-341d2b4a1e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158093814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1158093814
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3649085513
Short name T543
Test name
Test status
Simulation time 2509903753 ps
CPU time 7.01 seconds
Started Aug 02 04:57:12 PM PDT 24
Finished Aug 02 04:57:19 PM PDT 24
Peak memory 200800 kb
Host smart-0a5e8b4b-b60d-44bd-a881-95d4d09b3ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649085513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.3649085513
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.3723530294
Short name T228
Test name
Test status
Simulation time 2132772949 ps
CPU time 1.88 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:57:15 PM PDT 24
Peak memory 200736 kb
Host smart-c0c1e74a-0e2f-4645-bc70-6b65acc3e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723530294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.3723530294
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.83645037
Short name T756
Test name
Test status
Simulation time 9558976295 ps
CPU time 7.07 seconds
Started Aug 02 04:57:20 PM PDT 24
Finished Aug 02 04:57:27 PM PDT 24
Peak memory 200728 kb
Host smart-714575a9-e127-4bbe-aa5b-f05d416e3627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83645037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_str
ess_all.83645037
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.849757740
Short name T454
Test name
Test status
Simulation time 21434428955 ps
CPU time 51.78 seconds
Started Aug 02 04:57:19 PM PDT 24
Finished Aug 02 04:58:11 PM PDT 24
Peak memory 209340 kb
Host smart-c9645242-5d43-41e7-8801-2af29f10775e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849757740 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.849757740
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1459825024
Short name T485
Test name
Test status
Simulation time 3764105020 ps
CPU time 5.7 seconds
Started Aug 02 04:57:16 PM PDT 24
Finished Aug 02 04:57:22 PM PDT 24
Peak memory 200772 kb
Host smart-991d29e9-6d4b-4e84-82e7-b1d83c2e0135
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459825024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.1459825024
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1695847676
Short name T711
Test name
Test status
Simulation time 2040273166 ps
CPU time 1.85 seconds
Started Aug 02 04:57:16 PM PDT 24
Finished Aug 02 04:57:18 PM PDT 24
Peak memory 200780 kb
Host smart-6e9ba8d1-170d-464d-a6fa-7ff3f4fb8ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695847676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1695847676
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2239393197
Short name T643
Test name
Test status
Simulation time 91544504424 ps
CPU time 231.74 seconds
Started Aug 02 04:57:17 PM PDT 24
Finished Aug 02 05:01:09 PM PDT 24
Peak memory 200904 kb
Host smart-fa2c3347-f80f-44c6-85a6-036027de11fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239393197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
239393197
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1914010551
Short name T415
Test name
Test status
Simulation time 3481480305 ps
CPU time 8.76 seconds
Started Aug 02 04:57:19 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 200704 kb
Host smart-e5e4fb18-f1f8-42b6-9532-7536d02d2dd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914010551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.1914010551
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.918930576
Short name T191
Test name
Test status
Simulation time 2478740479 ps
CPU time 2.17 seconds
Started Aug 02 04:57:12 PM PDT 24
Finished Aug 02 04:57:14 PM PDT 24
Peak memory 200864 kb
Host smart-9920993d-229f-4371-b83d-86c27e5af549
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918930576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctr
l_edge_detect.918930576
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.4025021957
Short name T688
Test name
Test status
Simulation time 2636865043 ps
CPU time 1.79 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:57:15 PM PDT 24
Peak memory 200772 kb
Host smart-6f2e7744-fb5c-4450-9209-5d88140ee626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025021957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.4025021957
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.897570089
Short name T705
Test name
Test status
Simulation time 2475280725 ps
CPU time 2.48 seconds
Started Aug 02 04:57:19 PM PDT 24
Finished Aug 02 04:57:21 PM PDT 24
Peak memory 200828 kb
Host smart-7a3b8b66-4b0e-4074-9f01-7e090a11f377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897570089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.897570089
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1829878749
Short name T450
Test name
Test status
Simulation time 2289062497 ps
CPU time 1.97 seconds
Started Aug 02 04:57:19 PM PDT 24
Finished Aug 02 04:57:21 PM PDT 24
Peak memory 200752 kb
Host smart-da05805c-1be8-4637-80ed-f48a6a44d13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829878749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.1829878749
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3853279440
Short name T563
Test name
Test status
Simulation time 2513867162 ps
CPU time 7.21 seconds
Started Aug 02 04:57:18 PM PDT 24
Finished Aug 02 04:57:25 PM PDT 24
Peak memory 200652 kb
Host smart-2dd23c32-896d-4cf3-b1cf-9f08c6947b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853279440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3853279440
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.987719439
Short name T364
Test name
Test status
Simulation time 2141360863 ps
CPU time 1.31 seconds
Started Aug 02 04:57:12 PM PDT 24
Finished Aug 02 04:57:13 PM PDT 24
Peak memory 200672 kb
Host smart-424e9c0c-fc6c-4aa0-a270-aea7504588f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987719439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.987719439
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.3042630313
Short name T655
Test name
Test status
Simulation time 6800471265 ps
CPU time 2.6 seconds
Started Aug 02 04:57:13 PM PDT 24
Finished Aug 02 04:57:16 PM PDT 24
Peak memory 200784 kb
Host smart-bdbab397-f7d4-41c7-bbca-36e353a40f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042630313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.3042630313
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2484572374
Short name T199
Test name
Test status
Simulation time 58842382559 ps
CPU time 40.34 seconds
Started Aug 02 04:57:12 PM PDT 24
Finished Aug 02 04:57:52 PM PDT 24
Peak memory 217596 kb
Host smart-5215e214-7d1a-46ed-b41a-e7ced5c9ebdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484572374 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2484572374
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2850200629
Short name T753
Test name
Test status
Simulation time 12707129269 ps
CPU time 3.87 seconds
Started Aug 02 04:57:14 PM PDT 24
Finished Aug 02 04:57:18 PM PDT 24
Peak memory 200800 kb
Host smart-74ca28bc-8013-43bb-90c2-cd3f5153656a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850200629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2850200629
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3774670429
Short name T425
Test name
Test status
Simulation time 2043147912 ps
CPU time 1.88 seconds
Started Aug 02 04:57:23 PM PDT 24
Finished Aug 02 04:57:25 PM PDT 24
Peak memory 200844 kb
Host smart-2e070da5-adfa-4326-a885-7b59ff171b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774670429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3774670429
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3278078418
Short name T16
Test name
Test status
Simulation time 3372614438 ps
CPU time 1.84 seconds
Started Aug 02 04:57:24 PM PDT 24
Finished Aug 02 04:57:26 PM PDT 24
Peak memory 200808 kb
Host smart-3723ff78-7ba6-41e8-b9e6-314e420e0681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278078418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3
278078418
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2841487594
Short name T220
Test name
Test status
Simulation time 25610042536 ps
CPU time 17.88 seconds
Started Aug 02 04:57:20 PM PDT 24
Finished Aug 02 04:57:38 PM PDT 24
Peak memory 201080 kb
Host smart-a1abf591-a0fb-40d8-ae88-81369bd5e779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841487594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.2841487594
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3033447869
Short name T645
Test name
Test status
Simulation time 4126718266 ps
CPU time 5.44 seconds
Started Aug 02 04:57:24 PM PDT 24
Finished Aug 02 04:57:30 PM PDT 24
Peak memory 200812 kb
Host smart-6723d37b-28be-43bf-8cd7-a05f3177d56f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033447869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.3033447869
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.685156215
Short name T213
Test name
Test status
Simulation time 358274013935 ps
CPU time 855.5 seconds
Started Aug 02 04:57:20 PM PDT 24
Finished Aug 02 05:11:36 PM PDT 24
Peak memory 200804 kb
Host smart-ef7c2e85-0f7e-4efb-9663-86c896f78605
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685156215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctr
l_edge_detect.685156215
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3365437150
Short name T693
Test name
Test status
Simulation time 2652814167 ps
CPU time 1.49 seconds
Started Aug 02 04:57:23 PM PDT 24
Finished Aug 02 04:57:25 PM PDT 24
Peak memory 200852 kb
Host smart-bbdcb6ea-1dc2-40bb-a91c-9b8aa28cb513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365437150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3365437150
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1480199599
Short name T667
Test name
Test status
Simulation time 2486867292 ps
CPU time 2.07 seconds
Started Aug 02 04:57:19 PM PDT 24
Finished Aug 02 04:57:21 PM PDT 24
Peak memory 200752 kb
Host smart-4756b970-5dc7-446e-bbbf-8992a16e6c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480199599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1480199599
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2062243491
Short name T568
Test name
Test status
Simulation time 2259166254 ps
CPU time 1.21 seconds
Started Aug 02 04:57:18 PM PDT 24
Finished Aug 02 04:57:20 PM PDT 24
Peak memory 200880 kb
Host smart-877acfd2-f6f8-4db0-85cb-9d4a7112a1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062243491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.2062243491
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2532767611
Short name T692
Test name
Test status
Simulation time 2511558123 ps
CPU time 7.03 seconds
Started Aug 02 04:57:25 PM PDT 24
Finished Aug 02 04:57:32 PM PDT 24
Peak memory 200844 kb
Host smart-eb349cc7-f316-4852-bc51-6fb36447b876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532767611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.2532767611
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.3024821755
Short name T103
Test name
Test status
Simulation time 2157495912 ps
CPU time 1.32 seconds
Started Aug 02 04:57:15 PM PDT 24
Finished Aug 02 04:57:16 PM PDT 24
Peak memory 200668 kb
Host smart-194ced7c-9b4f-43e8-ac43-8af5401122f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024821755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.3024821755
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.881724146
Short name T127
Test name
Test status
Simulation time 15838197584 ps
CPU time 7.95 seconds
Started Aug 02 04:57:23 PM PDT 24
Finished Aug 02 04:57:31 PM PDT 24
Peak memory 200896 kb
Host smart-2929f338-c2db-44af-97a1-aec0e0454c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881724146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.881724146
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2017448798
Short name T353
Test name
Test status
Simulation time 1182096674712 ps
CPU time 20.66 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:41 PM PDT 24
Peak memory 200900 kb
Host smart-0a1441fc-758d-46c0-86c3-89172a03d630
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017448798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.2017448798
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.2331744614
Short name T406
Test name
Test status
Simulation time 2031784304 ps
CPU time 1.95 seconds
Started Aug 02 04:57:26 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 200708 kb
Host smart-9fc85a06-64a5-4c3f-a288-eedfe32b8bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331744614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.2331744614
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.261933886
Short name T569
Test name
Test status
Simulation time 3709528457 ps
CPU time 1.14 seconds
Started Aug 02 04:57:26 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 200756 kb
Host smart-e393647a-e142-47dc-ac0a-cc56f37c0ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261933886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.261933886
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.4286304455
Short name T310
Test name
Test status
Simulation time 163482688983 ps
CPU time 102.36 seconds
Started Aug 02 04:57:23 PM PDT 24
Finished Aug 02 04:59:06 PM PDT 24
Peak memory 200936 kb
Host smart-adcfc99a-9374-482a-b855-a767d92e27a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286304455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.4286304455
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1137747210
Short name T170
Test name
Test status
Simulation time 2704313837 ps
CPU time 8.03 seconds
Started Aug 02 04:57:20 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 200776 kb
Host smart-587e9828-c182-47a4-8c88-492056a0217e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137747210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.1137747210
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.1440220460
Short name T37
Test name
Test status
Simulation time 4104961595 ps
CPU time 2.84 seconds
Started Aug 02 04:57:37 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200788 kb
Host smart-e1743b1e-65b0-4d03-90ba-fe1937838fb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440220460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.1440220460
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.333196966
Short name T435
Test name
Test status
Simulation time 2615865421 ps
CPU time 4.1 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:26 PM PDT 24
Peak memory 200876 kb
Host smart-195cdcde-db49-49a1-95bd-36928c9d4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333196966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.333196966
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.1666934690
Short name T764
Test name
Test status
Simulation time 2471727316 ps
CPU time 3.31 seconds
Started Aug 02 04:57:23 PM PDT 24
Finished Aug 02 04:57:27 PM PDT 24
Peak memory 200848 kb
Host smart-d97755d2-5887-416b-8aee-d41468b62632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666934690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.1666934690
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2539190341
Short name T594
Test name
Test status
Simulation time 2119397597 ps
CPU time 5.65 seconds
Started Aug 02 04:57:22 PM PDT 24
Finished Aug 02 04:57:27 PM PDT 24
Peak memory 200736 kb
Host smart-220c980d-3f26-46b8-a3d4-9bd6705a0967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539190341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2539190341
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.566597634
Short name T511
Test name
Test status
Simulation time 2559504085 ps
CPU time 1.58 seconds
Started Aug 02 04:57:21 PM PDT 24
Finished Aug 02 04:57:22 PM PDT 24
Peak memory 200760 kb
Host smart-f8cce8f8-1edc-48a4-abca-5cbf2b721ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566597634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.566597634
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.2883306757
Short name T749
Test name
Test status
Simulation time 2114330042 ps
CPU time 3.49 seconds
Started Aug 02 04:57:23 PM PDT 24
Finished Aug 02 04:57:26 PM PDT 24
Peak memory 200628 kb
Host smart-6e13faf1-8f78-4c70-9f99-c18cf3d1cc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883306757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.2883306757
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.1395936103
Short name T238
Test name
Test status
Simulation time 91610297211 ps
CPU time 28.82 seconds
Started Aug 02 04:57:27 PM PDT 24
Finished Aug 02 04:57:56 PM PDT 24
Peak memory 201100 kb
Host smart-a7442010-9cdb-410d-96bd-1cfb733d4108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395936103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.1395936103
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2209047321
Short name T673
Test name
Test status
Simulation time 6577190165 ps
CPU time 6.86 seconds
Started Aug 02 04:57:23 PM PDT 24
Finished Aug 02 04:57:30 PM PDT 24
Peak memory 200892 kb
Host smart-98285cda-5bd1-4322-a002-de5b6de170e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209047321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.2209047321
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.4170197870
Short name T669
Test name
Test status
Simulation time 2046275828 ps
CPU time 1.85 seconds
Started Aug 02 04:55:56 PM PDT 24
Finished Aug 02 04:55:58 PM PDT 24
Peak memory 200812 kb
Host smart-af1a8324-f68a-4503-9e49-c635dec702dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170197870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.4170197870
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2006315523
Short name T24
Test name
Test status
Simulation time 3513752817 ps
CPU time 2.66 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 200896 kb
Host smart-082c2df4-dc5e-4aea-b3c7-542c9c46f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006315523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2006315523
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3075186940
Short name T657
Test name
Test status
Simulation time 2446911202 ps
CPU time 2.12 seconds
Started Aug 02 04:56:04 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 200848 kb
Host smart-056e2869-25bd-4380-87df-277956a8c575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075186940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.3075186940
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1163303443
Short name T221
Test name
Test status
Simulation time 2549986632 ps
CPU time 2.29 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 200784 kb
Host smart-1c3e7114-6989-48b6-9ea4-dfa9d07d83f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163303443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1163303443
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3513602828
Short name T616
Test name
Test status
Simulation time 32623658404 ps
CPU time 43.18 seconds
Started Aug 02 04:56:04 PM PDT 24
Finished Aug 02 04:56:47 PM PDT 24
Peak memory 201136 kb
Host smart-3821fd9e-4034-4ff8-8592-412332fcb0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513602828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3513602828
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1633026497
Short name T477
Test name
Test status
Simulation time 862827193716 ps
CPU time 910.96 seconds
Started Aug 02 04:56:01 PM PDT 24
Finished Aug 02 05:11:12 PM PDT 24
Peak memory 200816 kb
Host smart-af8eec07-58d2-4a27-ae5f-3de32359c171
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633026497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1633026497
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1881014289
Short name T186
Test name
Test status
Simulation time 3886695949 ps
CPU time 1.88 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:05 PM PDT 24
Peak memory 200860 kb
Host smart-355a2925-d129-46dd-b408-b5d3dbbb4b19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881014289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.1881014289
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1136525978
Short name T360
Test name
Test status
Simulation time 2631558159 ps
CPU time 1.85 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 200752 kb
Host smart-c65f970d-b63c-49c5-9d3d-90a4b62325f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136525978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.1136525978
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2217047233
Short name T495
Test name
Test status
Simulation time 2447908166 ps
CPU time 7.57 seconds
Started Aug 02 04:55:52 PM PDT 24
Finished Aug 02 04:56:00 PM PDT 24
Peak memory 200816 kb
Host smart-0c1dca91-d8de-41b7-9b9c-ad6dc5c53506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217047233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.2217047233
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1386319275
Short name T226
Test name
Test status
Simulation time 2111663897 ps
CPU time 5.81 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 200668 kb
Host smart-eca975c9-da08-4c8e-b996-df527d31b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386319275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1386319275
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1132929497
Short name T46
Test name
Test status
Simulation time 2510072120 ps
CPU time 6.97 seconds
Started Aug 02 04:56:04 PM PDT 24
Finished Aug 02 04:56:11 PM PDT 24
Peak memory 200756 kb
Host smart-a849ae5d-0dcd-4a3d-8c4c-d361ecb933ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132929497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1132929497
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.2698164817
Short name T479
Test name
Test status
Simulation time 2123038034 ps
CPU time 3.09 seconds
Started Aug 02 04:55:50 PM PDT 24
Finished Aug 02 04:55:54 PM PDT 24
Peak memory 200708 kb
Host smart-d151af2b-8976-405c-9d1b-8a02c4a05376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698164817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2698164817
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3157704959
Short name T314
Test name
Test status
Simulation time 124786175130 ps
CPU time 48.34 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:51 PM PDT 24
Peak memory 201036 kb
Host smart-ef453927-c3bd-4e2a-9b99-cd07611a1a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157704959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3157704959
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3809740250
Short name T39
Test name
Test status
Simulation time 37581610190 ps
CPU time 52.54 seconds
Started Aug 02 04:55:56 PM PDT 24
Finished Aug 02 04:56:49 PM PDT 24
Peak memory 217612 kb
Host smart-4d5c91a4-c36a-4e7b-a67e-ba307cf7576f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809740250 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.3809740250
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.4073120651
Short name T437
Test name
Test status
Simulation time 5022488060 ps
CPU time 1.92 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 200904 kb
Host smart-7bd0d3a6-74eb-4e5d-bce4-01e962d2cc82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073120651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.4073120651
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.936102688
Short name T284
Test name
Test status
Simulation time 2011085450 ps
CPU time 5.53 seconds
Started Aug 02 04:57:27 PM PDT 24
Finished Aug 02 04:57:32 PM PDT 24
Peak memory 200728 kb
Host smart-f990cbd8-1f7e-401c-8852-10b33de53e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936102688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.936102688
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4030647891
Short name T612
Test name
Test status
Simulation time 4054985443 ps
CPU time 1.28 seconds
Started Aug 02 04:57:22 PM PDT 24
Finished Aug 02 04:57:24 PM PDT 24
Peak memory 200804 kb
Host smart-fdcbcef0-3a48-4b15-aa72-524f9272a5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030647891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.4
030647891
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.262209700
Short name T242
Test name
Test status
Simulation time 117264412290 ps
CPU time 40.92 seconds
Started Aug 02 04:57:27 PM PDT 24
Finished Aug 02 04:58:08 PM PDT 24
Peak memory 200944 kb
Host smart-7920ca77-765c-4185-96a4-b840e2c34fa1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262209700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_combo_detect.262209700
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.165925342
Short name T524
Test name
Test status
Simulation time 26834759227 ps
CPU time 65.98 seconds
Started Aug 02 04:57:26 PM PDT 24
Finished Aug 02 04:58:32 PM PDT 24
Peak memory 201048 kb
Host smart-5133d424-c10b-49a5-907b-52395a5c03a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165925342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_wi
th_pre_cond.165925342
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2942771879
Short name T505
Test name
Test status
Simulation time 3131625648 ps
CPU time 8.32 seconds
Started Aug 02 04:57:24 PM PDT 24
Finished Aug 02 04:57:32 PM PDT 24
Peak memory 200712 kb
Host smart-8a32371d-43c8-4358-8c77-e79c853e0abf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942771879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.2942771879
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.739090625
Short name T179
Test name
Test status
Simulation time 2515532921 ps
CPU time 4.43 seconds
Started Aug 02 04:57:22 PM PDT 24
Finished Aug 02 04:57:27 PM PDT 24
Peak memory 200824 kb
Host smart-955125e5-b85d-46ee-b2d5-5c20a6593bc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739090625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctr
l_edge_detect.739090625
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3916367926
Short name T156
Test name
Test status
Simulation time 2610992989 ps
CPU time 6.46 seconds
Started Aug 02 04:57:20 PM PDT 24
Finished Aug 02 04:57:26 PM PDT 24
Peak memory 200764 kb
Host smart-b86d7885-c9ac-47fe-9be4-92b9da0cdb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916367926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3916367926
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1444493628
Short name T18
Test name
Test status
Simulation time 2462603101 ps
CPU time 4.2 seconds
Started Aug 02 04:57:23 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 200812 kb
Host smart-3ce49ca7-9829-4787-a255-48ec207e8140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444493628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1444493628
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3413498278
Short name T565
Test name
Test status
Simulation time 2102160279 ps
CPU time 5.5 seconds
Started Aug 02 04:57:24 PM PDT 24
Finished Aug 02 04:57:30 PM PDT 24
Peak memory 200748 kb
Host smart-3cea6b02-b223-44d9-8e36-58b8bf7bb29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413498278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.3413498278
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2033947089
Short name T504
Test name
Test status
Simulation time 2515937884 ps
CPU time 4.01 seconds
Started Aug 02 04:57:31 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 200808 kb
Host smart-c2daa37b-764a-45c8-a733-6c15a64f5f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033947089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2033947089
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.1481316436
Short name T502
Test name
Test status
Simulation time 2154548824 ps
CPU time 1.44 seconds
Started Aug 02 04:57:26 PM PDT 24
Finished Aug 02 04:57:28 PM PDT 24
Peak memory 200832 kb
Host smart-00b3cc4a-293f-4d94-9c6e-d548d205cb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481316436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.1481316436
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.4206747263
Short name T352
Test name
Test status
Simulation time 2219981059082 ps
CPU time 325.63 seconds
Started Aug 02 04:57:45 PM PDT 24
Finished Aug 02 05:03:11 PM PDT 24
Peak memory 200780 kb
Host smart-76bea26e-f2d7-411c-86bd-e79e43bf22c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206747263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.4206747263
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2273599546
Short name T557
Test name
Test status
Simulation time 5111682317 ps
CPU time 2.09 seconds
Started Aug 02 04:57:22 PM PDT 24
Finished Aug 02 04:57:24 PM PDT 24
Peak memory 200828 kb
Host smart-99bab099-0aad-47b3-9c3c-7dd41eca3714
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273599546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.2273599546
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.120474586
Short name T523
Test name
Test status
Simulation time 2010573459 ps
CPU time 5.72 seconds
Started Aug 02 04:57:27 PM PDT 24
Finished Aug 02 04:57:33 PM PDT 24
Peak memory 200744 kb
Host smart-aeeb5a3a-ff2e-41a1-a691-4dad9b1a270b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120474586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_tes
t.120474586
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.102457072
Short name T521
Test name
Test status
Simulation time 3623723717 ps
CPU time 1.42 seconds
Started Aug 02 04:57:30 PM PDT 24
Finished Aug 02 04:57:32 PM PDT 24
Peak memory 200804 kb
Host smart-56a70cda-56ba-4261-bf15-88f0c08a5d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102457072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.102457072
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3853928039
Short name T660
Test name
Test status
Simulation time 137987421573 ps
CPU time 375.94 seconds
Started Aug 02 04:57:30 PM PDT 24
Finished Aug 02 05:03:46 PM PDT 24
Peak memory 201048 kb
Host smart-dfade819-ba20-4045-b4fd-afc9c1338a4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853928039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.3853928039
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.560184738
Short name T625
Test name
Test status
Simulation time 24828615589 ps
CPU time 63.85 seconds
Started Aug 02 04:57:31 PM PDT 24
Finished Aug 02 04:58:35 PM PDT 24
Peak memory 201140 kb
Host smart-63690f01-476a-416b-97ac-e7d509bd9e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560184738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_wi
th_pre_cond.560184738
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2853854186
Short name T53
Test name
Test status
Simulation time 2409731210 ps
CPU time 3.55 seconds
Started Aug 02 04:57:30 PM PDT 24
Finished Aug 02 04:57:34 PM PDT 24
Peak memory 200764 kb
Host smart-d48ab6b9-0e7c-42e0-80cf-e142249dbfc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853854186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.2853854186
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3249500120
Short name T469
Test name
Test status
Simulation time 2916075878 ps
CPU time 1.48 seconds
Started Aug 02 04:57:29 PM PDT 24
Finished Aug 02 04:57:31 PM PDT 24
Peak memory 200772 kb
Host smart-5f9c2733-425b-4c1d-9491-7fc8f69bb393
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249500120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.3249500120
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1136929043
Short name T742
Test name
Test status
Simulation time 2614068818 ps
CPU time 6.1 seconds
Started Aug 02 04:57:30 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 200768 kb
Host smart-7d24b3f4-d949-4e8d-ba8f-aca7a7ac2626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136929043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1136929043
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.4125766757
Short name T509
Test name
Test status
Simulation time 2536811631 ps
CPU time 1.25 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:29 PM PDT 24
Peak memory 200772 kb
Host smart-822f8daf-b8e1-4962-879c-eea691e7efcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125766757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.4125766757
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2072828753
Short name T209
Test name
Test status
Simulation time 2124189989 ps
CPU time 1.92 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:57:35 PM PDT 24
Peak memory 200632 kb
Host smart-abffb658-861a-481a-ab14-ba3acec3e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072828753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2072828753
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.301462110
Short name T489
Test name
Test status
Simulation time 2561281188 ps
CPU time 1.53 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:30 PM PDT 24
Peak memory 200772 kb
Host smart-440fc30f-22f7-436f-920e-db2fe47733a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301462110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.301462110
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1453662043
Short name T633
Test name
Test status
Simulation time 2112976528 ps
CPU time 5.65 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:34 PM PDT 24
Peak memory 200636 kb
Host smart-e4b2e3ad-1b97-4418-87eb-6e936104ef94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453662043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1453662043
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.4272699932
Short name T516
Test name
Test status
Simulation time 8025773342 ps
CPU time 22.14 seconds
Started Aug 02 04:57:27 PM PDT 24
Finished Aug 02 04:57:50 PM PDT 24
Peak memory 200924 kb
Host smart-e8ac5511-b2b8-4e19-8d71-56dd63bdce28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272699932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.4272699932
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3773162447
Short name T547
Test name
Test status
Simulation time 6567566969 ps
CPU time 4.4 seconds
Started Aug 02 04:57:29 PM PDT 24
Finished Aug 02 04:57:33 PM PDT 24
Peak memory 200828 kb
Host smart-29280d90-1a67-452c-9a4a-cc9e4f2fddda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773162447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.3773162447
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.1577886288
Short name T441
Test name
Test status
Simulation time 2047292563 ps
CPU time 1.83 seconds
Started Aug 02 04:57:35 PM PDT 24
Finished Aug 02 04:57:37 PM PDT 24
Peak memory 200804 kb
Host smart-568428bb-dfd7-45a4-ae74-a1b789f26f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577886288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.1577886288
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.4192516609
Short name T427
Test name
Test status
Simulation time 63881385503 ps
CPU time 39.88 seconds
Started Aug 02 04:57:27 PM PDT 24
Finished Aug 02 04:58:07 PM PDT 24
Peak memory 200908 kb
Host smart-5e9bdc16-16c0-4d5d-ba0a-653e894a3917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192516609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.4
192516609
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.2856712571
Short name T316
Test name
Test status
Simulation time 84098996049 ps
CPU time 49.85 seconds
Started Aug 02 04:57:31 PM PDT 24
Finished Aug 02 04:58:21 PM PDT 24
Peak memory 200960 kb
Host smart-a61bcac5-ace2-4ed0-9b36-b9d4c622f8f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856712571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.2856712571
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3098208794
Short name T224
Test name
Test status
Simulation time 85325754406 ps
CPU time 53.06 seconds
Started Aug 02 04:57:27 PM PDT 24
Finished Aug 02 04:58:20 PM PDT 24
Peak memory 201028 kb
Host smart-a435e634-6408-4c93-a5c2-14cca0f7fdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098208794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.3098208794
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.594668629
Short name T395
Test name
Test status
Simulation time 3081240758 ps
CPU time 7.81 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 200840 kb
Host smart-7e071994-1a2c-437f-8bcd-ec56685bf1d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594668629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.594668629
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.669476715
Short name T780
Test name
Test status
Simulation time 461665059134 ps
CPU time 555.69 seconds
Started Aug 02 04:57:29 PM PDT 24
Finished Aug 02 05:06:45 PM PDT 24
Peak memory 200796 kb
Host smart-074e9928-fabc-4632-af9e-364f187c557a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669476715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctr
l_edge_detect.669476715
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.4064894856
Short name T787
Test name
Test status
Simulation time 2611772417 ps
CPU time 7.48 seconds
Started Aug 02 04:57:32 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200740 kb
Host smart-d3c140da-d2f3-4824-b267-09fe1a7eaee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064894856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.4064894856
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2263434028
Short name T734
Test name
Test status
Simulation time 2466451788 ps
CPU time 3.56 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:31 PM PDT 24
Peak memory 200804 kb
Host smart-2da1064b-0faa-4f2d-9904-f60b23268e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263434028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.2263434028
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3022198287
Short name T573
Test name
Test status
Simulation time 2261579564 ps
CPU time 2.08 seconds
Started Aug 02 04:57:32 PM PDT 24
Finished Aug 02 04:57:34 PM PDT 24
Peak memory 200796 kb
Host smart-40bd3f59-8075-472b-8a49-abf002c7be7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022198287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3022198287
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.365508045
Short name T730
Test name
Test status
Simulation time 2511782020 ps
CPU time 6.88 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200764 kb
Host smart-b51e7420-da2a-4f9c-9f34-b9f8e8e160ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365508045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.365508045
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.3230645125
Short name T500
Test name
Test status
Simulation time 2125546501 ps
CPU time 2.19 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:31 PM PDT 24
Peak memory 200732 kb
Host smart-768f3f69-a65e-4a12-b8e7-67445b64fb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230645125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.3230645125
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.661587145
Short name T216
Test name
Test status
Simulation time 134773560144 ps
CPU time 344.57 seconds
Started Aug 02 04:57:43 PM PDT 24
Finished Aug 02 05:03:28 PM PDT 24
Peak memory 200964 kb
Host smart-7a927e6e-f3ab-477c-b0c5-3e55b10564c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661587145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_st
ress_all.661587145
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2150376412
Short name T166
Test name
Test status
Simulation time 28499006864 ps
CPU time 68.31 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:58:42 PM PDT 24
Peak memory 209360 kb
Host smart-70d76682-714b-461a-b1d2-28dc672f4d6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150376412 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2150376412
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.1451887187
Short name T768
Test name
Test status
Simulation time 2040159982 ps
CPU time 1.97 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:30 PM PDT 24
Peak memory 200804 kb
Host smart-785ffa0a-daf3-4a89-9023-18c4d8715f18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451887187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.1451887187
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.681679613
Short name T707
Test name
Test status
Simulation time 109526123373 ps
CPU time 133.04 seconds
Started Aug 02 04:57:26 PM PDT 24
Finished Aug 02 04:59:39 PM PDT 24
Peak memory 200876 kb
Host smart-9e30e6c7-c25c-4568-aaf8-bf1993007a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681679613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.681679613
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1279393930
Short name T656
Test name
Test status
Simulation time 177748385057 ps
CPU time 437.46 seconds
Started Aug 02 04:57:29 PM PDT 24
Finished Aug 02 05:04:46 PM PDT 24
Peak memory 200924 kb
Host smart-31d5b6c2-cb4d-40c4-962a-45413dc750f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279393930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1279393930
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1462263952
Short name T721
Test name
Test status
Simulation time 3429875563 ps
CPU time 8.96 seconds
Started Aug 02 04:57:31 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200812 kb
Host smart-17a34d42-46ef-4e7c-a0c5-b1e354428fc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462263952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.1462263952
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.1278612284
Short name T670
Test name
Test status
Simulation time 4187777165 ps
CPU time 4.87 seconds
Started Aug 02 04:57:31 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 200832 kb
Host smart-04c9a8d3-a472-481c-aa4b-333d7c872a01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278612284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.1278612284
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3609469928
Short name T755
Test name
Test status
Simulation time 2617398847 ps
CPU time 3.78 seconds
Started Aug 02 04:57:29 PM PDT 24
Finished Aug 02 04:57:33 PM PDT 24
Peak memory 200684 kb
Host smart-b5a3f37f-cbf2-4a7f-a9cc-485ffa1b5382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609469928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.3609469928
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3318361463
Short name T791
Test name
Test status
Simulation time 2472191361 ps
CPU time 2.32 seconds
Started Aug 02 04:57:31 PM PDT 24
Finished Aug 02 04:57:34 PM PDT 24
Peak memory 200764 kb
Host smart-ba4d73f5-c601-4253-add4-ac1f3f2fd58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318361463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3318361463
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1207299673
Short name T14
Test name
Test status
Simulation time 2196086973 ps
CPU time 2.21 seconds
Started Aug 02 04:57:31 PM PDT 24
Finished Aug 02 04:57:34 PM PDT 24
Peak memory 200748 kb
Host smart-3b42209b-50b7-42bb-9c0c-82eb5dca0019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207299673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.1207299673
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3265063244
Short name T60
Test name
Test status
Simulation time 2570082244 ps
CPU time 1.32 seconds
Started Aug 02 04:57:30 PM PDT 24
Finished Aug 02 04:57:31 PM PDT 24
Peak memory 200740 kb
Host smart-6b19d545-3e40-4e2f-bcd7-2979b986ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265063244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3265063244
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.3570780844
Short name T409
Test name
Test status
Simulation time 2111179743 ps
CPU time 5.91 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:57:39 PM PDT 24
Peak memory 200632 kb
Host smart-eb3523f6-c508-43a1-b32a-1be1a1923051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570780844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.3570780844
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.1997795192
Short name T719
Test name
Test status
Simulation time 19629388857 ps
CPU time 37.69 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:58:10 PM PDT 24
Peak memory 200828 kb
Host smart-5f3ec7a4-eb1a-4b4a-8b40-00016b9e667c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997795192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.1997795192
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.534613469
Short name T723
Test name
Test status
Simulation time 36555744837 ps
CPU time 46.33 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:58:15 PM PDT 24
Peak memory 209368 kb
Host smart-09c6099f-1b91-49f4-a6fb-f0db589b90bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534613469 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.534613469
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4138000182
Short name T11
Test name
Test status
Simulation time 8492436864 ps
CPU time 2.36 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:30 PM PDT 24
Peak memory 200892 kb
Host smart-8e19c007-8fe9-495a-9388-7acd949f2ab5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138000182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.4138000182
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.809265489
Short name T463
Test name
Test status
Simulation time 2026899367 ps
CPU time 2.22 seconds
Started Aug 02 04:58:25 PM PDT 24
Finished Aug 02 04:58:28 PM PDT 24
Peak memory 199852 kb
Host smart-a2f71e26-dd33-4ad1-ae14-f3d6417c22fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809265489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_tes
t.809265489
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4035458595
Short name T75
Test name
Test status
Simulation time 3148891605 ps
CPU time 1.62 seconds
Started Aug 02 04:57:36 PM PDT 24
Finished Aug 02 04:57:37 PM PDT 24
Peak memory 200904 kb
Host smart-eee2f0fb-4aa8-444f-8e45-ffc04852f5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035458595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.4
035458595
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1225915656
Short name T766
Test name
Test status
Simulation time 76906455592 ps
CPU time 198.85 seconds
Started Aug 02 04:57:37 PM PDT 24
Finished Aug 02 05:00:56 PM PDT 24
Peak memory 201012 kb
Host smart-2dbf80ae-9370-40ac-97c0-4f2c376756b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225915656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.1225915656
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3453592188
Short name T748
Test name
Test status
Simulation time 3921418186 ps
CPU time 9.63 seconds
Started Aug 02 04:57:47 PM PDT 24
Finished Aug 02 04:57:57 PM PDT 24
Peak memory 200720 kb
Host smart-0a101c64-daea-49ef-846d-6f73b9aab2a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453592188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.3453592188
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3644063435
Short name T134
Test name
Test status
Simulation time 4034485843 ps
CPU time 8.49 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:37 PM PDT 24
Peak memory 200832 kb
Host smart-8112339c-e721-492c-8fa4-36b99d32af01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644063435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3644063435
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1830141187
Short name T513
Test name
Test status
Simulation time 2633761525 ps
CPU time 2.35 seconds
Started Aug 02 04:57:30 PM PDT 24
Finished Aug 02 04:57:32 PM PDT 24
Peak memory 200748 kb
Host smart-e3016ae2-2dd7-4315-8b9a-c7f3fe3d14df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830141187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1830141187
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1009688422
Short name T4
Test name
Test status
Simulation time 2479180903 ps
CPU time 2.45 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 200752 kb
Host smart-400db4ea-e2e5-4cbe-b7c9-4397603a1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009688422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1009688422
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4093269757
Short name T785
Test name
Test status
Simulation time 2226581001 ps
CPU time 6.56 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200760 kb
Host smart-f247e418-d1a8-4da7-a75f-d3d727549108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093269757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.4093269757
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2365063780
Short name T650
Test name
Test status
Simulation time 2516497276 ps
CPU time 4.08 seconds
Started Aug 02 04:57:28 PM PDT 24
Finished Aug 02 04:57:32 PM PDT 24
Peak memory 200788 kb
Host smart-d6690a19-8843-4260-9b75-53d562abe4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365063780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2365063780
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.3513381281
Short name T482
Test name
Test status
Simulation time 2112393765 ps
CPU time 3.04 seconds
Started Aug 02 04:57:31 PM PDT 24
Finished Aug 02 04:57:34 PM PDT 24
Peak memory 200680 kb
Host smart-1f99c65a-40b0-4275-8152-fe61ff23424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513381281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3513381281
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.3688886415
Short name T354
Test name
Test status
Simulation time 3144367978352 ps
CPU time 3390.58 seconds
Started Aug 02 04:57:29 PM PDT 24
Finished Aug 02 05:54:00 PM PDT 24
Peak memory 200788 kb
Host smart-d037a62f-4c7b-4d00-9a30-c28c5be9b50e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688886415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.3688886415
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1311615851
Short name T129
Test name
Test status
Simulation time 4735677953 ps
CPU time 1.57 seconds
Started Aug 02 04:57:27 PM PDT 24
Finished Aug 02 04:57:29 PM PDT 24
Peak memory 200840 kb
Host smart-dbe23060-8837-462e-a89d-75fc216752c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311615851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.1311615851
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.3491049508
Short name T488
Test name
Test status
Simulation time 2065471735 ps
CPU time 1.32 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200684 kb
Host smart-f1d77b7e-1807-4eb4-aa98-bd9299074076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491049508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.3491049508
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2763132036
Short name T140
Test name
Test status
Simulation time 3470226032 ps
CPU time 4.86 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:57:44 PM PDT 24
Peak memory 200740 kb
Host smart-9e031f07-2a57-4509-bdba-7789314d5ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763132036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.2
763132036
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3289454331
Short name T7
Test name
Test status
Simulation time 138681658215 ps
CPU time 132.2 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:59:51 PM PDT 24
Peak memory 201092 kb
Host smart-7d2eaef3-43b2-4628-819e-a2913dacfdf8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289454331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3289454331
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2884876764
Short name T470
Test name
Test status
Simulation time 3477876860 ps
CPU time 5.07 seconds
Started Aug 02 04:57:38 PM PDT 24
Finished Aug 02 04:57:43 PM PDT 24
Peak memory 200788 kb
Host smart-a2b1c9c8-019e-4b0b-b51d-bce40eae084c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884876764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.2884876764
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.1103144470
Short name T214
Test name
Test status
Simulation time 2776767269 ps
CPU time 1.15 seconds
Started Aug 02 04:57:35 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 200708 kb
Host smart-8a66ba55-ca48-4828-a66b-a7efc758eedd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103144470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.1103144470
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3212519188
Short name T420
Test name
Test status
Simulation time 2612252134 ps
CPU time 7.45 seconds
Started Aug 02 04:57:46 PM PDT 24
Finished Aug 02 04:57:54 PM PDT 24
Peak memory 200840 kb
Host smart-dfa3294b-b299-4a3b-b2e1-64fa9cdce5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212519188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3212519188
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.61519991
Short name T584
Test name
Test status
Simulation time 2469131229 ps
CPU time 2.42 seconds
Started Aug 02 04:57:38 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200752 kb
Host smart-c4b8e801-1c33-4a5a-89b0-b3bae3dc7f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61519991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.61519991
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1393551733
Short name T544
Test name
Test status
Simulation time 2077365992 ps
CPU time 5.27 seconds
Started Aug 02 04:57:47 PM PDT 24
Finished Aug 02 04:57:52 PM PDT 24
Peak memory 200668 kb
Host smart-afaa1536-d7ef-4fcd-b104-d466fcb20265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393551733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.1393551733
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2680530104
Short name T602
Test name
Test status
Simulation time 2528336808 ps
CPU time 2.31 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:57:46 PM PDT 24
Peak memory 200848 kb
Host smart-d24be774-1690-4d4b-83ca-ec1830da4446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680530104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2680530104
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.1556383852
Short name T759
Test name
Test status
Simulation time 2111720270 ps
CPU time 5.87 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:57:39 PM PDT 24
Peak memory 200736 kb
Host smart-6948e0ea-89dd-41fb-aeb5-7a789706dd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556383852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.1556383852
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.2999495690
Short name T629
Test name
Test status
Simulation time 43918090897 ps
CPU time 107.41 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:59:26 PM PDT 24
Peak memory 200948 kb
Host smart-36b99024-f5f2-47fb-935f-4b2d1ac4b8a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999495690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.2999495690
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.841968695
Short name T672
Test name
Test status
Simulation time 207939399886 ps
CPU time 35.09 seconds
Started Aug 02 04:57:41 PM PDT 24
Finished Aug 02 04:58:16 PM PDT 24
Peak memory 201292 kb
Host smart-6b54252c-2268-41e8-9994-f7f5231f94fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841968695 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.841968695
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3076749486
Short name T445
Test name
Test status
Simulation time 6591060329 ps
CPU time 2.39 seconds
Started Aug 02 04:57:38 PM PDT 24
Finished Aug 02 04:57:41 PM PDT 24
Peak memory 200896 kb
Host smart-71de1576-ff8e-4e4d-970b-a123b3947e1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076749486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.3076749486
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.3244393064
Short name T783
Test name
Test status
Simulation time 2010222150 ps
CPU time 5.92 seconds
Started Aug 02 04:57:36 PM PDT 24
Finished Aug 02 04:57:42 PM PDT 24
Peak memory 200796 kb
Host smart-9bde3b89-bf27-494f-bc1a-068974a4b85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244393064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.3244393064
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.108324927
Short name T536
Test name
Test status
Simulation time 3073247211 ps
CPU time 2.54 seconds
Started Aug 02 04:57:36 PM PDT 24
Finished Aug 02 04:57:39 PM PDT 24
Peak memory 200820 kb
Host smart-0628fadd-9217-42cf-b17f-8b24e815b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108324927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.108324927
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.753258206
Short name T241
Test name
Test status
Simulation time 76380243488 ps
CPU time 53.36 seconds
Started Aug 02 04:57:36 PM PDT 24
Finished Aug 02 04:58:30 PM PDT 24
Peak memory 200984 kb
Host smart-29d7acd8-89cc-4bef-a6a3-c617f4be75d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753258206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_combo_detect.753258206
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.442766866
Short name T550
Test name
Test status
Simulation time 3663325622 ps
CPU time 5.32 seconds
Started Aug 02 04:57:36 PM PDT 24
Finished Aug 02 04:57:42 PM PDT 24
Peak memory 200736 kb
Host smart-53bb3e13-30ef-43f0-bffc-686cff5d34d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442766866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ec_pwr_on_rst.442766866
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3071653736
Short name T144
Test name
Test status
Simulation time 4003314291 ps
CPU time 1.2 seconds
Started Aug 02 04:57:40 PM PDT 24
Finished Aug 02 04:57:41 PM PDT 24
Peak memory 200768 kb
Host smart-1937e587-af4d-422a-bb04-e53578f81b11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071653736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.3071653736
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3815403245
Short name T506
Test name
Test status
Simulation time 2660490990 ps
CPU time 1.48 seconds
Started Aug 02 04:57:35 PM PDT 24
Finished Aug 02 04:57:41 PM PDT 24
Peak memory 200808 kb
Host smart-334d4078-077a-4e9d-8c84-57362085a6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815403245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.3815403245
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1769645539
Short name T559
Test name
Test status
Simulation time 2441888676 ps
CPU time 3.93 seconds
Started Aug 02 04:57:35 PM PDT 24
Finished Aug 02 04:57:39 PM PDT 24
Peak memory 200764 kb
Host smart-20b4e02f-b327-4c0f-93f1-4d5b81ddcade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769645539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1769645539
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.573284383
Short name T503
Test name
Test status
Simulation time 2144368581 ps
CPU time 2.04 seconds
Started Aug 02 04:57:38 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200732 kb
Host smart-8230c1f2-dc40-4464-9a11-f1ed93801306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573284383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.573284383
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2768974703
Short name T552
Test name
Test status
Simulation time 2513110523 ps
CPU time 6.89 seconds
Started Aug 02 04:57:38 PM PDT 24
Finished Aug 02 04:57:45 PM PDT 24
Peak memory 200792 kb
Host smart-6de41d5e-4c98-4461-972a-c4cd3d40f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768974703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2768974703
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.124497784
Short name T200
Test name
Test status
Simulation time 2110437893 ps
CPU time 5.63 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:57:45 PM PDT 24
Peak memory 200716 kb
Host smart-821a5d88-48ba-4b9b-a703-48e004bb8ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124497784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.124497784
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.1340435367
Short name T740
Test name
Test status
Simulation time 89346609944 ps
CPU time 58 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:58:38 PM PDT 24
Peak memory 200804 kb
Host smart-9db3857a-b2c5-4c81-9ed5-da37c9d069f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340435367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.1340435367
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3098414967
Short name T496
Test name
Test status
Simulation time 16491369315 ps
CPU time 39.5 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:58:19 PM PDT 24
Peak memory 209392 kb
Host smart-addf5729-73ba-4da0-8129-6f501d0be197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098414967 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.3098414967
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1774879757
Short name T498
Test name
Test status
Simulation time 5620238302 ps
CPU time 1.79 seconds
Started Aug 02 04:57:38 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200852 kb
Host smart-c5ed9472-885f-486e-b1c9-3b6250812bf8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774879757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.1774879757
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.2535589270
Short name T556
Test name
Test status
Simulation time 2042976326 ps
CPU time 1.86 seconds
Started Aug 02 04:57:40 PM PDT 24
Finished Aug 02 04:57:42 PM PDT 24
Peak memory 200804 kb
Host smart-3ad7144c-7eef-4b03-bb20-40da36d95bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535589270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.2535589270
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3147729711
Short name T84
Test name
Test status
Simulation time 3756960121 ps
CPU time 1.12 seconds
Started Aug 02 04:57:49 PM PDT 24
Finished Aug 02 04:57:50 PM PDT 24
Peak memory 200872 kb
Host smart-e5c0cb13-b028-417e-bff0-e2a3858048ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147729711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3
147729711
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2900574980
Short name T240
Test name
Test status
Simulation time 42509951046 ps
CPU time 101.27 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:59:20 PM PDT 24
Peak memory 201012 kb
Host smart-6d09fea3-16fe-4c6a-97c5-3797ea055da6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900574980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.2900574980
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3088619862
Short name T192
Test name
Test status
Simulation time 59088614798 ps
CPU time 149.47 seconds
Started Aug 02 04:57:54 PM PDT 24
Finished Aug 02 05:00:23 PM PDT 24
Peak memory 201052 kb
Host smart-b56c048e-4531-4f82-be25-0de2e07a0d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088619862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.3088619862
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1622724358
Short name T600
Test name
Test status
Simulation time 3976051364 ps
CPU time 9.76 seconds
Started Aug 02 04:57:38 PM PDT 24
Finished Aug 02 04:57:48 PM PDT 24
Peak memory 200704 kb
Host smart-bc0fc373-2f4d-40ae-970b-dc0c6a9cf6a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622724358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.1622724358
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.92899904
Short name T189
Test name
Test status
Simulation time 4389792816 ps
CPU time 4.7 seconds
Started Aug 02 04:57:39 PM PDT 24
Finished Aug 02 04:57:44 PM PDT 24
Peak memory 200772 kb
Host smart-a46698a8-fe98-4670-92b1-933d6de98ced
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92899904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl
_edge_detect.92899904
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2736935318
Short name T359
Test name
Test status
Simulation time 2613168071 ps
CPU time 7.63 seconds
Started Aug 02 04:57:34 PM PDT 24
Finished Aug 02 04:57:42 PM PDT 24
Peak memory 200716 kb
Host smart-672e72a5-2f71-4336-9b95-04c0574b8761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736935318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.2736935318
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1965466930
Short name T411
Test name
Test status
Simulation time 2472631467 ps
CPU time 2.12 seconds
Started Aug 02 04:57:40 PM PDT 24
Finished Aug 02 04:57:42 PM PDT 24
Peak memory 200812 kb
Host smart-a6568b2f-ac04-40c6-90c0-f222c66d0399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965466930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.1965466930
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1893747883
Short name T555
Test name
Test status
Simulation time 2137480498 ps
CPU time 5.49 seconds
Started Aug 02 04:57:54 PM PDT 24
Finished Aug 02 04:57:59 PM PDT 24
Peak memory 200732 kb
Host smart-8d242e8c-607c-4c60-bc8a-efbf6390e043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893747883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.1893747883
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1911381846
Short name T614
Test name
Test status
Simulation time 2532329288 ps
CPU time 2.22 seconds
Started Aug 02 04:57:33 PM PDT 24
Finished Aug 02 04:57:36 PM PDT 24
Peak memory 200784 kb
Host smart-7308aeee-f15d-4085-ba80-74f1927a1b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911381846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1911381846
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.863876486
Short name T428
Test name
Test status
Simulation time 2119590590 ps
CPU time 3.19 seconds
Started Aug 02 04:57:49 PM PDT 24
Finished Aug 02 04:57:53 PM PDT 24
Peak memory 200764 kb
Host smart-dd925d87-d64b-49c9-aa97-0482bc1b5f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863876486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.863876486
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3752671778
Short name T750
Test name
Test status
Simulation time 29027591207 ps
CPU time 67.49 seconds
Started Aug 02 04:57:38 PM PDT 24
Finished Aug 02 04:58:46 PM PDT 24
Peak memory 217352 kb
Host smart-2073fc5c-f8a9-4503-909b-80fe7532d114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752671778 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.3752671778
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1539829258
Short name T519
Test name
Test status
Simulation time 6542069115 ps
CPU time 8.01 seconds
Started Aug 02 04:57:41 PM PDT 24
Finished Aug 02 04:57:49 PM PDT 24
Peak memory 200836 kb
Host smart-1e4bca97-112b-48f9-91da-4389faf8f34c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539829258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.1539829258
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.4014575158
Short name T49
Test name
Test status
Simulation time 2034845208 ps
CPU time 1.98 seconds
Started Aug 02 04:57:48 PM PDT 24
Finished Aug 02 04:57:50 PM PDT 24
Peak memory 200836 kb
Host smart-05b6099c-34d2-4f10-90ce-3bbd038d3271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014575158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.4014575158
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2864237368
Short name T381
Test name
Test status
Simulation time 3394655630 ps
CPU time 9.22 seconds
Started Aug 02 04:57:45 PM PDT 24
Finished Aug 02 04:57:54 PM PDT 24
Peak memory 200908 kb
Host smart-5f315f06-0496-419c-87df-b4cae92d68c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864237368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.2
864237368
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.296027150
Short name T234
Test name
Test status
Simulation time 106058243094 ps
CPU time 253 seconds
Started Aug 02 04:57:55 PM PDT 24
Finished Aug 02 05:02:08 PM PDT 24
Peak memory 201012 kb
Host smart-7c1d4cfc-a645-4cf1-a559-cdf449663641
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296027150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_combo_detect.296027150
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1282532905
Short name T86
Test name
Test status
Simulation time 62537449155 ps
CPU time 92.69 seconds
Started Aug 02 04:57:50 PM PDT 24
Finished Aug 02 04:59:23 PM PDT 24
Peak memory 201064 kb
Host smart-8cc49cb9-1329-4046-aae9-334c107d7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282532905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.1282532905
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4130537313
Short name T383
Test name
Test status
Simulation time 3230430877 ps
CPU time 2.61 seconds
Started Aug 02 04:57:42 PM PDT 24
Finished Aug 02 04:57:44 PM PDT 24
Peak memory 200652 kb
Host smart-2d365a87-9ef4-4d1a-974a-8c9b6bc918bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130537313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.4130537313
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2875444763
Short name T183
Test name
Test status
Simulation time 4042388746 ps
CPU time 7.71 seconds
Started Aug 02 04:57:52 PM PDT 24
Finished Aug 02 04:58:00 PM PDT 24
Peak memory 200896 kb
Host smart-88771924-d539-4c0d-adbe-44a1c83e1fc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875444763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.2875444763
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.211610707
Short name T106
Test name
Test status
Simulation time 2620890287 ps
CPU time 3.99 seconds
Started Aug 02 04:57:59 PM PDT 24
Finished Aug 02 04:58:03 PM PDT 24
Peak memory 200704 kb
Host smart-80997aba-c92c-479f-bb44-3fbc719ab00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211610707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.211610707
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2534355512
Short name T394
Test name
Test status
Simulation time 2499227969 ps
CPU time 2.52 seconds
Started Aug 02 04:57:41 PM PDT 24
Finished Aug 02 04:57:43 PM PDT 24
Peak memory 200784 kb
Host smart-390e70e4-d432-4ce6-892f-e1bbb36c63e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534355512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2534355512
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1751188310
Short name T484
Test name
Test status
Simulation time 2039488986 ps
CPU time 5.63 seconds
Started Aug 02 04:57:35 PM PDT 24
Finished Aug 02 04:57:40 PM PDT 24
Peak memory 200788 kb
Host smart-b3b3761b-8228-4816-b1fb-d2091ee553f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751188310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.1751188310
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.94131315
Short name T17
Test name
Test status
Simulation time 2510478002 ps
CPU time 7.15 seconds
Started Aug 02 04:57:51 PM PDT 24
Finished Aug 02 04:57:58 PM PDT 24
Peak memory 200844 kb
Host smart-98809e22-9ab3-4b43-91ef-183d9b766788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94131315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.94131315
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.1190147599
Short name T684
Test name
Test status
Simulation time 2113351406 ps
CPU time 5.89 seconds
Started Aug 02 04:57:45 PM PDT 24
Finished Aug 02 04:57:51 PM PDT 24
Peak memory 200744 kb
Host smart-0c1d43c7-0b6b-49b8-a610-d3fab22768cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190147599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.1190147599
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.3751250492
Short name T281
Test name
Test status
Simulation time 8155421553 ps
CPU time 5.59 seconds
Started Aug 02 04:57:42 PM PDT 24
Finished Aug 02 04:57:48 PM PDT 24
Peak memory 200764 kb
Host smart-6c32b7ce-d659-42e5-a7a7-0ed63f6966b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751250492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.3751250492
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4075083312
Short name T603
Test name
Test status
Simulation time 6515766404 ps
CPU time 3.74 seconds
Started Aug 02 04:57:47 PM PDT 24
Finished Aug 02 04:57:51 PM PDT 24
Peak memory 200900 kb
Host smart-06024645-9419-4591-9e54-cd212f0d97ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075083312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.4075083312
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.2134866470
Short name T446
Test name
Test status
Simulation time 2015092253 ps
CPU time 5.42 seconds
Started Aug 02 04:57:48 PM PDT 24
Finished Aug 02 04:57:54 PM PDT 24
Peak memory 200756 kb
Host smart-2047bd14-6ba0-4108-9c45-d6899e4b3df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134866470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.2134866470
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4003552141
Short name T575
Test name
Test status
Simulation time 2822474143 ps
CPU time 2.56 seconds
Started Aug 02 04:57:42 PM PDT 24
Finished Aug 02 04:57:45 PM PDT 24
Peak memory 200792 kb
Host smart-29c1a7ef-d6b2-4df5-adf8-3e72ee38d496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003552141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.4
003552141
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.2585840078
Short name T690
Test name
Test status
Simulation time 123033129003 ps
CPU time 158.75 seconds
Started Aug 02 04:58:02 PM PDT 24
Finished Aug 02 05:00:41 PM PDT 24
Peak memory 201036 kb
Host smart-a8d86914-4489-4292-9022-10319e02e21f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585840078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.2585840078
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3197883553
Short name T726
Test name
Test status
Simulation time 100015664428 ps
CPU time 133.19 seconds
Started Aug 02 04:57:48 PM PDT 24
Finished Aug 02 05:00:02 PM PDT 24
Peak memory 201108 kb
Host smart-417f9c51-f281-455b-86db-29abd51ffad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197883553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.3197883553
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1682833878
Short name T638
Test name
Test status
Simulation time 2767498211 ps
CPU time 2.57 seconds
Started Aug 02 04:57:42 PM PDT 24
Finished Aug 02 04:57:44 PM PDT 24
Peak memory 200804 kb
Host smart-e2ec498f-cae3-4cb7-a865-9ca57120a8c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682833878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1682833878
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2207695520
Short name T703
Test name
Test status
Simulation time 5659967008 ps
CPU time 2.29 seconds
Started Aug 02 04:57:46 PM PDT 24
Finished Aug 02 04:57:48 PM PDT 24
Peak memory 200812 kb
Host smart-6843a45e-cf60-4fe1-bf53-d4857a44472b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207695520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2207695520
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3207752949
Short name T654
Test name
Test status
Simulation time 2677262267 ps
CPU time 1.44 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:57:46 PM PDT 24
Peak memory 200776 kb
Host smart-1d849601-492b-432d-9f7a-006d714fc26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207752949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.3207752949
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4155134908
Short name T56
Test name
Test status
Simulation time 2500964642 ps
CPU time 1.7 seconds
Started Aug 02 04:57:54 PM PDT 24
Finished Aug 02 04:57:56 PM PDT 24
Peak memory 200804 kb
Host smart-791c2e30-687b-407f-abfc-f3df7b5bfacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155134908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.4155134908
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3421352711
Short name T733
Test name
Test status
Simulation time 2213149459 ps
CPU time 5.84 seconds
Started Aug 02 04:57:46 PM PDT 24
Finished Aug 02 04:57:52 PM PDT 24
Peak memory 200700 kb
Host smart-45acc9d8-60b8-46d2-8a60-5b20442f9a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421352711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3421352711
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.4150708637
Short name T700
Test name
Test status
Simulation time 2530609844 ps
CPU time 2.25 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:57:46 PM PDT 24
Peak memory 200800 kb
Host smart-1482b1fb-ca96-403d-8d44-db716145eace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150708637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.4150708637
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.2122788128
Short name T691
Test name
Test status
Simulation time 2120505345 ps
CPU time 3.32 seconds
Started Aug 02 04:57:56 PM PDT 24
Finished Aug 02 04:57:59 PM PDT 24
Peak memory 200720 kb
Host smart-fe382e2b-146f-459e-9252-8581a2b5e474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122788128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.2122788128
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2104519248
Short name T270
Test name
Test status
Simulation time 8738170972 ps
CPU time 14.36 seconds
Started Aug 02 04:57:48 PM PDT 24
Finished Aug 02 04:58:03 PM PDT 24
Peak memory 200836 kb
Host smart-58475385-6f26-4f14-8b33-a2d240ada7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104519248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.2104519248
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2785004599
Short name T168
Test name
Test status
Simulation time 85374073452 ps
CPU time 50.55 seconds
Started Aug 02 04:57:47 PM PDT 24
Finished Aug 02 04:58:38 PM PDT 24
Peak memory 209520 kb
Host smart-a979ed53-31ec-4625-b171-a83d196530b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785004599 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.2785004599
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3603500288
Short name T114
Test name
Test status
Simulation time 8200047047 ps
CPU time 7.43 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:57:52 PM PDT 24
Peak memory 200832 kb
Host smart-3db36d35-5592-4e27-91f0-ec02f9d48a90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603500288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3603500288
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.495241338
Short name T379
Test name
Test status
Simulation time 2015875214 ps
CPU time 5.72 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 200792 kb
Host smart-71ef02ac-2eb6-439e-89d8-9eb6e09954b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495241338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test
.495241338
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2799736825
Short name T564
Test name
Test status
Simulation time 3734188535 ps
CPU time 3.01 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:05 PM PDT 24
Peak memory 200512 kb
Host smart-ca12c6ac-2b64-4c0f-af07-e50fe2a157df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799736825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2799736825
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3508192784
Short name T679
Test name
Test status
Simulation time 162984632613 ps
CPU time 104.74 seconds
Started Aug 02 04:56:01 PM PDT 24
Finished Aug 02 04:57:46 PM PDT 24
Peak memory 201064 kb
Host smart-19c4fa48-d06d-4a4c-b0cd-320b71bd3188
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508192784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3508192784
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3404813375
Short name T19
Test name
Test status
Simulation time 29997841030 ps
CPU time 21.3 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:24 PM PDT 24
Peak memory 201128 kb
Host smart-6fc2cc27-c97c-44cc-a99d-84038748781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404813375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.3404813375
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1683626236
Short name T541
Test name
Test status
Simulation time 3075031535 ps
CPU time 8.07 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 200884 kb
Host smart-bcdc34e2-c22b-4cb8-a401-61531fc0bf59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683626236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.1683626236
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3799206683
Short name T609
Test name
Test status
Simulation time 5121102637 ps
CPU time 3.56 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 200780 kb
Host smart-8c2eb30a-1e36-48ac-982c-f438872f159d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799206683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3799206683
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3854885436
Short name T644
Test name
Test status
Simulation time 2613982315 ps
CPU time 7.24 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:11 PM PDT 24
Peak memory 200760 kb
Host smart-6e34f913-6fec-4806-8043-704645ea9830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854885436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3854885436
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1222128022
Short name T57
Test name
Test status
Simulation time 2480765752 ps
CPU time 2.69 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 200848 kb
Host smart-7b60c8e0-e82c-4cd1-9fab-f89dc63772e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222128022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1222128022
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4013999757
Short name T172
Test name
Test status
Simulation time 2251030700 ps
CPU time 3.49 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 200704 kb
Host smart-a6ffa023-1907-482d-9aa5-00f16234d5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013999757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.4013999757
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2874128243
Short name T388
Test name
Test status
Simulation time 2509662499 ps
CPU time 6.55 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 200784 kb
Host smart-47f7b389-e566-4f1d-89f1-dc362f767b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874128243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2874128243
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.4164008276
Short name T598
Test name
Test status
Simulation time 2112264894 ps
CPU time 5.83 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:11 PM PDT 24
Peak memory 200764 kb
Host smart-1f2f4656-03ae-4e42-a081-4ef5f716c029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164008276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.4164008276
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.2198619241
Short name T398
Test name
Test status
Simulation time 7362180609 ps
CPU time 5.03 seconds
Started Aug 02 04:55:55 PM PDT 24
Finished Aug 02 04:56:00 PM PDT 24
Peak memory 200876 kb
Host smart-97cc8d5d-2da7-4028-ad15-2092446c5e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198619241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.2198619241
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.4280238335
Short name T177
Test name
Test status
Simulation time 69251016855 ps
CPU time 46.41 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 209336 kb
Host smart-0b5c56ae-271c-43b7-ba00-5b5394493c3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280238335 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.4280238335
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.332899129
Short name T653
Test name
Test status
Simulation time 9593286378 ps
CPU time 8.03 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:10 PM PDT 24
Peak memory 200856 kb
Host smart-4d16cb3c-6dc3-4a7a-819a-cea4b53c63ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332899129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ultra_low_pwr.332899129
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1831513279
Short name T88
Test name
Test status
Simulation time 171052153718 ps
CPU time 117.89 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:59:42 PM PDT 24
Peak memory 201240 kb
Host smart-42690666-bb28-460d-abb8-69e5aba13340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831513279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1831513279
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1315658675
Short name T218
Test name
Test status
Simulation time 37081597670 ps
CPU time 82.52 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:59:07 PM PDT 24
Peak memory 201128 kb
Host smart-147e0847-24b5-41bd-b072-31b66cafafea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315658675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.1315658675
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3224079637
Short name T739
Test name
Test status
Simulation time 118203338994 ps
CPU time 140.72 seconds
Started Aug 02 04:57:48 PM PDT 24
Finished Aug 02 05:00:09 PM PDT 24
Peak memory 201128 kb
Host smart-02fc4a38-23c1-448d-87f8-f3efa2fadb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224079637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.3224079637
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1048099475
Short name T698
Test name
Test status
Simulation time 34179882524 ps
CPU time 44.21 seconds
Started Aug 02 04:57:46 PM PDT 24
Finished Aug 02 04:58:30 PM PDT 24
Peak memory 201100 kb
Host smart-bc5ba54c-a69c-4784-aa95-d423e164489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048099475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.1048099475
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.738472354
Short name T109
Test name
Test status
Simulation time 88293054626 ps
CPU time 237.31 seconds
Started Aug 02 04:57:53 PM PDT 24
Finished Aug 02 05:01:51 PM PDT 24
Peak memory 201176 kb
Host smart-5c9f759e-5713-4b67-8396-0b3705e094d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738472354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_wi
th_pre_cond.738472354
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1569635775
Short name T319
Test name
Test status
Simulation time 95502471631 ps
CPU time 70.08 seconds
Started Aug 02 04:57:51 PM PDT 24
Finished Aug 02 04:59:02 PM PDT 24
Peak memory 201188 kb
Host smart-b6031cd2-2cd1-4144-a6e2-e4571c78c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569635775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.1569635775
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4289101190
Short name T560
Test name
Test status
Simulation time 46368908234 ps
CPU time 123.47 seconds
Started Aug 02 04:57:46 PM PDT 24
Finished Aug 02 04:59:49 PM PDT 24
Peak memory 201100 kb
Host smart-62f9e171-d03d-40aa-99c1-bcf968a6af84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289101190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.4289101190
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1360287093
Short name T67
Test name
Test status
Simulation time 25334513945 ps
CPU time 69.2 seconds
Started Aug 02 04:57:50 PM PDT 24
Finished Aug 02 04:58:59 PM PDT 24
Peak memory 201220 kb
Host smart-fc79d6a5-3068-4aff-8aff-811d8edb353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360287093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.1360287093
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.2267632041
Short name T737
Test name
Test status
Simulation time 2038940303 ps
CPU time 1.52 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 200688 kb
Host smart-0eb0b8a5-4484-4cc9-be50-eacfaf3441fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267632041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.2267632041
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1484585020
Short name T25
Test name
Test status
Simulation time 3668134897 ps
CPU time 1.14 seconds
Started Aug 02 04:56:04 PM PDT 24
Finished Aug 02 04:56:05 PM PDT 24
Peak memory 200868 kb
Host smart-124bf521-37be-47df-bd5d-764a2cee5080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484585020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1484585020
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1531100367
Short name T570
Test name
Test status
Simulation time 71748451778 ps
CPU time 33.98 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:56:37 PM PDT 24
Peak memory 201020 kb
Host smart-6a73026b-e2c4-441a-9259-2a04a3d491e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531100367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.1531100367
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2690846181
Short name T219
Test name
Test status
Simulation time 22613425434 ps
CPU time 12.32 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:23 PM PDT 24
Peak memory 201104 kb
Host smart-c5193438-7b14-4002-90cc-049f38260470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690846181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.2690846181
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2253403666
Short name T606
Test name
Test status
Simulation time 3726371938 ps
CPU time 4.7 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:10 PM PDT 24
Peak memory 200772 kb
Host smart-92edd7be-fb36-43d1-bed9-7551b5591901
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253403666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2253403666
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1439795039
Short name T149
Test name
Test status
Simulation time 4192451545 ps
CPU time 2.66 seconds
Started Aug 02 04:56:09 PM PDT 24
Finished Aug 02 04:56:12 PM PDT 24
Peak memory 200836 kb
Host smart-7523dfdb-ab18-4fd7-a1d8-3d5ea3389bb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439795039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1439795039
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3605786037
Short name T356
Test name
Test status
Simulation time 2608452326 ps
CPU time 7.35 seconds
Started Aug 02 04:56:04 PM PDT 24
Finished Aug 02 04:56:12 PM PDT 24
Peak memory 200692 kb
Host smart-080b5bd5-3644-4bd6-92c6-77b138b418b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605786037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3605786037
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2828082651
Short name T194
Test name
Test status
Simulation time 2564062000 ps
CPU time 1.06 seconds
Started Aug 02 04:56:02 PM PDT 24
Finished Aug 02 04:56:04 PM PDT 24
Peak memory 200484 kb
Host smart-40d4896f-328f-4bc5-9e38-355ac882b0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828082651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2828082651
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.866686286
Short name T689
Test name
Test status
Simulation time 2080802658 ps
CPU time 5.8 seconds
Started Aug 02 04:56:08 PM PDT 24
Finished Aug 02 04:56:14 PM PDT 24
Peak memory 200732 kb
Host smart-f4098cb2-6d29-40f2-ae38-0840a4e00ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866686286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.866686286
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3643450121
Short name T494
Test name
Test status
Simulation time 2517653205 ps
CPU time 4.11 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:09 PM PDT 24
Peak memory 200736 kb
Host smart-11ad7637-f88b-4084-9f04-b8b9cd6ba725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643450121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.3643450121
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.4171588374
Short name T728
Test name
Test status
Simulation time 2132803209 ps
CPU time 2 seconds
Started Aug 02 04:56:01 PM PDT 24
Finished Aug 02 04:56:03 PM PDT 24
Peak memory 200668 kb
Host smart-ee92a05a-26ed-4b5a-afdc-6b97fa4f0d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171588374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.4171588374
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.579683223
Short name T747
Test name
Test status
Simulation time 16931252626 ps
CPU time 7.04 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200844 kb
Host smart-619e712d-2fe1-4ef9-90ed-c5fead142070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579683223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_str
ess_all.579683223
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2672581218
Short name T121
Test name
Test status
Simulation time 51933526086 ps
CPU time 130.89 seconds
Started Aug 02 04:56:03 PM PDT 24
Finished Aug 02 04:58:14 PM PDT 24
Peak memory 217512 kb
Host smart-7b07266f-f12c-4d19-ba7a-bf7f9c050dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672581218 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.2672581218
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.845861039
Short name T581
Test name
Test status
Simulation time 67576393507 ps
CPU time 177.8 seconds
Started Aug 02 04:57:49 PM PDT 24
Finished Aug 02 05:00:47 PM PDT 24
Peak memory 201140 kb
Host smart-16731961-1acb-4579-a273-92b3ecf87ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845861039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi
th_pre_cond.845861039
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2774922836
Short name T534
Test name
Test status
Simulation time 64256966375 ps
CPU time 72.64 seconds
Started Aug 02 04:57:43 PM PDT 24
Finished Aug 02 04:58:55 PM PDT 24
Peak memory 201100 kb
Host smart-881847a4-b9cf-4c75-a3e4-4bcc4c481351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774922836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2774922836
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.624730465
Short name T349
Test name
Test status
Simulation time 72571921558 ps
CPU time 190.87 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 200996 kb
Host smart-917bf2e6-8dc8-4871-b163-1e1009ba285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624730465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_wi
th_pre_cond.624730465
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2968302814
Short name T769
Test name
Test status
Simulation time 65604136236 ps
CPU time 17.87 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 04:58:02 PM PDT 24
Peak memory 201104 kb
Host smart-5047a7d9-d08e-4b1f-96d5-ae746b73a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968302814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.2968302814
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3448242342
Short name T440
Test name
Test status
Simulation time 65606363990 ps
CPU time 41.37 seconds
Started Aug 02 04:57:50 PM PDT 24
Finished Aug 02 04:58:31 PM PDT 24
Peak memory 201036 kb
Host smart-20a1b56f-3d2e-46f2-ad35-77fa3cc84233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448242342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.3448242342
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2582791432
Short name T318
Test name
Test status
Simulation time 91576540418 ps
CPU time 227.22 seconds
Started Aug 02 04:57:44 PM PDT 24
Finished Aug 02 05:01:32 PM PDT 24
Peak memory 201096 kb
Host smart-11b5d62a-bfd1-4fce-8c38-e535227c5f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582791432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.2582791432
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.92498214
Short name T115
Test name
Test status
Simulation time 2020443464 ps
CPU time 3.02 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 200736 kb
Host smart-6637acc5-7a4c-49b5-ac21-a8bd84da42de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92498214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.92498214
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2785717202
Short name T549
Test name
Test status
Simulation time 4310324810 ps
CPU time 3.11 seconds
Started Aug 02 04:56:10 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 200852 kb
Host smart-e834f1ed-5519-4178-a47a-70cb66873326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785717202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.2785717202
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.2016370137
Short name T233
Test name
Test status
Simulation time 30942247457 ps
CPU time 37.95 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:43 PM PDT 24
Peak memory 201052 kb
Host smart-58b79478-b3c2-422c-9e64-5e7a67b8d288
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016370137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.2016370137
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3743721548
Short name T343
Test name
Test status
Simulation time 25096791715 ps
CPU time 13.21 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 201108 kb
Host smart-17c00934-2ac6-42b1-b016-fb210fd4385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743721548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.3743721548
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2969445880
Short name T392
Test name
Test status
Simulation time 2474236347 ps
CPU time 7 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:12 PM PDT 24
Peak memory 200824 kb
Host smart-0f8ba73b-b1dc-4774-856f-caf23d8e3001
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969445880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.2969445880
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.1227371387
Short name T567
Test name
Test status
Simulation time 3134492026 ps
CPU time 3.46 seconds
Started Aug 02 04:56:04 PM PDT 24
Finished Aug 02 04:56:07 PM PDT 24
Peak memory 200928 kb
Host smart-900a5c86-4882-499d-8dc9-55c9855a17df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227371387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.1227371387
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3224516967
Short name T729
Test name
Test status
Simulation time 2633177263 ps
CPU time 2.36 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:07 PM PDT 24
Peak memory 200844 kb
Host smart-d4bcd501-b966-4860-b3d6-ea062e3f0ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224516967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.3224516967
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1544344062
Short name T579
Test name
Test status
Simulation time 2475338090 ps
CPU time 2.26 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:14 PM PDT 24
Peak memory 200760 kb
Host smart-aa8da33b-7d11-4fda-b65f-4d20794f01aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544344062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.1544344062
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1013335664
Short name T404
Test name
Test status
Simulation time 2082480624 ps
CPU time 4.32 seconds
Started Aug 02 04:56:04 PM PDT 24
Finished Aug 02 04:56:08 PM PDT 24
Peak memory 200744 kb
Host smart-9c930ee9-f41d-4570-9c67-cf6b5a4e3198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013335664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1013335664
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.541917037
Short name T61
Test name
Test status
Simulation time 2509104183 ps
CPU time 5.83 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:11 PM PDT 24
Peak memory 200756 kb
Host smart-2a9eb023-4951-481b-b97b-d3bbc57145c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541917037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.541917037
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.3930612898
Short name T512
Test name
Test status
Simulation time 2110205817 ps
CPU time 5.76 seconds
Started Aug 02 04:56:10 PM PDT 24
Finished Aug 02 04:56:16 PM PDT 24
Peak memory 200716 kb
Host smart-0e9c3b36-bf99-4f98-984c-f64d05ec0fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930612898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.3930612898
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.2865526917
Short name T87
Test name
Test status
Simulation time 91419380553 ps
CPU time 63.57 seconds
Started Aug 02 04:56:10 PM PDT 24
Finished Aug 02 04:57:13 PM PDT 24
Peak memory 201088 kb
Host smart-6880e46c-3912-4c70-95c9-4bfac694bb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865526917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.2865526917
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.122098844
Short name T761
Test name
Test status
Simulation time 7158855721 ps
CPU time 1.22 seconds
Started Aug 02 04:56:05 PM PDT 24
Finished Aug 02 04:56:06 PM PDT 24
Peak memory 200768 kb
Host smart-e148b6c3-0ab3-4398-8b7d-8c3f9c50db42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122098844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ultra_low_pwr.122098844
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.200500439
Short name T245
Test name
Test status
Simulation time 30839036828 ps
CPU time 39.77 seconds
Started Aug 02 04:57:58 PM PDT 24
Finished Aug 02 04:58:38 PM PDT 24
Peak memory 201132 kb
Host smart-5561ba1e-9462-48a3-a19f-964442820244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200500439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_wi
th_pre_cond.200500439
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.993141493
Short name T434
Test name
Test status
Simulation time 114790904847 ps
CPU time 282.41 seconds
Started Aug 02 04:58:04 PM PDT 24
Finished Aug 02 05:02:47 PM PDT 24
Peak memory 201104 kb
Host smart-56705796-082e-4c9b-a8f2-9853043bb9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993141493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_wi
th_pre_cond.993141493
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.786784902
Short name T788
Test name
Test status
Simulation time 55142958548 ps
CPU time 39.18 seconds
Started Aug 02 04:57:51 PM PDT 24
Finished Aug 02 04:58:30 PM PDT 24
Peak memory 201232 kb
Host smart-013cde43-b975-400d-9419-24367dbce5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786784902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_wi
th_pre_cond.786784902
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1705303859
Short name T237
Test name
Test status
Simulation time 159344613494 ps
CPU time 384.91 seconds
Started Aug 02 04:57:56 PM PDT 24
Finished Aug 02 05:04:21 PM PDT 24
Peak memory 201176 kb
Host smart-1fdadbee-980e-4234-8f55-a46c05168c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705303859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.1705303859
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.584285014
Short name T741
Test name
Test status
Simulation time 57980472235 ps
CPU time 148.85 seconds
Started Aug 02 04:57:54 PM PDT 24
Finished Aug 02 05:00:23 PM PDT 24
Peak memory 201088 kb
Host smart-36e80b00-dba0-4aef-9a31-d0fa5e666a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584285014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_wi
th_pre_cond.584285014
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2861442853
Short name T491
Test name
Test status
Simulation time 47961069207 ps
CPU time 18.79 seconds
Started Aug 02 04:57:58 PM PDT 24
Finished Aug 02 04:58:17 PM PDT 24
Peak memory 201160 kb
Host smart-4695d233-8cae-473b-9685-adcbe38a6b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861442853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.2861442853
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1083774970
Short name T715
Test name
Test status
Simulation time 44266955596 ps
CPU time 31.52 seconds
Started Aug 02 04:57:53 PM PDT 24
Finished Aug 02 04:58:25 PM PDT 24
Peak memory 201204 kb
Host smart-3aad7020-9293-4682-b797-a19d0567c7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083774970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.1083774970
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.590397494
Short name T636
Test name
Test status
Simulation time 117214813056 ps
CPU time 77.28 seconds
Started Aug 02 04:57:51 PM PDT 24
Finished Aug 02 04:59:09 PM PDT 24
Peak memory 201068 kb
Host smart-1593413d-5452-4c10-9ea8-40d3d851b2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590397494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_wi
th_pre_cond.590397494
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.2444191568
Short name T432
Test name
Test status
Simulation time 2026429862 ps
CPU time 1.87 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 200812 kb
Host smart-e4460eb4-bc11-4dd9-97cd-7988b8f42e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444191568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.2444191568
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1627708966
Short name T497
Test name
Test status
Simulation time 3249869681 ps
CPU time 8.66 seconds
Started Aug 02 04:56:14 PM PDT 24
Finished Aug 02 04:56:23 PM PDT 24
Peak memory 200844 kb
Host smart-aba7bea1-5d8c-4d8e-be9b-a61ae9c61bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627708966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1627708966
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.862827838
Short name T193
Test name
Test status
Simulation time 127570488062 ps
CPU time 71.09 seconds
Started Aug 02 04:56:10 PM PDT 24
Finished Aug 02 04:57:22 PM PDT 24
Peak memory 201068 kb
Host smart-2c537202-9a73-41a1-a015-4d7937c97f30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862827838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_combo_detect.862827838
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.664120940
Short name T520
Test name
Test status
Simulation time 35085958440 ps
CPU time 45.9 seconds
Started Aug 02 04:56:10 PM PDT 24
Finished Aug 02 04:56:56 PM PDT 24
Peak memory 201064 kb
Host smart-129d1f88-91db-4c08-a3e9-6a8ed99240a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664120940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wit
h_pre_cond.664120940
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.531330901
Short name T586
Test name
Test status
Simulation time 2638183892 ps
CPU time 6.97 seconds
Started Aug 02 04:56:15 PM PDT 24
Finished Aug 02 04:56:22 PM PDT 24
Peak memory 200816 kb
Host smart-54747dfb-d22b-4cce-acc0-65edbd78d060
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531330901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ec_pwr_on_rst.531330901
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2607412385
Short name T145
Test name
Test status
Simulation time 4572077869 ps
CPU time 2.78 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:15 PM PDT 24
Peak memory 200872 kb
Host smart-722c51b6-ff8c-40d6-a5f1-545c1c34e606
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607412385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2607412385
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3374043506
Short name T407
Test name
Test status
Simulation time 2626476833 ps
CPU time 2.55 seconds
Started Aug 02 04:56:14 PM PDT 24
Finished Aug 02 04:56:17 PM PDT 24
Peak memory 200748 kb
Host smart-9ea7176c-6900-4878-a9de-24440e4757f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374043506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3374043506
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.498413745
Short name T5
Test name
Test status
Simulation time 2495448638 ps
CPU time 2.24 seconds
Started Aug 02 04:56:10 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 200780 kb
Host smart-4c86ffc9-a9d8-486c-888b-59a607bae565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498413745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.498413745
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1600120170
Short name T743
Test name
Test status
Simulation time 2214315591 ps
CPU time 5.94 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200740 kb
Host smart-bd7eab13-9be7-427f-99af-38569c04e9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600120170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1600120170
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3269820437
Short name T646
Test name
Test status
Simulation time 2531743568 ps
CPU time 2.54 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:14 PM PDT 24
Peak memory 200836 kb
Host smart-963ac919-b0f5-4213-b88a-5b729c39e902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269820437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3269820437
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.815118427
Short name T15
Test name
Test status
Simulation time 2111048502 ps
CPU time 6.18 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200708 kb
Host smart-29ffaf9d-2f0f-4e5a-b700-1cbc11185929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815118427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.815118427
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.16098342
Short name T227
Test name
Test status
Simulation time 17099508878 ps
CPU time 12.47 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:24 PM PDT 24
Peak memory 200708 kb
Host smart-92b1b39a-af1e-4de2-81e9-5ae68a318644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16098342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stre
ss_all.16098342
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3226506735
Short name T52
Test name
Test status
Simulation time 8875103425 ps
CPU time 1.07 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 200864 kb
Host smart-42272986-a7cb-480e-a016-a98e6c5615a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226506735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.3226506735
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1617026207
Short name T553
Test name
Test status
Simulation time 68909188061 ps
CPU time 181.47 seconds
Started Aug 02 04:57:51 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 201088 kb
Host smart-a0dfb7ad-0836-4afd-a8d8-744aa21ac2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617026207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.1617026207
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.449849689
Short name T76
Test name
Test status
Simulation time 65131097036 ps
CPU time 159.26 seconds
Started Aug 02 04:58:01 PM PDT 24
Finished Aug 02 05:00:41 PM PDT 24
Peak memory 201196 kb
Host smart-cd6ab3f5-a8e0-46d1-91a0-2145bee09d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449849689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_wi
th_pre_cond.449849689
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3056385724
Short name T773
Test name
Test status
Simulation time 78277052548 ps
CPU time 202.99 seconds
Started Aug 02 04:58:00 PM PDT 24
Finished Aug 02 05:01:23 PM PDT 24
Peak memory 201140 kb
Host smart-bea5fdb9-079f-488e-80a2-89b6b7064572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056385724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.3056385724
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1722828552
Short name T345
Test name
Test status
Simulation time 67767347986 ps
CPU time 83.92 seconds
Started Aug 02 04:57:55 PM PDT 24
Finished Aug 02 04:59:19 PM PDT 24
Peak memory 201100 kb
Host smart-3471cf35-84a8-446a-a66b-1ac16aedde4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722828552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.1722828552
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.174075645
Short name T89
Test name
Test status
Simulation time 26080163475 ps
CPU time 72.27 seconds
Started Aug 02 04:57:54 PM PDT 24
Finished Aug 02 04:59:06 PM PDT 24
Peak memory 201028 kb
Host smart-7d94ef5a-2ecd-4c01-a185-e17317fe777e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174075645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wi
th_pre_cond.174075645
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2756475880
Short name T771
Test name
Test status
Simulation time 82215082890 ps
CPU time 54.86 seconds
Started Aug 02 04:58:01 PM PDT 24
Finished Aug 02 04:58:56 PM PDT 24
Peak memory 201080 kb
Host smart-0b9f2edb-e78d-42cc-9d9b-08c16937df3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756475880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.2756475880
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3417189347
Short name T706
Test name
Test status
Simulation time 101096913463 ps
CPU time 127.08 seconds
Started Aug 02 04:58:01 PM PDT 24
Finished Aug 02 05:00:09 PM PDT 24
Peak memory 201116 kb
Host smart-e02b1c5f-dc7a-45bc-a16b-eccb36175720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417189347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.3417189347
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2708794674
Short name T30
Test name
Test status
Simulation time 99637319868 ps
CPU time 260.57 seconds
Started Aug 02 04:57:50 PM PDT 24
Finished Aug 02 05:02:11 PM PDT 24
Peak memory 201140 kb
Host smart-ef274f8d-dea0-456a-9dda-06f6eead7bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708794674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.2708794674
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2078743163
Short name T751
Test name
Test status
Simulation time 123340335275 ps
CPU time 165.21 seconds
Started Aug 02 04:57:50 PM PDT 24
Finished Aug 02 05:00:35 PM PDT 24
Peak memory 201024 kb
Host smart-41db0396-b050-42c7-a09f-3f2637856d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078743163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.2078743163
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3627834999
Short name T225
Test name
Test status
Simulation time 34283091350 ps
CPU time 84.55 seconds
Started Aug 02 04:57:57 PM PDT 24
Finished Aug 02 04:59:22 PM PDT 24
Peak memory 201132 kb
Host smart-860c73f0-c856-4ea7-a43f-6436ef992f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627834999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3627834999
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.3620116054
Short name T417
Test name
Test status
Simulation time 2034403389 ps
CPU time 1.77 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:13 PM PDT 24
Peak memory 200844 kb
Host smart-0a1ef381-6124-4326-ab18-9548e62c5ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620116054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.3620116054
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1115956183
Short name T664
Test name
Test status
Simulation time 3896280720 ps
CPU time 5.84 seconds
Started Aug 02 04:56:10 PM PDT 24
Finished Aug 02 04:56:16 PM PDT 24
Peak memory 200876 kb
Host smart-89556507-19dc-44ba-83d6-4f9cf43435d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115956183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.1115956183
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3661402422
Short name T313
Test name
Test status
Simulation time 65097462260 ps
CPU time 159.98 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:58:52 PM PDT 24
Peak memory 201076 kb
Host smart-7457d20a-c6fa-4d37-8cd9-a87659e10361
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661402422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3661402422
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.243814453
Short name T320
Test name
Test status
Simulation time 104657167096 ps
CPU time 266.57 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 05:00:38 PM PDT 24
Peak memory 201112 kb
Host smart-31cb2488-b1fc-400e-be02-f35d3edeb21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243814453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wit
h_pre_cond.243814453
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3739528587
Short name T54
Test name
Test status
Simulation time 4968088791 ps
CPU time 12.76 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:24 PM PDT 24
Peak memory 200780 kb
Host smart-3a3b5b82-44a8-4a3d-996a-807e85cfd056
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739528587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3739528587
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.2094558294
Short name T483
Test name
Test status
Simulation time 2826593631 ps
CPU time 2.45 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:14 PM PDT 24
Peak memory 200856 kb
Host smart-5fedb257-a8a7-4664-9828-bd79dc934f21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094558294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.2094558294
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1571605582
Short name T577
Test name
Test status
Simulation time 2612813698 ps
CPU time 7.56 seconds
Started Aug 02 04:56:15 PM PDT 24
Finished Aug 02 04:56:23 PM PDT 24
Peak memory 200708 kb
Host smart-eec0f85d-3b91-4b29-9656-d216fa75bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571605582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.1571605582
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1020800686
Short name T229
Test name
Test status
Simulation time 2456894283 ps
CPU time 7.47 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200764 kb
Host smart-91b29453-44ff-43c5-b7e1-796fac96d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020800686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1020800686
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1623548782
Short name T551
Test name
Test status
Simulation time 2160738768 ps
CPU time 6.52 seconds
Started Aug 02 04:56:13 PM PDT 24
Finished Aug 02 04:56:19 PM PDT 24
Peak memory 200836 kb
Host smart-4c86b237-40ee-4cc3-a124-385b697505f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623548782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1623548782
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.43139483
Short name T195
Test name
Test status
Simulation time 2509390821 ps
CPU time 7.07 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200832 kb
Host smart-66dc2d59-59e4-460e-9670-2ebea87035db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43139483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.43139483
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.488850321
Short name T413
Test name
Test status
Simulation time 2117895672 ps
CPU time 3.23 seconds
Started Aug 02 04:56:11 PM PDT 24
Finished Aug 02 04:56:14 PM PDT 24
Peak memory 200652 kb
Host smart-98e2bede-f08b-48cc-b655-4db9ae709feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488850321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.488850321
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.2769952939
Short name T150
Test name
Test status
Simulation time 15024172870 ps
CPU time 37.59 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:50 PM PDT 24
Peak memory 200776 kb
Host smart-7d450ed6-6de3-4675-8571-a04bdeb96e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769952939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.2769952939
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2592678003
Short name T468
Test name
Test status
Simulation time 4775953560 ps
CPU time 5.33 seconds
Started Aug 02 04:56:12 PM PDT 24
Finished Aug 02 04:56:18 PM PDT 24
Peak memory 200908 kb
Host smart-f513a6d6-94c5-415e-b346-109a8da9bb7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592678003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.2592678003
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3115903998
Short name T161
Test name
Test status
Simulation time 24331320260 ps
CPU time 62.58 seconds
Started Aug 02 04:57:56 PM PDT 24
Finished Aug 02 04:58:59 PM PDT 24
Peak memory 200992 kb
Host smart-fb7e5dbc-8271-4623-b68d-cc6ca38904e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115903998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.3115903998
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1881820265
Short name T542
Test name
Test status
Simulation time 29136544137 ps
CPU time 7.47 seconds
Started Aug 02 04:57:53 PM PDT 24
Finished Aug 02 04:58:00 PM PDT 24
Peak memory 201240 kb
Host smart-9e05d797-0372-4544-9520-06638daf1daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881820265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.1881820265
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3431080925
Short name T68
Test name
Test status
Simulation time 62581608060 ps
CPU time 35.99 seconds
Started Aug 02 04:57:50 PM PDT 24
Finished Aug 02 04:58:26 PM PDT 24
Peak memory 201232 kb
Host smart-6506cd96-a329-4970-8443-60ef9428f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431080925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3431080925
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2062402286
Short name T325
Test name
Test status
Simulation time 143402710349 ps
CPU time 345.26 seconds
Started Aug 02 04:57:51 PM PDT 24
Finished Aug 02 05:03:36 PM PDT 24
Peak memory 201140 kb
Host smart-e4bb66d8-dd63-4fc0-bdf1-20c39acbbd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062402286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.2062402286
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.237589272
Short name T675
Test name
Test status
Simulation time 220314330899 ps
CPU time 228.83 seconds
Started Aug 02 04:58:11 PM PDT 24
Finished Aug 02 05:02:00 PM PDT 24
Peak memory 201032 kb
Host smart-026a6b4a-3f5b-4e77-9d44-21a2b60c2817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237589272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_wi
th_pre_cond.237589272
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1857914455
Short name T328
Test name
Test status
Simulation time 150214797033 ps
CPU time 191.4 seconds
Started Aug 02 04:57:52 PM PDT 24
Finished Aug 02 05:01:04 PM PDT 24
Peak memory 201088 kb
Host smart-9f4ab7b9-613f-4286-82b2-a919337d611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857914455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.1857914455
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3469703634
Short name T718
Test name
Test status
Simulation time 59394900206 ps
CPU time 140.54 seconds
Started Aug 02 04:57:57 PM PDT 24
Finished Aug 02 05:00:18 PM PDT 24
Peak memory 201132 kb
Host smart-9adf66cc-dc67-4856-b55e-ee359141252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469703634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.3469703634
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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