Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1338

1

T1

5

T12

13

T7

8

auto[1]

1899

1

T1

11

T7

16

T8

17

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2701

1

T1

11

T12

13

T7

20

auto[1]

536

1

T1

5

T7

4

T8

4

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3031

1

T1

16

T12

13

T7

24

auto[1]

206

1

T8

7

T9

13

T10

1

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3079

1

T1

14

T12

13

T7

24

auto[1]

158

1

T1

2

T30

3

T31

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3092

1

T1

16

T12

13

T7

20

auto[1]

145

1

T7

4

T8

2

T10

2

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1998

1

T1

1

T12

13

T7

4

auto[1]

1239

1

T1

15

T7

20

T8

13

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1391

1

T1

5

T12

3

T7

10

auto[1]

1846

1

T1

11

T12

10

T7

14

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1402

1

T1

8

T12

5

T7

10

auto[1]

1835

1

T1

8

T12

8

T7

14

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1463

1

T1

7

T12

1

T7

12

auto[1]

1774

1

T1

9

T12

12

T7

12

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1362

1

T1

6

T12

9

T7

7

auto[1]

1875

1

T1

10

T12

4

T7

17

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T8

1

T9

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T1

2

T7

1

T87

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T44

1

T107

1

T68

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T7

1

T30

1

T87

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T12

1

T10

1

T26

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T7

1

T42

1

T30

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T8

1

T9

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T1

1

T7

1

T42

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T12

1

T76

1

T107

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T42

1

T30

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T10

1

T42

1

T107

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T42

1

T87

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T12

1

T26

2

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T30

1

T67

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

48

1

T10

1

T106

1

T107

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

36

1

T72

1

T140

1

T200

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T8

1

T76

1

T68

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T7

1

T30

1

T72

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T8

1

T9

1

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T7

1

T200

1

T123

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T10

1

T76

2

T106

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T42

1

T68

2

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T34

1

T41

2

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T7

1

T30

1

T68

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T44

8

T76

1

T106

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T1

1

T71

1

T72

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T106

1

T107

2

T108

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T72

1

T199

1

T200

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T10

1

T26

3

T76

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T7

1

T87

2

T72

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

60

1

T7

1

T9

1

T34

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

47

1

T7

1

T30

2

T71

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T8

1

T10

1

T26

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T8

1

T30

1

T71

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T44

1

T31

1

T109

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T1

1

T30

1

T72

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T8

4

T9

1

T44

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T7

1

T42

1

T71

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

76

1

T8

6

T9

3

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T7

1

T8

3

T30

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T26

1

T67

1

T108

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T67

2

T72

4

T200

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

37

1

T10

1

T41

1

T108

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T1

1

T72

1

T121

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T1

1

T12

2

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T123

1

T233

1

T244

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

53

1

T10

2

T34

1

T41

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

63

1

T7

3

T30

1

T72

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T26

1

T44

1

T106

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T71

1

T87

1

T199

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T8

1

T10

1

T31

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T8

5

T87

1

T72

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T10

1

T76

2

T107

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T7

1

T68

5

T87

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T10

1

T76

2

T106

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

46

1

T1

1

T67

3

T87

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T12

8

T10

1

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T199

1

T200

1

T226

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T76

1

T109

2

T72

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

57

1

T1

1

T7

1

T30

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T10

1

T26

4

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

48

1

T30

1

T67

3

T87

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

276

1

T7

3

T9

13

T10

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T1

2

T30

1

T72

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T42

1

T71

1

T72

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T42

1

T87

1

T253

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T140

1

T327

1

T328

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T1

1

T42

1

T71

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T42

1

T200

1

T123

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T87

1

T199

1

T123

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T71

1

T140

1

T199

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T42

1

T72

1

T251

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T42

1

T87

1

T72

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T71

1

T72

1

T329

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T121

1

T251

1

T327

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T200

1

T328

1

T134

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T140

1

T233

1

T253

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T42

1

T71

1

T140

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T121

1

T253

1

T330

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T71

1

T72

1

T251

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T8

2

T42

1

T87

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T30

2

T87

1

T199

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T1

1

T8

2

T87

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T123

1

T253

1

T331

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T7

1

T232

1

T329

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T42

1

T233

1

T234

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T234

2

T149

1

T332

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T140

1

T251

1

T333

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T7

1

T42

1

T30

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T243

1

T334

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T72

1

T328

1

T134

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T7

1

T251

1

T253

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T226

2

T233

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T42

2

T71

1

T72

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T200

1

T251

1

T330

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

121

1

T1

3

T7

1

T42

7

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	24	72	75.00	24
Automatically Generated Cross Bins	96	24	72	75.00	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[0]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T8

1

T9

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T1

2

T7

1

T42

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

66

1

T44

1

T107

1

T68

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T7

1

T42

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T12

1

T10

1

T26

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T7

1

T42

1

T30

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T8

1

T9

3

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T1

2

T7

1

T42

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

32

1

T12

1

T9

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T42

2

T30

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T10

1

T42

1

T107

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T42

1

T87

2

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T12

1

T26

2

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T30

1

T67

1

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

53

1

T9

1

T10

1

T106

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

47

1

T42

1

T72

2

T140

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T8

1

T76

1

T68

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T7

1

T42

1

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T8

1

T9

2

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T7

1

T71

1

T72

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T10

1

T76

2

T106

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T42

1

T68

2

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T34

1

T41

2

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T7

1

T30

1

T68

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

59

1

T10

1

T44

8

T76

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T1

1

T71

1

T72

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T9

1

T106

1

T107

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

54

1

T42

1

T71

1

T72

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T9

1

T10

1

T26

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T7

1

T87

2

T72

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T7

1

T9

1

T34

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

56

1

T7

1

T30

2

T71

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T8

1

T10

1

T26

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T8

1

T42

1

T30

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T44

1

T31

1

T107

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

40

1

T1

1

T30

3

T87

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T8

4

T9

2

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

43

1

T1

1

T7

1

T42

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

78

1

T8

3

T9

3

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T8

3

T30

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T26

1

T67

1

T108

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T7

1

T67

2

T72

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T10

1

T41

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T1

1

T42

1

T72

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T1

1

T12

2

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T123

1

T233

1

T234

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

53

1

T9

1

T10

2

T34

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

78

1

T7

3

T30

1

T72

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T9

1

T26

1

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T7

1

T42

1

T30

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T8

1

T9

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T8

5

T87

1

T72

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T10

1

T76

2

T107

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T7

1

T68

5

T87

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

69

1

T10

1

T76

2

T106

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

54

1

T1

1

T7

1

T67

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T12

8

T10

1

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T199

1

T200

1

T226

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T76

1

T109

2

T72

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

68

1

T1

1

T7

1

T42

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T10

1

T26

4

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T30

1

T67

3

T87

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

159

1

T7

3

T9

1

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

122

1

T1

5

T7

1

T42

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T184

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T335

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T330

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T8

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T8

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T336

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T226

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T42

2

T123

3

T251

3

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T8

1

T9

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T1

2

T7

1

T42

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

66

1

T44

1

T107

1

T68

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T7

1

T42

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T12

1

T10

1

T26

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T7

1

T42

1

T30

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T8

1

T9

3

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T1

2

T7

1

T42

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

32

1

T12

1

T9

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T42

2

T30

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T10

1

T42

1

T107

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T42

1

T87

2

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T12

1

T26

2

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T30

1

T67

1

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T9

1

T10

1

T106

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

47

1

T42

1

T72

2

T140

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T8

1

T76

1

T68

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T7

1

T42

1

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T8

1

T9

2

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T7

1

T71

1

T72

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T10

1

T76

2

T106

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

38

1

T42

1

T68

2

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T34

1

T41

2

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T7

1

T30

1

T68

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

59

1

T10

1

T44

8

T76

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T1

1

T71

1

T72

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T9

1

T106

1

T107

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

54

1

T42

1

T71

1

T72

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T9

1

T10

1

T26

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T7

1

T87

2

T72

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

64

1

T7

1

T9

1

T34

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

56

1

T7

1

T30

2

T71

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T8

1

T10

1

T26

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T8

3

T42

1

T30

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T44

1

T31

1

T107

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

40

1

T1

1

T30

3

T87

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T8

4

T9

2

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

45

1

T1

1

T7

1

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

76

1

T8

6

T9

3

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T8

3

T30

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T26

1

T67

1

T108

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T7

1

T67

2

T72

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T10

1

T41

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T1

1

T42

1

T72

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T1

1

T12

2

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T123

1

T233

1

T234

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T9

1

T10

2

T34

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

78

1

T7

3

T30

1

T72

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T9

1

T26

1

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T7

1

T42

1

T30

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T8

1

T9

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T8

5

T87

1

T72

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T10

1

T76

2

T107

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T7

1

T68

5

T87

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

70

1

T10

1

T76

2

T106

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

54

1

T1

1

T7

1

T67

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T12

8

T10

1

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T199

1

T200

1

T226

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T76

1

T109

2

T72

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

68

1

T1

1

T7

1

T42

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T10

1

T26

4

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T30

1

T67

3

T87

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

195

1

T7

3

T9

14

T10

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

114

1

T1

3

T7

1

T42

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T119

1

T335

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T337

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

23

1

T1

2

T72

3

T140

5

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T8

1

T9

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T1

2

T7

1

T42

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

65

1

T44

1

T107

1

T68

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T7

1

T42

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T12

1

T10

1

T26

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T7

1

T42

1

T30

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

63

1

T8

1

T9

3

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T1

2

T7

1

T42

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

32

1

T12

1

T9

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T42

2

T30

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T10

1

T42

1

T107

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T42

1

T87

2

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T12

1

T26

2

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T30

1

T67

1

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

53

1

T9

1

T10

1

T106

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

47

1

T42

1

T72

2

T140

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T8

1

T76

1

T68

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T7

1

T42

1

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T8

1

T9

2

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T7

1

T71

1

T72

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T10

1

T76

2

T106

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

38

1

T42

1

T68

2

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T34

1

T41

2

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T7

1

T30

1

T68

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T10

1

T44

8

T76

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T1

1

T71

1

T72

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

56

1

T9

1

T106

1

T107

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

54

1

T42

1

T71

1

T72

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T9

1

T10

1

T26

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T7

1

T87

2

T72

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T7

1

T9

1

T34

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

56

1

T7

1

T30

2

T71

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T8

1

T10

1

T26

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T8

1

T42

1

T30

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T44

1

T31

1

T107

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

40

1

T1

1

T30

3

T87

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

61

1

T8

4

T9

2

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

45

1

T1

1

T7

1

T8

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

80

1

T8

6

T9

3

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T8

3

T30

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T26

1

T67

1

T108

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T7

1

T67

2

T72

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

37

1

T10

1

T41

1

T106

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T1

1

T42

1

T72

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T1

1

T12

2

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T123

1

T233

1

T234

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T9

1

T10

2

T34

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

78

1

T7

3

T30

1

T72

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T9

1

T26

1

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T7

1

T42

1

T30

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T8

1

T9

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T8

5

T87

1

T72

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T10

1

T76

2

T107

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T7

1

T68

5

T87

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

77

1

T10

1

T76

2

T106

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

54

1

T1

1

T7

1

T67

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T12

8

T10

1

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T199

1

T200

1

T226

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T76

1

T109

2

T72

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

68

1

T1

1

T7

1

T42

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T10

1

T26

4

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T30

1

T67

3

T87

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

190

1

T9

14

T10

1

T42

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

128

1

T1

5

T42

3

T30

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T8

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T7

1

T42

4

T72

2

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded