Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
865 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T23 |
11 |
| auto[1] |
815 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T23 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T21 |
7 |
|
T22 |
14 |
|
T23 |
8 |
| auto[1] |
841 |
1 |
|
|
T21 |
13 |
|
T22 |
6 |
|
T23 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T21 |
9 |
|
T22 |
13 |
|
T23 |
12 |
| auto[1] |
837 |
1 |
|
|
T21 |
11 |
|
T22 |
7 |
|
T23 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T21 |
10 |
|
T22 |
9 |
|
T23 |
9 |
| auto[1] |
831 |
1 |
|
|
T21 |
10 |
|
T22 |
11 |
|
T23 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T21 |
8 |
|
T22 |
10 |
|
T23 |
9 |
| auto[1] |
850 |
1 |
|
|
T21 |
12 |
|
T22 |
10 |
|
T23 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
856 |
1 |
|
|
T21 |
12 |
|
T22 |
8 |
|
T23 |
10 |
| auto[1] |
824 |
1 |
|
|
T21 |
8 |
|
T22 |
12 |
|
T23 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
815 |
1 |
|
|
T21 |
4 |
|
T22 |
10 |
|
T23 |
7 |
| auto[1] |
865 |
1 |
|
|
T21 |
16 |
|
T22 |
10 |
|
T23 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T21 |
6 |
|
T22 |
8 |
|
T23 |
10 |
| auto[1] |
860 |
1 |
|
|
T21 |
14 |
|
T22 |
12 |
|
T23 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T21 |
12 |
|
T22 |
8 |
|
T23 |
8 |
| auto[1] |
849 |
1 |
|
|
T21 |
8 |
|
T22 |
12 |
|
T23 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
850 |
1 |
|
|
T21 |
9 |
|
T22 |
10 |
|
T23 |
8 |
| auto[1] |
830 |
1 |
|
|
T21 |
11 |
|
T22 |
10 |
|
T23 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
837 |
1 |
|
|
T21 |
10 |
|
T22 |
14 |
|
T23 |
10 |
| auto[1] |
843 |
1 |
|
|
T21 |
10 |
|
T22 |
6 |
|
T23 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T21 |
6 |
|
T22 |
7 |
|
T23 |
11 |
| auto[1] |
839 |
1 |
|
|
T21 |
14 |
|
T22 |
13 |
|
T23 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T21 |
9 |
|
T22 |
12 |
|
T23 |
10 |
| auto[1] |
847 |
1 |
|
|
T21 |
11 |
|
T22 |
8 |
|
T23 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T21 |
7 |
|
T22 |
14 |
|
T23 |
8 |
| auto[1] |
841 |
1 |
|
|
T21 |
13 |
|
T22 |
6 |
|
T23 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
846 |
1 |
|
|
T21 |
8 |
|
T22 |
10 |
|
T23 |
7 |
| auto[1] |
834 |
1 |
|
|
T21 |
12 |
|
T22 |
10 |
|
T23 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T21 |
11 |
|
T22 |
8 |
|
T23 |
10 |
| auto[1] |
826 |
1 |
|
|
T21 |
9 |
|
T22 |
12 |
|
T23 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
809 |
1 |
|
|
T21 |
10 |
|
T22 |
12 |
|
T23 |
6 |
| auto[1] |
871 |
1 |
|
|
T21 |
10 |
|
T22 |
8 |
|
T23 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
817 |
1 |
|
|
T21 |
12 |
|
T22 |
8 |
|
T23 |
7 |
| auto[1] |
863 |
1 |
|
|
T21 |
8 |
|
T22 |
12 |
|
T23 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T21 |
12 |
|
T22 |
9 |
|
T23 |
7 |
| auto[1] |
840 |
1 |
|
|
T21 |
8 |
|
T22 |
11 |
|
T23 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
825 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T23 |
8 |
| auto[1] |
855 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T23 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T21 |
13 |
|
T22 |
9 |
|
T23 |
11 |
| auto[1] |
860 |
1 |
|
|
T21 |
7 |
|
T22 |
11 |
|
T23 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T21 |
10 |
|
T22 |
9 |
|
T23 |
8 |
| auto[1] |
814 |
1 |
|
|
T21 |
10 |
|
T22 |
11 |
|
T23 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T21 |
11 |
|
T22 |
7 |
|
T23 |
12 |
| auto[1] |
827 |
1 |
|
|
T21 |
9 |
|
T22 |
13 |
|
T23 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T21 |
6 |
|
T22 |
7 |
|
T23 |
11 |
| auto[1] |
839 |
1 |
|
|
T21 |
14 |
|
T22 |
13 |
|
T23 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T21 |
3 |
|
T22 |
7 |
|
T23 |
3 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T23 |
4 |
| auto[1] |
auto[0] |
416 |
1 |
|
|
T21 |
6 |
|
T22 |
6 |
|
T23 |
9 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T23 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T21 |
5 |
|
T22 |
4 |
|
T23 |
3 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T23 |
7 |
| auto[1] |
auto[0] |
415 |
1 |
|
|
T21 |
5 |
|
T22 |
5 |
|
T23 |
6 |
| auto[1] |
auto[1] |
411 |
1 |
|
|
T21 |
4 |
|
T22 |
7 |
|
T23 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
393 |
1 |
|
|
T21 |
6 |
|
T22 |
5 |
|
T23 |
4 |
| auto[0] |
auto[1] |
416 |
1 |
|
|
T21 |
4 |
|
T22 |
7 |
|
T23 |
2 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T21 |
2 |
|
T22 |
5 |
|
T23 |
5 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T21 |
8 |
|
T22 |
3 |
|
T23 |
9 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
410 |
1 |
|
|
T21 |
9 |
|
T22 |
2 |
|
T23 |
5 |
| auto[0] |
auto[1] |
407 |
1 |
|
|
T21 |
3 |
|
T22 |
6 |
|
T23 |
2 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T21 |
3 |
|
T22 |
6 |
|
T23 |
5 |
| auto[1] |
auto[1] |
417 |
1 |
|
|
T21 |
5 |
|
T22 |
6 |
|
T23 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
393 |
1 |
|
|
T21 |
2 |
|
T22 |
5 |
|
T59 |
6 |
| auto[0] |
auto[1] |
447 |
1 |
|
|
T21 |
10 |
|
T22 |
4 |
|
T23 |
7 |
| auto[1] |
auto[0] |
422 |
1 |
|
|
T21 |
2 |
|
T22 |
5 |
|
T23 |
7 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T21 |
6 |
|
T22 |
6 |
|
T23 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
388 |
1 |
|
|
T21 |
1 |
|
T22 |
4 |
|
T23 |
2 |
| auto[0] |
auto[1] |
437 |
1 |
|
|
T21 |
7 |
|
T22 |
5 |
|
T23 |
6 |
| auto[1] |
auto[0] |
432 |
1 |
|
|
T21 |
5 |
|
T22 |
4 |
|
T23 |
8 |
| auto[1] |
auto[1] |
423 |
1 |
|
|
T21 |
7 |
|
T22 |
7 |
|
T23 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
443 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T23 |
3 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T21 |
5 |
|
T22 |
6 |
|
T23 |
5 |
| auto[1] |
auto[0] |
407 |
1 |
|
|
T21 |
4 |
|
T22 |
7 |
|
T23 |
5 |
| auto[1] |
auto[1] |
407 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T23 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T23 |
6 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T23 |
6 |
| auto[1] |
auto[0] |
407 |
1 |
|
|
T21 |
4 |
|
T22 |
10 |
|
T23 |
4 |
| auto[1] |
auto[1] |
420 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T23 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
432 |
1 |
|
|
T21 |
4 |
|
T22 |
8 |
|
T23 |
4 |
| auto[0] |
auto[1] |
401 |
1 |
|
|
T21 |
5 |
|
T22 |
4 |
|
T23 |
6 |
| auto[1] |
auto[0] |
433 |
1 |
|
|
T21 |
7 |
|
T22 |
4 |
|
T23 |
7 |
| auto[1] |
auto[1] |
414 |
1 |
|
|
T21 |
4 |
|
T22 |
4 |
|
T23 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
839 |
1 |
|
|
T21 |
7 |
|
T22 |
14 |
|
T23 |
8 |
| auto[1] |
auto[1] |
841 |
1 |
|
|
T21 |
13 |
|
T22 |
6 |
|
T23 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
415 |
1 |
|
|
T21 |
11 |
|
T22 |
5 |
|
T23 |
4 |
| auto[0] |
auto[1] |
405 |
1 |
|
|
T21 |
2 |
|
T22 |
4 |
|
T23 |
7 |
| auto[1] |
auto[0] |
416 |
1 |
|
|
T21 |
1 |
|
T22 |
3 |
|
T23 |
4 |
| auto[1] |
auto[1] |
444 |
1 |
|
|
T21 |
6 |
|
T22 |
8 |
|
T23 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
841 |
1 |
|
|
T21 |
6 |
|
T22 |
7 |
|
T23 |
11 |
| auto[1] |
auto[1] |
839 |
1 |
|
|
T21 |
14 |
|
T22 |
13 |
|
T23 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T40 |
11 |
|
T136 |
9 |
|
T154 |
13 |
| auto[1] |
129 |
1 |
|
|
T40 |
9 |
|
T136 |
11 |
|
T154 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T40 |
7 |
|
T136 |
13 |
|
T154 |
12 |
| auto[1] |
140 |
1 |
|
|
T40 |
13 |
|
T136 |
7 |
|
T154 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T40 |
12 |
|
T136 |
6 |
|
T154 |
8 |
| auto[1] |
121 |
1 |
|
|
T40 |
8 |
|
T136 |
14 |
|
T154 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T40 |
12 |
|
T136 |
8 |
|
T154 |
7 |
| auto[1] |
128 |
1 |
|
|
T40 |
8 |
|
T136 |
12 |
|
T154 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T40 |
9 |
|
T136 |
11 |
|
T154 |
9 |
| auto[1] |
120 |
1 |
|
|
T40 |
11 |
|
T136 |
9 |
|
T154 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T40 |
12 |
|
T136 |
11 |
|
T154 |
9 |
| auto[1] |
131 |
1 |
|
|
T40 |
8 |
|
T136 |
9 |
|
T154 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T40 |
11 |
|
T136 |
11 |
|
T154 |
14 |
| auto[1] |
131 |
1 |
|
|
T40 |
9 |
|
T136 |
9 |
|
T154 |
6 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T40 |
9 |
|
T136 |
12 |
|
T154 |
9 |
| auto[1] |
124 |
1 |
|
|
T40 |
11 |
|
T136 |
8 |
|
T154 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T40 |
10 |
|
T136 |
12 |
|
T154 |
9 |
| auto[1] |
117 |
1 |
|
|
T40 |
10 |
|
T136 |
8 |
|
T154 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T40 |
7 |
|
T136 |
12 |
|
T154 |
10 |
| auto[1] |
143 |
1 |
|
|
T40 |
13 |
|
T136 |
8 |
|
T154 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T40 |
8 |
|
T136 |
11 |
|
T154 |
10 |
| auto[1] |
130 |
1 |
|
|
T40 |
12 |
|
T136 |
9 |
|
T154 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T40 |
11 |
|
T136 |
13 |
|
T154 |
13 |
| auto[1] |
110 |
1 |
|
|
T40 |
9 |
|
T136 |
7 |
|
T154 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T40 |
8 |
|
T136 |
10 |
|
T154 |
10 |
| auto[1] |
134 |
1 |
|
|
T40 |
12 |
|
T136 |
10 |
|
T154 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T40 |
7 |
|
T136 |
13 |
|
T154 |
12 |
| auto[1] |
140 |
1 |
|
|
T40 |
13 |
|
T136 |
7 |
|
T154 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T40 |
14 |
|
T136 |
12 |
|
T154 |
12 |
| auto[1] |
122 |
1 |
|
|
T40 |
6 |
|
T136 |
8 |
|
T154 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T40 |
8 |
|
T136 |
6 |
|
T154 |
7 |
| auto[1] |
135 |
1 |
|
|
T40 |
12 |
|
T136 |
14 |
|
T154 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
106 |
1 |
|
|
T40 |
7 |
|
T136 |
12 |
|
T154 |
10 |
| auto[1] |
154 |
1 |
|
|
T40 |
13 |
|
T136 |
8 |
|
T154 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T40 |
12 |
|
T136 |
12 |
|
T154 |
10 |
| auto[1] |
119 |
1 |
|
|
T40 |
8 |
|
T136 |
8 |
|
T154 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T40 |
7 |
|
T136 |
8 |
|
T154 |
10 |
| auto[1] |
132 |
1 |
|
|
T40 |
13 |
|
T136 |
12 |
|
T154 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T40 |
11 |
|
T136 |
11 |
|
T154 |
7 |
| auto[1] |
145 |
1 |
|
|
T40 |
9 |
|
T136 |
9 |
|
T154 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T40 |
10 |
|
T136 |
9 |
|
T154 |
7 |
| auto[1] |
142 |
1 |
|
|
T40 |
10 |
|
T136 |
11 |
|
T154 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T40 |
5 |
|
T136 |
9 |
|
T154 |
9 |
| auto[1] |
147 |
1 |
|
|
T40 |
15 |
|
T136 |
11 |
|
T154 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T40 |
10 |
|
T136 |
10 |
|
T154 |
7 |
| auto[1] |
134 |
1 |
|
|
T40 |
10 |
|
T136 |
10 |
|
T154 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T40 |
11 |
|
T136 |
13 |
|
T154 |
13 |
| auto[1] |
110 |
1 |
|
|
T40 |
9 |
|
T136 |
7 |
|
T154 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
79 |
1 |
|
|
T40 |
7 |
|
T136 |
5 |
|
T154 |
6 |
| auto[0] |
auto[1] |
59 |
1 |
|
|
T40 |
7 |
|
T136 |
7 |
|
T154 |
6 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T40 |
5 |
|
T136 |
1 |
|
T154 |
2 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T40 |
1 |
|
T136 |
7 |
|
T154 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T40 |
4 |
|
T136 |
3 |
|
T154 |
3 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T40 |
4 |
|
T136 |
3 |
|
T154 |
4 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T40 |
8 |
|
T136 |
5 |
|
T154 |
4 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T40 |
4 |
|
T136 |
9 |
|
T154 |
9 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T40 |
3 |
|
T136 |
6 |
|
T154 |
5 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T40 |
4 |
|
T136 |
6 |
|
T154 |
5 |
| auto[1] |
auto[0] |
81 |
1 |
|
|
T40 |
6 |
|
T136 |
5 |
|
T154 |
4 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T40 |
7 |
|
T136 |
3 |
|
T154 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T40 |
7 |
|
T136 |
6 |
|
T154 |
5 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T40 |
5 |
|
T136 |
6 |
|
T154 |
5 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T40 |
5 |
|
T136 |
5 |
|
T154 |
4 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T40 |
3 |
|
T136 |
3 |
|
T154 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T40 |
2 |
|
T136 |
4 |
|
T154 |
7 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T40 |
5 |
|
T136 |
4 |
|
T154 |
3 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T40 |
9 |
|
T136 |
7 |
|
T154 |
7 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T40 |
4 |
|
T136 |
5 |
|
T154 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T40 |
3 |
|
T136 |
6 |
|
T154 |
3 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T40 |
8 |
|
T136 |
5 |
|
T154 |
4 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T40 |
6 |
|
T136 |
6 |
|
T154 |
6 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T40 |
3 |
|
T136 |
3 |
|
T154 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T40 |
2 |
|
T136 |
6 |
|
T154 |
5 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T40 |
3 |
|
T136 |
3 |
|
T154 |
4 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T40 |
5 |
|
T136 |
6 |
|
T154 |
5 |
| auto[1] |
auto[1] |
89 |
1 |
|
|
T40 |
10 |
|
T136 |
5 |
|
T154 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T40 |
5 |
|
T136 |
6 |
|
T154 |
4 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T40 |
5 |
|
T136 |
4 |
|
T154 |
3 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T40 |
3 |
|
T136 |
5 |
|
T154 |
6 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T40 |
7 |
|
T136 |
5 |
|
T154 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T40 |
5 |
|
T136 |
4 |
|
T154 |
6 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T40 |
3 |
|
T136 |
6 |
|
T154 |
4 |
| auto[1] |
auto[0] |
68 |
1 |
|
|
T40 |
6 |
|
T136 |
5 |
|
T154 |
7 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T40 |
6 |
|
T136 |
5 |
|
T154 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
120 |
1 |
|
|
T40 |
7 |
|
T136 |
13 |
|
T154 |
12 |
| auto[1] |
auto[1] |
140 |
1 |
|
|
T40 |
13 |
|
T136 |
7 |
|
T154 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T40 |
7 |
|
T136 |
6 |
|
T154 |
2 |
| auto[0] |
auto[1] |
57 |
1 |
|
|
T40 |
3 |
|
T136 |
3 |
|
T154 |
5 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T40 |
3 |
|
T136 |
6 |
|
T154 |
7 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T40 |
7 |
|
T136 |
5 |
|
T154 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
150 |
1 |
|
|
T40 |
11 |
|
T136 |
13 |
|
T154 |
13 |
| auto[1] |
auto[1] |
110 |
1 |
|
|
T40 |
9 |
|
T136 |
7 |
|
T154 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T40 |
9 |
|
T371 |
7 |
|
T308 |
9 |
| auto[1] |
52 |
1 |
|
|
T40 |
11 |
|
T371 |
13 |
|
T308 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
44 |
1 |
|
|
T40 |
8 |
|
T371 |
10 |
|
T308 |
7 |
| auto[1] |
56 |
1 |
|
|
T40 |
12 |
|
T371 |
10 |
|
T308 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T40 |
12 |
|
T371 |
9 |
|
T308 |
11 |
| auto[1] |
45 |
1 |
|
|
T40 |
8 |
|
T371 |
11 |
|
T308 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T40 |
11 |
|
T371 |
8 |
|
T308 |
9 |
| auto[1] |
53 |
1 |
|
|
T40 |
9 |
|
T371 |
12 |
|
T308 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T40 |
6 |
|
T371 |
9 |
|
T308 |
9 |
| auto[1] |
54 |
1 |
|
|
T40 |
14 |
|
T371 |
11 |
|
T308 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T40 |
11 |
|
T371 |
9 |
|
T308 |
9 |
| auto[1] |
48 |
1 |
|
|
T40 |
9 |
|
T371 |
11 |
|
T308 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T40 |
12 |
|
T371 |
10 |
|
T308 |
10 |
| auto[1] |
45 |
1 |
|
|
T40 |
8 |
|
T371 |
10 |
|
T308 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T40 |
14 |
|
T371 |
9 |
|
T308 |
15 |
| auto[1] |
43 |
1 |
|
|
T40 |
6 |
|
T371 |
11 |
|
T308 |
5 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T40 |
10 |
|
T371 |
10 |
|
T308 |
6 |
| auto[1] |
55 |
1 |
|
|
T40 |
10 |
|
T371 |
10 |
|
T308 |
14 |