Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_out   cfg.vif.pwrb_out   COUNT   AT LEAST   STATUS   TEST   COUNT   
auto[0] auto[0] 6 1 T349 6
auto[0] auto[1] 5 1 T349 5
auto[1] auto[0] 3 1 T349 3
auto[1] auto[1] 6 1 T349 6


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_present   cfg.vif.ac_present   COUNT   AT LEAST   STATUS   TEST   COUNT   
auto[0] auto[0] 6 1 T349 6
auto[0] auto[1] 4 1 T349 4
auto[1] auto[0] 7 1 T349 7
auto[1] auto[1] 3 1 T349 3


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disable   cfg.vif.bat_disable   COUNT   AT LEAST   STATUS   TEST   COUNT   
auto[0] auto[0] 8 1 T349 8
auto[1] auto[1] 12 1 T349 12


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_open   cfg.vif.lid_open   COUNT   AT LEAST   STATUS   TEST   COUNT   
auto[0] auto[0] 8 1 T349 8
auto[0] auto[1] 2 1 T349 2
auto[1] auto[0] 3 1 T349 3
auto[1] auto[1] 7 1 T349 7


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeup   cfg.vif.z3_wakeup   COUNT   AT LEAST   STATUS   TEST   COUNT   
auto[0] auto[0] 13 1 T349 13
auto[1] auto[1] 7 1 T349 7


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid0 0 Excluded
invalid1 0 Excluded