Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.30	100.00	97.89				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_onehot_check

	Line No.	Total	Covered	Percent
TOTAL		187	187	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	136	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv' or '../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
86	35	35
87	35	35
95	38	38(25 unreachable)
96	38	38(25 unreachable)
98	37	37(26 unreachable)
108	1	1
111	1	1
121	1	1
136	1	1

---

Cond Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Conditions	616	603	97.89
Logical	616	603	97.89
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
95-96	100.00
96-98	94.86
98-121	100.00

---

Assert Coverage for Module : prim_onehot_check

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrImpliesEnable_A	818	818	0	0
AddrRange_A	818	818	0	0
AddrWidth_A	818	818	0	0
NumSources_A	818	818	0	0
Onehot0Check_A	501412727	46	0	0
gen_enable_check.gen_not_strict.EnableCheck_A	501412727	55	0	0
gen_generic.AssertConnected_A	818	818	0	0

AddrImpliesEnable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

AddrRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

AddrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

NumSources_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

Onehot0Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501412727	46	0	0
T134	200368	12	0	0
T135	962411	6	0	0
T136	100350	11	0	0
T137	200371	6	0	0
T138	244543	11	0	0

gen_enable_check.gen_not_strict.EnableCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501412727	55	0	0
T134	200368	12	0	0
T135	962411	8	0	0
T136	100350	13	0	0
T137	200371	8	0	0
T138	244543	14	0	0

gen_generic.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

	Line No.	Total	Covered	Percent
TOTAL		187	187	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	95	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	96	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	98	0	0
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	136	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv' or '../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
86	35	35
87	35	35
95	38	38(25 unreachable)
96	38	38(25 unreachable)
98	37	37(26 unreachable)
108	1	1
111	1	1
121	1	1
136	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

	Total	Covered	Percent
Conditions	498	498	100.00
Logical	498	498	100.00
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
95-96	100.00
96-98	100.00
98-121	100.00

---

Assert Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrImpliesEnable_A	818	818	0	0
AddrRange_A	818	818	0	0
AddrWidth_A	818	818	0	0
NumSources_A	818	818	0	0
Onehot0Check_A	501412727	46	0	0
gen_enable_check.gen_not_strict.EnableCheck_A	501412727	55	0	0
gen_generic.AssertConnected_A	818	818	0	0

AddrImpliesEnable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

AddrRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

AddrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

NumSources_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0

Onehot0Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501412727	46	0	0
T134	200368	12	0	0
T135	962411	6	0	0
T136	100350	11	0	0
T137	200371	6	0	0
T138	244543	11	0	0

gen_enable_check.gen_not_strict.EnableCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	501412727	55	0	0
T134	200368	12	0	0
T135	962411	8	0	0
T136	100350	13	0	0
T137	200371	8	0	0
T138	244543	14	0	0

gen_generic.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818	818	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T127	1	1	0	0
T128	1	1	0	0
T129	1	1	0	0
T130	1	1	0	0