Module Definition
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Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ec_rst_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_ac_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_lid_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_ulp_pwrb_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 100.00 92.31 100.00 100.00 u_ulp_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.88 100.00 87.50 100.00 100.00 u_wkup_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_invert_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_allowed_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_pin_out_value_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_intr_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_key_intr_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_auto_block_debounce_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_auto_block_out_ctl_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT3,T19,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT3,T19,T53
11CoveredT1,T5,T2

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 234874 0 0
SrcPulseCheck_M 2147483647 238761 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 234874 0 0
T1 2741492 144 0 0
T2 2412254 64 0 0
T3 3150238 0 0 0
T4 9271020 130 0 0
T5 1435486 48 0 0
T6 2366338 0 0 0
T7 16889889 68 0 0
T8 5519043 0 0 0
T9 4040319 0 0 0
T10 0 288 0 0
T11 0 221 0 0
T12 0 192 0 0
T13 632944 0 0 0
T14 730605 0 0 0
T15 3772515 0 0 0
T20 0 16 0 0
T21 1134561 0 0 0
T22 64387 0 0 0
T25 865130 14 0 0
T26 748510 12 0 0
T27 2785570 17 0 0
T32 0 16 0 0
T36 0 16 0 0
T39 0 12 0 0
T41 0 1 0 0
T42 0 17 0 0
T43 1281370 14 0 0
T44 0 14 0 0
T45 0 12 0 0
T46 0 4 0 0
T47 1233410 0 0 0
T48 1909940 0 0 0
T49 361013 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 238761 0 0
T1 2741492 144 0 0
T2 2412254 64 0 0
T3 3150238 0 0 0
T4 9271020 130 0 0
T5 1435486 48 0 0
T6 2366338 0 0 0
T7 16889889 68 0 0
T8 5019303 0 0 0
T9 3593157 0 0 0
T10 0 288 0 0
T11 0 221 0 0
T12 0 192 0 0
T13 632944 0 0 0
T14 730605 0 0 0
T15 3772515 0 0 0
T20 0 16 0 0
T21 1009428 0 0 0
T22 495 0 0 0
T25 865130 14 0 0
T26 748510 12 0 0
T27 2785570 17 0 0
T32 0 16 0 0
T36 0 16 0 0
T39 0 12 0 0
T41 0 1 0 0
T42 0 17 0 0
T43 1140212 14 0 0
T44 0 14 0 0
T45 0 12 0 0
T46 0 4 0 0
T47 1233410 0 0 0
T48 1909940 0 0 0
T49 752 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT16,T17,T18

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT16,T17,T18
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1916 0 0
SrcPulseCheck_M 1299919929 2029 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1916 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 8 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 2029 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 8 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT16,T17,T18

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT16,T17,T18
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 2018 0 0
SrcPulseCheck_M 9714182 2018 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 2018 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 8 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 2018 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 8 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T31,T19
11CoveredT3,T19,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T19,T53
11CoveredT3,T31,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 925 0 0
SrcPulseCheck_M 1299919929 1034 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 925 0 0
T3 2057 2 0 0
T4 24722 0 0 0
T7 15140 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 523 0 0 0
T48 761 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1034 0 0
T3 240269 2 0 0
T4 593346 0 0 0
T7 719203 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T31,T19
11CoveredT3,T19,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T19,T53
11CoveredT3,T31,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1022 0 0
SrcPulseCheck_M 9714182 1022 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1022 0 0
T3 240269 2 0 0
T4 593346 0 0 0
T7 719203 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1022 0 0
T3 2057 2 0 0
T4 24722 0 0 0
T7 15140 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 523 0 0 0
T48 761 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T31,T19
11CoveredT3,T19,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T19,T53
11CoveredT3,T31,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 926 0 0
SrcPulseCheck_M 1299919929 1041 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 926 0 0
T3 2057 2 0 0
T4 24722 0 0 0
T7 15140 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 523 0 0 0
T48 761 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1041 0 0
T3 240269 2 0 0
T4 593346 0 0 0
T7 719203 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T31,T19
11CoveredT3,T19,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T19,T53
11CoveredT3,T31,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1031 0 0
SrcPulseCheck_M 9714182 1031 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1031 0 0
T3 240269 2 0 0
T4 593346 0 0 0
T7 719203 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1031 0 0
T3 2057 2 0 0
T4 24722 0 0 0
T7 15140 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 523 0 0 0
T48 761 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T31,T19
11CoveredT3,T19,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T19,T53
11CoveredT3,T31,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 898 0 0
SrcPulseCheck_M 1299919929 1010 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 898 0 0
T3 2057 2 0 0
T4 24722 0 0 0
T7 15140 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 523 0 0 0
T48 761 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1010 0 0
T3 240269 2 0 0
T4 593346 0 0 0
T7 719203 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T31,T19
11CoveredT3,T19,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T31,T19
10CoveredT3,T19,T53
11CoveredT3,T31,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 996 0 0
SrcPulseCheck_M 9714182 996 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 996 0 0
T3 240269 2 0 0
T4 593346 0 0 0
T7 719203 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 996 0 0
T3 2057 2 0 0
T4 24722 0 0 0
T7 15140 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 3 0 0
T20 0 1 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 0 0 0
T31 0 1 0 0
T32 0 3 0 0
T47 523 0 0 0
T48 761 0 0 0
T53 0 2 0 0
T54 0 2 0 0
T55 0 3 0 0
T56 0 1 0 0
T57 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T19,T20
10CoveredT3,T19,T20
11CoveredT3,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T19,T20
10CoveredT3,T19,T20
11CoveredT3,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 905 0 0
SrcPulseCheck_M 1299919929 1019 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 905 0 0
T3 2057 4 0 0
T4 24722 0 0 0
T7 15140 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 4 0 0
T20 0 2 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T76 0 2 0 0
T77 0 2 0 0
T78 0 2 0 0
T79 0 2 0 0
T80 0 2 0 0
T81 0 2 0 0
T82 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1019 0 0
T3 240269 4 0 0
T4 593346 0 0 0
T7 719203 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 4 0 0
T20 0 2 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T76 0 2 0 0
T77 0 2 0 0
T78 0 2 0 0
T79 0 2 0 0
T80 0 2 0 0
T81 0 2 0 0
T82 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T19,T20
10CoveredT3,T19,T20
11CoveredT3,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT3,T19,T20
10CoveredT3,T19,T20
11CoveredT3,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1006 0 0
SrcPulseCheck_M 9714182 1006 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1006 0 0
T3 240269 4 0 0
T4 593346 0 0 0
T7 719203 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 4 0 0
T20 0 2 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T76 0 2 0 0
T77 0 2 0 0
T78 0 2 0 0
T79 0 2 0 0
T80 0 2 0 0
T81 0 2 0 0
T82 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1006 0 0
T3 2057 4 0 0
T4 24722 0 0 0
T7 15140 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 4 0 0
T20 0 2 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T76 0 2 0 0
T77 0 2 0 0
T78 0 2 0 0
T79 0 2 0 0
T80 0 2 0 0
T81 0 2 0 0
T82 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T10

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T2,T3
10CoveredT3,T4,T10
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1071 0 0
SrcPulseCheck_M 1299919929 1183 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1071 0 0
T1 26361 2 0 0
T2 13744 3 0 0
T3 2057 2 0 0
T4 24722 9 0 0
T5 8493 0 0 0
T6 422 0 0 0
T7 15140 2 0 0
T10 0 21 0 0
T11 0 4 0 0
T12 0 3 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T19 0 2 0 0
T52 0 10 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1183 0 0
T1 184523 2 0 0
T2 171814 3 0 0
T3 240269 2 0 0
T4 593346 9 0 0
T5 101929 0 0 0
T6 181604 0 0 0
T7 719203 2 0 0
T10 0 21 0 0
T11 0 4 0 0
T12 0 3 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T19 0 2 0 0
T52 0 10 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT21,T22,T23
10CoveredT21,T22,T23
11CoveredT21,T22,T23

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT21,T22,T23
10CoveredT21,T22,T23
11CoveredT21,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 2899 0 0
SrcPulseCheck_M 1299919929 3011 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 2899 0 0
T9 933 0 0 0
T10 47669 0 0 0
T11 33091 0 0 0
T21 492 20 0 0
T22 495 20 0 0
T23 0 20 0 0
T49 752 0 0 0
T58 0 20 0 0
T59 0 20 0 0
T60 0 20 0 0
T61 0 20 0 0
T62 0 20 0 0
T63 0 20 0 0
T64 0 20 0 0
T65 522 0 0 0
T66 430 0 0 0
T67 426 0 0 0
T68 525 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 3011 0 0
T9 448095 0 0 0
T10 116790 0 0 0
T11 397094 0 0 0
T21 125625 20 0 0
T22 64387 20 0 0
T23 0 20 0 0
T49 361013 0 0 0
T58 0 20 0 0
T59 0 20 0 0
T60 0 20 0 0
T61 0 20 0 0
T62 0 20 0 0
T63 0 20 0 0
T64 0 20 0 0
T65 255969 0 0 0
T66 55893 0 0 0
T67 53311 0 0 0
T68 65763 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT21,T22,T23
10CoveredT21,T22,T23
11CoveredT21,T22,T23

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT21,T22,T23
10CoveredT21,T22,T23
11CoveredT21,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 2998 0 0
SrcPulseCheck_M 9714182 2998 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 2998 0 0
T9 448095 0 0 0
T10 116790 0 0 0
T11 397094 0 0 0
T21 125625 20 0 0
T22 64387 20 0 0
T23 0 20 0 0
T49 361013 0 0 0
T58 0 20 0 0
T59 0 20 0 0
T60 0 20 0 0
T61 0 20 0 0
T62 0 20 0 0
T63 0 20 0 0
T64 0 20 0 0
T65 255969 0 0 0
T66 55893 0 0 0
T67 53311 0 0 0
T68 65763 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 2998 0 0
T9 933 0 0 0
T10 47669 0 0 0
T11 33091 0 0 0
T21 492 20 0 0
T22 495 20 0 0
T23 0 20 0 0
T49 752 0 0 0
T58 0 20 0 0
T59 0 20 0 0
T60 0 20 0 0
T61 0 20 0 0
T62 0 20 0 0
T63 0 20 0 0
T64 0 20 0 0
T65 522 0 0 0
T66 430 0 0 0
T67 426 0 0 0
T68 525 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT13,T4,T14
10CoveredT13,T4,T14
11CoveredT13,T4,T14

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT13,T4,T14
10CoveredT13,T4,T14
11CoveredT13,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 6563 0 0
SrcPulseCheck_M 1299919929 6680 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 6563 0 0
T3 2057 0 0 0
T4 24722 20 0 0
T7 15140 0 0 0
T10 0 20 0 0
T13 507 20 0 0
T14 507 20 0 0
T15 501 20 0 0
T21 0 1 0 0
T22 0 1 0 0
T25 686 0 0 0
T27 5516 0 0 0
T47 523 20 0 0
T48 761 0 0 0
T65 0 20 0 0
T68 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 6680 0 0
T3 240269 0 0 0
T4 593346 20 0 0
T7 719203 0 0 0
T10 0 20 0 0
T13 48181 20 0 0
T14 48200 20 0 0
T15 251000 20 0 0
T21 0 1 0 0
T22 0 1 0 0
T25 85827 0 0 0
T27 273041 0 0 0
T47 122818 20 0 0
T48 190233 0 0 0
T65 0 20 0 0
T68 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT13,T4,T14
10CoveredT13,T4,T14
11CoveredT13,T4,T14

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT13,T4,T14
10CoveredT13,T4,T14
11CoveredT13,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 6664 0 0
SrcPulseCheck_M 9714182 6664 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 6664 0 0
T3 240269 0 0 0
T4 593346 20 0 0
T7 719203 0 0 0
T10 0 20 0 0
T13 48181 20 0 0
T14 48200 20 0 0
T15 251000 20 0 0
T21 0 1 0 0
T22 0 1 0 0
T25 85827 0 0 0
T27 273041 0 0 0
T47 122818 20 0 0
T48 190233 0 0 0
T65 0 20 0 0
T68 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 6664 0 0
T3 2057 0 0 0
T4 24722 20 0 0
T7 15140 0 0 0
T10 0 20 0 0
T13 507 20 0 0
T14 507 20 0 0
T15 501 20 0 0
T21 0 1 0 0
T22 0 1 0 0
T25 686 0 0 0
T27 5516 0 0 0
T47 523 20 0 0
T48 761 0 0 0
T65 0 20 0 0
T68 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT13,T4,T14

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT13,T4,T14
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 7761 0 0
SrcPulseCheck_M 1299919929 7879 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7761 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 30 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T13 507 20 0 0
T14 507 20 0 0
T15 501 20 0 0
T27 0 1 0 0
T47 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7879 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 30 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T13 48181 20 0 0
T14 48200 20 0 0
T15 251000 20 0 0
T27 0 1 0 0
T47 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT13,T4,T14

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT13,T4,T14
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 7863 0 0
SrcPulseCheck_M 9714182 7863 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7863 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 30 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T13 48181 20 0 0
T14 48200 20 0 0
T15 251000 20 0 0
T27 0 1 0 0
T47 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7863 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 30 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T13 507 20 0 0
T14 507 20 0 0
T15 501 20 0 0
T27 0 1 0 0
T47 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT13,T4,T14
10CoveredT13,T4,T14
11CoveredT13,T4,T14

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT13,T4,T14
10CoveredT13,T4,T14
11CoveredT13,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 6453 0 0
SrcPulseCheck_M 1299919929 6571 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 6453 0 0
T3 2057 0 0 0
T4 24722 20 0 0
T7 15140 0 0 0
T10 0 20 0 0
T13 507 20 0 0
T14 507 20 0 0
T15 501 20 0 0
T25 686 0 0 0
T27 5516 0 0 0
T47 523 20 0 0
T48 761 0 0 0
T65 0 20 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 6571 0 0
T3 240269 0 0 0
T4 593346 20 0 0
T7 719203 0 0 0
T10 0 20 0 0
T13 48181 20 0 0
T14 48200 20 0 0
T15 251000 20 0 0
T25 85827 0 0 0
T27 273041 0 0 0
T47 122818 20 0 0
T48 190233 0 0 0
T65 0 20 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT13,T4,T14
10CoveredT13,T4,T14
11CoveredT13,T4,T14

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT13,T4,T14
10CoveredT13,T4,T14
11CoveredT13,T4,T14

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 6553 0 0
SrcPulseCheck_M 9714182 6553 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 6553 0 0
T3 240269 0 0 0
T4 593346 20 0 0
T7 719203 0 0 0
T10 0 20 0 0
T13 48181 20 0 0
T14 48200 20 0 0
T15 251000 20 0 0
T25 85827 0 0 0
T27 273041 0 0 0
T47 122818 20 0 0
T48 190233 0 0 0
T65 0 20 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 20 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 6553 0 0
T3 2057 0 0 0
T4 24722 20 0 0
T7 15140 0 0 0
T10 0 20 0 0
T13 507 20 0 0
T14 507 20 0 0
T15 501 20 0 0
T25 686 0 0 0
T27 5516 0 0 0
T47 523 20 0 0
T48 761 0 0 0
T65 0 20 0 0
T68 0 20 0 0
T69 0 20 0 0
T70 0 20 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT8,T9,T24
10CoveredT8,T9,T24
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT8,T9,T24
10CoveredT83,T50,T16
11CoveredT8,T9,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 921 0 0
SrcPulseCheck_M 1299919929 1034 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 921 0 0
T8 1043 1 0 0
T9 933 1 0 0
T10 47669 0 0 0
T21 492 0 0 0
T22 495 0 0 0
T24 0 1 0 0
T32 0 4 0 0
T33 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 1 0 0
T43 644 0 0 0
T49 752 0 0 0
T65 522 0 0 0
T66 430 0 0 0
T67 426 0 0 0
T71 0 1 0 0
T72 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1034 0 0
T8 500783 1 0 0
T9 448095 1 0 0
T10 116790 0 0 0
T21 125625 0 0 0
T22 64387 0 0 0
T24 0 1 0 0
T32 0 4 0 0
T33 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 1 0 0
T43 141802 0 0 0
T49 361013 0 0 0
T65 255969 0 0 0
T66 55893 0 0 0
T67 53311 0 0 0
T71 0 1 0 0
T72 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT8,T9,T24
10CoveredT8,T9,T24
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT8,T9,T24
10CoveredT83,T50,T16
11CoveredT8,T9,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1022 0 0
SrcPulseCheck_M 9714182 1022 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1022 0 0
T8 500783 1 0 0
T9 448095 1 0 0
T10 116790 0 0 0
T21 125625 0 0 0
T22 64387 0 0 0
T24 0 1 0 0
T32 0 4 0 0
T33 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 1 0 0
T43 141802 0 0 0
T49 361013 0 0 0
T65 255969 0 0 0
T66 55893 0 0 0
T67 53311 0 0 0
T71 0 1 0 0
T72 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1022 0 0
T8 1043 1 0 0
T9 933 1 0 0
T10 47669 0 0 0
T21 492 0 0 0
T22 495 0 0 0
T24 0 1 0 0
T32 0 4 0 0
T33 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 0 1 0 0
T43 644 0 0 0
T49 752 0 0 0
T65 522 0 0 0
T66 430 0 0 0
T67 426 0 0 0
T71 0 1 0 0
T72 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1895 0 0
SrcPulseCheck_M 1299919929 2009 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1895 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T8 0 1 0 0
T9 0 1 0 0
T10 0 18 0 0
T11 0 13 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 2009 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T8 0 1 0 0
T9 0 1 0 0
T10 0 18 0 0
T11 0 13 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1997 0 0
SrcPulseCheck_M 9714182 1997 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1997 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T8 0 1 0 0
T9 0 1 0 0
T10 0 18 0 0
T11 0 13 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1997 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T8 0 1 0 0
T9 0 1 0 0
T10 0 18 0 0
T11 0 13 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT4,T25,T26
10CoveredT4,T25,T26
11CoveredT4,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT4,T25,T26
10CoveredT4,T25,T26
11CoveredT4,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1244 0 0
SrcPulseCheck_M 1299919929 1359 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1244 0 0
T4 24722 6 0 0
T7 15140 0 0 0
T8 1043 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T20 0 5 0 0
T25 686 4 0 0
T26 618 3 0 0
T27 5516 0 0 0
T32 0 5 0 0
T36 0 5 0 0
T43 0 4 0 0
T44 0 4 0 0
T45 0 3 0 0
T46 0 1 0 0
T47 523 0 0 0
T48 761 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1359 0 0
T4 593346 6 0 0
T7 719203 0 0 0
T8 500783 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T20 0 5 0 0
T25 85827 4 0 0
T26 74233 3 0 0
T27 273041 0 0 0
T32 0 5 0 0
T36 0 5 0 0
T43 0 4 0 0
T44 0 4 0 0
T45 0 3 0 0
T46 0 1 0 0
T47 122818 0 0 0
T48 190233 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT4,T25,T26
10CoveredT4,T25,T26
11CoveredT4,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT4,T25,T26
10CoveredT4,T25,T26
11CoveredT4,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1347 0 0
SrcPulseCheck_M 9714182 1347 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1347 0 0
T4 593346 6 0 0
T7 719203 0 0 0
T8 500783 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T20 0 5 0 0
T25 85827 4 0 0
T26 74233 3 0 0
T27 273041 0 0 0
T32 0 5 0 0
T36 0 5 0 0
T43 0 4 0 0
T44 0 4 0 0
T45 0 3 0 0
T46 0 1 0 0
T47 122818 0 0 0
T48 190233 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1347 0 0
T4 24722 6 0 0
T7 15140 0 0 0
T8 1043 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T20 0 5 0 0
T25 686 4 0 0
T26 618 3 0 0
T27 5516 0 0 0
T32 0 5 0 0
T36 0 5 0 0
T43 0 4 0 0
T44 0 4 0 0
T45 0 3 0 0
T46 0 1 0 0
T47 523 0 0 0
T48 761 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT4,T25,T26
10CoveredT4,T25,T26
11CoveredT4,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT4,T25,T26
10CoveredT4,T25,T26
11CoveredT4,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1099 0 0
SrcPulseCheck_M 1299919929 1209 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1099 0 0
T4 24722 3 0 0
T7 15140 0 0 0
T8 1043 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T20 0 3 0 0
T25 686 3 0 0
T26 618 3 0 0
T27 5516 0 0 0
T32 0 3 0 0
T36 0 3 0 0
T43 0 3 0 0
T44 0 3 0 0
T45 0 3 0 0
T46 0 1 0 0
T47 523 0 0 0
T48 761 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1209 0 0
T4 593346 3 0 0
T7 719203 0 0 0
T8 500783 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T20 0 3 0 0
T25 85827 3 0 0
T26 74233 3 0 0
T27 273041 0 0 0
T32 0 3 0 0
T36 0 3 0 0
T43 0 3 0 0
T44 0 3 0 0
T45 0 3 0 0
T46 0 1 0 0
T47 122818 0 0 0
T48 190233 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT4,T25,T26
10CoveredT4,T25,T26
11CoveredT4,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT4,T25,T26
10CoveredT4,T25,T26
11CoveredT4,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1198 0 0
SrcPulseCheck_M 9714182 1198 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1198 0 0
T4 593346 3 0 0
T7 719203 0 0 0
T8 500783 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T20 0 3 0 0
T25 85827 3 0 0
T26 74233 3 0 0
T27 273041 0 0 0
T32 0 3 0 0
T36 0 3 0 0
T43 0 3 0 0
T44 0 3 0 0
T45 0 3 0 0
T46 0 1 0 0
T47 122818 0 0 0
T48 190233 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1198 0 0
T4 24722 3 0 0
T7 15140 0 0 0
T8 1043 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T20 0 3 0 0
T25 686 3 0 0
T26 618 3 0 0
T27 5516 0 0 0
T32 0 3 0 0
T36 0 3 0 0
T43 0 3 0 0
T44 0 3 0 0
T45 0 3 0 0
T46 0 1 0 0
T47 523 0 0 0
T48 761 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 7388 0 0
SrcPulseCheck_M 1299919929 7503 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7388 0 0
T7 15140 70 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 71 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 51 0 0
T39 0 74 0 0
T40 0 80 0 0
T41 0 84 0 0
T42 0 64 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7503 0 0
T7 719203 70 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 71 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 51 0 0
T39 0 74 0 0
T40 0 80 0 0
T41 0 84 0 0
T42 0 64 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 7491 0 0
SrcPulseCheck_M 9714182 7491 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7491 0 0
T7 719203 70 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 71 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 51 0 0
T39 0 74 0 0
T40 0 80 0 0
T41 0 84 0 0
T42 0 64 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7491 0 0
T7 15140 70 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 71 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 51 0 0
T39 0 74 0 0
T40 0 80 0 0
T41 0 84 0 0
T42 0 64 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 7459 0 0
SrcPulseCheck_M 1299919929 7577 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7459 0 0
T7 15140 62 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 75 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 51 0 0
T39 0 85 0 0
T40 0 62 0 0
T41 0 60 0 0
T42 0 64 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7577 0 0
T7 719203 62 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 75 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 51 0 0
T39 0 85 0 0
T40 0 62 0 0
T41 0 60 0 0
T42 0 64 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 7565 0 0
SrcPulseCheck_M 9714182 7565 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7565 0 0
T7 719203 62 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 75 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 51 0 0
T39 0 85 0 0
T40 0 62 0 0
T41 0 60 0 0
T42 0 64 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7565 0 0
T7 15140 62 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 75 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 51 0 0
T39 0 85 0 0
T40 0 62 0 0
T41 0 60 0 0
T42 0 64 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 7410 0 0
SrcPulseCheck_M 1299919929 7529 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7410 0 0
T7 15140 60 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 75 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 51 0 0
T39 0 75 0 0
T40 0 71 0 0
T41 0 66 0 0
T42 0 64 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 51 0 0
T74 0 58 0 0
T75 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7529 0 0
T7 719203 60 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 75 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 51 0 0
T39 0 75 0 0
T40 0 71 0 0
T41 0 66 0 0
T42 0 64 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 51 0 0
T74 0 58 0 0
T75 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 7518 0 0
SrcPulseCheck_M 9714182 7518 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7518 0 0
T7 719203 60 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 75 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 51 0 0
T39 0 75 0 0
T40 0 71 0 0
T41 0 66 0 0
T42 0 64 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 51 0 0
T74 0 58 0 0
T75 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7518 0 0
T7 15140 60 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 75 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 51 0 0
T39 0 75 0 0
T40 0 71 0 0
T41 0 66 0 0
T42 0 64 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 51 0 0
T74 0 58 0 0
T75 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 7440 0 0
SrcPulseCheck_M 1299919929 7558 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7440 0 0
T7 15140 64 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 79 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 51 0 0
T39 0 88 0 0
T40 0 76 0 0
T41 0 84 0 0
T42 0 51 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7558 0 0
T7 719203 64 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 79 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 51 0 0
T39 0 88 0 0
T40 0 76 0 0
T41 0 84 0 0
T42 0 51 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 7546 0 0
SrcPulseCheck_M 9714182 7546 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 7546 0 0
T7 719203 64 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 79 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 51 0 0
T39 0 88 0 0
T40 0 76 0 0
T41 0 84 0 0
T42 0 51 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 7546 0 0
T7 15140 64 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 79 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 51 0 0
T39 0 88 0 0
T40 0 76 0 0
T41 0 84 0 0
T42 0 51 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 51 0 0
T74 0 66 0 0
T75 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT83,T50,T16
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1181 0 0
SrcPulseCheck_M 1299919929 1296 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1181 0 0
T7 15140 4 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 13 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1296 0 0
T7 719203 4 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 13 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT83,T50,T16
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1283 0 0
SrcPulseCheck_M 9714182 1283 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1283 0 0
T7 719203 4 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 13 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1283 0 0
T7 15140 4 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 13 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT83,T50,T16
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1131 0 0
SrcPulseCheck_M 1299919929 1243 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1131 0 0
T7 15140 4 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 13 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1243 0 0
T7 719203 4 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 13 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT83,T50,T16
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1231 0 0
SrcPulseCheck_M 9714182 1231 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1231 0 0
T7 719203 4 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 13 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1231 0 0
T7 15140 4 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 13 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT83,T50,T16
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1147 0 0
SrcPulseCheck_M 1299919929 1262 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1147 0 0
T7 15140 4 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 13 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1262 0 0
T7 719203 4 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 13 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT83,T50,T16
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1251 0 0
SrcPulseCheck_M 9714182 1251 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1251 0 0
T7 719203 4 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 13 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1251 0 0
T7 15140 4 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 13 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT83,T50,T16
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1138 0 0
SrcPulseCheck_M 1299919929 1249 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1138 0 0
T7 15140 4 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 13 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1249 0 0
T7 719203 4 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 13 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT7,T27,T11
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT7,T27,T11
10CoveredT83,T50,T16
11CoveredT7,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1238 0 0
SrcPulseCheck_M 9714182 1238 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1238 0 0
T7 719203 4 0 0
T8 500783 0 0 0
T9 448095 0 0 0
T11 0 13 0 0
T21 125625 0 0 0
T25 85827 0 0 0
T26 74233 0 0 0
T27 273041 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 141802 0 0 0
T47 122818 0 0 0
T48 190233 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1238 0 0
T7 15140 4 0 0
T8 1043 0 0 0
T9 933 0 0 0
T11 0 13 0 0
T21 492 0 0 0
T25 686 0 0 0
T26 618 0 0 0
T27 5516 1 0 0
T39 0 12 0 0
T40 0 3 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 644 0 0 0
T47 523 0 0 0
T48 761 0 0 0
T73 0 1 0 0
T74 0 8 0 0
T75 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT7,T27,T11
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 8046 0 0
SrcPulseCheck_M 1299919929 8161 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 8046 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 70 0 0
T10 0 18 0 0
T11 0 71 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 51 0 0
T42 0 64 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 8161 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 70 0 0
T10 0 18 0 0
T11 0 71 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 51 0 0
T42 0 64 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT7,T27,T11
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 8149 0 0
SrcPulseCheck_M 9714182 8149 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 8149 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 70 0 0
T10 0 18 0 0
T11 0 71 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 51 0 0
T42 0 64 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 8149 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 70 0 0
T10 0 18 0 0
T11 0 71 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 51 0 0
T42 0 64 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT7,T27,T11
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 8068 0 0
SrcPulseCheck_M 1299919929 8186 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 8068 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 62 0 0
T10 0 18 0 0
T11 0 75 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 51 0 0
T42 0 64 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 8186 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 62 0 0
T10 0 18 0 0
T11 0 75 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 51 0 0
T42 0 64 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT7,T27,T11
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 8175 0 0
SrcPulseCheck_M 9714182 8175 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 8175 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 62 0 0
T10 0 18 0 0
T11 0 75 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 51 0 0
T42 0 64 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 8175 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 62 0 0
T10 0 18 0 0
T11 0 75 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 51 0 0
T42 0 64 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT7,T27,T11
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 8016 0 0
SrcPulseCheck_M 1299919929 8134 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 8016 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 60 0 0
T10 0 18 0 0
T11 0 75 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 51 0 0
T42 0 64 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 8134 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 60 0 0
T10 0 18 0 0
T11 0 75 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 51 0 0
T42 0 64 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT7,T27,T11
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 8122 0 0
SrcPulseCheck_M 9714182 8122 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 8122 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 60 0 0
T10 0 18 0 0
T11 0 75 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 51 0 0
T42 0 64 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 8122 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 60 0 0
T10 0 18 0 0
T11 0 75 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 51 0 0
T42 0 64 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT7,T27,T11
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 8079 0 0
SrcPulseCheck_M 1299919929 8193 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 8079 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 64 0 0
T10 0 18 0 0
T11 0 79 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 51 0 0
T42 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 8193 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 64 0 0
T10 0 18 0 0
T11 0 79 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 51 0 0
T42 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT7,T27,T11

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT7,T27,T11
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 8182 0 0
SrcPulseCheck_M 9714182 8182 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 8182 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 64 0 0
T10 0 18 0 0
T11 0 79 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 51 0 0
T42 0 51 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 8182 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 64 0 0
T10 0 18 0 0
T11 0 79 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 51 0 0
T42 0 51 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1808 0 0
SrcPulseCheck_M 1299919929 1926 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1808 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1926 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1913 0 0
SrcPulseCheck_M 9714182 1913 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1913 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1913 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1795 0 0
SrcPulseCheck_M 1299919929 1911 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1795 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1911 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1897 0 0
SrcPulseCheck_M 9714182 1897 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1897 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1897 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1763 0 0
SrcPulseCheck_M 1299919929 1877 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1763 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1877 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1865 0 0
SrcPulseCheck_M 9714182 1865 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1865 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1865 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1794 0 0
SrcPulseCheck_M 1299919929 1905 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1794 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1905 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1894 0 0
SrcPulseCheck_M 9714182 1894 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1894 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1894 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1824 0 0
SrcPulseCheck_M 1299919929 1940 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1824 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1940 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1928 0 0
SrcPulseCheck_M 9714182 1928 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1928 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1928 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1782 0 0
SrcPulseCheck_M 1299919929 1893 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1782 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1893 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1881 0 0
SrcPulseCheck_M 9714182 1881 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1881 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1881 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1786 0 0
SrcPulseCheck_M 1299919929 1899 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1786 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1899 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1888 0 0
SrcPulseCheck_M 9714182 1888 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1888 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1888 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 9714182 1757 0 0
SrcPulseCheck_M 1299919929 1865 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1757 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1865 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS2833100.00
CONT_ASSIGN4600
CONT_ASSIGN4900
ALWAYS5200
ALWAYS8633100.00
CONT_ASSIGN9411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
31 1 1
46 unreachable
49 unreachable
52 unreachable
53 unreachable
55 unreachable
86 1 1
87 1 1
89 1 1
94 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT1,T5,T2
11CoveredT83,T50,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT1,T5,T2
10CoveredT83,T50,T16
11CoveredT1,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 28 2 2 100.00
IF 86 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


LineNo. Expression -1-: 86 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1299919929 1854 0 0
SrcPulseCheck_M 9714182 1854 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1299919929 1854 0 0
T1 184523 9 0 0
T2 171814 4 0 0
T3 240269 0 0 0
T4 593346 7 0 0
T5 101929 3 0 0
T6 181604 0 0 0
T7 719203 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 48181 0 0 0
T14 48200 0 0 0
T15 251000 0 0 0
T27 0 1 0 0
T42 0 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 9714182 1854 0 0
T1 26361 9 0 0
T2 13744 4 0 0
T3 2057 0 0 0
T4 24722 7 0 0
T5 8493 3 0 0
T6 422 0 0 0
T7 15140 4 0 0
T10 0 18 0 0
T11 0 13 0 0
T12 0 12 0 0
T13 507 0 0 0
T14 507 0 0 0
T15 501 0 0 0
T27 0 1 0 0
T42 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%