dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_det_ctl_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_det_ctl_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_det_ctl_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_0_bat_disable_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_0_interrupt_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_0_ec_rst_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_0_rst_req_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_1_bat_disable_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_1_interrupt_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_1_ec_rst_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_1_rst_req_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_2_bat_disable_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_2_interrupt_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_2_ec_rst_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_2_rst_req_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_3_bat_disable_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_3_interrupt_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_3_ec_rst_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_com_out_ctl_3_rst_req_3


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_combo_intr_status_combo0_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_combo_intr_status_combo1_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_combo_intr_status_combo2_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_combo_intr_status_combo3_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_pwrb_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_key0_in_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_key1_in_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb
tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb
tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb
tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb
tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb
tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb
tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb
tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T7,T8 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T7 

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7 

 LINE       32
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T7
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	32	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT52,T53,T54
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT52,T53,T54
11CoveredT52,T53,T54 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT52,T53,T54 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT17,T19,T22
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT17,T19,T22
11CoveredT17,T19,T22 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT17,T19,T22 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT16,T20,T52
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT16,T20,T52
11CoveredT16,T20,T52 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT16,T20,T52 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT16,T17,T19
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT16,T17,T19
11CoveredT16,T17,T19 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT16,T17,T19 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT14,T21,T50
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT14,T21,T50
11CoveredT14,T21,T50 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT14,T21,T50 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT55,T47,T56
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT55,T56,T57
11CoveredT55,T47,T56 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT55,T47,T56 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT21,T23,T58
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT21,T23,T58
11CoveredT21,T23,T58 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT21,T23,T58 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%