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Module Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_key2_in_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_ac_present_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_ec_rst_l_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_flash_wp_l_h2l


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_pwrb_l2h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_key0_in_l2h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_key1_in_l2h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_key2_in_l2h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_ac_present_l2h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_ec_rst_l_l2h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_key_intr_status_flash_wp_l_l2h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb
tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT50,T58,T47
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT50,T58,T57
11CoveredT50,T58,T47 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT50,T58,T47 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT23,T50,T58
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT23,T50,T58
11CoveredT23,T50,T58 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT23,T50,T58 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT14,T50,T47
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT14,T50,T56
11CoveredT14,T50,T47 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT14,T50,T47 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT21,T23,T50
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT21,T23,T50
11CoveredT21,T23,T50 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT21,T23,T50 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT14,T21,T23
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT14,T21,T23
11CoveredT14,T21,T23 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT14,T21,T23 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT18,T21,T50
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT18,T21,T50
11CoveredT18,T21,T50 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT18,T21,T50 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT21,T23,T50
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT21,T23,T50
11CoveredT21,T23,T50 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT21,T23,T50 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT18,T21,T23
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT18,T21,T23
11CoveredT18,T21,T23 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT18,T21,T23 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT14,T18,T21
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT14,T18,T21
11CoveredT14,T18,T21 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT14,T18,T21 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT18,T21,T50
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT18,T21,T50
11CoveredT18,T21,T50 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT18,T21,T50 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT21,T23,T47
10CoveredT1,T2,T3 

 LINE       57
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT21,T23,T59
11CoveredT21,T23,T47 

 LINE       57
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT21,T23,T47 

 LINE       57
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T5,T6
1CoveredT1,T2,T3
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%