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 LINE       6677
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T276
1	1	1	Covered	T1,T2,T3

 LINE       6679
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T275,T281,T282
1	1	1	Covered	T1,T2,T3

 LINE       6681
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6683
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T275,T277,T281
1	1	1	Covered	T1,T2,T3

 LINE       6685
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T275,T278,T281
1	1	1	Covered	T1,T2,T3

 LINE       6687
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T277,T283
1	1	1	Covered	T1,T2,T3

 LINE       6689
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T9,T275
1	1	1	Covered	T1,T2,T3

 LINE       6702
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T278
1	1	1	Covered	T1,T2,T3

 LINE       6719
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6728
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T275,T278,T281
1	1	1	Covered	T1,T2,T3

 LINE       6737
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T9,T275
1	1	1	Covered	T1,T2,T3

 LINE       6752
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6754
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T284
1	1	1	Covered	T1,T2,T3

 LINE       6757
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6764
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T5,T275
1	1	1	Covered	T1,T2,T3

 LINE       6770
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T276,T277
1	1	1	Covered	T1,T2,T3

 LINE       6776
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T278
1	1	1	Covered	T1,T2,T3

 LINE       6782
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T276
1	1	1	Covered	T1,T2,T3

 LINE       6788
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6790
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T275,T277,T285
1	1	1	Covered	T1,T2,T3

 LINE       6792
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T276
1	1	1	Covered	T1,T2,T3

 LINE       6794
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T5,T275,T276
1	1	1	Covered	T1,T2,T3

 LINE       6796
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T276
1	1	1	Covered	T1,T2,T3

 LINE       6802
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6808
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6814
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6820
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T276
1	1	1	Covered	T1,T2,T3

 LINE       6822
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T284
1	1	1	Covered	T1,T2,T3

 LINE       6824
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T276,T277
1	1	1	Covered	T1,T2,T3

 LINE       6826
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T284
1	1	1	Covered	T1,T2,T3

 LINE       6828
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T276,T278
1	1	1	Covered	T1,T2,T3

 LINE       6833
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T275,T276,T278
1	1	1	Covered	T1,T2,T3

 LINE       6838
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T5,T275,T277
1	1	1	Covered	T1,T2,T3

 LINE       6843
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T275,T276,T281
1	1	1	Covered	T1,T2,T3

 LINE       6848
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T275,T276
1	1	1	Covered	T2,T3,T5

 LINE       6853
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T277,T278
1	1	1	Covered	T1,T2,T3

 LINE       7075
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3