Module Definition
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Module Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.84 92.00 68.75 82.61 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.84 92.00 68.75 82.61 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.10 100.00 68.75 95.65 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.10 100.00 68.75 95.65 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4600
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
ALWAYS851212100.00
ALWAYS1291212100.00
ALWAYS17355100.00
ALWAYS18255100.00
ALWAYS19600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 unreachable
60 1 1
61 1 1
85 1 1
88 1 1
89 1 1
91 1 1
95 1 1
96 1 1
99 1 1
100 1 1
MISSING_ELSE
107 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
129 1 1
132 1 1
133 1 1
135 1 1
139 1 1
140 1 1
143 1 1
144 1 1
MISSING_ELSE
151 1 1
152 1 1
155 1 1
156 1 1
MISSING_ELSE
173 1 1
174 1 1
175 1 1
177 1 1
178 1 1
182 1 1
183 1 1
184 1 1
186 1 1
187 1 1
196 unreachable
197 unreachable
198 unreachable
199 unreachable
==> MISSING_ELSE


Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 91 4 4 100.00
CASE 135 4 4 100.00
IF 173 2 2 100.00
IF 182 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 91 case (src_fsm_cs) -2-: 99 if (src_handshake) -3-: 111 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T14,T17,T24
EVEN 0 - Covered T14,T16,T17
ODD - 1 Covered T24,T25,T26
ODD - 0 Covered T14,T24,T25


LineNo. Expression -1-: 135 case (dst_fsm_cs) -2-: 143 if (dst_handshake) -3-: 155 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T14,T16,T17
EVEN 0 - Covered T14,T15,T16
ODD - 1 Covered T24,T25,T26
ODD - 0 Covered T14,T16,T17


LineNo. Expression -1-: 173 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


LineNo. Expression -1-: 182 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1868600804 2877 0 0
SyncReqAckHoldReq 18956701 986 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1868600804 2877 0 0
T1 87714 5 0 0
T6 420087 1 0 0
T7 159276 10 0 0
T8 151935 7 0 0
T9 147896 6 0 0
T10 29938 9 0 0
T14 7632 3 0 0
T16 1550624 71 0 0
T17 9129 3 0 0
T24 2321632 24 0 0
T25 1464808 24 0 0
T26 22216 7 0 0
T28 901332 6 0 0
T29 365000 3 0 0
T30 666815 6 0 0
T31 142405 4 0 0
T32 178641 4 0 0
T43 418904 47 0 0
T44 27266 3 0 0
T45 12214 1 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 18956701 986 0 0
T1 491368 1 0 0
T6 1485 1 0 0
T7 1033 2 0 0
T8 1646 5 0 0
T9 1414 6 0 0
T10 1046 8 0 0
T14 409 1 0 0
T24 3216 3 0 0
T25 2262 4 0 0
T27 1036 3 0 0
T28 5994 4 0 0
T29 2318 2 0 0
T30 53744 6 0 0
T31 992 3 0 0
T32 888 3 0 0
T33 779 4 0 0
T35 5323 1 0 0
T36 7391 1 0 0
T43 2472 4 0 0
T44 7440 1 0 0
T45 664 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4600
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
ALWAYS851212100.00
ALWAYS1291212100.00
ALWAYS17355100.00
ALWAYS18255100.00
ALWAYS19600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 unreachable
60 1 1
61 1 1
85 1 1
88 1 1
89 1 1
91 1 1
95 1 1
96 1 1
99 1 1
100 1 1
MISSING_ELSE
107 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
129 1 1
132 1 1
133 1 1
135 1 1
139 1 1
140 1 1
143 1 1
144 1 1
MISSING_ELSE
151 1 1
152 1 1
155 1 1
156 1 1
MISSING_ELSE
173 1 1
174 1 1
175 1 1
177 1 1
178 1 1
182 1 1
183 1 1
184 1 1
186 1 1
187 1 1
196 unreachable
197 unreachable
198 unreachable
199 unreachable
==> MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 91 4 4 100.00
CASE 135 4 4 100.00
IF 173 2 2 100.00
IF 182 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 91 case (src_fsm_cs) -2-: 99 if (src_handshake) -3-: 111 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T14,T17,T24
EVEN 0 - Covered T14,T16,T17
ODD - 1 Covered T25,T26,T43
ODD - 0 Covered T14,T24,T25


LineNo. Expression -1-: 135 case (dst_fsm_cs) -2-: 143 if (dst_handshake) -3-: 155 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T14,T16,T17
EVEN 0 - Covered T14,T15,T16
ODD - 1 Covered T25,T26,T43
ODD - 0 Covered T14,T16,T17


LineNo. Expression -1-: 173 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


LineNo. Expression -1-: 182 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 385899751 616 0 0
SyncReqAckHoldReq 3843545 124 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 385899751 616 0 0
T1 29238 2 0 0
T7 53092 4 0 0
T14 2544 1 0 0
T16 387656 16 0 0
T17 3043 1 0 0
T24 580408 2 0 0
T25 366202 2 0 0
T26 5554 2 0 0
T43 104726 6 0 0
T44 13633 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 3843545 124 0 0
T1 491368 1 0 0
T6 1485 1 0 0
T7 1033 2 0 0
T14 409 1 0 0
T24 1608 2 0 0
T25 1131 1 0 0
T43 1236 2 0 0
T44 7440 1 0 0
T45 664 1 0 0
T46 851 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4600
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
ALWAYS851212100.00
ALWAYS1291212100.00
ALWAYS17355100.00
ALWAYS18255100.00
ALWAYS19600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 unreachable
60 1 1
61 1 1
85 1 1
88 1 1
89 1 1
91 1 1
95 1 1
96 1 1
99 1 1
100 1 1
MISSING_ELSE
107 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
129 1 1
132 1 1
133 1 1
135 1 1
139 1 1
140 1 1
143 1 1
144 1 1
MISSING_ELSE
151 1 1
152 1 1
155 1 1
156 1 1
MISSING_ELSE
173 1 1
174 1 1
175 1 1
177 1 1
178 1 1
182 1 1
183 1 1
184 1 1
186 1 1
187 1 1
196 unreachable
197 unreachable
198 unreachable
199 unreachable
==> MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 91 4 4 100.00
CASE 135 4 4 100.00
IF 173 2 2 100.00
IF 182 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 91 case (src_fsm_cs) -2-: 99 if (src_handshake) -3-: 111 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T14,T17,T24
EVEN 0 - Covered T14,T16,T17
ODD - 1 Covered T24,T25,T26
ODD - 0 Covered T14,T24,T25


LineNo. Expression -1-: 135 case (dst_fsm_cs) -2-: 143 if (dst_handshake) -3-: 155 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T14,T16,T17
EVEN 0 - Covered T14,T15,T16
ODD - 1 Covered T24,T25,T26
ODD - 0 Covered T14,T16,T17


LineNo. Expression -1-: 173 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


LineNo. Expression -1-: 182 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 385899751 728 0 0
SyncReqAckHoldReq 3843545 275 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 385899751 728 0 0
T1 29238 2 0 0
T7 53092 4 0 0
T8 50645 1 0 0
T14 2544 1 0 0
T16 387656 19 0 0
T17 3043 1 0 0
T24 580408 9 0 0
T25 366202 4 0 0
T26 5554 2 0 0
T43 104726 17 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 3843545 275 0 0
T1 491368 2 0 0
T7 1033 4 0 0
T8 823 1 0 0
T9 707 1 0 0
T10 523 1 0 0
T14 409 1 0 0
T24 1608 2 0 0
T25 1131 2 0 0
T43 1236 2 0 0
T44 7440 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4600
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
ALWAYS851212100.00
ALWAYS1291212100.00
ALWAYS17355100.00
ALWAYS18255100.00
ALWAYS19600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 unreachable
60 1 1
61 1 1
85 1 1
88 1 1
89 1 1
91 1 1
95 1 1
96 1 1
99 1 1
100 1 1
MISSING_ELSE
107 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
129 1 1
132 1 1
133 1 1
135 1 1
139 1 1
140 1 1
143 1 1
144 1 1
MISSING_ELSE
151 1 1
152 1 1
155 1 1
156 1 1
MISSING_ELSE
173 1 1
174 1 1
175 1 1
177 1 1
178 1 1
182 1 1
183 1 1
184 1 1
186 1 1
187 1 1
196 unreachable
197 unreachable
198 unreachable
199 unreachable
==> MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 91 4 4 100.00
CASE 135 4 4 100.00
IF 173 2 2 100.00
IF 182 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 91 case (src_fsm_cs) -2-: 99 if (src_handshake) -3-: 111 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T14,T17,T24
EVEN 0 - Covered T14,T16,T17
ODD - 1 Covered T24,T25,T26
ODD - 0 Covered T14,T24,T25


LineNo. Expression -1-: 135 case (dst_fsm_cs) -2-: 143 if (dst_handshake) -3-: 155 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T14,T16,T17
EVEN 0 - Covered T14,T15,T16
ODD - 1 Covered T24,T25,T26
ODD - 0 Covered T14,T16,T17


LineNo. Expression -1-: 173 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


LineNo. Expression -1-: 182 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 385899751 576 0 0
SyncReqAckHoldReq 3843545 122 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 385899751 576 0 0
T14 2544 1 0 0
T16 387656 18 0 0
T17 3043 1 0 0
T24 580408 7 0 0
T25 366202 10 0 0
T26 5554 2 0 0
T29 182500 2 0 0
T31 142405 4 0 0
T32 178641 4 0 0
T43 104726 8 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 3843545 122 0 0
T14 409 1 0 0
T24 1608 2 0 0
T25 1131 2 0 0
T27 1036 3 0 0
T29 1159 1 0 0
T31 992 3 0 0
T32 888 3 0 0
T35 5323 1 0 0
T36 7391 1 0 0
T43 1236 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4600
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
ALWAYS851212100.00
ALWAYS1291212100.00
ALWAYS17355100.00
ALWAYS18255100.00
ALWAYS19600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 unreachable
60 1 1
61 1 1
85 1 1
88 1 1
89 1 1
91 1 1
95 1 1
96 1 1
99 1 1
100 1 1
MISSING_ELSE
107 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
129 1 1
132 1 1
133 1 1
135 1 1
139 1 1
140 1 1
143 1 1
144 1 1
MISSING_ELSE
151 1 1
152 1 1
155 1 1
156 1 1
MISSING_ELSE
173 1 1
174 1 1
175 1 1
177 1 1
178 1 1
182 1 1
183 1 1
184 1 1
186 1 1
187 1 1
196 unreachable
197 unreachable
198 unreachable
199 unreachable
==> MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 91 4 4 100.00
CASE 135 4 4 100.00
IF 173 2 2 100.00
IF 182 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 91 case (src_fsm_cs) -2-: 99 if (src_handshake) -3-: 111 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T24,T25,T26
EVEN 0 - Covered T16,T18,T24
ODD - 1 Covered T24,T25,T43
ODD - 0 Covered T24,T25,T26


LineNo. Expression -1-: 135 case (dst_fsm_cs) -2-: 143 if (dst_handshake) -3-: 155 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T16,T24,T25
EVEN 0 - Covered T14,T15,T16
ODD - 1 Covered T24,T25,T43
ODD - 0 Covered T16,T24,T25


LineNo. Expression -1-: 173 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


LineNo. Expression -1-: 182 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T14,T15,T16
0 Covered T14,T15,T16


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 385899751 726 0 0
SyncReqAckHoldReq 3843545 235 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 385899751 726 0 0
T8 50645 4 0 0
T9 73948 4 0 0
T10 14969 6 0 0
T16 387656 18 0 0
T24 580408 6 0 0
T25 366202 8 0 0
T26 5554 1 0 0
T28 450666 4 0 0
T30 666815 6 0 0
T43 104726 16 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 3843545 235 0 0
T8 823 3 0 0
T9 707 4 0 0
T10 523 5 0 0
T24 1608 1 0 0
T25 1131 2 0 0
T28 2997 2 0 0
T30 53744 6 0 0
T33 779 4 0 0
T34 84981 9 0 0
T43 1236 2 0 0

Line Coverage for Instance : tb.dut.u_prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN4600
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
ALWAYS851212100.00
ALWAYS1291212100.00
ALWAYS17355100.00
ALWAYS18255100.00
ALWAYS19600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 unreachable
60 1 1
61 1 1
85 1 1
88 1 1
89 1 1
91 1 1
95 1 1
96 1 1
99 1 1
100 1 1
MISSING_ELSE
107 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
129 1 1
132 1 1
133 1 1
135 1 1
139 1 1
140 1 1
143 1 1
144 1 1
MISSING_ELSE
151 1 1
152 1 1
155 1 1
156 1 1
MISSING_ELSE
173 1 1
174 1 1
175 1 1
177 1 1
178 1 1
182 1 1
183 1 1
184 1 1
186 1 1
187 1 1
196 unreachable
197 unreachable
198 unreachable
199 unreachable
==> MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 91 4 4 100.00
CASE 135 4 4 100.00
IF 173 2 2 100.00
IF 182 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 91 case (src_fsm_cs) -2-: 99 if (src_handshake) -3-: 111 if (src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T7,T8
EVEN 0 - Covered T1,T7,T8
ODD - 1 Covered T7,T8,T9
ODD - 0 Covered T1,T7,T8


LineNo. Expression -1-: 135 case (dst_fsm_cs) -2-: 143 if (dst_handshake) -3-: 155 if (dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T7,T8
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T7,T8,T9
ODD - 0 Covered T1,T7,T8


LineNo. Expression -1-: 173 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 182 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 325001800 231 0 0
SyncReqAckHoldReq 3582521 230 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 325001800 231 0 0
T1 29238 1 0 0
T6 420087 1 0 0
T7 53092 2 0 0
T8 50645 2 0 0
T9 73948 2 0 0
T10 14969 3 0 0
T28 450666 2 0 0
T29 182500 1 0 0
T44 13633 1 0 0
T45 12214 1 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 3582521 230 0 0
T1 491368 1 0 0
T6 1485 1 0 0
T7 1033 2 0 0
T8 823 2 0 0
T9 707 2 0 0
T10 523 3 0 0
T28 2997 2 0 0
T29 1159 1 0 0
T44 7440 1 0 0
T45 664 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%