dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.08 100.00 92.31 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.22 100.00 96.88 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.10 96.99 82.19 93.22 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 91.04 95.92 77.55 90.70 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.10 96.99 82.19 93.22 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 91.04 95.92 77.55 90.70 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.06 100.00 85.92 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 95.34 100.00 83.67 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_ec_rst_ctl_cdc
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
tb.dut.u_reg.u_ulp_ctl_cdc
tb.dut.u_reg.u_ulp_status_cdc
tb.dut.u_reg.u_wkup_status_cdc
tb.dut.u_reg.u_key_invert_ctl_cdc
tb.dut.u_reg.u_pin_allowed_ctl_cdc
tb.dut.u_reg.u_pin_out_ctl_cdc
tb.dut.u_reg.u_pin_out_value_cdc
tb.dut.u_reg.u_key_intr_ctl_cdc
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
tb.dut.u_reg.u_auto_block_out_ctl_cdc
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
tb.dut.u_reg.u_com_sel_ctl_0_cdc
tb.dut.u_reg.u_com_sel_ctl_1_cdc
tb.dut.u_reg.u_com_sel_ctl_2_cdc
tb.dut.u_reg.u_com_sel_ctl_3_cdc
tb.dut.u_reg.u_com_det_ctl_0_cdc
tb.dut.u_reg.u_com_det_ctl_1_cdc
tb.dut.u_reg.u_com_det_ctl_2_cdc
tb.dut.u_reg.u_com_det_ctl_3_cdc
tb.dut.u_reg.u_com_out_ctl_0_cdc
tb.dut.u_reg.u_com_out_ctl_1_cdc
tb.dut.u_reg.u_com_out_ctl_2_cdc
tb.dut.u_reg.u_com_out_ctl_3_cdc
tb.dut.u_reg.u_combo_intr_status_cdc
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 1468413 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 2045 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1468413 0 0
T1 204421 2938 0 0
T2 721280 20748 0 0
T3 193189 7555 0 0
T4 0 260 0 0
T5 100977 0 0 0
T6 202924 463 0 0
T7 203164 13096 0 0
T8 0 23692 0 0
T9 0 358 0 0
T10 0 8381 0 0
T11 0 182 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 2045 0 0
T1 204421 2 0 0
T2 721280 15 0 0
T3 193189 21 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 17 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 788923 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1042 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 788923 0 0
T1 204421 1472 0 0
T2 721280 21017 0 0
T3 193189 4320 0 0
T4 0 235 0 0
T5 100977 0 0 0
T6 202924 502 0 0
T7 203164 12840 0 0
T8 0 26726 0 0
T9 0 322 0 0
T10 0 8243 0 0
T11 0 443 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1042 0 0
T1 204421 1 0 0
T2 721280 15 0 0
T3 193189 12 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 19 0 0
T9 0 1 0 0
T10 0 10 0 0
T11 0 1 0 0
T12 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 781708 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1047 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 781708 0 0
T1 204421 2959 0 0
T2 721280 9823 0 0
T3 193189 6167 0 0
T4 0 257 0 0
T5 100977 0 0 0
T6 202924 611 0 0
T7 203164 12855 0 0
T8 0 27928 0 0
T9 0 272 0 0
T10 0 7757 0 0
T11 0 413 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1047 0 0
T1 204421 2 0 0
T2 721280 7 0 0
T3 193189 17 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 778182 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1033 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 778182 0 0
T1 204421 2925 0 0
T2 721280 6990 0 0
T3 193189 2509 0 0
T4 0 247 0 0
T5 100977 0 0 0
T6 202924 494 0 0
T7 203164 13742 0 0
T8 0 28120 0 0
T9 0 278 0 0
T10 0 8054 0 0
T11 0 428 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1033 0 0
T1 204421 2 0 0
T2 721280 5 0 0
T3 193189 7 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT6,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 778771 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1039 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 778771 0 0
T1 204421 2888 0 0
T2 721280 14006 0 0
T3 193189 3234 0 0
T4 0 223 0 0
T5 100977 0 0 0
T6 202924 473 0 0
T7 203164 12144 0 0
T8 0 28086 0 0
T9 0 279 0 0
T10 0 8380 0 0
T11 0 303 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1039 0 0
T1 204421 2 0 0
T2 721280 10 0 0
T3 193189 9 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 18 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT2,T3,T7
1-CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT15,T50,T51
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Not Covered
11CoveredT15,T50,T51

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 602163 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 620 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 602163 0 0
T1 204421 3418 0 0
T2 721280 21534 0 0
T3 193189 7628 0 0
T4 0 293 0 0
T5 100977 0 0 0
T6 202924 606 0 0
T7 203164 13643 0 0
T8 0 26545 0 0
T9 0 322 0 0
T10 0 8341 0 0
T11 0 489 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 620 0 0
T1 204421 2 0 0
T2 721280 12 0 0
T3 193189 16 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 19 0 0
T9 0 1 0 0
T10 0 10 0 0
T11 0 1 0 0
T12 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT6,T2,T3
1-CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01CoveredT14,T15,T16
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Not Covered
11CoveredT14,T15,T16

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 1036912 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1225 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1036912 0 0
T1 204421 1456 0 0
T2 721280 10317 0 0
T3 193189 2205 0 0
T4 0 235 0 0
T5 100977 0 0 0
T6 202924 561 0 0
T7 203164 13424 0 0
T8 0 28110 0 0
T9 0 280 0 0
T10 0 8562 0 0
T11 0 234 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1225 0 0
T1 204421 1 0 0
T2 721280 6 0 0
T3 193189 5 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 20 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0
T43 0 10 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 2029511 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 2687 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 2029511 0 0
T1 204421 2902 0 0
T2 721280 11190 0 0
T3 193189 4683 0 0
T4 0 284 0 0
T5 100977 0 0 0
T6 202924 406 0 0
T7 203164 13604 0 0
T8 0 27866 0 0
T9 0 325 0 0
T10 0 8409 0 0
T11 0 86 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 2687 0 0
T1 204421 2 0 0
T2 721280 8 0 0
T3 193189 13 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 4850597 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 5879 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 4850597 0 0
T1 204421 2963 0 0
T2 721280 14016 0 0
T3 193189 4374 0 0
T4 0 251 0 0
T5 100977 0 0 0
T6 202924 421 0 0
T7 203164 13632 0 0
T8 0 26645 0 0
T9 0 290 0 0
T10 0 8155 0 0
T11 0 418 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 5879 0 0
T1 204421 2 0 0
T2 721280 10 0 0
T3 193189 12 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 19 0 0
T9 0 1 0 0
T10 0 10 0 0
T11 0 1 0 0
T12 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 5725141 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 6981 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 5725141 0 0
T1 204421 2987 0 0
T2 721280 4201 0 0
T3 193189 6472 0 0
T4 0 233 0 0
T5 100977 0 0 0
T6 202924 578 0 0
T7 203164 12819 0 0
T8 0 27766 0 0
T9 0 341 0 0
T10 0 8139 0 0
T11 0 515 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 6981 0 0
T1 204421 2 0 0
T2 721280 3 0 0
T3 193189 18 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T11 0 1 0 0
T12 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 4781844 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 5759 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 4781844 0 0
T1 204421 2852 0 0
T2 721280 25206 0 0
T3 193189 4991 0 0
T4 0 256 0 0
T5 100977 0 0 0
T6 202924 460 0 0
T7 203164 13708 0 0
T8 0 26600 0 0
T9 0 299 0 0
T10 0 7479 0 0
T11 0 112 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 5759 0 0
T1 204421 2 0 0
T2 721280 18 0 0
T3 193189 14 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 19 0 0
T10 0 9 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0
T43 0 10 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 802246 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1069 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 802246 0 0
T1 204421 2946 0 0
T2 721280 23805 0 0
T3 193189 3240 0 0
T4 0 290 0 0
T5 100977 0 0 0
T6 202924 389 0 0
T7 203164 13597 0 0
T8 0 28007 0 0
T9 0 258 0 0
T10 0 8510 0 0
T11 0 178 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1069 0 0
T1 204421 2 0 0
T2 721280 17 0 0
T3 193189 9 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 1468555 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 2016 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1468555 0 0
T1 204421 2942 0 0
T2 721280 9692 0 0
T3 193189 6161 0 0
T4 0 277 0 0
T5 100977 0 0 0
T6 202924 455 0 0
T7 203164 13571 0 0
T8 0 26640 0 0
T9 0 327 0 0
T10 0 7524 0 0
T11 0 259 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 2016 0 0
T1 204421 2 0 0
T2 721280 7 0 0
T3 193189 17 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 19 0 0
T10 0 10 0 0
T11 0 1 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 1025541 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1324 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1025541 0 0
T1 204421 2922 0 0
T2 721280 19628 0 0
T3 193189 6897 0 0
T4 0 290 0 0
T5 100977 0 0 0
T6 202924 619 0 0
T7 203164 12986 0 0
T8 0 28053 0 0
T9 0 293 0 0
T10 0 8497 0 0
T11 0 34 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1324 0 0
T1 204421 2 0 0
T2 721280 14 0 0
T3 193189 19 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 842817 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1134 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 842817 0 0
T1 204421 2947 0 0
T2 721280 9804 0 0
T3 193189 5045 0 0
T4 0 255 0 0
T5 100977 0 0 0
T6 202924 558 0 0
T7 203164 13578 0 0
T8 0 25090 0 0
T9 0 254 0 0
T10 0 8430 0 0
T11 0 241 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1134 0 0
T1 204421 2 0 0
T2 721280 7 0 0
T3 193189 14 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 18 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 5695474 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 7620 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 5695474 0 0
T1 204421 2898 0 0
T2 721280 11189 0 0
T3 193189 5072 0 0
T4 0 260 0 0
T5 100977 0 0 0
T6 202924 539 0 0
T7 203164 12735 0 0
T8 0 22435 0 0
T9 0 323 0 0
T10 0 7988 0 0
T11 0 201 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 7620 0 0
T1 204421 2 0 0
T2 721280 8 0 0
T3 193189 14 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 16 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0
T43 0 10 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 5574867 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 7602 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 5574867 0 0
T1 204421 2872 0 0
T2 721280 13988 0 0
T3 193189 2816 0 0
T4 0 243 0 0
T5 100977 0 0 0
T6 202924 437 0 0
T7 203164 13600 0 0
T8 0 26444 0 0
T9 0 347 0 0
T10 0 8033 0 0
T11 0 357 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 7602 0 0
T1 204421 2 0 0
T2 721280 10 0 0
T3 193189 8 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 19 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 5602524 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 7710 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 5602524 0 0
T1 204421 2922 0 0
T2 721280 12573 0 0
T3 193189 1011 0 0
T4 0 247 0 0
T5 100977 0 0 0
T6 202924 468 0 0
T7 203164 12898 0 0
T8 0 26671 0 0
T9 0 291 0 0
T10 0 7425 0 0
T11 0 349 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 7710 0 0
T1 204421 2 0 0
T2 721280 9 0 0
T3 193189 3 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 19 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0
T43 0 10 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 5435472 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 7554 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 5435472 0 0
T1 204421 2946 0 0
T2 721280 15154 0 0
T3 193189 2879 0 0
T4 0 281 0 0
T5 100977 0 0 0
T6 202924 426 0 0
T7 203164 12812 0 0
T8 0 25026 0 0
T9 0 306 0 0
T10 0 6833 0 0
T11 0 216 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 7554 0 0
T1 204421 2 0 0
T2 721280 10 0 0
T3 193189 8 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 18 0 0
T9 0 1 0 0
T10 0 9 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 944534 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1264 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 944534 0 0
T1 204421 2866 0 0
T2 721280 11160 0 0
T3 193189 2511 0 0
T4 0 224 0 0
T5 100977 0 0 0
T6 202924 365 0 0
T7 203164 12803 0 0
T8 0 26812 0 0
T9 0 333 0 0
T10 0 7945 0 0
T11 0 247 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1264 0 0
T1 204421 2 0 0
T2 721280 8 0 0
T3 193189 7 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 19 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 957830 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1287 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 957830 0 0
T1 204421 2910 0 0
T2 721280 16818 0 0
T3 193189 7886 0 0
T4 0 298 0 0
T5 100977 0 0 0
T6 202924 392 0 0
T7 203164 13806 0 0
T8 0 28027 0 0
T9 0 316 0 0
T10 0 8488 0 0
T11 0 467 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1287 0 0
T1 204421 2 0 0
T2 721280 12 0 0
T3 193189 22 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 904293 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1235 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 904293 0 0
T1 204421 2856 0 0
T2 721280 12578 0 0
T3 193189 3214 0 0
T4 0 247 0 0
T5 100977 0 0 0
T6 202924 376 0 0
T7 203164 12816 0 0
T8 0 25267 0 0
T9 0 247 0 0
T10 0 7991 0 0
T11 0 379 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1235 0 0
T1 204421 2 0 0
T2 721280 9 0 0
T3 193189 9 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 18 0 0
T9 0 1 0 0
T10 0 10 0 0
T11 0 1 0 0
T12 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 931338 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1260 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 931338 0 0
T1 204421 2925 0 0
T2 721280 19631 0 0
T3 193189 2567 0 0
T4 0 259 0 0
T5 100977 0 0 0
T6 202924 484 0 0
T7 203164 13420 0 0
T8 0 28034 0 0
T9 0 248 0 0
T10 0 7858 0 0
T11 0 87 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1260 0 0
T1 204421 2 0 0
T2 721280 14 0 0
T3 193189 7 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 6295440 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 8349 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 6295440 0 0
T1 204421 2880 0 0
T2 721280 13999 0 0
T3 193189 4318 0 0
T4 0 270 0 0
T5 100977 0 0 0
T6 202924 520 0 0
T7 203164 13531 0 0
T8 0 27942 0 0
T9 0 266 0 0
T10 0 8126 0 0
T11 0 409 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 8349 0 0
T1 204421 2 0 0
T2 721280 10 0 0
T3 193189 12 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 20 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0
T43 0 10 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 6128034 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 8287 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 6128034 0 0
T1 204421 2955 0 0
T2 721280 19561 0 0
T3 193189 3608 0 0
T4 0 240 0 0
T5 100977 0 0 0
T6 202924 481 0 0
T7 203164 13550 0 0
T8 0 27987 0 0
T9 0 327 0 0
T10 0 7728 0 0
T11 0 137 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 8287 0 0
T1 204421 2 0 0
T2 721280 14 0 0
T3 193189 10 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0
T43 0 10 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 6121712 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 8328 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 6121712 0 0
T1 204421 2966 0 0
T2 721280 25188 0 0
T3 193189 2130 0 0
T4 0 260 0 0
T5 100977 0 0 0
T6 202924 609 0 0
T7 203164 13687 0 0
T8 0 26567 0 0
T9 0 315 0 0
T10 0 8199 0 0
T11 0 448 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 8328 0 0
T1 204421 2 0 0
T2 721280 18 0 0
T3 193189 6 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 20 0 0
T8 0 19 0 0
T9 0 1 0 0
T10 0 10 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 5939916 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 8195 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 5939916 0 0
T1 204421 2920 0 0
T2 721280 8384 0 0
T3 193189 2515 0 0
T4 0 254 0 0
T5 100977 0 0 0
T6 202924 596 0 0
T7 203164 12890 0 0
T8 0 26741 0 0
T9 0 349 0 0
T10 0 6863 0 0
T11 0 342 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 8195 0 0
T1 204421 2 0 0
T2 721280 6 0 0
T3 193189 7 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 19 0 0
T9 0 1 0 0
T10 0 9 0 0
T12 0 1 0 0
T13 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 1508248 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 2008 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1508248 0 0
T1 204421 2900 0 0
T2 721280 29405 0 0
T3 193189 6040 0 0
T4 0 264 0 0
T5 100977 0 0 0
T6 202924 414 0 0
T7 203164 12900 0 0
T8 0 26502 0 0
T9 0 293 0 0
T10 0 7613 0 0
T11 0 269 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0
T25 406 6 0 0
T26 405 5 0 0
T27 413 13 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 2008 0 0
T1 204421 2 0 0
T2 721280 21 0 0
T3 193189 17 0 0
T4 0 2 0 0
T5 100977 0 0 0
T6 202924 0 0 0
T7 203164 19 0 0
T8 0 19 0 0
T9 0 1 0 0
T10 0 10 0 0
T11 0 1 0 0
T12 0 1 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1167781941 0 0
T1 204421 204367 0 0
T2 721280 721213 0 0
T3 193189 193113 0 0
T5 100977 100878 0 0
T6 202924 199876 0 0
T7 203164 202997 0 0
T24 202158 202085 0 0
T25 50831 50774 0 0
T26 97297 97198 0 0
T27 206781 206720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T6,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T6,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T6
01Unreachable
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T2
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T6
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T6
0 1 - Covered T1,T6,T2
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1169432265 1391424 0 0
DstReqKnown_A 6383776 5634201 0 0
SrcAckBusyChk_A 1169432265 1899 0 0
SrcBusyKnown_A 1169432265 1167781941 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1169432265 1391424 0 0
T1 204421 2951 0 0
T2 721280 14003 0 0
T3 193189 3537 0 0
T4 0 214 0 0
T5 100977 0 0 0
T6 202924 447 0 0
T7 203164 12910 0 0
T8 0 26670 0 0
T9 0 304 0 0
T10 0 8101 0 0
T11 0 351 0 0
T24 202158 0 0 0
T25 50831 0 0 0
T26 97297 0 0 0
T27 206781 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6383776 5634201 0 0
T1 408 8 0 0
T2 1534 1134 0 0
T3 1545 1145 0 0
T5 404 4 0 0
T6 410 4 0 0
T7 8464 64 0 0
T24 408 8 0 0