3bda020dd| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | TOTAL | 155 | 205 | 75.61 | |
| V2 | combo_detect | sysrst_ctrl_combo_detect | 0 | 0 | -- |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 0 | 0 | -- |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 0 | 0 | -- |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_override_test | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 0 | 0 | -- |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 0 | 0 | -- |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 0 | 0 | -- |
| V2 | alert_test | sysrst_ctrl_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 0 | 50 | 0.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 190 | 240 | 79.17 | |
| V2S | tl_intg_err | sysrst_ctrl_tl_intg_err | 19 | 20 | 95.00 |
| V2S | TOTAL | 19 | 20 | 95.00 | |
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |
| Unmapped tests | sysrst_ctrl_stress_all | 0 | 50 | 0.00 | |
| TOTAL | 364 | 565 | 64.42 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 12 | 6 | 5 | 41.67 |
| V2S | 1 | 1 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.81 | 98.93 | 86.58 | 97.46 | -- | 91.30 | 91.55 | 79.06 |
UVM_WARNING [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.sysrst_ctrl_stress_all.229944269
Line 298, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.sysrst_ctrl_stress_all.714707159
Line 298, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.sysrst_ctrl_stress_all_with_rand_reset.3499516151
Line 299, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 8040060 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 8040060 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.sysrst_ctrl_stress_all_with_rand_reset.466613527
Line 299, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 8023208 ps: [BDTYP] Cannot create an object of type 'sysrst_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 8023208 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status has 50 failures:
0.sysrst_ctrl_combo_detect_ec_rst.53724182
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/out/run.log
UVM_ERROR @ 409684065 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status
UVM_INFO @ 629004065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sysrst_ctrl_combo_detect_ec_rst.1148655275
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/out/run.log
UVM_ERROR @ 409994344 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status
UVM_INFO @ 636537783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:460) [sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (* [*] vs *xX [x]) has 50 failures:
0.sysrst_ctrl_intr_test.3632609790
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/out/run.log
UVM_ERROR @ 9698878 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 10178878 ps: (cip_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 2/6
UVM_ERROR @ 12018878 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 12018878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sysrst_ctrl_intr_test.3335982345
Line 300, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/out/run.log
UVM_ERROR @ 8161526 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 8185056 ps: (cip_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 2/6
UVM_ERROR @ 8302706 ps: (cip_base_vseq.sv:460) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0xX [x])
UVM_INFO @ 8302706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.ec_rst_ctl has 1 failures:
7.sysrst_ctrl_tl_intg_err.2710733271
Line 423, in log /usr/local/google/home/chencindy/nightly_openTitan/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/out/run.log
UVM_ERROR @ 28293055075 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (3042 [0xbe2] vs 2000 [0x7d0]) Regname: sysrst_ctrl_reg_block.ec_rst_ctl
UVM_INFO @ 28293216691 ps: (cip_tl_seq_item.sv:106) uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below:
a_addr: 0xd8c70fd8
-> 0xd8c70fda a_opcode: 0x4
-> 0x4 a_mask: 0xf