e80d18267e80d18267| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 205 | 205 | 100.00 | |
| V2 | combo_detect | sysrst_ctrl_combo_detect | 50 | 50 | 100.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 50 | 50 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 32 | 50 | 64.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_override_test | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 50 | 50 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 50 | 50 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 45 | 50 | 90.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 567 | 590 | 96.10 | |
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 19 | 20 | 95.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 24 | 25 | 96.00 | |
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 29 | 50 | 58.00 |
| V3 | TOTAL | 29 | 50 | 58.00 | |
| TOTAL | 825 | 870 | 94.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 13 | 13 | 11 | 84.62 |
| V2S | 3 | 2 | 1 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.91 | 98.21 | 92.94 | 100.00 | 87.88 | 95.42 | 98.27 | 63.65 |
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:100) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at Key1Idx has 7 failures:
7.sysrst_ctrl_edge_detect.564762361
Line 342, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 1750675818 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_ERROR @ 1750675818 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
UVM_INFO @ 1750675818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.sysrst_ctrl_edge_detect.3856082330
Line 341, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 415645622 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_ERROR @ 440667256 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 440667256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
11.sysrst_ctrl_stress_all_with_rand_reset.2637535362
Line 2565, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 13670650970 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_ERROR @ 13670650970 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
UVM_INFO @ 13670650970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.sysrst_ctrl_stress_all_with_rand_reset.2969668798
Line 4280, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 54926001429 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_ERROR @ 54926001429 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_INFO @ 54926001429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:100) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at PwrbIdx has 6 failures:
1.sysrst_ctrl_edge_detect.3019099247
Line 343, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 250785757111 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 250785757111 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_INFO @ 250785757111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.sysrst_ctrl_edge_detect.949207485
Line 342, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 1150965355 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 1150965355 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_INFO @ 1150965355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
10.sysrst_ctrl_stress_all_with_rand_reset.1173932780
Line 2463, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 979745716145 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 979745716145 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_INFO @ 979745716145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.sysrst_ctrl_stress_all_with_rand_reset.452437038
Line 1136, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 12865981348 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 12890621348 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 12890621348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:108) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (* [*] vs * [*]) Compare mismatch at Key2Idx has 5 failures:
Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
2.sysrst_ctrl_stress_all_with_rand_reset.579675537
Line 3545, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 34400799546 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 34425590442 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (1024 [0x400] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 34425590442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.sysrst_ctrl_stress_all_with_rand_reset.1589472125
Line 1412, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 14720718388 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 14720718388 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_INFO @ 14720718388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_edge_detect has 2 failures.
5.sysrst_ctrl_edge_detect.800496718
Line 342, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 1666067550 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 1690595524 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (1024 [0x400] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 1690595524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.sysrst_ctrl_edge_detect.1276472882
Line 343, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 2996182252 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 2996182252 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_INFO @ 2996182252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all has 1 failures.
8.sysrst_ctrl_stress_all.2642279385
Line 341, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/out/run.log
UVM_ERROR @ 2550753751 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 2575744134 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (1024 [0x400] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 2575744134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:100) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at Key0Idx has 5 failures:
6.sysrst_ctrl_stress_all_with_rand_reset.2869131420
Line 1243, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 4991467080 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_ERROR @ 4991467080 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_INFO @ 4991467080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.sysrst_ctrl_stress_all_with_rand_reset.285210944
Line 2096, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 16865700994 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_ERROR @ 16865700994 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_INFO @ 16865700994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
22.sysrst_ctrl_stress_all.1530481802
Line 343, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/out/run.log
UVM_ERROR @ 4030715217 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_ERROR @ 4030715217 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_INFO @ 4030715217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.sysrst_ctrl_stress_all.3673917155
Line 342, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/out/run.log
UVM_ERROR @ 3230646053 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_ERROR @ 3255556053 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (2 [0x2] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 3255556053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:100) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at AcPresentIdx has 4 failures:
2.sysrst_ctrl_edge_detect.2200383448
Line 344, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 920733873 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_ERROR @ 920733873 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_INFO @ 920733873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.sysrst_ctrl_edge_detect.326985029
Line 342, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 1020756041 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_ERROR @ 1045569335 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (16 [0x10] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 1045569335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
23.sysrst_ctrl_stress_all_with_rand_reset.4035867238
Line 4054, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 22176171916 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_ERROR @ 22176171916 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at EcRstIdx
UVM_INFO @ 22176171916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:100) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at EcRstIdx has 4 failures:
Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
4.sysrst_ctrl_stress_all_with_rand_reset.3207975109
Line 1229, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 8656360419 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at EcRstIdx
UVM_ERROR @ 8656360419 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
UVM_INFO @ 8656360419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.sysrst_ctrl_stress_all_with_rand_reset.3479562505
Line 2192, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 20360829705 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at EcRstIdx
UVM_ERROR @ 20360829705 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_INFO @ 20360829705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_edge_detect has 2 failures.
40.sysrst_ctrl_edge_detect.1859587456
Line 341, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 1025857010 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at EcRstIdx
UVM_ERROR @ 1025857010 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_INFO @ 1025857010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.sysrst_ctrl_edge_detect.149719360
Line 342, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 581013846 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at EcRstIdx
UVM_ERROR @ 581013846 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_INFO @ 581013846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:100) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at Key2Idx has 4 failures:
12.sysrst_ctrl_stress_all_with_rand_reset.2492273009
Line 4699, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 61785767893 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 61785767893 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at EcRstIdx
UVM_INFO @ 61785767893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.sysrst_ctrl_stress_all_with_rand_reset.2873040571
Line 1024, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 7581252387 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 7581252387 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
UVM_INFO @ 7581252387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
19.sysrst_ctrl_edge_detect.3983488473
Line 346, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 520822045 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_ERROR @ 520822045 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_INFO @ 520822045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:108) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (* [*] vs * [*]) Compare mismatch at PwrbIdx has 4 failures:
Test sysrst_ctrl_edge_detect has 2 failures.
18.sysrst_ctrl_edge_detect.2474509579
Line 341, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 1555769209 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 1555769209 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_INFO @ 1555769209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.sysrst_ctrl_edge_detect.1813321515
Line 340, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 601388972 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 626055836 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (128 [0x80] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 626055836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all has 1 failures.
33.sysrst_ctrl_stress_all.2255124776
Line 343, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/out/run.log
UVM_ERROR @ 2515712180 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 2540572180 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (128 [0x80] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 2540572180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
34.sysrst_ctrl_stress_all_with_rand_reset.1119339788
Line 2332, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 17075750330 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 17075750330 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key0Idx
UVM_INFO @ 17075750330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:100) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at FlashWpIdx has 3 failures:
Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
9.sysrst_ctrl_stress_all_with_rand_reset.2043163779
Line 3099, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 20620975907 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
UVM_ERROR @ 20620975907 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key2Idx
UVM_INFO @ 20620975907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.sysrst_ctrl_stress_all_with_rand_reset.2056447723
Line 4449, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 107951032111 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
UVM_ERROR @ 107975657308 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (64 [0x40] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 107975657308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_edge_detect has 1 failures.
30.sysrst_ctrl_edge_detect.957170019
Line 342, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/out/run.log
UVM_ERROR @ 435762824 ps: (sysrst_ctrl_edge_detect_vseq.sv:100) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
UVM_ERROR @ 435762824 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_INFO @ 435762824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!dst_pulse_o)' has 1 failures:
2.sysrst_ctrl_tl_intg_err.3334934250
Line 449, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/out/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 22262562997 ps: (prim_pulse_sync.sv:88) [ASSERT FAILED] DstPulseCheck_A
"../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 88: tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A: started at 22262550651ps failed at 22262562997ps
Offending '(!dst_pulse_o)'
UVM_ERROR @ 22262562997 ps: (prim_pulse_sync.sv:88) [ASSERT FAILED] DstPulseCheck_A
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:108) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (* [*] vs * [*]) Compare mismatch at AcPresentIdx has 1 failures:
11.sysrst_ctrl_stress_all.2697141693
Line 355, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/out/run.log
UVM_ERROR @ 19855900721 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
UVM_ERROR @ 19880627969 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (2048 [0x800] vs 0 [0x0]) Regname: sysrst_ctrl_reg_block.key_intr_status
UVM_INFO @ 19880627969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:108) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (* [*] vs * [*]) Compare mismatch at Key1Idx has 1 failures:
27.sysrst_ctrl_stress_all_with_rand_reset.1224917118
Line 1255, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/out/run.log
UVM_ERROR @ 17216291657 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at Key1Idx
UVM_ERROR @ 17216291657 ps: (sysrst_ctrl_edge_detect_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
UVM_INFO @ 17216291657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---