SYSRST_CTRL Simulation Results

Sunday June 26 2022 08:05:35 UTC

GitHub Revision: e80d18267
Foundry Revision: e80d18267

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1856535565

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 50 50 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 20 20 100.00
sysrst_ctrl_csr_aliasing 5 5 100.00
V1 TOTAL 205 205 100.00
V2 combo_detect sysrst_ctrl_combo_detect 50 50 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 32 50 64.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_override_test 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 50 50 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 50 50 100.00
V2 stress_all sysrst_ctrl_stress_all 45 50 90.00
V2 alert_test sysrst_ctrl_alert_test 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_rw 20 20 100.00
sysrst_ctrl_csr_aliasing 5 5 100.00
sysrst_ctrl_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_rw 20 20 100.00
sysrst_ctrl_csr_aliasing 5 5 100.00
sysrst_ctrl_same_csr_outstanding 20 20 100.00
V2 TOTAL 567 590 96.10
V2S tl_intg_err sysrst_ctrl_sec_cm 5 5 100.00
sysrst_ctrl_tl_intg_err 19 20 95.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S TOTAL 24 25 96.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 29 50 58.00
V3 TOTAL 29 50 58.00
TOTAL 825 870 94.83

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 13 13 11 84.62
V2S 3 2 1 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.91 98.21 92.94 100.00 87.88 95.42 98.27 63.65

Failure Buckets

Past Results