ADAPTER_SRAM Lint Results
Thursday May 16 2024 19:02:11 UTC
Branch: os_regression
Tool: ASCENTLINT
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Messages for Build Mode 'default'
Lint Infos
I VAR_INDEX_WRITE: tlul_adapter_sram.sv:390 Variable index expression 'wmask_intg[woffset]' encountered New
I VAR_INDEX_WRITE: tlul_adapter_sram.sv:391 Variable index expression 'wdata_intg[woffset]' encountered New
I VAR_INDEX_WRITE: tlul_adapter_sram.sv:455 Variable range select expression 'gen_rmask.rmask[8 * i +: 8]' encountered New
I CASE_INC: tlul_err.sv:62 Case statement tag not specified for value 'h3 New
I ONE_BIT_VEC: prim_fifo_sync.sv:32 Declaration range '[DepthW - 1:0]' ([0:0]) of 'depth_o' has a length of one, instance 'tlul_adapter_sram.u_reqfifo' of module 'prim_fifo_sync' (Depth=1,DepthW=1 ('prim_util_pkg::vbits(Depth + 1)')) New
I ONE_BIT_VEC: prim_fifo_sync.sv:63 Declaration range '[gen_normal_fifo.PtrW - 1:0]' ([0:0]) of 'gen_normal_fifo.fifo_wptr' has a length of one, instance 'tlul_adapter_sram.u_reqfifo' of module 'prim_fifo_sync' (Depth=1,gen_normal_fifo.PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_fifo_sync.sv:105 Declaration range '[Depth - 1:0]' ([0:0]) of 'gen_normal_fifo.storage' has a length of one, instance 'tlul_adapter_sram.u_reqfifo' of module 'prim_fifo_sync' (Depth=1,Width=17) New
I ONE_BIT_VEC: prim_fifo_sync_cnt.sv:25 Declaration range '[PtrW - 1:0]' ([0:0]) of 'wptr_o' has a length of one, instance 'tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_fifo_sync_cnt.sv:26 Declaration range '[PtrW - 1:0]' ([0:0]) of 'rptr_o' has a length of one, instance 'tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,PtrW=1 ('prim_util_pkg::vbits(Depth)')) New
I ONE_BIT_VEC: prim_fifo_sync_cnt.sv:31 Declaration range '[DepthW - 1:0]' ([0:0]) of 'depth_o' has a length of one, instance 'tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt' of module 'prim_fifo_sync_cnt' (Depth=1,DepthW=1 ('prim_util_pkg::vbits(Depth + 1)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:180 Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'sram_req_t' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:180 Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'sramreqfifo_wdata' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:180 Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'woffset' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:349 Declaration range '[WoffsetWidth - 1:0]' ([0:0]) of 'woffset' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataBitWidth=2 ('prim_util_pkg::vbits(SramByte)'),SramByte=4 ('SramDw / 8'),SramDw=32,WoffsetWidth=1 ('(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:362 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_combined' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=32 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=0,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:363 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_combined' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=32 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=0,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:366 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_int' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:367 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_int' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:370 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wmask_intg' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataIntgWidth=7,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:371 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'wdata_intg' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataIntgWidth=7,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_adapter_sram.sv:431 Declaration range '[WidthMult - 1:0]' ([0:0]) of 'rdata_reshaped' has a length of one, instance 'tlul_adapter_sram' of module 'tlul_adapter_sram' (DataIntgWidth=7,DataWidth=32 ('EnableDataIntgPt ? top_pkg::TL_DW + DataIntgWidth : top_pkg::TL_DW'),EnableDataIntgPt=0,SramDw=32,WidthMult=1 ('SramDw / top_pkg::TL_DW')) New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_int' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_out' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_sram_i' has a length of one New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:51 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:52 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_util_pkg.sv:85 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_sram_byte.sv:108 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_err.sv:69 Bit length not specified for constant "'h1" New
I EXPLICIT_BITLEN: tlul_err.sv:77 Bit length not specified for constant "'h2" New
I INSIDE_OP_CONTEXT: tlul_adapter_sram.sv:343 'inside' operator is not within an always block or subprogram New
I MIN_NAME_LEN: tlul_adapter_sram.sv:378 Name 'i' is shorter than minimum length 2 New
I MIN_NAME_LEN: tlul_adapter_sram.sv:454 Name 'i' is shorter than minimum length 2 New
I MIN_NAME_LEN: tlul_sram_byte.sv:191 Name 'i' is shorter than minimum length 2 New
I CONST_OUTPUT: prim_fifo_sync.sv:98 Output 'err_o' is driven by constant zero by port 'gen_normal_fifo.u_fifo_cnt.err_o' in module 'prim_fifo_sync' (Width=32'h11,Pass=1'h0,Depth=32'h1) New
I CONST_OUTPUT: prim_fifo_sync_cnt.sv:136 Output 'err_o' is driven by constant zero in module 'prim_fifo_sync_cnt' (Depth=32'h1) New
I CONST_OUTPUT: tlul_adapter_sram.sv:163 Output 'rmw_in_progress_o' is driven by constant zero by port 'u_sram_byte.rmw_in_progress_o' New
I CONST_OUTPUT: tlul_sram_byte.sv:326 Output 'rmw_in_progress_o' is driven by constant zero New
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