UART Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	34.690s	5.784ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.590s	12.453us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	13.652us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.410s	227.314us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	29.391us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.360s	29.472us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	13.652us	20	20	100.00
		uart_csr_aliasing	0.770s	29.391us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.680m	237.475ms	50	50	100.00
V2	parity	uart_smoke	34.690s	5.784ms	50	50	100.00
		uart_tx_rx	4.680m	237.475ms	50	50	100.00
V2	parity_error	uart_intr	40.367m	2.249s	48	50	96.00
		uart_rx_parity_err	6.013m	236.010ms	50	50	100.00
V2	watermark	uart_tx_rx	4.680m	237.475ms	50	50	100.00
		uart_intr	40.367m	2.249s	48	50	96.00
V2	fifo_full	uart_fifo_full	14.973m	124.611ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.612m	246.769ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.935m	161.524ms	300	300	100.00
V2	rx_frame_err	uart_intr	40.367m	2.249s	48	50	96.00
V2	rx_break_err	uart_intr	40.367m	2.249s	48	50	96.00
V2	rx_timeout	uart_intr	40.367m	2.249s	48	50	96.00
V2	perf	uart_perf	34.026m	38.483ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.470s	8.215ms	50	50	100.00
V2	line_loopback	uart_loopback	27.470s	8.215ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.450m	145.075ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.666m	64.272ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	43.160s	12.773ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	36.970s	4.293ms	44	50	88.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.208m	170.626ms	50	50	100.00
V2	stress_all	uart_stress_all	1.332h	2.751s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	32.731m	130.053ms	99	100	99.00
V2	alert_test	uart_alert_test	0.630s	12.594us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	15.705us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.290s	87.639us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.290s	87.639us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.590s	12.453us	5	5	100.00
		uart_csr_rw	0.630s	13.652us	20	20	100.00
		uart_csr_aliasing	0.770s	29.391us	5	5	100.00
		uart_same_csr_outstanding	0.760s	105.116us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.590s	12.453us	5	5	100.00
		uart_csr_rw	0.630s	13.652us	20	20	100.00
		uart_csr_aliasing	0.770s	29.391us	5	5	100.00
		uart_same_csr_outstanding	0.760s	105.116us	20	20	100.00
V2		TOTAL			1181	1190	99.24
V2S	tl_intg_err	uart_sec_cm	0.870s	115.708us	5	5	100.00
		uart_tl_intg_err	1.410s	96.498us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	96.498us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1311	1320	99.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	16	84.21
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.80	98.45	100.00	--	99.76	100.00	97.51

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 6 failures:

Test uart_rx_oversample has 6 failures.

19.uart_rx_oversample.3582055140
Line 221, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 1536574578 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (56489 [0xdca9] vs 48467 [0xbd53]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 1961504282 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/18
  UVM_ERROR @ 1980474578 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (14367 [0x381f] vs 29758 [0x743e]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 1989174578 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (16954 [0x423a] vs 38004 [0x9474]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 1997710399 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 8/18

20.uart_rx_oversample.1568634394
Line 218, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 763159904 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (49433 [0xc119] vs 33331 [0x8233]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 771693682 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/14
  UVM_ERROR @ 771874242 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (33019 [0x80fb] vs 503 [0x1f7]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 1175590190 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/14
  UVM_INFO @ 1598807015 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/14

... and 4 more failures.

UVM_ERROR (uart_scoreboard.sv:418) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

15.uart_stress_all_with_rand_reset.670879506
Line 538, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 37274453024 ps: (uart_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_ERROR @ 37274453024 ps: (uart_scoreboard.sv:420) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
  UVM_INFO @ 37276684612 ps: (cip_base_vseq.sv:711) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 37276868284 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_intr has 1 failures.
  - 30.uart_intr.1758346393
    Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 39.uart_intr.1825166158
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_intr/latest/run.log
```
  Job ID: smart:86c5c8dc-40fa-4583-9122-24c234d1747a
```