UART Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	26.130s	5.851ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.590s	16.425us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	20.105us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.290s	675.978us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	46.693us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.610s	33.532us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	20.105us	20	20	100.00
		uart_csr_aliasing	0.770s	46.693us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.761m	47.228ms	50	50	100.00
V2	parity	uart_smoke	26.130s	5.851ms	50	50	100.00
		uart_tx_rx	3.761m	47.228ms	50	50	100.00
V2	parity_error	uart_intr	44.846m	1.761s	49	50	98.00
		uart_rx_parity_err	13.787m	84.876ms	50	50	100.00
V2	watermark	uart_tx_rx	3.761m	47.228ms	50	50	100.00
		uart_intr	44.846m	1.761s	49	50	98.00
V2	fifo_full	uart_fifo_full	6.895m	368.472ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.935m	306.854ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.376m	74.942ms	300	300	100.00
V2	rx_frame_err	uart_intr	44.846m	1.761s	49	50	98.00
V2	rx_break_err	uart_intr	44.846m	1.761s	49	50	98.00
V2	rx_timeout	uart_intr	44.846m	1.761s	49	50	98.00
V2	perf	uart_perf	33.411m	37.288ms	50	50	100.00
V2	sys_loopback	uart_loopback	18.830s	10.687ms	50	50	100.00
V2	line_loopback	uart_loopback	18.830s	10.687ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	8.053m	181.012ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	53.540s	37.788ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	36.180s	6.668ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	29.800s	3.211ms	45	50	90.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.649m	160.317ms	50	50	100.00
V2	stress_all	uart_stress_all	51.923m	360.705ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	30.541m	302.714ms	99	100	99.00
V2	alert_test	uart_alert_test	0.600s	14.626us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	105.767us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.520s	454.087us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.520s	454.087us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.590s	16.425us	5	5	100.00
		uart_csr_rw	0.650s	20.105us	20	20	100.00
		uart_csr_aliasing	0.770s	46.693us	5	5	100.00
		uart_same_csr_outstanding	0.820s	32.447us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.590s	16.425us	5	5	100.00
		uart_csr_rw	0.650s	20.105us	20	20	100.00
		uart_csr_aliasing	0.770s	46.693us	5	5	100.00
		uart_same_csr_outstanding	0.820s	32.447us	20	20	100.00
V2		TOTAL			1183	1190	99.41
V2S	tl_intg_err	uart_sec_cm	0.930s	1.117ms	5	5	100.00
		uart_tl_intg_err	1.380s	304.912us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.380s	304.912us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1313	1320	99.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	16	84.21
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.80	98.45	100.00	--	99.76	100.00	97.70

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 5 failures:

Test uart_rx_oversample has 5 failures.

6.uart_rx_oversample.2895145978
Line 218, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 283827032 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (51800 [0xca58] vs 38064 [0x94b0]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 496423392 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/20
  UVM_INFO @ 532412853 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/20
  UVM_INFO @ 569312853 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/20
  UVM_INFO @ 984756736 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/20

11.uart_rx_oversample.4175170743
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_rx_oversample/latest/run.log

  UVM_ERROR @  31675796 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (31505 [0x7b11] vs 31538 [0x7b32]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @  40342480 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (63889 [0xf991] vs 60067 [0xeaa3]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  48628265 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/2
  UVM_ERROR @  49009164 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (32374 [0x7e76] vs 31860 [0x7c74]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 359939062 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/2

... and 3 more failures.

Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test uart_intr has 1 failures.
  - 18.uart_intr.2970692228
    Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_intr/latest/run.log
```
  Job ID: smart:5fc53a26-f494-4dff-9011-841329bc75b1
```

UVM_ERROR (uart_scoreboard.sv:420) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

61.uart_stress_all_with_rand_reset.3484881203
Line 621, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48529565983 ps: (uart_scoreboard.sv:420) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
  UVM_INFO @ 48575285983 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 143/743
  UVM_INFO @ 48649165983 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 144/743
  UVM_INFO @ 48765225983 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 145/743
  UVM_INFO @ 48940825983 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 146/743