UART Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	31.580s	6.205ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.910s	1.075ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	18.909us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.370s	171.351us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	17.011us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.040s	27.813us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	18.909us	20	20	100.00
		uart_csr_aliasing	0.770s	17.011us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	8.779m	131.212ms	50	50	100.00
V2	parity	uart_smoke	31.580s	6.205ms	50	50	100.00
		uart_tx_rx	8.779m	131.212ms	50	50	100.00
V2	parity_error	uart_intr	54.075m	2.345s	49	50	98.00
		uart_rx_parity_err	8.164m	279.942ms	50	50	100.00
V2	watermark	uart_tx_rx	8.779m	131.212ms	50	50	100.00
		uart_intr	54.075m	2.345s	49	50	98.00
V2	fifo_full	uart_fifo_full	6.566m	364.866ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.749m	261.490ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	13.486m	188.352ms	300	300	100.00
V2	rx_frame_err	uart_intr	54.075m	2.345s	49	50	98.00
V2	rx_break_err	uart_intr	54.075m	2.345s	49	50	98.00
V2	rx_timeout	uart_intr	54.075m	2.345s	49	50	98.00
V2	perf	uart_perf	23.467m	25.109ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.590s	9.280ms	50	50	100.00
V2	line_loopback	uart_loopback	27.590s	9.280ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	2.856m	144.530ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.987m	77.878ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	37.150s	6.431ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	43.340s	4.133ms	43	50	86.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.915m	159.079ms	50	50	100.00
V2	stress_all	uart_stress_all	35.273m	458.791ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	38.594m	97.008ms	99	100	99.00
V2	alert_test	uart_alert_test	0.590s	54.695us	50	50	100.00
V2	intr_test	uart_intr_test	0.600s	18.386us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.360s	559.618us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.360s	559.618us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.910s	1.075ms	5	5	100.00
		uart_csr_rw	0.640s	18.909us	20	20	100.00
		uart_csr_aliasing	0.770s	17.011us	5	5	100.00
		uart_same_csr_outstanding	0.800s	64.184us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.910s	1.075ms	5	5	100.00
		uart_csr_rw	0.640s	18.909us	20	20	100.00
		uart_csr_aliasing	0.770s	17.011us	5	5	100.00
		uart_same_csr_outstanding	0.800s	64.184us	20	20	100.00
V2		TOTAL			1181	1190	99.24
V2S	tl_intg_err	uart_sec_cm	0.840s	33.586us	5	5	100.00
		uart_tl_intg_err	1.430s	901.521us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.430s	901.521us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1311	1320	99.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	16	84.21
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.80	98.45	100.00	--	99.76	100.00	97.55

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 7 failures:

Test uart_rx_oversample has 7 failures.

13.uart_rx_oversample.51230463
Line 216, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_rx_oversample/latest/run.log

  UVM_ERROR @  33416339 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28513 [0x6f61] vs 57026 [0xdec2]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @  42082971 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28311 [0x6e97] vs 56622 [0xdd2e]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  50535530 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/4
  UVM_ERROR @  50749603 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (32454 [0x7ec6] vs 64908 [0xfd8c]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 460678929 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/4

28.uart_rx_oversample.33432506
Line 226, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 2951537920 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (4743 [0x1287] vs 9486 [0x250e]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 2970345053 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 12/14
  UVM_ERROR @ 2970479248 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (41986 [0xa402] vs 42050 [0xa442]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 3389321544 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 13/14
  UVM_ERROR @ 3408306280 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (49647 [0xc1ef] vs 50126 [0xc3ce]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 5 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_intr has 1 failures.
  - 4.uart_intr.850893427
    Line 261, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_scoreboard.sv:418) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

29.uart_stress_all_with_rand_reset.2502635728
Line 624, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 24314575916 ps: (uart_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: TxWatermark
  UVM_INFO @ 24320725916 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 104/999
  UVM_ERROR @ 24337625916 ps: (uart_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: TxWatermark
  UVM_INFO @ 24380575916 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 105/999
  UVM_INFO @ 24430935916 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 106/999