UART Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	48.340s	6.213ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.340s	1.039ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	19.228us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.510s	855.753us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	16.869us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.450s	107.008us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	19.228us	20	20	100.00
		uart_csr_aliasing	0.760s	16.869us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.611m	77.401ms	50	50	100.00
V2	parity	uart_smoke	48.340s	6.213ms	50	50	100.00
		uart_tx_rx	3.611m	77.401ms	50	50	100.00
V2	parity_error	uart_intr	48.529m	1.922s	49	50	98.00
		uart_rx_parity_err	6.578m	275.290ms	50	50	100.00
V2	watermark	uart_tx_rx	3.611m	77.401ms	50	50	100.00
		uart_intr	48.529m	1.922s	49	50	98.00
V2	fifo_full	uart_fifo_full	9.156m	238.064ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	10.073m	200.249ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.020m	127.368ms	300	300	100.00
V2	rx_frame_err	uart_intr	48.529m	1.922s	49	50	98.00
V2	rx_break_err	uart_intr	48.529m	1.922s	49	50	98.00
V2	rx_timeout	uart_intr	48.529m	1.922s	49	50	98.00
V2	perf	uart_perf	34.806m	45.483ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.110s	10.931ms	50	50	100.00
V2	line_loopback	uart_loopback	21.110s	10.931ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.036m	70.183ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.040m	44.688ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	43.230s	6.461ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	41.200s	5.089ms	47	50	94.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.168m	156.398ms	50	50	100.00
V2	stress_all	uart_stress_all	58.510m	1.904s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	1.101h	143.547ms	99	100	99.00
V2	alert_test	uart_alert_test	0.620s	95.540us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	43.853us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.650s	159.477us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.650s	159.477us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.340s	1.039ms	5	5	100.00
		uart_csr_rw	0.650s	19.228us	20	20	100.00
		uart_csr_aliasing	0.760s	16.869us	5	5	100.00
		uart_same_csr_outstanding	0.800s	113.042us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.340s	1.039ms	5	5	100.00
		uart_csr_rw	0.650s	19.228us	20	20	100.00
		uart_csr_aliasing	0.760s	16.869us	5	5	100.00
		uart_same_csr_outstanding	0.800s	113.042us	20	20	100.00
V2		TOTAL			1185	1190	99.58
V2S	tl_intg_err	uart_sec_cm	0.840s	169.906us	5	5	100.00
		uart_tl_intg_err	1.380s	71.255us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.380s	71.255us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	16	84.21
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.80	98.45	100.00	--	99.76	100.00	97.53

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 3 failures:

Test uart_rx_oversample has 3 failures.

10.uart_rx_oversample.3184960913
Line 216, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 453739307 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (48269 [0xbc8d] vs 31003 [0x791b]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 462177938 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/6
  UVM_ERROR @ 462405939 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (45533 [0xb1dd] vs 25530 [0x63ba]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 885835211 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/6
  UVM_ERROR @ 904570837 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (26538 [0x67aa] vs 53076 [0xcf54]) Regname: uart_reg_block.val.rx reset value: 0x0

39.uart_rx_oversample.1868897421
Line 220, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 1509140039 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (13334 [0x3416] vs 9269 [0x2435]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 1517806723 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (2065 [0x811] vs 2338 [0x922]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 1526092508 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/11
  UVM_ERROR @ 1526473407 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (33264 [0x81f0] vs 33762 [0x83e2]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 1545806779 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (25969 [0x6571] vs 25937 [0x6551]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_intr has 1 failures.
  - 9.uart_intr.3269737480
    Line 221, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_intr/latest/run.log
```
  UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

18.uart_stress_all_with_rand_reset.2702343912
Line 419, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 194254029699 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 194254029699 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: c1
  UVM_ERROR @ 194357429699 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 194357429699 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: c1
  UVM_ERROR @ 194459829699 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])