UART Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 26.440s 11.594ms 50 50 100.00
V1 csr_hw_reset uart_csr_hw_reset 0.590s 32.340us 5 5 100.00
V1 csr_rw uart_csr_rw 0.700s 18.484us 20 20 100.00
V1 csr_bit_bash uart_csr_bit_bash 2.380s 177.976us 5 5 100.00
V1 csr_aliasing uart_csr_aliasing 0.760s 109.064us 5 5 100.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 1.230s 106.798us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0.700s 18.484us 20 20 100.00
uart_csr_aliasing 0.760s 109.064us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 base_random_seq uart_tx_rx 6.120m 107.811ms 50 50 100.00
V2 parity uart_smoke 26.440s 11.594ms 50 50 100.00
uart_tx_rx 6.120m 107.811ms 50 50 100.00
V2 parity_error uart_intr 43.992m 1.505s 47 50 94.00
uart_rx_parity_err 6.736m 322.053ms 50 50 100.00
V2 watermark uart_tx_rx 6.120m 107.811ms 50 50 100.00
uart_intr 43.992m 1.505s 47 50 94.00
V2 fifo_full uart_fifo_full 12.543m 370.795ms 50 50 100.00
V2 fifo_overflow uart_fifo_overflow 5.064m 170.940ms 50 50 100.00
V2 fifo_reset uart_fifo_reset 6.434m 44.545ms 300 300 100.00
V2 rx_frame_err uart_intr 43.992m 1.505s 47 50 94.00
V2 rx_break_err uart_intr 43.992m 1.505s 47 50 94.00
V2 rx_timeout uart_intr 43.992m 1.505s 47 50 94.00
V2 perf uart_perf 19.334m 23.740ms 50 50 100.00
V2 sys_loopback uart_loopback 16.520s 8.193ms 50 50 100.00
V2 line_loopback uart_loopback 16.520s 8.193ms 50 50 100.00
V2 rx_noise_filter uart_noise_filter 11.171m 154.626ms 50 50 100.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 1.330m 48.641ms 50 50 100.00
V2 tx_overide uart_tx_ovrd 27.340s 12.057ms 50 50 100.00
V2 rx_oversample uart_rx_oversample 36.150s 3.616ms 46 50 92.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 17.692m 116.268ms 50 50 100.00
V2 stress_all uart_stress_all 1.022h 1.557s 50 50 100.00
V2 stress_all_with_reset uart_stress_all_with_rand_reset 53.249m 215.941ms 99 100 99.00
V2 alert_test uart_alert_test 0.590s 12.834us 50 50 100.00
V2 intr_test uart_intr_test 0.630s 16.604us 50 50 100.00
V2 tl_d_oob_addr_access uart_tl_errors 2.490s 263.197us 20 20 100.00
V2 tl_d_illegal_access uart_tl_errors 2.490s 263.197us 20 20 100.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0.590s 32.340us 5 5 100.00
uart_csr_rw 0.700s 18.484us 20 20 100.00
uart_csr_aliasing 0.760s 109.064us 5 5 100.00
uart_same_csr_outstanding 0.750s 377.189us 20 20 100.00
V2 tl_d_partial_access uart_csr_hw_reset 0.590s 32.340us 5 5 100.00
uart_csr_rw 0.700s 18.484us 20 20 100.00
uart_csr_aliasing 0.760s 109.064us 5 5 100.00
uart_same_csr_outstanding 0.750s 377.189us 20 20 100.00
V2 TOTAL 1182 1190 99.33
V2S tl_intg_err uart_sec_cm 0.880s 141.138us 5 5 100.00
uart_tl_intg_err 2.170s 3.706ms 20 20 100.00
V2S sec_cm_bus_integrity uart_tl_intg_err 2.170s 3.706ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 1312 1320 99.39

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 19 19 16 84.21
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.26 99.80 98.45 100.00 -- 99.76 100.00 97.53

Failure Buckets

Past Results