877a77116
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | uart_smoke | 26.440s | 11.594ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | uart_csr_hw_reset | 0.590s | 32.340us | 5 | 5 | 100.00 |
V1 | csr_rw | uart_csr_rw | 0.700s | 18.484us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | uart_csr_bit_bash | 2.380s | 177.976us | 5 | 5 | 100.00 |
V1 | csr_aliasing | uart_csr_aliasing | 0.760s | 109.064us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 1.230s | 106.798us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.700s | 18.484us | 20 | 20 | 100.00 |
uart_csr_aliasing | 0.760s | 109.064us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | base_random_seq | uart_tx_rx | 6.120m | 107.811ms | 50 | 50 | 100.00 |
V2 | parity | uart_smoke | 26.440s | 11.594ms | 50 | 50 | 100.00 |
uart_tx_rx | 6.120m | 107.811ms | 50 | 50 | 100.00 | ||
V2 | parity_error | uart_intr | 43.992m | 1.505s | 47 | 50 | 94.00 |
uart_rx_parity_err | 6.736m | 322.053ms | 50 | 50 | 100.00 | ||
V2 | watermark | uart_tx_rx | 6.120m | 107.811ms | 50 | 50 | 100.00 |
uart_intr | 43.992m | 1.505s | 47 | 50 | 94.00 | ||
V2 | fifo_full | uart_fifo_full | 12.543m | 370.795ms | 50 | 50 | 100.00 |
V2 | fifo_overflow | uart_fifo_overflow | 5.064m | 170.940ms | 50 | 50 | 100.00 |
V2 | fifo_reset | uart_fifo_reset | 6.434m | 44.545ms | 300 | 300 | 100.00 |
V2 | rx_frame_err | uart_intr | 43.992m | 1.505s | 47 | 50 | 94.00 |
V2 | rx_break_err | uart_intr | 43.992m | 1.505s | 47 | 50 | 94.00 |
V2 | rx_timeout | uart_intr | 43.992m | 1.505s | 47 | 50 | 94.00 |
V2 | perf | uart_perf | 19.334m | 23.740ms | 50 | 50 | 100.00 |
V2 | sys_loopback | uart_loopback | 16.520s | 8.193ms | 50 | 50 | 100.00 |
V2 | line_loopback | uart_loopback | 16.520s | 8.193ms | 50 | 50 | 100.00 |
V2 | rx_noise_filter | uart_noise_filter | 11.171m | 154.626ms | 50 | 50 | 100.00 |
V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 1.330m | 48.641ms | 50 | 50 | 100.00 |
V2 | tx_overide | uart_tx_ovrd | 27.340s | 12.057ms | 50 | 50 | 100.00 |
V2 | rx_oversample | uart_rx_oversample | 36.150s | 3.616ms | 46 | 50 | 92.00 |
V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 17.692m | 116.268ms | 50 | 50 | 100.00 |
V2 | stress_all | uart_stress_all | 1.022h | 1.557s | 50 | 50 | 100.00 |
V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | 53.249m | 215.941ms | 99 | 100 | 99.00 |
V2 | alert_test | uart_alert_test | 0.590s | 12.834us | 50 | 50 | 100.00 |
V2 | intr_test | uart_intr_test | 0.630s | 16.604us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | uart_tl_errors | 2.490s | 263.197us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | uart_tl_errors | 2.490s | 263.197us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.590s | 32.340us | 5 | 5 | 100.00 |
uart_csr_rw | 0.700s | 18.484us | 20 | 20 | 100.00 | ||
uart_csr_aliasing | 0.760s | 109.064us | 5 | 5 | 100.00 | ||
uart_same_csr_outstanding | 0.750s | 377.189us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | uart_csr_hw_reset | 0.590s | 32.340us | 5 | 5 | 100.00 |
uart_csr_rw | 0.700s | 18.484us | 20 | 20 | 100.00 | ||
uart_csr_aliasing | 0.760s | 109.064us | 5 | 5 | 100.00 | ||
uart_same_csr_outstanding | 0.750s | 377.189us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1182 | 1190 | 99.33 | |||
V2S | tl_intg_err | uart_sec_cm | 0.880s | 141.138us | 5 | 5 | 100.00 |
uart_tl_intg_err | 2.170s | 3.706ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | uart_tl_intg_err | 2.170s | 3.706ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 1312 | 1320 | 99.39 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 19 | 19 | 16 | 84.21 |
V2S | 2 | 2 | 2 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.26 | 99.80 | 98.45 | 100.00 | -- | 99.76 | 100.00 | 97.53 |
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: *
has 4 failures:
5.uart_rx_oversample.2833822140
Line 230, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_rx_oversample/latest/run.log
UVM_ERROR @ 2234027776 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (26892 [0x690c] vs 21772 [0x550c]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 2260451307 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 16/16
UVM_INFO @ 2380392826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.uart_rx_oversample.2259749489
Line 219, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_rx_oversample/latest/run.log
UVM_ERROR @ 578208856 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (45537 [0xb1e1] vs 41441 [0xa1e1]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 990639530 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/14
UVM_INFO @ 1186492046 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/14
UVM_INFO @ 1205276102 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/14
UVM_INFO @ 1232365937 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 8/14
... and 2 more failures.
Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 1 failures:
38.uart_intr.2968490147
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_intr/latest/run.log
Job ID: smart:dcae769e-3338-40dd-b3f2-e6e69f22412f
UVM_ERROR (uart_scoreboard.sv:418) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty
has 1 failures:
44.uart_intr.2548916196
Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/44.uart_intr/latest/run.log
UVM_ERROR @ 172963674993 ps: (uart_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
UVM_ERROR @ 172963674993 ps: (uart_scoreboard.sv:420) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxEmpty
UVM_INFO @ 172967549993 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing RxParityErr
UVM_INFO @ 173014674993 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
UVM_ERROR (uart_scoreboard.sv:420) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark
has 1 failures:
44.uart_stress_all_with_rand_reset.2055993884
Line 217, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1891747 ps: (uart_scoreboard.sv:420) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: TxWatermark
UVM_INFO @ 7265503 ps: (cip_base_vseq.sv:711) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Reset is issued for run 1/10
UVM_INFO @ 7265503 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/7
UVM_INFO @ 7265503 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/7
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
47.uart_intr.3896382456
Line 259, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_intr/latest/run.log
UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---