Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	128543	1			T3	1		T4	1		T5	5
all_values[1]	128543	1			T3	1		T4	1		T5	5
all_values[2]	128543	1			T3	1		T4	1		T5	5
all_values[3]	128543	1			T3	1		T4	1		T5	5
all_values[4]	128543	1			T3	1		T4	1		T5	5
all_values[5]	128543	1			T3	1		T4	1		T5	5
all_values[6]	128543	1			T3	1		T4	1		T5	5
all_values[7]	128543	1			T3	1		T4	1		T5	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

531053

1

T3

8

T4

8

T5

21

auto[1]

497291

1

T5

19

T6

21

T37

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1010541

1

T3

8

T4

8

T5

29

auto[1]

17803

1

T5

11

T6

21

T37

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	57030	1			T3	1		T4	1		T5	1
all_values[0]	auto[0]	auto[1]	2790	1			T5	1		T52	4		T411	2
all_values[0]	auto[1]	auto[0]	66299	1			T5	3		T6	4		T37	6
all_values[0]	auto[1]	auto[1]	2424	1			T37	1		T38	2		T52	1
all_values[1]	auto[0]	auto[0]	62252	1			T3	1		T4	1		T5	2
all_values[1]	auto[0]	auto[1]	2545	1			T37	3		T52	2		T411	3
all_values[1]	auto[1]	auto[0]	61658	1			T5	3		T6	1		T37	2
all_values[1]	auto[1]	auto[1]	2088	1			T6	3		T411	4		T72	1
all_values[2]	auto[0]	auto[0]	63316	1			T3	1		T4	1		T5	4
all_values[2]	auto[0]	auto[1]	2772	1			T37	2		T38	1		T52	2
all_values[2]	auto[1]	auto[0]	60143	1			T5	1		T6	2		T37	3
all_values[2]	auto[1]	auto[1]	2312	1			T6	2		T37	1		T52	2
all_values[3]	auto[0]	auto[0]	67366	1			T3	1		T4	1		T5	2
all_values[3]	auto[0]	auto[1]	265	1			T6	3		T37	2		T411	1
all_values[3]	auto[1]	auto[0]	60697	1			T5	3		T6	1		T37	3
all_values[3]	auto[1]	auto[1]	215	1			T37	2		T52	4		T411	2
all_values[4]	auto[0]	auto[0]	69468	1			T3	1		T4	1		T5	1
all_values[4]	auto[0]	auto[1]	404	1			T5	2		T6	4		T37	1
all_values[4]	auto[1]	auto[0]	58221	1			T37	3		T52	1		T411	2
all_values[4]	auto[1]	auto[1]	450	1			T5	2		T37	2		T52	1
all_values[5]	auto[0]	auto[0]	65581	1			T3	1		T4	1		T5	1
all_values[5]	auto[0]	auto[1]	202	1			T5	3		T6	2		T52	3
all_values[5]	auto[1]	auto[0]	62564	1			T6	1		T37	2		T38	1
all_values[5]	auto[1]	auto[1]	196	1			T5	1		T6	2		T52	2
all_values[6]	auto[0]	auto[0]	69654	1			T3	1		T4	1		T6	3
all_values[6]	auto[0]	auto[1]	181	1			T6	2		T37	1		T52	2
all_values[6]	auto[1]	auto[0]	58504	1			T5	4		T37	1		T38	2
all_values[6]	auto[1]	auto[1]	204	1			T5	1		T37	2		T411	1
all_values[7]	auto[0]	auto[0]	66851	1			T3	1		T4	1		T5	4
all_values[7]	auto[0]	auto[1]	376	1			T37	1		T38	1		T52	1
all_values[7]	auto[1]	auto[0]	60937	1			T6	2		T37	1		T38	2
all_values[7]	auto[1]	auto[1]	379	1			T5	1		T6	3		T38	2