Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2550

1

T1

11

T2

11

T3

1

auto[UartRx]

2550

1

T1

11

T2

11

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4508	1			T1	22		T2	22		T3	2
values[1]	38	1			T30	1		T228	1		T334	1
values[2]	40	1			T23	1		T228	2		T454	1
values[3]	56	1			T23	1		T28	1		T30	3
values[4]	58	1			T13	1		T154	1		T419	1
values[5]	69	1			T13	1		T28	1		T154	1
values[6]	69	1			T26	2		T28	3		T30	1
values[7]	75	1			T13	1		T26	3		T23	1
values[8]	43	1			T13	2		T26	1		T28	1
values[9]	55	1			T26	1		T30	1		T154	3
values[10]	52	1			T23	1		T30	1		T154	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2344	1			T1	11		T2	11		T3	1
auto[UartTx]	values[1]	12	1			T30	1		T334	1		T406	1
auto[UartTx]	values[2]	16	1			T228	2		T454	1		T334	1
auto[UartTx]	values[3]	13	1			T30	1		T419	1		T455	1
auto[UartTx]	values[4]	19	1			T13	1		T334	1		T456	1
auto[UartTx]	values[5]	20	1			T134	1		T70	2		T457	1
auto[UartTx]	values[6]	23	1			T420	1		T77	1		T227	1
auto[UartTx]	values[7]	34	1			T23	1		T134	1		T228	1
auto[UartTx]	values[8]	22	1			T13	1		T26	1		T28	1
auto[UartTx]	values[9]	21	1			T26	1		T154	1		T328	1
auto[UartTx]	values[10]	16	1			T328	1		T443	1		T69	1
auto[UartRx]	values[0]	2164	1			T1	11		T2	11		T3	1
auto[UartRx]	values[1]	26	1			T228	1		T456	1		T79	2
auto[UartRx]	values[2]	24	1			T23	1		T334	1		T458	1
auto[UartRx]	values[3]	43	1			T23	1		T28	1		T30	2
auto[UartRx]	values[4]	39	1			T154	1		T419	1		T254	2
auto[UartRx]	values[5]	49	1			T13	1		T28	1		T154	1
auto[UartRx]	values[6]	46	1			T26	2		T28	3		T30	1
auto[UartRx]	values[7]	41	1			T13	1		T26	3		T328	1
auto[UartRx]	values[8]	21	1			T13	1		T154	1		T228	2
auto[UartRx]	values[9]	34	1			T30	1		T154	2		T419	1
auto[UartRx]	values[10]	36	1			T23	1		T30	1		T154	1