Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1970	1			T12	7		T13	7		T18	2
auto[BaudRate115200]	2183	1			T12	8		T13	8		T17	1
auto[BaudRate230400]	2043	1			T13	9		T18	1		T19	1
auto[BaudRate128Kbps]	1947	1			T13	11		T17	3		T18	1
auto[BaudRate256Kbps]	2162	1			T11	2		T13	12		T17	1
auto[BaudRate1Mbps]	1809	1			T11	2		T17	1		T18	1
auto[BaudRate1p5Mbps]	1324	1			T11	2		T18	1		T20	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1514	1			T11	6		T16	17		T15	1
freqs[25]	1307	1			T14	9		T119	42		T322	5
freqs[48]	467	1			T426	2		T425	2		T429	2
freqs[50]	845	1			T120	8		T111	5		T167	8
freqs[100]	1405	1			T26	6		T344	6		T165	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	216	1			T16	1		T331	1		T29	5
auto[BaudRate9600]	freqs[25]	191	1			T119	5		T27	1		T143	1
auto[BaudRate9600]	freqs[48]	66	1			T144	1		T459	1		T419	1
auto[BaudRate9600]	freqs[50]	109	1			T111	1		T167	1		T354	1
auto[BaudRate9600]	freqs[100]	176	1			T26	2		T181	2		T421	1
auto[BaudRate115200]	freqs[24]	277	1			T16	4		T29	3		T416	2
auto[BaudRate115200]	freqs[25]	225	1			T119	5		T27	1		T143	1
auto[BaudRate115200]	freqs[48]	65	1			T426	1		T425	1		T144	1
auto[BaudRate115200]	freqs[50]	127	1			T120	3		T111	1		T372	1
auto[BaudRate115200]	freqs[100]	193	1			T344	1		T165	2		T181	1
auto[BaudRate230400]	freqs[24]	220	1			T16	3		T331	1		T29	1
auto[BaudRate230400]	freqs[25]	208	1			T119	6		T27	1		T143	3
auto[BaudRate230400]	freqs[48]	61	1			T419	1		T286	2		T460	1
auto[BaudRate230400]	freqs[50]	132	1			T120	2		T111	1		T167	2
auto[BaudRate230400]	freqs[100]	214	1			T26	1		T344	2		T165	2
auto[BaudRate128Kbps]	freqs[24]	225	1			T16	2		T15	1		T331	2
auto[BaudRate128Kbps]	freqs[25]	179	1			T119	11		T143	2		T417	3
auto[BaudRate128Kbps]	freqs[48]	63	1			T144	1		T419	2		T461	1
auto[BaudRate128Kbps]	freqs[50]	110	1			T167	2		T372	1		T462	3
auto[BaudRate128Kbps]	freqs[100]	214	1			T26	1		T421	4		T168	2
auto[BaudRate256Kbps]	freqs[24]	215	1			T11	2		T16	4		T442	1
auto[BaudRate256Kbps]	freqs[25]	193	1			T14	5		T119	4		T322	1
auto[BaudRate256Kbps]	freqs[48]	80	1			T425	1		T144	3		T419	2
auto[BaudRate256Kbps]	freqs[50]	125	1			T120	1		T372	1		T354	2
auto[BaudRate256Kbps]	freqs[100]	203	1			T26	1		T344	2		T165	1
auto[BaudRate1Mbps]	freqs[24]	232	1			T11	2		T16	2		T331	2
auto[BaudRate1Mbps]	freqs[25]	207	1			T14	3		T119	7		T322	1
auto[BaudRate1Mbps]	freqs[48]	58	1			T144	1		T463	2		T464	2
auto[BaudRate1Mbps]	freqs[50]	116	1			T120	1		T111	2		T167	2
auto[BaudRate1Mbps]	freqs[100]	208	1			T26	1		T344	1		T165	2
auto[BaudRate1p5Mbps]	freqs[25]	104	1			T14	1		T119	4		T322	3
auto[BaudRate1p5Mbps]	freqs[48]	74	1			T426	1		T429	2		T144	1
auto[BaudRate1p5Mbps]	freqs[50]	126	1			T120	1		T167	1		T372	2
auto[BaudRate1p5Mbps]	freqs[100]	197	1			T165	2		T181	1		T421	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded