Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1885 1 T6 3 T37 3 T52 2
all_levels[1] 521 1 T18 1 T19 1 T40 2
all_levels[2] 358 1 T19 2 T16 5 T331 2
all_levels[3] 424 1 T20 2 T16 1 T331 1
all_levels[4] 361 1 T211 2 T239 4 T333 1
all_levels[5] 437 1 T20 1 T26 1 T42 2
all_levels[6] 437 1 T17 3 T18 2 T211 3
all_levels[7] 199 1 T239 1 T119 2 T28 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%