Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	128543	1			T3	1		T4	1		T5	5
all_pins[1]	128543	1			T3	1		T4	1		T5	5
all_pins[2]	128543	1			T3	1		T4	1		T5	5
all_pins[3]	128543	1			T3	1		T4	1		T5	5
all_pins[4]	128543	1			T3	1		T4	1		T5	5
all_pins[5]	128543	1			T3	1		T4	1		T5	5
all_pins[6]	128543	1			T3	1		T4	1		T5	5
all_pins[7]	128543	1			T3	1		T4	1		T5	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1019339	1			T3	8		T4	8		T5	35
values[0x1]	9005	1			T5	5		T6	10		T37	8
transitions[0x0=>0x1]	8083	1			T5	1		T6	8		T37	6
transitions[0x1=>0x0]	8101	1			T5	2		T6	8		T37	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	126066	1			T3	1		T4	1		T5	5
all_pins[0]	values[0x1]	2477	1			T37	1		T38	2		T52	1
all_pins[0]	transitions[0x0=>0x1]	2206	1			T37	1		T38	2		T52	1
all_pins[0]	transitions[0x1=>0x0]	1814	1			T6	3		T411	4		T74	2
all_pins[1]	values[0x0]	126458	1			T3	1		T4	1		T5	5
all_pins[1]	values[0x1]	2085	1			T6	3		T411	4		T72	1
all_pins[1]	transitions[0x0=>0x1]	1791	1			T6	1		T411	4		T74	3
all_pins[1]	transitions[0x1=>0x0]	2078	1			T37	1		T52	2		T72	1
all_pins[2]	values[0x0]	126171	1			T3	1		T4	1		T5	5
all_pins[2]	values[0x1]	2372	1			T6	2		T37	1		T52	2
all_pins[2]	transitions[0x0=>0x1]	2315	1			T6	2		T37	1		T72	1
all_pins[2]	transitions[0x1=>0x0]	158	1			T37	2		T52	2		T411	2
all_pins[3]	values[0x0]	128328	1			T3	1		T4	1		T5	5
all_pins[3]	values[0x1]	215	1			T37	2		T52	4		T411	2
all_pins[3]	transitions[0x0=>0x1]	165	1			T52	3		T411	1		T72	1
all_pins[3]	transitions[0x1=>0x0]	400	1			T5	2		T411	2		T72	2
all_pins[4]	values[0x0]	128093	1			T3	1		T4	1		T5	3
all_pins[4]	values[0x1]	450	1			T5	2		T37	2		T52	1
all_pins[4]	transitions[0x0=>0x1]	368	1			T5	1		T37	2		T52	1
all_pins[4]	transitions[0x1=>0x0]	153	1			T6	2		T52	2		T72	1
all_pins[5]	values[0x0]	128308	1			T3	1		T4	1		T5	4
all_pins[5]	values[0x1]	235	1			T5	1		T6	2		T52	2
all_pins[5]	transitions[0x0=>0x1]	187	1			T6	2		T52	2		T411	1
all_pins[5]	transitions[0x1=>0x0]	744	1			T37	2		T411	1		T72	1
all_pins[6]	values[0x0]	127751	1			T3	1		T4	1		T5	4
all_pins[6]	values[0x1]	792	1			T5	1		T37	2		T411	1
all_pins[6]	transitions[0x0=>0x1]	740	1			T37	2		T411	1		T72	1
all_pins[6]	transitions[0x1=>0x0]	327	1			T6	3		T38	2		T411	3
all_pins[7]	values[0x0]	128164	1			T3	1		T4	1		T5	4
all_pins[7]	values[0x1]	379	1			T5	1		T6	3		T38	2
all_pins[7]	transitions[0x0=>0x1]	311	1			T6	3		T38	1		T411	2
all_pins[7]	transitions[0x1=>0x0]	2427	1			T37	1		T38	1		T52	1