Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	812	1			T5	4		T6	4		T37	7
all_values[1]	812	1			T5	4		T6	4		T37	7
all_values[2]	812	1			T5	4		T6	4		T37	7
all_values[3]	812	1			T5	4		T6	4		T37	7
all_values[4]	812	1			T5	4		T6	4		T37	7
all_values[5]	812	1			T5	4		T6	4		T37	7
all_values[6]	812	1			T5	4		T6	4		T37	7
all_values[7]	812	1			T5	4		T6	4		T37	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3445

1

T5

17

T6

16

T37

31

auto[1]

3051

1

T5

15

T6

16

T37

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2458

1

T5

15

T6

11

T37

23

auto[1]

4038

1

T5

17

T6

21

T37

33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3780

1

T5

21

T6

19

T37

32

auto[1]

2716

1

T5

11

T6

13

T37

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	155	1			T6	1		T37	1		T411	1
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T5	1		T52	1		T411	1
all_values[0]	auto[0]	auto[1]	auto[0]	156	1			T5	2		T6	3		T37	3
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T37	1		T38	1		T52	1
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T5	1		T52	2		T411	1
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T37	2		T38	2		T52	1
all_values[1]	auto[0]	auto[0]	auto[0]	178	1			T5	2		T6	1		T38	1
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T37	1		T52	1		T411	3
all_values[1]	auto[0]	auto[1]	auto[0]	120	1			T5	1		T37	2		T38	2
all_values[1]	auto[0]	auto[1]	auto[1]	99	1			T6	1		T411	2		T72	1
all_values[1]	auto[1]	auto[0]	auto[1]	173	1			T37	3		T52	2		T411	1
all_values[1]	auto[1]	auto[1]	auto[1]	164	1			T5	1		T6	2		T37	1
all_values[2]	auto[0]	auto[0]	auto[0]	161	1			T5	3		T6	1		T37	1
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T37	1		T411	2		T72	1
all_values[2]	auto[0]	auto[1]	auto[0]	138	1			T6	1		T37	1		T38	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T6	1		T37	1		T63	1
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T37	2		T38	2		T411	4
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T5	1		T6	1		T37	1
all_values[3]	auto[0]	auto[0]	auto[0]	172	1			T5	1		T38	1		T411	1
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T6	1		T37	1		T72	1
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T5	2		T6	1		T38	2
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T37	1		T52	2		T411	1
all_values[3]	auto[1]	auto[0]	auto[1]	185	1			T5	1		T6	2		T37	1
all_values[3]	auto[1]	auto[1]	auto[1]	145	1			T37	4		T38	1		T52	3
all_values[4]	auto[0]	auto[0]	auto[0]	181	1			T37	3		T38	2		T52	4
all_values[4]	auto[0]	auto[0]	auto[1]	68	1			T5	1		T6	2		T412	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T37	1		T52	2		T411	1
all_values[4]	auto[0]	auto[1]	auto[1]	92	1			T37	1		T411	2		T72	1
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T5	1		T6	2		T37	1
all_values[4]	auto[1]	auto[1]	auto[1]	145	1			T5	2		T37	1		T411	2
all_values[5]	auto[0]	auto[0]	auto[0]	157	1			T37	4		T38	2		T52	1
all_values[5]	auto[0]	auto[0]	auto[1]	80	1			T5	2		T52	1		T72	2
all_values[5]	auto[0]	auto[1]	auto[0]	138	1			T37	1		T38	1		T411	2
all_values[5]	auto[0]	auto[1]	auto[1]	80	1			T6	1		T52	1		T411	1
all_values[5]	auto[1]	auto[0]	auto[1]	195	1			T5	1		T6	2		T38	1
all_values[5]	auto[1]	auto[1]	auto[1]	162	1			T5	1		T6	1		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	163	1			T6	2		T37	2		T38	1
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T6	1		T37	2		T52	1
all_values[6]	auto[0]	auto[1]	auto[0]	153	1			T5	2		T38	3		T52	3
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T5	1		T72	1		T63	1
all_values[6]	auto[1]	auto[0]	auto[1]	184	1			T6	1		T37	1		T52	1
all_values[6]	auto[1]	auto[1]	auto[1]	147	1			T5	1		T37	2		T411	2
all_values[7]	auto[0]	auto[0]	auto[0]	186	1			T5	2		T37	4		T52	5
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T5	1		T38	1		T411	2
all_values[7]	auto[0]	auto[1]	auto[0]	120	1			T6	1		T38	1		T411	1
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T6	1		T38	1		T411	1
all_values[7]	auto[1]	auto[0]	auto[1]	190	1			T37	3		T38	1		T52	1
all_values[7]	auto[1]	auto[1]	auto[1]	148	1			T5	1		T6	2		T52	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal