Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.30 99.79 98.45 100.00 99.76 100.00 97.77


Total test records in report: 1296
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T1256 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1718330436 Dec 24 01:39:52 PM PST 23 Dec 24 01:39:54 PM PST 23 151152134 ps
T1257 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1017387986 Dec 24 01:40:16 PM PST 23 Dec 24 01:40:26 PM PST 23 40255568 ps
T96 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3205971669 Dec 24 01:40:36 PM PST 23 Dec 24 01:40:39 PM PST 23 246761009 ps
T82 /workspace/coverage/cover_reg_top/12.uart_csr_rw.684116441 Dec 24 01:40:13 PM PST 23 Dec 24 01:40:21 PM PST 23 23875214 ps
T1258 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.96488785 Dec 24 01:40:34 PM PST 23 Dec 24 01:40:37 PM PST 23 35782235 ps
T97 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1365640319 Dec 24 01:39:55 PM PST 23 Dec 24 01:39:57 PM PST 23 136105069 ps
T1259 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2163758890 Dec 24 01:40:09 PM PST 23 Dec 24 01:40:16 PM PST 23 25216097 ps
T410 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1400968983 Dec 24 01:40:08 PM PST 23 Dec 24 01:40:11 PM PST 23 858680337 ps
T1260 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2627157376 Dec 24 01:40:09 PM PST 23 Dec 24 01:40:16 PM PST 23 96394924 ps
T1261 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2769736004 Dec 24 01:40:33 PM PST 23 Dec 24 01:40:35 PM PST 23 135156223 ps
T1262 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2466919974 Dec 24 01:40:39 PM PST 23 Dec 24 01:40:43 PM PST 23 30319494 ps
T1263 /workspace/coverage/cover_reg_top/40.uart_intr_test.2868157108 Dec 24 01:41:30 PM PST 23 Dec 24 01:41:32 PM PST 23 11180709 ps
T1264 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3844611316 Dec 24 01:40:13 PM PST 23 Dec 24 01:40:21 PM PST 23 53181339 ps
T1265 /workspace/coverage/cover_reg_top/31.uart_intr_test.2566561177 Dec 24 01:41:09 PM PST 23 Dec 24 01:41:10 PM PST 23 45936319 ps
T1266 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2225615600 Dec 24 01:40:16 PM PST 23 Dec 24 01:40:27 PM PST 23 109512418 ps
T1267 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1732527484 Dec 24 01:40:33 PM PST 23 Dec 24 01:40:36 PM PST 23 361727827 ps
T1268 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1994531171 Dec 24 01:40:12 PM PST 23 Dec 24 01:40:21 PM PST 23 23441088 ps
T1269 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2274800679 Dec 24 01:40:34 PM PST 23 Dec 24 01:40:37 PM PST 23 14347809 ps
T1270 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.918489698 Dec 24 01:40:22 PM PST 23 Dec 24 01:40:29 PM PST 23 174264873 ps
T1271 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.873259642 Dec 24 01:40:10 PM PST 23 Dec 24 01:40:21 PM PST 23 76210877 ps
T1272 /workspace/coverage/cover_reg_top/14.uart_intr_test.672599546 Dec 24 01:40:39 PM PST 23 Dec 24 01:40:43 PM PST 23 13465952 ps
T1273 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1345702497 Dec 24 01:40:39 PM PST 23 Dec 24 01:40:45 PM PST 23 49527909 ps
T1274 /workspace/coverage/cover_reg_top/17.uart_intr_test.934947933 Dec 24 01:40:23 PM PST 23 Dec 24 01:40:29 PM PST 23 36759104 ps
T1275 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3688362925 Dec 24 01:40:22 PM PST 23 Dec 24 01:40:29 PM PST 23 30353768 ps
T1276 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1895370496 Dec 24 01:40:14 PM PST 23 Dec 24 01:40:21 PM PST 23 44005789 ps
T1277 /workspace/coverage/cover_reg_top/6.uart_intr_test.2032106223 Dec 24 01:40:12 PM PST 23 Dec 24 01:40:21 PM PST 23 44881878 ps
T1278 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2085172880 Dec 24 01:40:12 PM PST 23 Dec 24 01:40:21 PM PST 23 72122031 ps
T1279 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.731983191 Dec 24 01:39:54 PM PST 23 Dec 24 01:39:56 PM PST 23 27227995 ps
T1280 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.783054628 Dec 24 01:40:36 PM PST 23 Dec 24 01:40:39 PM PST 23 72157427 ps
T1281 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3084361292 Dec 24 01:40:41 PM PST 23 Dec 24 01:40:47 PM PST 23 102713711 ps
T83 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1650723458 Dec 24 01:40:35 PM PST 23 Dec 24 01:40:38 PM PST 23 20542344 ps
T1282 /workspace/coverage/cover_reg_top/13.uart_intr_test.1027239249 Dec 24 01:40:20 PM PST 23 Dec 24 01:40:28 PM PST 23 18722632 ps
T1283 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3852867149 Dec 24 01:40:36 PM PST 23 Dec 24 01:40:40 PM PST 23 210312762 ps
T1284 /workspace/coverage/cover_reg_top/21.uart_intr_test.3605600655 Dec 24 01:40:38 PM PST 23 Dec 24 01:40:41 PM PST 23 56138034 ps
T1285 /workspace/coverage/cover_reg_top/48.uart_intr_test.1930219927 Dec 24 01:42:16 PM PST 23 Dec 24 01:42:18 PM PST 23 44137023 ps
T1286 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2798399553 Dec 24 01:40:11 PM PST 23 Dec 24 01:40:21 PM PST 23 14464875 ps
T1287 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.893313202 Dec 24 01:40:42 PM PST 23 Dec 24 01:40:47 PM PST 23 21249441 ps
T1288 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1443225290 Dec 24 01:40:38 PM PST 23 Dec 24 01:40:43 PM PST 23 342512926 ps
T1289 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.673194565 Dec 24 01:40:37 PM PST 23 Dec 24 01:40:40 PM PST 23 845180450 ps
T1290 /workspace/coverage/cover_reg_top/27.uart_intr_test.1937486310 Dec 24 01:40:38 PM PST 23 Dec 24 01:40:41 PM PST 23 14924049 ps
T1291 /workspace/coverage/cover_reg_top/16.uart_intr_test.3897245595 Dec 24 01:40:16 PM PST 23 Dec 24 01:40:26 PM PST 23 12163810 ps
T1292 /workspace/coverage/cover_reg_top/38.uart_intr_test.2347684929 Dec 24 01:41:15 PM PST 23 Dec 24 01:41:17 PM PST 23 29529861 ps
T1293 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2103455867 Dec 24 01:40:14 PM PST 23 Dec 24 01:40:21 PM PST 23 33750583 ps
T1294 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1409142608 Dec 24 01:40:32 PM PST 23 Dec 24 01:40:34 PM PST 23 185214462 ps
T1295 /workspace/coverage/cover_reg_top/36.uart_intr_test.1752997824 Dec 24 01:41:29 PM PST 23 Dec 24 01:41:31 PM PST 23 11759401 ps
T1296 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.531264430 Dec 24 01:40:38 PM PST 23 Dec 24 01:40:42 PM PST 23 35064020 ps

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2749175954
Short name T10
Test name
Test status
Simulation time 638960112 ps
CPU time 1.29 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 199240 kb
Host smart-fee8770f-d38e-4492-8518-a32617f44bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749175954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2749175954
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3828238269
Short name T13
Test name
Test status
Simulation time 404250965199 ps
CPU time 841.94 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:50:28 PM PST 23
Peak memory 211724 kb
Host smart-38719df9-3fac-466e-8e0a-6908e34dea90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828238269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3828238269
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2915624503
Short name T28
Test name
Test status
Simulation time 242049270076 ps
CPU time 649.78 seconds
Started Dec 24 01:38:03 PM PST 23
Finished Dec 24 01:48:54 PM PST 23
Peak memory 225112 kb
Host smart-bc3ee2c8-57ee-47ad-92c0-c91861f68072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915624503 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2915624503
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4245251822
Short name T411
Test name
Test status
Simulation time 116910816 ps
CPU time 0.62 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 194380 kb
Host smart-e42cda30-3cca-4bc0-bf3f-0d0e55e6dace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245251822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4245251822
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2097483966
Short name T106
Test name
Test status
Simulation time 139595460484 ps
CPU time 309.62 seconds
Started Dec 24 01:32:30 PM PST 23
Finished Dec 24 01:37:41 PM PST 23
Peak memory 200244 kb
Host smart-a154e061-b7c1-4330-bcfa-6452d9408e28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097483966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2097483966
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1250144490
Short name T30
Test name
Test status
Simulation time 95705860401 ps
CPU time 706.11 seconds
Started Dec 24 01:35:41 PM PST 23
Finished Dec 24 01:47:28 PM PST 23
Peak memory 225108 kb
Host smart-0d9e83dc-c3de-4845-8b0e-10a1239a9818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250144490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1250144490
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.3524276502
Short name T242
Test name
Test status
Simulation time 272437521528 ps
CPU time 463.48 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:43:49 PM PST 23
Peak memory 200212 kb
Host smart-9404ba9e-7939-434e-98ce-a9a22445f8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524276502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3524276502
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3666128577
Short name T44
Test name
Test status
Simulation time 40773303 ps
CPU time 1.9 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:22 PM PST 23
Peak memory 200192 kb
Host smart-8fa346c4-cb5d-4114-b833-adc05a9fc68f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666128577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3666128577
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_stress_all.1087195650
Short name T119
Test name
Test status
Simulation time 377893543767 ps
CPU time 319.86 seconds
Started Dec 24 01:31:55 PM PST 23
Finished Dec 24 01:37:16 PM PST 23
Peak memory 200072 kb
Host smart-a71f3f40-0e40-4088-8a0e-c549fe99dcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087195650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1087195650
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all.2581500592
Short name T225
Test name
Test status
Simulation time 715728470824 ps
CPU time 1531 seconds
Started Dec 24 01:34:32 PM PST 23
Finished Dec 24 02:00:04 PM PST 23
Peak memory 208828 kb
Host smart-4c0163c0-f8a1-4183-89e3-b13d88ef8e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581500592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2581500592
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2651792241
Short name T19
Test name
Test status
Simulation time 87977380598 ps
CPU time 34.55 seconds
Started Dec 24 01:39:55 PM PST 23
Finished Dec 24 01:40:31 PM PST 23
Peak memory 200168 kb
Host smart-0f85c6ef-1c74-4076-98ff-3236b339b53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651792241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2651792241
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.55039332
Short name T228
Test name
Test status
Simulation time 362742054766 ps
CPU time 1342.16 seconds
Started Dec 24 01:38:04 PM PST 23
Finished Dec 24 02:00:27 PM PST 23
Peak memory 224832 kb
Host smart-940bdb54-2341-4438-99cc-a8d5c90d025f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55039332 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.55039332
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1874348965
Short name T54
Test name
Test status
Simulation time 15183655 ps
CPU time 0.59 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:40 PM PST 23
Peak memory 195548 kb
Host smart-6e729fb1-4d2b-4229-9e81-c1965c524cfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874348965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1874348965
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.144004360
Short name T418
Test name
Test status
Simulation time 333674077898 ps
CPU time 85.73 seconds
Started Dec 24 01:33:25 PM PST 23
Finished Dec 24 01:34:52 PM PST 23
Peak memory 199632 kb
Host smart-e5b44de3-867f-4380-8109-c0b56b9ed995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144004360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.144004360
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3214252391
Short name T48
Test name
Test status
Simulation time 164003180 ps
CPU time 1.98 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:40:27 PM PST 23
Peak memory 200212 kb
Host smart-59e215ed-c9d8-4060-a4d7-29a4a69fba6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214252391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3214252391
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/default/23.uart_stress_all.438777773
Short name T325
Test name
Test status
Simulation time 995677680290 ps
CPU time 400.16 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:41:36 PM PST 23
Peak memory 200220 kb
Host smart-ae58d86e-5804-481d-b8fa-4f86af5cc75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438777773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.438777773
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2930776533
Short name T90
Test name
Test status
Simulation time 65186976 ps
CPU time 0.86 seconds
Started Dec 24 01:32:01 PM PST 23
Finished Dec 24 01:32:02 PM PST 23
Peak memory 218672 kb
Host smart-71cd6d1c-504f-4b24-b3e5-1bda52375957
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930776533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2930776533
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/13.uart_stress_all.1078589490
Short name T31
Test name
Test status
Simulation time 166805227340 ps
CPU time 712.56 seconds
Started Dec 24 01:33:37 PM PST 23
Finished Dec 24 01:45:31 PM PST 23
Peak memory 200180 kb
Host smart-0a70b6da-68c5-49c4-8d3e-643aaef3b9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078589490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1078589490
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.651015215
Short name T406
Test name
Test status
Simulation time 455959407452 ps
CPU time 1028.64 seconds
Started Dec 24 01:36:03 PM PST 23
Finished Dec 24 01:53:12 PM PST 23
Peak memory 233100 kb
Host smart-66c9b514-7978-4a77-9639-530b4ebd2b38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651015215 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.651015215
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3681512945
Short name T260
Test name
Test status
Simulation time 61959026311 ps
CPU time 27.27 seconds
Started Dec 24 01:35:23 PM PST 23
Finished Dec 24 01:35:51 PM PST 23
Peak memory 199340 kb
Host smart-ef0422f2-f3e2-4b99-8879-2367bf3e59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681512945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3681512945
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.580997964
Short name T58
Test name
Test status
Simulation time 16455930 ps
CPU time 0.61 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:40:26 PM PST 23
Peak memory 195548 kb
Host smart-0c20b343-1e9c-43ae-8938-cde918411f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580997964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.580997964
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2029374641
Short name T154
Test name
Test status
Simulation time 272767042552 ps
CPU time 377.05 seconds
Started Dec 24 01:37:54 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 216900 kb
Host smart-a9b4f0a0-e53e-4072-ac9b-0cc2effee4eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029374641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2029374641
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3871580627
Short name T37
Test name
Test status
Simulation time 29550546 ps
CPU time 0.63 seconds
Started Dec 24 01:42:07 PM PST 23
Finished Dec 24 01:42:09 PM PST 23
Peak memory 183640 kb
Host smart-1e89d536-c124-43e1-a843-8073a6afc98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871580627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3871580627
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2457781239
Short name T354
Test name
Test status
Simulation time 42607782334 ps
CPU time 37.89 seconds
Started Dec 24 01:38:21 PM PST 23
Finished Dec 24 01:39:00 PM PST 23
Peak memory 199860 kb
Host smart-4b516c86-1d35-450f-aa7d-8a95c11129ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457781239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2457781239
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.790852497
Short name T23
Test name
Test status
Simulation time 123539775874 ps
CPU time 554.76 seconds
Started Dec 24 01:37:48 PM PST 23
Finished Dec 24 01:47:06 PM PST 23
Peak memory 216936 kb
Host smart-a5e234b6-89e1-4dfe-bd6d-1e3a20aaf256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790852497 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.790852497
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3999876426
Short name T144
Test name
Test status
Simulation time 38200457897 ps
CPU time 33.48 seconds
Started Dec 24 01:38:06 PM PST 23
Finished Dec 24 01:38:40 PM PST 23
Peak memory 200228 kb
Host smart-8e2cf43e-d299-49eb-9427-47108b8fad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999876426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3999876426
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3205971669
Short name T96
Test name
Test status
Simulation time 246761009 ps
CPU time 1.23 seconds
Started Dec 24 01:40:36 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 199252 kb
Host smart-b4c85377-8aa9-46f6-b8c5-56f24f48005a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205971669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3205971669
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/33.uart_stress_all.454771807
Short name T327
Test name
Test status
Simulation time 123717141345 ps
CPU time 174.1 seconds
Started Dec 24 01:36:19 PM PST 23
Finished Dec 24 01:39:13 PM PST 23
Peak memory 200240 kb
Host smart-c09e6d8c-39a7-49f5-9676-04b55b225d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454771807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.454771807
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_alert_test.523757420
Short name T101
Test name
Test status
Simulation time 35509541 ps
CPU time 0.54 seconds
Started Dec 24 01:32:13 PM PST 23
Finished Dec 24 01:32:15 PM PST 23
Peak memory 194768 kb
Host smart-f8cacf74-ffde-4812-9e20-7410e10a9ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523757420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.523757420
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_stress_all.1514112503
Short name T158
Test name
Test status
Simulation time 284016677666 ps
CPU time 272.13 seconds
Started Dec 24 01:33:42 PM PST 23
Finished Dec 24 01:38:15 PM PST 23
Peak memory 200220 kb
Host smart-c96ef30f-9b28-4e2a-b33e-92f996afc69f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514112503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1514112503
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.4136132472
Short name T132
Test name
Test status
Simulation time 44163696516 ps
CPU time 45.22 seconds
Started Dec 24 01:39:23 PM PST 23
Finished Dec 24 01:40:09 PM PST 23
Peak memory 200252 kb
Host smart-e7ba75ed-411f-4270-a700-69f3e6b627fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136132472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4136132472
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3425668485
Short name T55
Test name
Test status
Simulation time 34540728 ps
CPU time 0.74 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 197228 kb
Host smart-327ddd5a-f3d6-4f92-9bcb-95d7ce99de7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425668485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3425668485
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2168545210
Short name T141
Test name
Test status
Simulation time 139808776216 ps
CPU time 195.92 seconds
Started Dec 24 01:39:33 PM PST 23
Finished Dec 24 01:42:57 PM PST 23
Peak memory 200152 kb
Host smart-c4ea1559-8e1f-4cee-92ff-94a72c3858ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168545210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2168545210
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.513996789
Short name T286
Test name
Test status
Simulation time 49564061724 ps
CPU time 42.74 seconds
Started Dec 24 01:38:48 PM PST 23
Finished Dec 24 01:39:32 PM PST 23
Peak memory 200016 kb
Host smart-9219f96d-b340-403e-b790-b70ea7948818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513996789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.513996789
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.518077880
Short name T371
Test name
Test status
Simulation time 17725429566 ps
CPU time 14.89 seconds
Started Dec 24 01:38:51 PM PST 23
Finished Dec 24 01:39:06 PM PST 23
Peak memory 200080 kb
Host smart-02290e3d-5059-4a59-8936-8812b44fbd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518077880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.518077880
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2949509929
Short name T295
Test name
Test status
Simulation time 175031107854 ps
CPU time 118.82 seconds
Started Dec 24 01:33:37 PM PST 23
Finished Dec 24 01:35:38 PM PST 23
Peak memory 200252 kb
Host smart-cfe94f17-64f5-421c-8649-7bbaba8107f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949509929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2949509929
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1081316387
Short name T189
Test name
Test status
Simulation time 136783145109 ps
CPU time 94.46 seconds
Started Dec 24 01:39:18 PM PST 23
Finished Dec 24 01:40:54 PM PST 23
Peak memory 200224 kb
Host smart-221f2a3a-1211-42b4-ac8b-5fe905c3ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081316387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1081316387
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4058004592
Short name T218
Test name
Test status
Simulation time 17024618567 ps
CPU time 14.56 seconds
Started Dec 24 01:39:53 PM PST 23
Finished Dec 24 01:40:09 PM PST 23
Peak memory 200120 kb
Host smart-b3ae9920-5564-45c9-b762-7d8785ef4306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058004592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4058004592
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.249917608
Short name T351
Test name
Test status
Simulation time 85495712880 ps
CPU time 30.39 seconds
Started Dec 24 01:34:37 PM PST 23
Finished Dec 24 01:35:10 PM PST 23
Peak memory 200288 kb
Host smart-0f7e769d-7c23-482b-a925-70bbdb58156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249917608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.249917608
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3077446072
Short name T308
Test name
Test status
Simulation time 44089814766 ps
CPU time 17.73 seconds
Started Dec 24 01:39:30 PM PST 23
Finished Dec 24 01:39:49 PM PST 23
Peak memory 199800 kb
Host smart-8cb07aeb-19a0-48d2-aa0e-1a453371f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077446072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3077446072
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1308936611
Short name T357
Test name
Test status
Simulation time 35083500638 ps
CPU time 30.89 seconds
Started Dec 24 01:35:28 PM PST 23
Finished Dec 24 01:36:00 PM PST 23
Peak memory 200204 kb
Host smart-69bca155-1065-4d32-83a0-2261373d4988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308936611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1308936611
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2332170536
Short name T163
Test name
Test status
Simulation time 61235097499 ps
CPU time 45.6 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:39:36 PM PST 23
Peak memory 199668 kb
Host smart-b3957f73-789c-494c-9905-aa9ee68c5652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332170536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2332170536
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.494434285
Short name T361
Test name
Test status
Simulation time 210420253264 ps
CPU time 95.18 seconds
Started Dec 24 01:38:53 PM PST 23
Finished Dec 24 01:40:29 PM PST 23
Peak memory 200192 kb
Host smart-07f47ed9-293f-4b7d-a0d4-e3817f0d7282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494434285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.494434285
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.793325258
Short name T143
Test name
Test status
Simulation time 141587295106 ps
CPU time 57.53 seconds
Started Dec 24 01:39:16 PM PST 23
Finished Dec 24 01:40:15 PM PST 23
Peak memory 200068 kb
Host smart-e176e1d4-5087-45a0-9498-11c4f108be31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793325258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.793325258
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1489285506
Short name T1099
Test name
Test status
Simulation time 82546077683 ps
CPU time 38.24 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:41:20 PM PST 23
Peak memory 200156 kb
Host smart-b0d9874f-6177-4d79-882a-2b0d4fcae202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489285506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1489285506
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all.2496577321
Short name T216
Test name
Test status
Simulation time 440108431184 ps
CPU time 129.42 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:38:38 PM PST 23
Peak memory 208608 kb
Host smart-80275054-d8d6-414b-9823-f22c93a6e2ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496577321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2496577321
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1459674435
Short name T275
Test name
Test status
Simulation time 420931338967 ps
CPU time 1535.63 seconds
Started Dec 24 01:38:30 PM PST 23
Finished Dec 24 02:04:07 PM PST 23
Peak memory 225128 kb
Host smart-2317df01-85d2-43b3-a693-2c59e4c9e921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459674435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1459674435
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4218346300
Short name T369
Test name
Test status
Simulation time 569974871842 ps
CPU time 467.72 seconds
Started Dec 24 01:38:14 PM PST 23
Finished Dec 24 01:46:03 PM PST 23
Peak memory 216576 kb
Host smart-1a08991d-c592-4401-af8a-bca76b0b143d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218346300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4218346300
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1697415942
Short name T52
Test name
Test status
Simulation time 52721222 ps
CPU time 0.56 seconds
Started Dec 24 01:40:35 PM PST 23
Finished Dec 24 01:40:37 PM PST 23
Peak memory 185264 kb
Host smart-44ca3f0c-92d5-4a24-bdfe-85a76453eab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697415942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1697415942
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3106950704
Short name T232
Test name
Test status
Simulation time 22293159079 ps
CPU time 9.64 seconds
Started Dec 24 01:38:34 PM PST 23
Finished Dec 24 01:38:45 PM PST 23
Peak memory 199920 kb
Host smart-495e95cc-c35d-41b3-8133-bc66e2b4722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106950704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3106950704
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.274976474
Short name T398
Test name
Test status
Simulation time 25936863495 ps
CPU time 12.22 seconds
Started Dec 24 01:38:51 PM PST 23
Finished Dec 24 01:39:04 PM PST 23
Peak memory 198436 kb
Host smart-3a58fa72-03f5-4616-abce-a0cd24186723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274976474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.274976474
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2700013179
Short name T246
Test name
Test status
Simulation time 19443971688 ps
CPU time 33.12 seconds
Started Dec 24 01:38:55 PM PST 23
Finished Dec 24 01:39:29 PM PST 23
Peak memory 200136 kb
Host smart-73cabde4-8f41-4b0a-b07b-782bc92f41e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700013179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2700013179
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1425242534
Short name T202
Test name
Test status
Simulation time 134110505417 ps
CPU time 181.19 seconds
Started Dec 24 01:39:35 PM PST 23
Finished Dec 24 01:42:43 PM PST 23
Peak memory 200188 kb
Host smart-c022ae7a-3ba3-4ecd-8f52-d68c4287bbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425242534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1425242534
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3390070489
Short name T40
Test name
Test status
Simulation time 122499313473 ps
CPU time 49.77 seconds
Started Dec 24 01:39:24 PM PST 23
Finished Dec 24 01:40:15 PM PST 23
Peak memory 200204 kb
Host smart-46462852-1b07-43eb-a59c-1dc4f254dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390070489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3390070489
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2830927582
Short name T194
Test name
Test status
Simulation time 110410602591 ps
CPU time 152.73 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 200104 kb
Host smart-fcd09e50-283c-4c2f-90bd-0f083d9d4b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830927582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2830927582
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1714844459
Short name T25
Test name
Test status
Simulation time 2124096785336 ps
CPU time 831.24 seconds
Started Dec 24 01:33:34 PM PST 23
Finished Dec 24 01:47:27 PM PST 23
Peak memory 200188 kb
Host smart-25d239ee-d05c-492c-9df9-51330cadb0d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714844459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1714844459
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1996972739
Short name T180
Test name
Test status
Simulation time 17645982785 ps
CPU time 28.31 seconds
Started Dec 24 01:38:35 PM PST 23
Finished Dec 24 01:39:04 PM PST 23
Peak memory 200288 kb
Host smart-55d8990c-5975-4b44-a4ee-b9606933b132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996972739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1996972739
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3815855974
Short name T391
Test name
Test status
Simulation time 120031011976 ps
CPU time 49.67 seconds
Started Dec 24 01:39:20 PM PST 23
Finished Dec 24 01:40:11 PM PST 23
Peak memory 200224 kb
Host smart-6360a1f1-2307-40f0-b311-d796482991eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815855974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3815855974
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3191080762
Short name T1207
Test name
Test status
Simulation time 42507114463 ps
CPU time 69.37 seconds
Started Dec 24 01:39:53 PM PST 23
Finished Dec 24 01:41:04 PM PST 23
Peak memory 200292 kb
Host smart-1aa9555b-129d-4b31-8c5f-6ac08db48126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191080762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3191080762
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2210724176
Short name T345
Test name
Test status
Simulation time 22002890969 ps
CPU time 36.5 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:41:02 PM PST 23
Peak memory 200016 kb
Host smart-257bddbb-748c-4577-95f3-f69a9e55ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210724176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2210724176
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.610349012
Short name T287
Test name
Test status
Simulation time 121607117018 ps
CPU time 45.42 seconds
Started Dec 24 01:37:32 PM PST 23
Finished Dec 24 01:38:23 PM PST 23
Peak memory 200192 kb
Host smart-eaab9bc1-01ca-40b0-8972-a6e8ed1be179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610349012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.610349012
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.136843914
Short name T254
Test name
Test status
Simulation time 76110454946 ps
CPU time 453.25 seconds
Started Dec 24 01:33:36 PM PST 23
Finished Dec 24 01:41:11 PM PST 23
Peak memory 216568 kb
Host smart-70b4e10b-34c0-4545-a76e-a973cef15b6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136843914 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.136843914
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1774609524
Short name T294
Test name
Test status
Simulation time 74675790428 ps
CPU time 32.78 seconds
Started Dec 24 01:38:52 PM PST 23
Finished Dec 24 01:39:25 PM PST 23
Peak memory 200084 kb
Host smart-43725ecb-d9a2-42ed-b04a-12dc3fa1e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774609524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1774609524
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3052911334
Short name T305
Test name
Test status
Simulation time 97443917855 ps
CPU time 168.1 seconds
Started Dec 24 01:38:51 PM PST 23
Finished Dec 24 01:41:40 PM PST 23
Peak memory 200172 kb
Host smart-befeaf7f-deac-4738-82b9-796015946d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052911334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3052911334
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.371181993
Short name T199
Test name
Test status
Simulation time 39290260259 ps
CPU time 34.98 seconds
Started Dec 24 01:38:37 PM PST 23
Finished Dec 24 01:39:13 PM PST 23
Peak memory 200180 kb
Host smart-a9409734-058a-493e-93af-238a49d6a360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371181993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.371181993
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1000183972
Short name T292
Test name
Test status
Simulation time 64899771959 ps
CPU time 28.6 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:39:02 PM PST 23
Peak memory 200204 kb
Host smart-c20ec79f-fc09-4a48-ac58-ca32557cd847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000183972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1000183972
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.197623241
Short name T252
Test name
Test status
Simulation time 37080297190 ps
CPU time 28.09 seconds
Started Dec 24 01:38:52 PM PST 23
Finished Dec 24 01:39:21 PM PST 23
Peak memory 200200 kb
Host smart-7a2d4a92-5e39-4af1-ab46-255b4def2357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197623241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.197623241
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2054647969
Short name T290
Test name
Test status
Simulation time 79587617288 ps
CPU time 33.01 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 01:39:24 PM PST 23
Peak memory 199952 kb
Host smart-550d0347-0bc5-442b-b19a-060916163bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054647969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2054647969
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3761668526
Short name T220
Test name
Test status
Simulation time 171613586065 ps
CPU time 81.71 seconds
Started Dec 24 01:38:57 PM PST 23
Finished Dec 24 01:40:20 PM PST 23
Peak memory 200312 kb
Host smart-2af47424-f0e1-4223-8a82-a667a3af6b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761668526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3761668526
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3648167614
Short name T177
Test name
Test status
Simulation time 63250545762 ps
CPU time 53.19 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:48 PM PST 23
Peak memory 200040 kb
Host smart-35b7b964-e2bc-47be-9bdb-f765378d1978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648167614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3648167614
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.15319331
Short name T408
Test name
Test status
Simulation time 38614409863 ps
CPU time 32.06 seconds
Started Dec 24 01:38:57 PM PST 23
Finished Dec 24 01:39:30 PM PST 23
Peak memory 200292 kb
Host smart-574d80e6-2763-492e-86bc-8c43407e1769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15319331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.15319331
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3061615756
Short name T196
Test name
Test status
Simulation time 119691075095 ps
CPU time 14.82 seconds
Started Dec 24 01:39:34 PM PST 23
Finished Dec 24 01:39:56 PM PST 23
Peak memory 200140 kb
Host smart-8c3109ab-d581-4572-8556-9135bbd5f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061615756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3061615756
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1947803449
Short name T370
Test name
Test status
Simulation time 27289441464 ps
CPU time 15.47 seconds
Started Dec 24 01:39:21 PM PST 23
Finished Dec 24 01:39:37 PM PST 23
Peak memory 200020 kb
Host smart-1bf89c5d-ea7e-4c34-abe2-210ad6193003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947803449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1947803449
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1425303913
Short name T359
Test name
Test status
Simulation time 149201870739 ps
CPU time 31.49 seconds
Started Dec 24 01:39:54 PM PST 23
Finished Dec 24 01:40:27 PM PST 23
Peak memory 200184 kb
Host smart-6da0a1cb-262b-4173-9b2f-bff80cb2e158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425303913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1425303913
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.734908027
Short name T282
Test name
Test status
Simulation time 20695168512 ps
CPU time 8.48 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:36:37 PM PST 23
Peak memory 198820 kb
Host smart-e3b9512a-2c08-4b8c-ad26-a5db2d4c9e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734908027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.734908027
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_stress_all.1257810599
Short name T364
Test name
Test status
Simulation time 143534085122 ps
CPU time 782.82 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:49:36 PM PST 23
Peak memory 200216 kb
Host smart-7aac1eb4-7c96-45ad-80aa-48bd12698b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257810599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1257810599
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3579138643
Short name T374
Test name
Test status
Simulation time 264918563327 ps
CPU time 1826.37 seconds
Started Dec 24 01:37:36 PM PST 23
Finished Dec 24 02:08:09 PM PST 23
Peak memory 229768 kb
Host smart-2e6ab368-23dd-4f49-801e-48f80124ad0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579138643 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3579138643
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2755928317
Short name T77
Test name
Test status
Simulation time 125871739127 ps
CPU time 1174.84 seconds
Started Dec 24 01:37:38 PM PST 23
Finished Dec 24 01:57:19 PM PST 23
Peak memory 213156 kb
Host smart-ca445b90-d2a2-4192-82cc-0a6bfcc1cc30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755928317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2755928317
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1480161428
Short name T223
Test name
Test status
Simulation time 178319650434 ps
CPU time 434.17 seconds
Started Dec 24 01:33:26 PM PST 23
Finished Dec 24 01:40:41 PM PST 23
Peak memory 216580 kb
Host smart-0529870c-bfe1-49cd-af5b-094cc63baf96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480161428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1480161428
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4107410020
Short name T206
Test name
Test status
Simulation time 56496342552 ps
CPU time 25.34 seconds
Started Dec 24 01:37:41 PM PST 23
Finished Dec 24 01:38:12 PM PST 23
Peak memory 200216 kb
Host smart-f8bffffa-e54b-41ff-8a23-efc8afe53cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107410020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4107410020
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.661827289
Short name T1133
Test name
Test status
Simulation time 157441702962 ps
CPU time 58.73 seconds
Started Dec 24 01:38:36 PM PST 23
Finished Dec 24 01:39:35 PM PST 23
Peak memory 200212 kb
Host smart-5625b2f1-2c93-4784-a39d-8a8cc4e15015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661827289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.661827289
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2627157376
Short name T1260
Test name
Test status
Simulation time 96394924 ps
CPU time 1.3 seconds
Started Dec 24 01:40:09 PM PST 23
Finished Dec 24 01:40:16 PM PST 23
Peak memory 199376 kb
Host smart-db40ca8b-46c4-4462-9146-07cd9e58ec94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627157376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2627157376
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2688748249
Short name T72
Test name
Test status
Simulation time 66220730 ps
CPU time 0.58 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 185208 kb
Host smart-63820737-7180-4263-87ed-20ddd15aaf58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688748249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2688748249
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.531180142
Short name T1171
Test name
Test status
Simulation time 16583875039 ps
CPU time 14.29 seconds
Started Dec 24 01:32:00 PM PST 23
Finished Dec 24 01:32:15 PM PST 23
Peak memory 200096 kb
Host smart-e85d3bbc-3cf7-4504-a704-3bee19bc2c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531180142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.531180142
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1951452939
Short name T841
Test name
Test status
Simulation time 62472015573 ps
CPU time 89.57 seconds
Started Dec 24 01:33:42 PM PST 23
Finished Dec 24 01:35:13 PM PST 23
Peak memory 200144 kb
Host smart-5488fdb4-cb21-4f0c-ab28-d9993f4133d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951452939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1951452939
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1228631838
Short name T187
Test name
Test status
Simulation time 18460574261 ps
CPU time 31.41 seconds
Started Dec 24 01:38:48 PM PST 23
Finished Dec 24 01:39:20 PM PST 23
Peak memory 200268 kb
Host smart-7a5bf622-f788-4de2-8f4e-e878e466ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228631838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1228631838
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1347736604
Short name T259
Test name
Test status
Simulation time 91306889993 ps
CPU time 277.54 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:40:19 PM PST 23
Peak memory 216408 kb
Host smart-c52f7bb5-0bce-4779-8018-7b7c34b04578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347736604 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1347736604
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2840870168
Short name T1088
Test name
Test status
Simulation time 119141252498 ps
CPU time 172.17 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 01:41:43 PM PST 23
Peak memory 199952 kb
Host smart-e498b8ca-a474-484a-8a2f-2de57cc1122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840870168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2840870168
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1143341101
Short name T316
Test name
Test status
Simulation time 12623835721 ps
CPU time 21.82 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 01:39:12 PM PST 23
Peak memory 200224 kb
Host smart-90f67704-cc27-4651-98b8-6983e33c444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143341101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1143341101
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1374997536
Short name T306
Test name
Test status
Simulation time 147707701711 ps
CPU time 23.98 seconds
Started Dec 24 01:33:40 PM PST 23
Finished Dec 24 01:34:05 PM PST 23
Peak memory 200164 kb
Host smart-7415b1c9-3521-4849-a0ef-782b6f0bcc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374997536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1374997536
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1757668295
Short name T376
Test name
Test status
Simulation time 59412343665 ps
CPU time 98.67 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:40:29 PM PST 23
Peak memory 200204 kb
Host smart-98d431ad-50a4-4bc2-84c9-fa95fab36e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757668295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1757668295
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4011679313
Short name T261
Test name
Test status
Simulation time 31073931076 ps
CPU time 27.65 seconds
Started Dec 24 01:38:52 PM PST 23
Finished Dec 24 01:39:21 PM PST 23
Peak memory 200064 kb
Host smart-be0a5c23-b63a-4a65-b9bd-1c3bd84ee4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011679313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4011679313
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2311988708
Short name T319
Test name
Test status
Simulation time 154783219073 ps
CPU time 263.71 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:38:23 PM PST 23
Peak memory 200216 kb
Host smart-43f22b5b-853c-4947-af49-b110b9a794d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311988708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2311988708
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1081155320
Short name T284
Test name
Test status
Simulation time 140249298555 ps
CPU time 43.58 seconds
Started Dec 24 01:38:56 PM PST 23
Finished Dec 24 01:39:40 PM PST 23
Peak memory 200352 kb
Host smart-99c0e899-719a-4a78-9e12-0182525864c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081155320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1081155320
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2293974167
Short name T392
Test name
Test status
Simulation time 71413543816 ps
CPU time 8.16 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:34:28 PM PST 23
Peak memory 199996 kb
Host smart-965b6a74-90f7-4194-a214-df6d5b2eb059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293974167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2293974167
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3511789447
Short name T268
Test name
Test status
Simulation time 23190011719 ps
CPU time 38.52 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:35:01 PM PST 23
Peak memory 200204 kb
Host smart-cbf5534d-7a9e-4514-948e-469c2ac69ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511789447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3511789447
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.202977618
Short name T315
Test name
Test status
Simulation time 43826650228 ps
CPU time 20.11 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:35:00 PM PST 23
Peak memory 200280 kb
Host smart-198e0d18-8918-474a-8d10-a4b6a35ae867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202977618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.202977618
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1809996252
Short name T405
Test name
Test status
Simulation time 81825091655 ps
CPU time 26.14 seconds
Started Dec 24 01:36:13 PM PST 23
Finished Dec 24 01:36:40 PM PST 23
Peak memory 199852 kb
Host smart-a4d8d822-7f7f-4a00-929a-00e41f6e478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809996252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1809996252
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1884267285
Short name T270
Test name
Test status
Simulation time 25005737460 ps
CPU time 45.63 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:35:07 PM PST 23
Peak memory 200012 kb
Host smart-ae3e2ec0-9395-40c3-b931-ee8e9280a696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884267285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1884267285
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1508990624
Short name T214
Test name
Test status
Simulation time 122858330362 ps
CPU time 45.6 seconds
Started Dec 24 01:39:21 PM PST 23
Finished Dec 24 01:40:07 PM PST 23
Peak memory 200036 kb
Host smart-64006a48-419c-4740-a798-9fee94386207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508990624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1508990624
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.688981720
Short name T263
Test name
Test status
Simulation time 59090545825 ps
CPU time 21.58 seconds
Started Dec 24 01:39:29 PM PST 23
Finished Dec 24 01:39:53 PM PST 23
Peak memory 199824 kb
Host smart-98a8b23e-4ee8-4648-8111-74b33c967d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688981720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.688981720
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.1838642164
Short name T205
Test name
Test status
Simulation time 284586705161 ps
CPU time 437.07 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 200588 kb
Host smart-de79e1cd-cc36-4ca5-a800-9f781f9601c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838642164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1838642164
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1157618031
Short name T396
Test name
Test status
Simulation time 66110579653 ps
CPU time 18.06 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:35:02 PM PST 23
Peak memory 200272 kb
Host smart-57a4a0ee-55d4-4c17-afd9-03452546a131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157618031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1157618031
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.698878390
Short name T313
Test name
Test status
Simulation time 230826004333 ps
CPU time 99.01 seconds
Started Dec 24 01:39:20 PM PST 23
Finished Dec 24 01:41:00 PM PST 23
Peak memory 200248 kb
Host smart-33bedd86-dcd0-4366-8e0d-e71db912616a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698878390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.698878390
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1472210244
Short name T304
Test name
Test status
Simulation time 94735615620 ps
CPU time 162.02 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 200196 kb
Host smart-1afa9a24-8eae-4f2e-93e8-c0fe1f7d2258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472210244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1472210244
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_perf.1800036232
Short name T314
Test name
Test status
Simulation time 18337786087 ps
CPU time 845.71 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:49:31 PM PST 23
Peak memory 199992 kb
Host smart-6c51bc91-f138-49a2-a3a4-3568e2bc427e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800036232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1800036232
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1031402381
Short name T121
Test name
Test status
Simulation time 29172664639 ps
CPU time 31.34 seconds
Started Dec 24 01:40:09 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 200212 kb
Host smart-aa972fb8-2b07-4164-90a0-559176722652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031402381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1031402381
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3947048526
Short name T131
Test name
Test status
Simulation time 79943787332 ps
CPU time 105.86 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:42:06 PM PST 23
Peak memory 199876 kb
Host smart-4d2cb45f-8736-4d47-9119-5a9216852d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947048526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3947048526
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3038669446
Short name T402
Test name
Test status
Simulation time 74838070780 ps
CPU time 19.77 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:36:28 PM PST 23
Peak memory 199528 kb
Host smart-d3823b80-9b15-4350-a6df-dcb12c9cde4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038669446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3038669446
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3897851507
Short name T387
Test name
Test status
Simulation time 53779196183 ps
CPU time 24.78 seconds
Started Dec 24 01:36:17 PM PST 23
Finished Dec 24 01:36:43 PM PST 23
Peak memory 200144 kb
Host smart-f5c3d43f-536a-4ff9-87a8-739b2b57c74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897851507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3897851507
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.854122074
Short name T229
Test name
Test status
Simulation time 35467922198 ps
CPU time 51.86 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:37:19 PM PST 23
Peak memory 200136 kb
Host smart-e86fa6fa-1fd8-4ace-a1ad-cedba8b2f657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854122074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.854122074
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_perf.2617564200
Short name T301
Test name
Test status
Simulation time 4902852032 ps
CPU time 236.02 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:40:23 PM PST 23
Peak memory 200272 kb
Host smart-d2a8618d-c79b-43f0-b6fa-4ffe507dba53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617564200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2617564200
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3989325978
Short name T311
Test name
Test status
Simulation time 105233878190 ps
CPU time 165.45 seconds
Started Dec 24 01:32:40 PM PST 23
Finished Dec 24 01:35:26 PM PST 23
Peak memory 200192 kb
Host smart-f338bb92-6883-4f98-8794-2741db9c6362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989325978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3989325978
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1804958965
Short name T1150
Test name
Test status
Simulation time 81706971681 ps
CPU time 126.3 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:38:39 PM PST 23
Peak memory 200116 kb
Host smart-6e539138-dd3b-476f-9bc3-3fa2660ddde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804958965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1804958965
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_stress_all.960794663
Short name T366
Test name
Test status
Simulation time 280463893366 ps
CPU time 366.28 seconds
Started Dec 24 01:37:16 PM PST 23
Finished Dec 24 01:43:23 PM PST 23
Peak memory 200076 kb
Host smart-4d862b59-cdf8-4276-a46a-f3a3deadb8a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960794663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.960794663
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all.1672804855
Short name T309
Test name
Test status
Simulation time 653241176161 ps
CPU time 351.78 seconds
Started Dec 24 01:37:17 PM PST 23
Finished Dec 24 01:43:10 PM PST 23
Peak memory 208636 kb
Host smart-67a08fbd-10a3-409b-964e-2d229d1be1bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672804855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1672804855
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3776252971
Short name T321
Test name
Test status
Simulation time 18701710749 ps
CPU time 20 seconds
Started Dec 24 01:37:17 PM PST 23
Finished Dec 24 01:37:38 PM PST 23
Peak memory 200028 kb
Host smart-fa77c57a-d423-422e-aa85-930c0e2637d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776252971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3776252971
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1338875153
Short name T302
Test name
Test status
Simulation time 138553205630 ps
CPU time 120.45 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:39:30 PM PST 23
Peak memory 200272 kb
Host smart-bad6fba8-7c28-4735-9ab9-312d902d03cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338875153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1338875153
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3609591034
Short name T368
Test name
Test status
Simulation time 354666931430 ps
CPU time 34.39 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:07 PM PST 23
Peak memory 199584 kb
Host smart-a4797a2f-749a-4e74-ab21-ae66fa9300c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609591034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3609591034
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2589471872
Short name T231
Test name
Test status
Simulation time 15280904454 ps
CPU time 7.55 seconds
Started Dec 24 01:37:53 PM PST 23
Finished Dec 24 01:38:01 PM PST 23
Peak memory 199564 kb
Host smart-d90253dc-b3df-4834-bda3-ff2fbd932ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589471872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2589471872
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2138288927
Short name T399
Test name
Test status
Simulation time 509458792415 ps
CPU time 1225.9 seconds
Started Dec 24 01:38:02 PM PST 23
Finished Dec 24 01:58:29 PM PST 23
Peak memory 233340 kb
Host smart-4da831b8-3e83-41db-b37a-3f7757a5ce6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138288927 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2138288927
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2513704438
Short name T353
Test name
Test status
Simulation time 99287825683 ps
CPU time 27.61 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:38:49 PM PST 23
Peak memory 200228 kb
Host smart-3d9a99fe-af67-4cc0-a9df-c1806d616fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513704438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2513704438
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.765368674
Short name T68
Test name
Test status
Simulation time 30493937 ps
CPU time 0.66 seconds
Started Dec 24 01:39:53 PM PST 23
Finished Dec 24 01:39:55 PM PST 23
Peak memory 194976 kb
Host smart-ff4b9aed-a798-4a72-a950-860c81d40e78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765368674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.765368674
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3427152906
Short name T60
Test name
Test status
Simulation time 57157242 ps
CPU time 2.32 seconds
Started Dec 24 01:39:38 PM PST 23
Finished Dec 24 01:39:47 PM PST 23
Peak memory 197720 kb
Host smart-2b395872-0a0b-4023-9fdf-be41788d9993
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427152906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3427152906
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.980940687
Short name T34
Test name
Test status
Simulation time 50085189 ps
CPU time 0.61 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195516 kb
Host smart-ae8f7a05-88c2-47ad-a55e-53c2b14ad392
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980940687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.980940687
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.731983191
Short name T1279
Test name
Test status
Simulation time 27227995 ps
CPU time 0.85 seconds
Started Dec 24 01:39:54 PM PST 23
Finished Dec 24 01:39:56 PM PST 23
Peak memory 199980 kb
Host smart-50334211-bc6e-4eab-9e31-fd3085cc21bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731983191 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.731983191
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1358500891
Short name T479
Test name
Test status
Simulation time 51573604 ps
CPU time 0.53 seconds
Started Dec 24 01:39:38 PM PST 23
Finished Dec 24 01:39:46 PM PST 23
Peak memory 185244 kb
Host smart-afdb1b6c-584e-4f7f-b06d-91e89500c1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358500891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1358500891
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.651511328
Short name T53
Test name
Test status
Simulation time 30901444 ps
CPU time 0.62 seconds
Started Dec 24 01:40:14 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 196080 kb
Host smart-21ae9a9a-3707-4faf-83e1-fa67432f94ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651511328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.651511328
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1718330436
Short name T1256
Test name
Test status
Simulation time 151152134 ps
CPU time 1.14 seconds
Started Dec 24 01:39:52 PM PST 23
Finished Dec 24 01:39:54 PM PST 23
Peak memory 199916 kb
Host smart-8ca7649b-55d4-42d4-b727-442efe360beb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718330436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1718330436
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4135903040
Short name T94
Test name
Test status
Simulation time 85847590 ps
CPU time 0.92 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 198700 kb
Host smart-bc4b9ab5-5ca2-4ad6-b540-15deca4f2c31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135903040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4135903040
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2798399553
Short name T1286
Test name
Test status
Simulation time 14464875 ps
CPU time 0.7 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 194580 kb
Host smart-fa789e36-848a-4e32-a51f-d2ef659406cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798399553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2798399553
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3852867149
Short name T1283
Test name
Test status
Simulation time 210312762 ps
CPU time 2.18 seconds
Started Dec 24 01:40:36 PM PST 23
Finished Dec 24 01:40:40 PM PST 23
Peak memory 197760 kb
Host smart-1f6c118d-cfac-4df1-946c-1c6f4103aafb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852867149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3852867149
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1895370496
Short name T1276
Test name
Test status
Simulation time 44005789 ps
CPU time 0.56 seconds
Started Dec 24 01:40:14 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195468 kb
Host smart-58c64dd6-dc19-4902-b094-82d6a7ffe364
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895370496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1895370496
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.624718509
Short name T73
Test name
Test status
Simulation time 29908889 ps
CPU time 0.8 seconds
Started Dec 24 01:39:53 PM PST 23
Finished Dec 24 01:39:56 PM PST 23
Peak memory 199268 kb
Host smart-e81ed9a0-f1e6-4071-b81f-52e751e512c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624718509 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.624718509
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2163758890
Short name T1259
Test name
Test status
Simulation time 25216097 ps
CPU time 0.62 seconds
Started Dec 24 01:40:09 PM PST 23
Finished Dec 24 01:40:16 PM PST 23
Peak memory 195656 kb
Host smart-6eefc846-ec72-40dd-879d-727f53ac8b1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163758890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2163758890
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.531264430
Short name T1296
Test name
Test status
Simulation time 35064020 ps
CPU time 0.79 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:42 PM PST 23
Peak memory 196916 kb
Host smart-e080e283-0cab-495e-b7ea-452746233878
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531264430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.531264430
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.405743086
Short name T473
Test name
Test status
Simulation time 448688783 ps
CPU time 1.77 seconds
Started Dec 24 01:40:33 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 200116 kb
Host smart-dc7c182e-514b-4a36-a24f-cd72ede3ac05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405743086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.405743086
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2605666071
Short name T98
Test name
Test status
Simulation time 230310509 ps
CPU time 0.95 seconds
Started Dec 24 01:39:41 PM PST 23
Finished Dec 24 01:39:47 PM PST 23
Peak memory 198864 kb
Host smart-8517b901-0d10-4757-9761-4f8b8a14e303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605666071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2605666071
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3895464602
Short name T51
Test name
Test status
Simulation time 32286218 ps
CPU time 0.68 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 197780 kb
Host smart-4266c63c-e85f-4428-a302-3d26ff906666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895464602 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3895464602
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2618922422
Short name T57
Test name
Test status
Simulation time 45108873 ps
CPU time 0.59 seconds
Started Dec 24 01:40:35 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 195568 kb
Host smart-ef2bc97e-c90e-434c-9938-55318b679f59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618922422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2618922422
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3770436460
Short name T469
Test name
Test status
Simulation time 48334372 ps
CPU time 0.55 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 194576 kb
Host smart-418c3925-127d-4c63-ab24-7865e43d6119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770436460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3770436460
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.783054628
Short name T1280
Test name
Test status
Simulation time 72157427 ps
CPU time 0.71 seconds
Started Dec 24 01:40:36 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 197004 kb
Host smart-13fec643-2102-459a-bf40-50fcf0ce84be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783054628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.783054628
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4055058416
Short name T49
Test name
Test status
Simulation time 78817840 ps
CPU time 1.72 seconds
Started Dec 24 01:40:09 PM PST 23
Finished Dec 24 01:40:18 PM PST 23
Peak memory 200172 kb
Host smart-bc11873b-b0af-4853-bbae-46db13a06049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055058416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4055058416
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.537163876
Short name T2
Test name
Test status
Simulation time 410544362 ps
CPU time 0.88 seconds
Started Dec 24 01:40:35 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 198656 kb
Host smart-3ffea978-dccd-49f6-9f2e-2206b16dd5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537163876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.537163876
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.977807207
Short name T50
Test name
Test status
Simulation time 24256682 ps
CPU time 1.42 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 200172 kb
Host smart-4e23b9f0-ce50-4a1f-9305-ab933de2aff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977807207 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.977807207
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.538149314
Short name T484
Test name
Test status
Simulation time 15062221 ps
CPU time 0.6 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195572 kb
Host smart-a8204a69-7a23-47a9-8068-6eac8077455e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538149314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.538149314
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1732527484
Short name T1267
Test name
Test status
Simulation time 361727827 ps
CPU time 2.07 seconds
Started Dec 24 01:40:33 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 200116 kb
Host smart-110f4ab1-15dc-4a5d-bbb7-60181b6bdd72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732527484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1732527484
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.71474717
Short name T1236
Test name
Test status
Simulation time 102629098 ps
CPU time 1.31 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:37 PM PST 23
Peak memory 199308 kb
Host smart-aa7e8ad8-78da-4650-8a5b-b9c97bc359be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71474717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.71474717
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.743352760
Short name T489
Test name
Test status
Simulation time 17848504 ps
CPU time 0.87 seconds
Started Dec 24 01:40:09 PM PST 23
Finished Dec 24 01:40:17 PM PST 23
Peak memory 199968 kb
Host smart-6b37b435-0197-480b-bebc-1806595490b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743352760 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.743352760
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.684116441
Short name T82
Test name
Test status
Simulation time 23875214 ps
CPU time 0.61 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195552 kb
Host smart-fa6d8ecb-c2ad-40c7-8673-5e95bee88e65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684116441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.684116441
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3922257984
Short name T468
Test name
Test status
Simulation time 27926048 ps
CPU time 0.57 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 185180 kb
Host smart-66f7d688-30f9-403e-ad2e-e2035ef8bf33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922257984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3922257984
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1496573209
Short name T478
Test name
Test status
Simulation time 76975704 ps
CPU time 0.65 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195720 kb
Host smart-92078f89-2f44-4488-baee-5854c007da5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496573209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1496573209
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1520661521
Short name T491
Test name
Test status
Simulation time 33421127 ps
CPU time 1.65 seconds
Started Dec 24 01:40:33 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 199996 kb
Host smart-b4892d78-af46-4647-b382-5786bcb00c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520661521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1520661521
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1874741663
Short name T409
Test name
Test status
Simulation time 167929381 ps
CPU time 1.31 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 199236 kb
Host smart-4b77f6c4-d0e0-465b-9c4b-0498531e232e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874741663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1874741663
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3688362925
Short name T1275
Test name
Test status
Simulation time 30353768 ps
CPU time 1.4 seconds
Started Dec 24 01:40:22 PM PST 23
Finished Dec 24 01:40:29 PM PST 23
Peak memory 200128 kb
Host smart-b96fa6e0-43b3-4535-a401-b0fb7245a411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688362925 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3688362925
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1017387986
Short name T1257
Test name
Test status
Simulation time 40255568 ps
CPU time 0.59 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:40:26 PM PST 23
Peak memory 195528 kb
Host smart-0285ce38-f5d0-454e-8af5-5ffa2e0cf905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017387986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1017387986
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1027239249
Short name T1282
Test name
Test status
Simulation time 18722632 ps
CPU time 0.55 seconds
Started Dec 24 01:40:20 PM PST 23
Finished Dec 24 01:40:28 PM PST 23
Peak memory 185236 kb
Host smart-3a16d2e8-931a-4c52-b984-9b3749368d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027239249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1027239249
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.841285353
Short name T477
Test name
Test status
Simulation time 45591621 ps
CPU time 0.6 seconds
Started Dec 24 01:40:37 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 195556 kb
Host smart-c17f9ed7-0137-428a-b0f6-10b21615b3cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841285353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.841285353
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.4062059564
Short name T116
Test name
Test status
Simulation time 83133419 ps
CPU time 1.03 seconds
Started Dec 24 01:40:08 PM PST 23
Finished Dec 24 01:40:11 PM PST 23
Peak memory 199864 kb
Host smart-0dad77de-cf0d-4f1b-ab3d-ec32db0313d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062059564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4062059564
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.192358185
Short name T476
Test name
Test status
Simulation time 99153038 ps
CPU time 1.46 seconds
Started Dec 24 01:40:33 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 200152 kb
Host smart-3295058e-863d-4dbc-9baf-0815b01ec0f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192358185 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.192358185
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.803781992
Short name T497
Test name
Test status
Simulation time 12022058 ps
CPU time 0.57 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195544 kb
Host smart-28a0b09d-bf17-45f7-82f0-77e4534ee37f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803781992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.803781992
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.672599546
Short name T1272
Test name
Test status
Simulation time 13465952 ps
CPU time 0.61 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 185264 kb
Host smart-5a7ab6ac-ece9-4793-8320-63a3ed035734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672599546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.672599546
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2061182992
Short name T1238
Test name
Test status
Simulation time 61191137 ps
CPU time 0.74 seconds
Started Dec 24 01:40:22 PM PST 23
Finished Dec 24 01:40:29 PM PST 23
Peak memory 196988 kb
Host smart-a88c568f-c5c2-4296-9e15-dfb5fde3f2c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061182992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2061182992
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4071635434
Short name T1246
Test name
Test status
Simulation time 492948811 ps
CPU time 1 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:44 PM PST 23
Peak memory 198872 kb
Host smart-bbccc2e8-1e25-4ddf-997c-70a2fd5d8e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071635434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4071635434
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2234249452
Short name T495
Test name
Test status
Simulation time 149293225 ps
CPU time 0.82 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 199868 kb
Host smart-7c3e5043-410c-4ce6-b772-75e5ed4ad4a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234249452 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2234249452
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3168397925
Short name T1254
Test name
Test status
Simulation time 41341158 ps
CPU time 0.58 seconds
Started Dec 24 01:40:36 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 195548 kb
Host smart-5c8af685-7dba-4ca5-b60e-700398d5154e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168397925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3168397925
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1358146688
Short name T1242
Test name
Test status
Simulation time 36700799 ps
CPU time 0.57 seconds
Started Dec 24 01:40:33 PM PST 23
Finished Dec 24 01:40:35 PM PST 23
Peak memory 185236 kb
Host smart-538105c8-c9ed-406c-a68c-ce166c7d87cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358146688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1358146688
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.157692199
Short name T117
Test name
Test status
Simulation time 101083276 ps
CPU time 0.72 seconds
Started Dec 24 01:40:15 PM PST 23
Finished Dec 24 01:40:25 PM PST 23
Peak memory 196848 kb
Host smart-e106dc77-e45b-4a8d-af6d-5e9ef7e00fef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157692199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.157692199
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1345702497
Short name T1273
Test name
Test status
Simulation time 49527909 ps
CPU time 0.97 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:45 PM PST 23
Peak memory 198904 kb
Host smart-3d964076-ab53-40f8-8b4d-1fbe98f07fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345702497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1345702497
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3497332035
Short name T475
Test name
Test status
Simulation time 21372511 ps
CPU time 1.06 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:45 PM PST 23
Peak memory 199896 kb
Host smart-16e57112-316d-4218-a627-2337214e632f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497332035 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3497332035
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2085172880
Short name T1278
Test name
Test status
Simulation time 72122031 ps
CPU time 0.61 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195684 kb
Host smart-e2cb6168-38b2-40ce-b58a-ab0ca59f9a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085172880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2085172880
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3897245595
Short name T1291
Test name
Test status
Simulation time 12163810 ps
CPU time 0.55 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:40:26 PM PST 23
Peak memory 185292 kb
Host smart-b238cac7-55b8-4542-a639-fb5a22634c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897245595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3897245595
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.475066456
Short name T1243
Test name
Test status
Simulation time 137084566 ps
CPU time 0.79 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 196620 kb
Host smart-d7712b26-4f6c-4c11-89bf-9cc63ecca0ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475066456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.475066456
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3084361292
Short name T1281
Test name
Test status
Simulation time 102713711 ps
CPU time 1.41 seconds
Started Dec 24 01:40:41 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 198880 kb
Host smart-007a7c4b-8c0e-407a-b5de-79688ac165aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084361292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3084361292
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.673194565
Short name T1289
Test name
Test status
Simulation time 845180450 ps
CPU time 0.95 seconds
Started Dec 24 01:40:37 PM PST 23
Finished Dec 24 01:40:40 PM PST 23
Peak memory 198968 kb
Host smart-16e20bbe-1c51-4a67-b077-5a8e69b16cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673194565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.673194565
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2955818069
Short name T1255
Test name
Test status
Simulation time 16272071 ps
CPU time 0.72 seconds
Started Dec 24 01:40:15 PM PST 23
Finished Dec 24 01:40:22 PM PST 23
Peak memory 198672 kb
Host smart-cf98d42e-b317-4b3f-9a5a-48cb7f80320a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955818069 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2955818069
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.781169868
Short name T81
Test name
Test status
Simulation time 80455935 ps
CPU time 0.61 seconds
Started Dec 24 01:40:23 PM PST 23
Finished Dec 24 01:40:29 PM PST 23
Peak memory 195588 kb
Host smart-36fbd825-8a1d-489a-ba1b-395b06fe76ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781169868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.781169868
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.934947933
Short name T1274
Test name
Test status
Simulation time 36759104 ps
CPU time 0.55 seconds
Started Dec 24 01:40:23 PM PST 23
Finished Dec 24 01:40:29 PM PST 23
Peak memory 185160 kb
Host smart-15f40991-1aca-4150-abb5-11df533184ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934947933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.934947933
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4154577780
Short name T64
Test name
Test status
Simulation time 51195773 ps
CPU time 0.74 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:44 PM PST 23
Peak memory 196084 kb
Host smart-6910e8ba-3197-4271-8a03-6f234e589d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154577780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4154577780
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2225615600
Short name T1266
Test name
Test status
Simulation time 109512418 ps
CPU time 1.94 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:40:27 PM PST 23
Peak memory 200084 kb
Host smart-3abd5c9e-b39d-462b-bf29-5175cbc432f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225615600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2225615600
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3096925302
Short name T99
Test name
Test status
Simulation time 139950311 ps
CPU time 1.29 seconds
Started Dec 24 01:40:19 PM PST 23
Finished Dec 24 01:40:28 PM PST 23
Peak memory 199388 kb
Host smart-7a65ade5-7851-45ce-89b5-0a194f005707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096925302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3096925302
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.893313202
Short name T1287
Test name
Test status
Simulation time 21249441 ps
CPU time 0.73 seconds
Started Dec 24 01:40:42 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 199552 kb
Host smart-c5c5597b-02ba-4cef-9076-785b870724e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893313202 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.893313202
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1306388519
Short name T1239
Test name
Test status
Simulation time 22218140 ps
CPU time 0.55 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:42 PM PST 23
Peak memory 194424 kb
Host smart-0f5d643d-3912-4246-bffb-d0f1ffaba487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306388519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1306388519
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3525510200
Short name T7
Test name
Test status
Simulation time 61061675 ps
CPU time 0.76 seconds
Started Dec 24 01:40:36 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 197976 kb
Host smart-a67f8d3b-dc6b-4acf-82e4-f6b13180b5e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525510200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3525510200
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1443225290
Short name T1288
Test name
Test status
Simulation time 342512926 ps
CPU time 1.67 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 200116 kb
Host smart-2b696233-0d6e-439f-98f3-5c53b2e6b4f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443225290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1443225290
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1947787981
Short name T95
Test name
Test status
Simulation time 684008047 ps
CPU time 0.92 seconds
Started Dec 24 01:40:21 PM PST 23
Finished Dec 24 01:40:28 PM PST 23
Peak memory 198708 kb
Host smart-aae8e021-a05b-479a-bb72-215d61c5949f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947787981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1947787981
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2175063234
Short name T470
Test name
Test status
Simulation time 24104214 ps
CPU time 0.65 seconds
Started Dec 24 01:40:36 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 197704 kb
Host smart-c173d165-6b8d-4a02-97ed-0bf8e71f86e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175063234 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2175063234
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2201208036
Short name T485
Test name
Test status
Simulation time 42984483 ps
CPU time 0.59 seconds
Started Dec 24 01:40:41 PM PST 23
Finished Dec 24 01:40:46 PM PST 23
Peak memory 195416 kb
Host smart-97ab53ab-1faa-4b8c-93ff-6ef9726c49ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201208036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2201208036
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.4221069722
Short name T492
Test name
Test status
Simulation time 13106164 ps
CPU time 0.59 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 194476 kb
Host smart-d3a42e68-1201-4f0c-95ad-46a851c809f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221069722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4221069722
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1662000298
Short name T1249
Test name
Test status
Simulation time 38152449 ps
CPU time 0.66 seconds
Started Dec 24 01:40:42 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 195588 kb
Host smart-2b976e66-a9f7-41f5-b994-450319747f22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662000298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1662000298
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2911344529
Short name T4
Test name
Test status
Simulation time 89931453 ps
CPU time 1.89 seconds
Started Dec 24 01:40:41 PM PST 23
Finished Dec 24 01:40:48 PM PST 23
Peak memory 199096 kb
Host smart-60d980a2-d1f5-417f-adb0-30714f0264de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911344529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2911344529
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.372465632
Short name T1251
Test name
Test status
Simulation time 65359150 ps
CPU time 0.65 seconds
Started Dec 24 01:39:52 PM PST 23
Finished Dec 24 01:39:54 PM PST 23
Peak memory 195548 kb
Host smart-8fa5783e-4232-41f0-8e73-4d10ae505ea4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372465632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.372465632
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4052943415
Short name T33
Test name
Test status
Simulation time 202542848 ps
CPU time 1.41 seconds
Started Dec 24 01:39:53 PM PST 23
Finished Dec 24 01:39:56 PM PST 23
Peak memory 197716 kb
Host smart-144d3629-7c54-46ac-a359-2eeafc4fe4cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052943415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4052943415
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2749333328
Short name T35
Test name
Test status
Simulation time 27234759 ps
CPU time 0.57 seconds
Started Dec 24 01:40:35 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 195540 kb
Host smart-d910968a-bfe6-4ccb-8553-ae970a009a9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749333328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2749333328
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3162614082
Short name T472
Test name
Test status
Simulation time 64173677 ps
CPU time 1 seconds
Started Dec 24 01:39:54 PM PST 23
Finished Dec 24 01:39:56 PM PST 23
Peak memory 200000 kb
Host smart-56819f2e-e334-4bc2-837a-72974832b7b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162614082 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3162614082
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3390239358
Short name T67
Test name
Test status
Simulation time 51462037 ps
CPU time 0.62 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195648 kb
Host smart-4ea6e902-3925-4208-b99b-45bd41120714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390239358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3390239358
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3093162101
Short name T47
Test name
Test status
Simulation time 23894251 ps
CPU time 0.65 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195700 kb
Host smart-5d58b89d-816b-4230-84d6-9a0c144669a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093162101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3093162101
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3110694080
Short name T501
Test name
Test status
Simulation time 375521430 ps
CPU time 2.05 seconds
Started Dec 24 01:39:40 PM PST 23
Finished Dec 24 01:39:47 PM PST 23
Peak memory 200060 kb
Host smart-b36a8dd1-b64c-4c0a-a6ae-bd0eb6f3bd31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110694080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3110694080
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1365640319
Short name T97
Test name
Test status
Simulation time 136105069 ps
CPU time 1.2 seconds
Started Dec 24 01:39:55 PM PST 23
Finished Dec 24 01:39:57 PM PST 23
Peak memory 199104 kb
Host smart-224d6dcf-03f9-4db4-bef4-283de0435b21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365640319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1365640319
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.429878314
Short name T74
Test name
Test status
Simulation time 43775671 ps
CPU time 0.53 seconds
Started Dec 24 01:40:46 PM PST 23
Finished Dec 24 01:40:51 PM PST 23
Peak memory 185020 kb
Host smart-7c904a9a-ef79-422f-86a1-13e6a37d63fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429878314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.429878314
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3605600655
Short name T1284
Test name
Test status
Simulation time 56138034 ps
CPU time 0.59 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:41 PM PST 23
Peak memory 185220 kb
Host smart-8b3b1104-5e41-459d-b379-1b446b47258f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605600655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3605600655
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2581250737
Short name T487
Test name
Test status
Simulation time 20076480 ps
CPU time 0.55 seconds
Started Dec 24 01:40:42 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 194400 kb
Host smart-5ea295ee-2647-4922-9097-2a01fca6933b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581250737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2581250737
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2717324425
Short name T500
Test name
Test status
Simulation time 13932084 ps
CPU time 0.57 seconds
Started Dec 24 01:40:44 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 185292 kb
Host smart-b49dcdd5-5155-4792-9116-e36db43a68b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717324425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2717324425
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.214533328
Short name T412
Test name
Test status
Simulation time 36479532 ps
CPU time 0.58 seconds
Started Dec 24 01:40:41 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 185124 kb
Host smart-83b2c989-06cb-4be0-8d35-dd2c27e29c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214533328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.214533328
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.131266592
Short name T482
Test name
Test status
Simulation time 15204775 ps
CPU time 0.58 seconds
Started Dec 24 01:40:47 PM PST 23
Finished Dec 24 01:40:52 PM PST 23
Peak memory 194260 kb
Host smart-a5621369-464e-4885-92af-669f82bacf78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131266592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.131266592
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1846988055
Short name T65
Test name
Test status
Simulation time 15938786 ps
CPU time 0.55 seconds
Started Dec 24 01:40:55 PM PST 23
Finished Dec 24 01:40:56 PM PST 23
Peak memory 194476 kb
Host smart-ea879cba-da8b-443d-80ba-810fba27dddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846988055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1846988055
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1937486310
Short name T1290
Test name
Test status
Simulation time 14924049 ps
CPU time 0.55 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:41 PM PST 23
Peak memory 185036 kb
Host smart-f424f59d-00ee-4822-a87a-986c30b86832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937486310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1937486310
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2287346411
Short name T1250
Test name
Test status
Simulation time 14088062 ps
CPU time 0.6 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:32 PM PST 23
Peak memory 184948 kb
Host smart-d74d746f-b24d-4681-a077-1a3cda2a7388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287346411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2287346411
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.96488785
Short name T1258
Test name
Test status
Simulation time 35782235 ps
CPU time 0.66 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:37 PM PST 23
Peak memory 195016 kb
Host smart-90a75f6e-fcb6-4826-8dfb-a6bff7d4ff70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96488785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.96488785
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.761933256
Short name T496
Test name
Test status
Simulation time 58459485 ps
CPU time 2.21 seconds
Started Dec 24 01:40:35 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 197708 kb
Host smart-56a21314-0ece-45d7-a2c0-e78aec9f5d7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761933256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.761933256
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1811307298
Short name T36
Test name
Test status
Simulation time 15177304 ps
CPU time 0.6 seconds
Started Dec 24 01:40:14 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195544 kb
Host smart-cee60a58-0efe-406e-a71f-8889c2b63f1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811307298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1811307298
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3079612583
Short name T490
Test name
Test status
Simulation time 94966578 ps
CPU time 0.88 seconds
Started Dec 24 01:40:42 PM PST 23
Finished Dec 24 01:40:48 PM PST 23
Peak memory 199744 kb
Host smart-1d5a200f-74f0-4a6e-a4a8-9ba728c63ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079612583 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3079612583
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.885475887
Short name T59
Test name
Test status
Simulation time 23546927 ps
CPU time 0.59 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 195556 kb
Host smart-24ebf3b0-c72a-411f-a6bf-357db96c5f44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885475887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.885475887
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3455594858
Short name T80
Test name
Test status
Simulation time 24293758 ps
CPU time 0.58 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:37 PM PST 23
Peak memory 194496 kb
Host smart-727b0ffe-f321-40ce-a29b-6749c804b207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455594858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3455594858
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2400385627
Short name T84
Test name
Test status
Simulation time 100600674 ps
CPU time 0.75 seconds
Started Dec 24 01:40:10 PM PST 23
Finished Dec 24 01:40:18 PM PST 23
Peak memory 197176 kb
Host smart-9853cc38-8c14-47d4-a27b-56ef91028124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400385627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2400385627
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3998489765
Short name T46
Test name
Test status
Simulation time 20865626 ps
CPU time 0.92 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 199752 kb
Host smart-1ef284c0-f314-4ba0-b3d9-a1dd3e73985e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998489765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3998489765
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3643721665
Short name T9
Test name
Test status
Simulation time 928902879 ps
CPU time 1.33 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 199288 kb
Host smart-ca6bc714-561e-4b4b-9297-3f298be01384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643721665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3643721665
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2587129369
Short name T493
Test name
Test status
Simulation time 25099216 ps
CPU time 0.58 seconds
Started Dec 24 01:40:56 PM PST 23
Finished Dec 24 01:40:58 PM PST 23
Peak memory 185104 kb
Host smart-a050c275-21b7-4a5e-8600-818274170a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587129369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2587129369
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2566561177
Short name T1265
Test name
Test status
Simulation time 45936319 ps
CPU time 0.6 seconds
Started Dec 24 01:41:09 PM PST 23
Finished Dec 24 01:41:10 PM PST 23
Peak memory 194372 kb
Host smart-e75060a1-6ff3-41f6-b080-cbe14f22f4fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566561177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2566561177
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3098764435
Short name T6
Test name
Test status
Simulation time 12566573 ps
CPU time 0.57 seconds
Started Dec 24 01:41:10 PM PST 23
Finished Dec 24 01:41:12 PM PST 23
Peak memory 194452 kb
Host smart-119c76a8-1b9d-48a8-b79e-d14621cf3e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098764435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3098764435
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3494214472
Short name T494
Test name
Test status
Simulation time 45493468 ps
CPU time 0.54 seconds
Started Dec 24 01:41:09 PM PST 23
Finished Dec 24 01:41:10 PM PST 23
Peak memory 185172 kb
Host smart-a3f38192-5f95-4e42-b50c-dade9a05fbfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494214472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3494214472
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4136162415
Short name T1244
Test name
Test status
Simulation time 61120454 ps
CPU time 0.55 seconds
Started Dec 24 01:40:53 PM PST 23
Finished Dec 24 01:40:55 PM PST 23
Peak memory 185104 kb
Host smart-c076e125-da0f-4b7f-8e15-795f789407c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136162415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4136162415
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1736503586
Short name T486
Test name
Test status
Simulation time 14211962 ps
CPU time 0.56 seconds
Started Dec 24 01:40:55 PM PST 23
Finished Dec 24 01:40:57 PM PST 23
Peak memory 194208 kb
Host smart-4a7135a6-0ab3-407a-a4dc-543f1aa51039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736503586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1736503586
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1752997824
Short name T1295
Test name
Test status
Simulation time 11759401 ps
CPU time 0.56 seconds
Started Dec 24 01:41:29 PM PST 23
Finished Dec 24 01:41:31 PM PST 23
Peak memory 185224 kb
Host smart-c26b0272-2cb5-4056-8e00-98f9496a484f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752997824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1752997824
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1478362593
Short name T474
Test name
Test status
Simulation time 12890110 ps
CPU time 0.59 seconds
Started Dec 24 01:40:59 PM PST 23
Finished Dec 24 01:41:00 PM PST 23
Peak memory 185232 kb
Host smart-59209542-f441-478a-a4e9-f809be120350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478362593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1478362593
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2347684929
Short name T1292
Test name
Test status
Simulation time 29529861 ps
CPU time 0.55 seconds
Started Dec 24 01:41:15 PM PST 23
Finished Dec 24 01:41:17 PM PST 23
Peak memory 194388 kb
Host smart-2a5f3852-dbea-4bee-9e7c-6c5b3fbbe732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347684929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2347684929
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1338385848
Short name T63
Test name
Test status
Simulation time 59906949 ps
CPU time 0.57 seconds
Started Dec 24 01:41:24 PM PST 23
Finished Dec 24 01:41:26 PM PST 23
Peak memory 185172 kb
Host smart-274d27a3-e64c-4735-afc2-598adf3833b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338385848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1338385848
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1650723458
Short name T83
Test name
Test status
Simulation time 20542344 ps
CPU time 0.66 seconds
Started Dec 24 01:40:35 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 195480 kb
Host smart-68c93414-8e5c-4f5f-9bc6-3b6287b4c2a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650723458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1650723458
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3560259794
Short name T1235
Test name
Test status
Simulation time 284767027 ps
CPU time 1.38 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:22 PM PST 23
Peak memory 198168 kb
Host smart-1b1e2ffc-2d32-4da9-9094-9c9b95d1ac95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560259794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3560259794
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2497275239
Short name T1252
Test name
Test status
Simulation time 30785584 ps
CPU time 0.59 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195532 kb
Host smart-e0f7bd5e-3fa9-4cd4-bba7-13a8292e2e35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497275239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2497275239
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1095733375
Short name T45
Test name
Test status
Simulation time 32441580 ps
CPU time 1.08 seconds
Started Dec 24 01:40:15 PM PST 23
Finished Dec 24 01:40:23 PM PST 23
Peak memory 200160 kb
Host smart-8aebb53c-37b2-48ea-a928-1ef726b95702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095733375 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1095733375
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.235766982
Short name T1247
Test name
Test status
Simulation time 12456072 ps
CPU time 0.57 seconds
Started Dec 24 01:40:15 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195464 kb
Host smart-0c401fa3-c742-4341-9c6f-008111cfca1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235766982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.235766982
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3513417079
Short name T5
Test name
Test status
Simulation time 13453458 ps
CPU time 0.56 seconds
Started Dec 24 01:40:10 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 185224 kb
Host smart-dc64c061-c031-4981-b0fe-eea63e2e6529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513417079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3513417079
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2910253214
Short name T115
Test name
Test status
Simulation time 23097918 ps
CPU time 0.68 seconds
Started Dec 24 01:40:32 PM PST 23
Finished Dec 24 01:40:33 PM PST 23
Peak memory 194968 kb
Host smart-97048f50-259b-45c0-8d8e-9c9f290a7930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910253214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2910253214
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1108723037
Short name T499
Test name
Test status
Simulation time 455358101 ps
CPU time 2.26 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:40:27 PM PST 23
Peak memory 200112 kb
Host smart-b47fce6a-5063-45a5-9504-fa47f7fbd6fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108723037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1108723037
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1400968983
Short name T410
Test name
Test status
Simulation time 858680337 ps
CPU time 0.94 seconds
Started Dec 24 01:40:08 PM PST 23
Finished Dec 24 01:40:11 PM PST 23
Peak memory 198812 kb
Host smart-68c42dbf-6a65-461b-8e79-566433323483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400968983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1400968983
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2868157108
Short name T1263
Test name
Test status
Simulation time 11180709 ps
CPU time 0.58 seconds
Started Dec 24 01:41:30 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 185160 kb
Host smart-eee2ba71-d0ce-48f5-8cc2-6841f7f7e093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868157108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2868157108
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1166652388
Short name T1237
Test name
Test status
Simulation time 15986789 ps
CPU time 0.6 seconds
Started Dec 24 01:41:31 PM PST 23
Finished Dec 24 01:41:33 PM PST 23
Peak memory 185216 kb
Host smart-daeeca3f-d2f9-4d85-8f9e-08c98ab8355a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166652388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1166652388
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.484988469
Short name T480
Test name
Test status
Simulation time 15778280 ps
CPU time 0.56 seconds
Started Dec 24 01:40:56 PM PST 23
Finished Dec 24 01:40:58 PM PST 23
Peak memory 185212 kb
Host smart-14d87b2d-7a28-478b-b1f0-a3d4242e6e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484988469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.484988469
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2402855532
Short name T66
Test name
Test status
Simulation time 39135262 ps
CPU time 0.54 seconds
Started Dec 24 01:41:24 PM PST 23
Finished Dec 24 01:41:25 PM PST 23
Peak memory 185248 kb
Host smart-bb5fb7ef-14ff-4c82-8d95-e31943ee0dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402855532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2402855532
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3395657211
Short name T1245
Test name
Test status
Simulation time 13032053 ps
CPU time 0.57 seconds
Started Dec 24 01:41:58 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 185180 kb
Host smart-d886c626-720f-4696-8800-d0a3e31273be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395657211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3395657211
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.575634987
Short name T1248
Test name
Test status
Simulation time 124379666 ps
CPU time 0.57 seconds
Started Dec 24 01:42:18 PM PST 23
Finished Dec 24 01:42:21 PM PST 23
Peak memory 194476 kb
Host smart-06aacda4-9ce6-43d8-9065-029c7e3adb13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575634987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.575634987
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1871067266
Short name T467
Test name
Test status
Simulation time 13651648 ps
CPU time 0.55 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 185148 kb
Host smart-0979a569-5802-409d-aa87-3822e116d3d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871067266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1871067266
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1875160064
Short name T471
Test name
Test status
Simulation time 13614665 ps
CPU time 0.57 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:01 PM PST 23
Peak memory 185228 kb
Host smart-f2fa74bc-eb34-4f96-9658-8705c2713ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875160064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1875160064
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1930219927
Short name T1285
Test name
Test status
Simulation time 44137023 ps
CPU time 0.59 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:18 PM PST 23
Peak memory 185244 kb
Host smart-64496227-9ebb-4434-bf72-26ad94e3db0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930219927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1930219927
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1367908635
Short name T38
Test name
Test status
Simulation time 61858969 ps
CPU time 0.57 seconds
Started Dec 24 01:41:58 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 185244 kb
Host smart-5cfbe8b8-6ae2-42ef-9359-68bc0d8b254c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367908635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1367908635
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.8067259
Short name T1241
Test name
Test status
Simulation time 48837087 ps
CPU time 0.76 seconds
Started Dec 24 01:40:10 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 198880 kb
Host smart-a356eccf-6c71-4a00-99fa-69d1ed4638f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8067259 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.8067259
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2274800679
Short name T1269
Test name
Test status
Simulation time 14347809 ps
CPU time 0.57 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:37 PM PST 23
Peak memory 195572 kb
Host smart-b89a440f-4cee-4030-8846-7ca0fd60c072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274800679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2274800679
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3483987497
Short name T1240
Test name
Test status
Simulation time 16924618 ps
CPU time 0.57 seconds
Started Dec 24 01:40:10 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 185052 kb
Host smart-36483713-96a3-451a-96d9-df7d19aa04b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483987497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3483987497
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3335450886
Short name T114
Test name
Test status
Simulation time 306513594 ps
CPU time 0.8 seconds
Started Dec 24 01:40:15 PM PST 23
Finished Dec 24 01:40:24 PM PST 23
Peak memory 197132 kb
Host smart-6d48eb1a-2261-4079-b045-40cdbd9fdcb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335450886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3335450886
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.10352299
Short name T3
Test name
Test status
Simulation time 101189831 ps
CPU time 1.54 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 200140 kb
Host smart-c3c83d1f-0ed7-4dd4-8f25-0dde996868ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10352299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.10352299
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2769736004
Short name T1261
Test name
Test status
Simulation time 135156223 ps
CPU time 0.91 seconds
Started Dec 24 01:40:33 PM PST 23
Finished Dec 24 01:40:35 PM PST 23
Peak memory 198840 kb
Host smart-da7c1599-fe8c-4753-a8c9-de111fff84fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769736004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2769736004
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2466919974
Short name T1262
Test name
Test status
Simulation time 30319494 ps
CPU time 0.95 seconds
Started Dec 24 01:40:39 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 199924 kb
Host smart-b7282c56-425f-4189-a89a-9f9955e953c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466919974 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2466919974
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1028314616
Short name T56
Test name
Test status
Simulation time 111066354 ps
CPU time 0.57 seconds
Started Dec 24 01:40:15 PM PST 23
Finished Dec 24 01:40:22 PM PST 23
Peak memory 195568 kb
Host smart-abcb668c-34e1-4046-af3f-3020306065e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028314616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1028314616
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2032106223
Short name T1277
Test name
Test status
Simulation time 44881878 ps
CPU time 0.56 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 194268 kb
Host smart-a8710d17-5e7b-4702-9c46-07033cc1292a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032106223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2032106223
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2763374781
Short name T118
Test name
Test status
Simulation time 179884644 ps
CPU time 0.69 seconds
Started Dec 24 01:40:42 PM PST 23
Finished Dec 24 01:40:48 PM PST 23
Peak memory 195708 kb
Host smart-e80cb44e-177a-44bf-b195-e8da8cd7acba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763374781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2763374781
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1409142608
Short name T1294
Test name
Test status
Simulation time 185214462 ps
CPU time 1.07 seconds
Started Dec 24 01:40:32 PM PST 23
Finished Dec 24 01:40:34 PM PST 23
Peak memory 199972 kb
Host smart-ef5c4b65-c30d-45ef-ab29-ab7106cafb04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409142608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1409142608
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3973250229
Short name T43
Test name
Test status
Simulation time 41461916 ps
CPU time 0.92 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:37 PM PST 23
Peak memory 199088 kb
Host smart-e3032811-d5cd-45d1-a2cc-4e6324366efc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973250229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3973250229
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2103455867
Short name T1293
Test name
Test status
Simulation time 33750583 ps
CPU time 0.7 seconds
Started Dec 24 01:40:14 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 198668 kb
Host smart-2e0f1a70-1868-499e-b52f-96389857a006
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103455867 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2103455867
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3844611316
Short name T1264
Test name
Test status
Simulation time 53181339 ps
CPU time 0.57 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195572 kb
Host smart-c5eb5ba5-1986-4a48-b52b-f075f2f3fb3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844611316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3844611316
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2886409092
Short name T1253
Test name
Test status
Simulation time 63737166 ps
CPU time 0.56 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 194364 kb
Host smart-c892028e-bf2e-413e-92c4-404642861746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886409092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2886409092
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2040570914
Short name T61
Test name
Test status
Simulation time 53464241 ps
CPU time 0.72 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 195856 kb
Host smart-0d8e960a-b5d8-4f54-a5c5-5fa4467a2dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040570914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2040570914
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.920979826
Short name T498
Test name
Test status
Simulation time 239748658 ps
CPU time 1.95 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:40:27 PM PST 23
Peak memory 200060 kb
Host smart-6c480944-7ffb-42d9-a96e-7b45b73179a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920979826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.920979826
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1851704573
Short name T76
Test name
Test status
Simulation time 23484522 ps
CPU time 0.79 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:37 PM PST 23
Peak memory 199068 kb
Host smart-a2d522a1-41a8-4919-8f6c-c7027c295129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851704573 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1851704573
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1574390689
Short name T71
Test name
Test status
Simulation time 47183700 ps
CPU time 0.59 seconds
Started Dec 24 01:40:10 PM PST 23
Finished Dec 24 01:40:19 PM PST 23
Peak memory 195492 kb
Host smart-7c4daadd-a321-4f63-ade0-726033a7378c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574390689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1574390689
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.306314039
Short name T481
Test name
Test status
Simulation time 27645877 ps
CPU time 0.56 seconds
Started Dec 24 01:40:35 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 185128 kb
Host smart-6bec7fe1-0a43-47d6-9576-508811d6cb07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306314039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.306314039
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1994531171
Short name T1268
Test name
Test status
Simulation time 23441088 ps
CPU time 0.64 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 195604 kb
Host smart-cd56edb8-ad5c-41bc-9a1d-c8afac49db86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994531171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1994531171
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1580278885
Short name T483
Test name
Test status
Simulation time 38456755 ps
CPU time 1.14 seconds
Started Dec 24 01:40:13 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 200124 kb
Host smart-6b576fea-e3c4-47c0-a5e2-9561a5b7fc46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580278885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1580278885
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.918489698
Short name T1270
Test name
Test status
Simulation time 174264873 ps
CPU time 0.98 seconds
Started Dec 24 01:40:22 PM PST 23
Finished Dec 24 01:40:29 PM PST 23
Peak memory 199044 kb
Host smart-a61db80d-fa3f-44e1-ba16-d34b692ce538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918489698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.918489698
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.930730213
Short name T62
Test name
Test status
Simulation time 47917691 ps
CPU time 0.65 seconds
Started Dec 24 01:40:12 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 196440 kb
Host smart-c28a604a-9ae2-4a6c-8d1e-d88e05764939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930730213 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.930730213
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2042800814
Short name T75
Test name
Test status
Simulation time 19494400 ps
CPU time 0.57 seconds
Started Dec 24 01:40:34 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 195548 kb
Host smart-b1861650-c588-4892-ad06-1f70f0193b00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042800814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2042800814
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.697734175
Short name T488
Test name
Test status
Simulation time 62829093 ps
CPU time 0.54 seconds
Started Dec 24 01:40:33 PM PST 23
Finished Dec 24 01:40:35 PM PST 23
Peak memory 185220 kb
Host smart-b1db4d49-1384-4969-9006-1f3e7479325b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697734175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.697734175
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.873259642
Short name T1271
Test name
Test status
Simulation time 76210877 ps
CPU time 0.71 seconds
Started Dec 24 01:40:10 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 196908 kb
Host smart-8aa99f8a-3f90-4b47-a4c6-7c2fb976ae20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873259642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.873259642
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.471722149
Short name T8
Test name
Test status
Simulation time 56521205 ps
CPU time 0.87 seconds
Started Dec 24 01:40:16 PM PST 23
Finished Dec 24 01:40:26 PM PST 23
Peak memory 199840 kb
Host smart-2c26ef55-d346-43d9-be2c-0eb70d3e91e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471722149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.471722149
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3716337854
Short name T1
Test name
Test status
Simulation time 135787029 ps
CPU time 0.95 seconds
Started Dec 24 01:40:10 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 199076 kb
Host smart-1afe1dcc-83e3-4dc5-837e-1e0c8d4c2c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716337854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3716337854
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.207877193
Short name T906
Test name
Test status
Simulation time 20186748030 ps
CPU time 13.53 seconds
Started Dec 24 01:31:53 PM PST 23
Finished Dec 24 01:32:07 PM PST 23
Peak memory 200188 kb
Host smart-09e1645d-e49e-4e77-a378-acfd20e2e18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207877193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.207877193
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1392503633
Short name T795
Test name
Test status
Simulation time 109563950224 ps
CPU time 33.24 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 01:32:26 PM PST 23
Peak memory 200236 kb
Host smart-15335a5d-38b8-4c02-bb81-29bfe5d4c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392503633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1392503633
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2981822480
Short name T1010
Test name
Test status
Simulation time 17021177298 ps
CPU time 15.42 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 01:32:08 PM PST 23
Peak memory 200240 kb
Host smart-c3672a5a-709c-4bb0-9ab0-248f99fddddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981822480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2981822480
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3610868557
Short name T124
Test name
Test status
Simulation time 104327777457 ps
CPU time 80.95 seconds
Started Dec 24 01:31:53 PM PST 23
Finished Dec 24 01:33:15 PM PST 23
Peak memory 199996 kb
Host smart-f61e465f-41a8-438e-b08f-0e536de4a2c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610868557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3610868557
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.15337551
Short name T706
Test name
Test status
Simulation time 132636757479 ps
CPU time 873.46 seconds
Started Dec 24 01:31:57 PM PST 23
Finished Dec 24 01:46:31 PM PST 23
Peak memory 200272 kb
Host smart-36544249-b61e-476d-b768-2c9dc6b1dc5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15337551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.15337551
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4026894614
Short name T767
Test name
Test status
Simulation time 4062343680 ps
CPU time 2.63 seconds
Started Dec 24 01:31:55 PM PST 23
Finished Dec 24 01:31:58 PM PST 23
Peak memory 198336 kb
Host smart-5d37281c-9ef6-4cd9-bc65-3998b166e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026894614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4026894614
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2163829008
Short name T17
Test name
Test status
Simulation time 112531863281 ps
CPU time 41.99 seconds
Started Dec 24 01:32:11 PM PST 23
Finished Dec 24 01:32:55 PM PST 23
Peak memory 200460 kb
Host smart-dbe72bb6-ee8d-4b6b-9abb-aaa40d3b8d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163829008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2163829008
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.933218431
Short name T198
Test name
Test status
Simulation time 23018112163 ps
CPU time 645.28 seconds
Started Dec 24 01:32:11 PM PST 23
Finished Dec 24 01:42:57 PM PST 23
Peak memory 200288 kb
Host smart-f388ec98-2a31-4887-b344-1555a6359598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933218431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.933218431
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3409863042
Short name T568
Test name
Test status
Simulation time 2034966924 ps
CPU time 9.02 seconds
Started Dec 24 01:31:56 PM PST 23
Finished Dec 24 01:32:06 PM PST 23
Peak memory 197916 kb
Host smart-367cd8d2-6720-4d3f-9320-d962d157a44b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409863042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3409863042
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.330383440
Short name T1130
Test name
Test status
Simulation time 149379930962 ps
CPU time 73.77 seconds
Started Dec 24 01:32:10 PM PST 23
Finished Dec 24 01:33:25 PM PST 23
Peak memory 200164 kb
Host smart-6317e8dc-0a39-4e72-a20b-8666d5d5100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330383440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.330383440
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3538927098
Short name T442
Test name
Test status
Simulation time 1632986586 ps
CPU time 1.3 seconds
Started Dec 24 01:31:57 PM PST 23
Finished Dec 24 01:31:59 PM PST 23
Peak memory 195624 kb
Host smart-1f3dbe48-11a6-4cab-9d24-70d4e3a4a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538927098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3538927098
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.763313182
Short name T92
Test name
Test status
Simulation time 175236884 ps
CPU time 0.76 seconds
Started Dec 24 01:32:11 PM PST 23
Finished Dec 24 01:32:14 PM PST 23
Peak memory 217636 kb
Host smart-5b0bb07b-a336-426c-9217-dc9c87cfb3fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763313182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.763313182
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.572985569
Short name T702
Test name
Test status
Simulation time 284398282 ps
CPU time 1.82 seconds
Started Dec 24 01:31:53 PM PST 23
Finished Dec 24 01:31:55 PM PST 23
Peak memory 198020 kb
Host smart-ddde4307-4301-4964-bc10-cbdc1edac0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572985569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.572985569
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3330750
Short name T1008
Test name
Test status
Simulation time 76700963027 ps
CPU time 700.89 seconds
Started Dec 24 01:32:13 PM PST 23
Finished Dec 24 01:43:55 PM PST 23
Peak memory 216612 kb
Host smart-46430928-5024-497e-9d84-6aea6701b969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330750 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3330750
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1424335099
Short name T614
Test name
Test status
Simulation time 589676537 ps
CPU time 1.38 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 01:31:55 PM PST 23
Peak memory 198148 kb
Host smart-75775823-a621-4148-8a61-8ea473d631c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424335099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1424335099
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3484109740
Short name T1024
Test name
Test status
Simulation time 29231240538 ps
CPU time 25.73 seconds
Started Dec 24 01:31:52 PM PST 23
Finished Dec 24 01:32:19 PM PST 23
Peak memory 200120 kb
Host smart-ee9a5e12-b8de-434d-8561-9bbf7a60b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484109740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3484109740
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.579082129
Short name T831
Test name
Test status
Simulation time 14019937 ps
CPU time 0.56 seconds
Started Dec 24 01:31:59 PM PST 23
Finished Dec 24 01:32:01 PM PST 23
Peak memory 195608 kb
Host smart-1def4a51-7b33-4e8c-8e73-c3677ac08e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579082129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.579082129
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2023666628
Short name T356
Test name
Test status
Simulation time 34275586184 ps
CPU time 19.54 seconds
Started Dec 24 01:32:11 PM PST 23
Finished Dec 24 01:32:32 PM PST 23
Peak memory 200180 kb
Host smart-2e5155cc-0d84-4c92-a511-9b193608e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023666628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2023666628
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1019998412
Short name T1065
Test name
Test status
Simulation time 138074693534 ps
CPU time 221.07 seconds
Started Dec 24 01:31:55 PM PST 23
Finished Dec 24 01:35:37 PM PST 23
Peak memory 200096 kb
Host smart-80bdac0d-8e90-4265-893c-ad9c75c3cf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019998412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1019998412
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.684510527
Short name T653
Test name
Test status
Simulation time 65427747955 ps
CPU time 99.7 seconds
Started Dec 24 01:31:54 PM PST 23
Finished Dec 24 01:33:35 PM PST 23
Peak memory 199900 kb
Host smart-b81b18f9-bfc0-4d75-8d03-0a683ac1dad7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684510527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.684510527
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3148770957
Short name T430
Test name
Test status
Simulation time 74475561796 ps
CPU time 177.4 seconds
Started Dec 24 01:31:59 PM PST 23
Finished Dec 24 01:34:58 PM PST 23
Peak memory 200164 kb
Host smart-d94bdc64-5549-462b-a765-c0d8839e5738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148770957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3148770957
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3143714719
Short name T693
Test name
Test status
Simulation time 5163859722 ps
CPU time 14.91 seconds
Started Dec 24 01:31:59 PM PST 23
Finished Dec 24 01:32:15 PM PST 23
Peak memory 199080 kb
Host smart-b3a16e52-f2e4-458e-975e-c2298ba866a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143714719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3143714719
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1404564694
Short name T559
Test name
Test status
Simulation time 69498613848 ps
CPU time 117.37 seconds
Started Dec 24 01:31:56 PM PST 23
Finished Dec 24 01:33:55 PM PST 23
Peak memory 208720 kb
Host smart-28546e42-dd33-4aff-9246-57b139a895be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404564694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1404564694
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3197378187
Short name T108
Test name
Test status
Simulation time 10381788489 ps
CPU time 153.53 seconds
Started Dec 24 01:31:55 PM PST 23
Finished Dec 24 01:34:30 PM PST 23
Peak memory 200144 kb
Host smart-c1b61c7e-e456-4b3f-af09-4c691f9f392a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197378187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3197378187
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2477987533
Short name T1110
Test name
Test status
Simulation time 3967279612 ps
CPU time 10.49 seconds
Started Dec 24 01:31:59 PM PST 23
Finished Dec 24 01:32:11 PM PST 23
Peak memory 198436 kb
Host smart-2047be80-789e-4136-9e0e-429796a097f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477987533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2477987533
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.744759778
Short name T1216
Test name
Test status
Simulation time 81751877456 ps
CPU time 23.49 seconds
Started Dec 24 01:31:59 PM PST 23
Finished Dec 24 01:32:23 PM PST 23
Peak memory 200012 kb
Host smart-7ec29b25-57d5-45b6-82f7-668c758a705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744759778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.744759778
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.515852524
Short name T942
Test name
Test status
Simulation time 614168747 ps
CPU time 1.72 seconds
Started Dec 24 01:31:54 PM PST 23
Finished Dec 24 01:31:57 PM PST 23
Peak memory 195752 kb
Host smart-a5d3ac0f-a0f4-4dbe-8e69-a596356b67a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515852524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.515852524
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.2915140996
Short name T957
Test name
Test status
Simulation time 501042450 ps
CPU time 3.09 seconds
Started Dec 24 01:32:11 PM PST 23
Finished Dec 24 01:32:16 PM PST 23
Peak memory 199088 kb
Host smart-016e45c2-f6a9-4215-af3e-7fd5a2754857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915140996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2915140996
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.4183693295
Short name T1212
Test name
Test status
Simulation time 9385411620 ps
CPU time 21.61 seconds
Started Dec 24 01:31:56 PM PST 23
Finished Dec 24 01:32:18 PM PST 23
Peak memory 199884 kb
Host smart-fdd75a66-5006-4729-8732-7d02e1e3129d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183693295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4183693295
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2461404772
Short name T979
Test name
Test status
Simulation time 71534991621 ps
CPU time 467.06 seconds
Started Dec 24 01:31:56 PM PST 23
Finished Dec 24 01:39:43 PM PST 23
Peak memory 210796 kb
Host smart-395e2823-809c-485d-b9d6-7232d4ebad74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461404772 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2461404772
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.145289854
Short name T429
Test name
Test status
Simulation time 535195386 ps
CPU time 1.17 seconds
Started Dec 24 01:31:58 PM PST 23
Finished Dec 24 01:32:00 PM PST 23
Peak memory 196828 kb
Host smart-898a7c91-7d6f-415b-ae90-6ca4066ff1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145289854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.145289854
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1596378116
Short name T1146
Test name
Test status
Simulation time 272844633 ps
CPU time 0.79 seconds
Started Dec 24 01:32:12 PM PST 23
Finished Dec 24 01:32:14 PM PST 23
Peak memory 196100 kb
Host smart-775c82c2-e3ef-4bd9-a50c-31de2e679c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596378116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1596378116
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3276306512
Short name T504
Test name
Test status
Simulation time 43228778 ps
CPU time 0.55 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:33:33 PM PST 23
Peak memory 195648 kb
Host smart-676c3d64-5de2-4a9d-83af-fa812462898f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276306512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3276306512
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3723177708
Short name T815
Test name
Test status
Simulation time 123157800010 ps
CPU time 285 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:38:18 PM PST 23
Peak memory 200144 kb
Host smart-90b5b6aa-b64f-4670-9a7d-6ffd8f50a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723177708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3723177708
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3511856355
Short name T558
Test name
Test status
Simulation time 33855838249 ps
CPU time 56.46 seconds
Started Dec 24 01:33:15 PM PST 23
Finished Dec 24 01:34:12 PM PST 23
Peak memory 199540 kb
Host smart-c060c5a1-a705-476b-a4af-1b7c3d70c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511856355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3511856355
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1032721273
Short name T245
Test name
Test status
Simulation time 74137140468 ps
CPU time 119.37 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:35:36 PM PST 23
Peak memory 200244 kb
Host smart-1d6d96a2-f37e-4240-874a-c2568aa7570e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032721273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1032721273
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2713709304
Short name T958
Test name
Test status
Simulation time 48519739391 ps
CPU time 212.11 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:37:12 PM PST 23
Peak memory 200136 kb
Host smart-361832a3-8361-473b-8581-f681c48dc7f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713709304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2713709304
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1161897769
Short name T1189
Test name
Test status
Simulation time 1679398310 ps
CPU time 0.96 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:33:38 PM PST 23
Peak memory 195692 kb
Host smart-19897776-a301-4aca-b667-bc63a34a2f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161897769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1161897769
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.186061414
Short name T1187
Test name
Test status
Simulation time 59794122291 ps
CPU time 71.24 seconds
Started Dec 24 01:33:28 PM PST 23
Finished Dec 24 01:34:41 PM PST 23
Peak memory 198788 kb
Host smart-b421fd8c-5996-43d9-8ee8-e5be2ea162a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186061414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.186061414
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2028162979
Short name T554
Test name
Test status
Simulation time 16503708324 ps
CPU time 146.54 seconds
Started Dec 24 01:33:30 PM PST 23
Finished Dec 24 01:35:58 PM PST 23
Peak memory 200148 kb
Host smart-3e37d8c9-30ee-4c32-bdbb-8f4a4e302935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028162979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2028162979
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.257234935
Short name T1001
Test name
Test status
Simulation time 2316781627 ps
CPU time 16.14 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:33:52 PM PST 23
Peak memory 198640 kb
Host smart-b1577a72-055e-4033-bee0-b68b23610235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257234935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.257234935
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2825665583
Short name T872
Test name
Test status
Simulation time 66203419921 ps
CPU time 53.82 seconds
Started Dec 24 01:33:37 PM PST 23
Finished Dec 24 01:34:32 PM PST 23
Peak memory 200272 kb
Host smart-24da8157-098a-460d-a461-a3f335a447ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825665583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2825665583
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.267352379
Short name T695
Test name
Test status
Simulation time 6693459847 ps
CPU time 12.16 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:33:49 PM PST 23
Peak memory 195812 kb
Host smart-bddaf39f-5c5c-4ebc-95b9-9572030bb36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267352379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.267352379
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3676073013
Short name T621
Test name
Test status
Simulation time 755830938 ps
CPU time 1.14 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:33:40 PM PST 23
Peak memory 197984 kb
Host smart-2e944e6a-3352-47e8-989f-962843fe61d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676073013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3676073013
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1674251057
Short name T579
Test name
Test status
Simulation time 310712998773 ps
CPU time 365.08 seconds
Started Dec 24 01:33:34 PM PST 23
Finished Dec 24 01:39:40 PM PST 23
Peak memory 208704 kb
Host smart-02994135-f0b4-4d91-a548-3e1a0e82e41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674251057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1674251057
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2677017952
Short name T456
Test name
Test status
Simulation time 24243072072 ps
CPU time 208.81 seconds
Started Dec 24 01:33:34 PM PST 23
Finished Dec 24 01:37:04 PM PST 23
Peak memory 215732 kb
Host smart-2c97752c-f05b-4c8c-a7ff-a61ab15d5479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677017952 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2677017952
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4176196191
Short name T1015
Test name
Test status
Simulation time 1023152755 ps
CPU time 1.29 seconds
Started Dec 24 01:33:37 PM PST 23
Finished Dec 24 01:33:40 PM PST 23
Peak memory 198344 kb
Host smart-1789af41-3f12-476e-8ba2-13abe9b0e09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176196191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4176196191
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3026273464
Short name T762
Test name
Test status
Simulation time 118212418021 ps
CPU time 47.6 seconds
Started Dec 24 01:38:35 PM PST 23
Finished Dec 24 01:39:24 PM PST 23
Peak memory 200244 kb
Host smart-dac002b4-61eb-4362-a7c0-0f41aebc1051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026273464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3026273464
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3029317777
Short name T222
Test name
Test status
Simulation time 94120740189 ps
CPU time 77.23 seconds
Started Dec 24 01:38:33 PM PST 23
Finished Dec 24 01:39:51 PM PST 23
Peak memory 200188 kb
Host smart-0355f87d-241e-4819-a65a-b0c696c0f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029317777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3029317777
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.916169542
Short name T385
Test name
Test status
Simulation time 38259297793 ps
CPU time 36.98 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:38:59 PM PST 23
Peak memory 200108 kb
Host smart-cfae7d6f-795a-4ed5-b206-d7c342a48b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916169542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.916169542
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.4217653028
Short name T249
Test name
Test status
Simulation time 201734536715 ps
CPU time 90.96 seconds
Started Dec 24 01:38:37 PM PST 23
Finished Dec 24 01:40:09 PM PST 23
Peak memory 200168 kb
Host smart-4362dc85-d442-48bd-8362-8937354ee2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217653028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.4217653028
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3528828267
Short name T159
Test name
Test status
Simulation time 31851985872 ps
CPU time 51.26 seconds
Started Dec 24 01:38:19 PM PST 23
Finished Dec 24 01:39:12 PM PST 23
Peak memory 199476 kb
Host smart-eb58fe62-85b1-4901-986c-d122b81e3759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528828267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3528828267
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2418719999
Short name T157
Test name
Test status
Simulation time 43541779758 ps
CPU time 55.64 seconds
Started Dec 24 01:38:31 PM PST 23
Finished Dec 24 01:39:27 PM PST 23
Peak memory 200144 kb
Host smart-9e30fbe3-a39e-4daa-a0f5-e5a8fadb46cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418719999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2418719999
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1838267675
Short name T137
Test name
Test status
Simulation time 24703721759 ps
CPU time 11.1 seconds
Started Dec 24 01:38:48 PM PST 23
Finished Dec 24 01:39:00 PM PST 23
Peak memory 200088 kb
Host smart-51c5f85e-8a14-401b-bc48-2e56dffa952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838267675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1838267675
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4114780824
Short name T1193
Test name
Test status
Simulation time 15400648 ps
CPU time 0.56 seconds
Started Dec 24 01:33:37 PM PST 23
Finished Dec 24 01:33:39 PM PST 23
Peak memory 195572 kb
Host smart-a9d78f4e-d8a9-4ce9-a298-c4f74211d04b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114780824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4114780824
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2759491321
Short name T190
Test name
Test status
Simulation time 133924265065 ps
CPU time 182.44 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:36:38 PM PST 23
Peak memory 200292 kb
Host smart-711bf532-c223-4436-8546-c257733c935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759491321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2759491321
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1408307492
Short name T1098
Test name
Test status
Simulation time 165381163068 ps
CPU time 85.5 seconds
Started Dec 24 01:33:40 PM PST 23
Finished Dec 24 01:35:07 PM PST 23
Peak memory 200200 kb
Host smart-73eb04f7-c988-4122-956d-44dfdfbcb021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408307492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1408307492
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2153950136
Short name T1077
Test name
Test status
Simulation time 47824857212 ps
CPU time 69.54 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:34:42 PM PST 23
Peak memory 200184 kb
Host smart-9bc100d9-59c9-4d0d-8519-c2f439a48fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153950136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2153950136
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1835898911
Short name T459
Test name
Test status
Simulation time 358727451710 ps
CPU time 273.98 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:40:15 PM PST 23
Peak memory 198688 kb
Host smart-cd111fdf-59d0-4f5d-af1e-5a821ef8e464
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835898911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1835898911
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1072514573
Short name T602
Test name
Test status
Simulation time 146787367054 ps
CPU time 416.02 seconds
Started Dec 24 01:33:29 PM PST 23
Finished Dec 24 01:40:27 PM PST 23
Peak memory 200260 kb
Host smart-efffe6c8-409f-40a7-bc2d-367ac3e622c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072514573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1072514573
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2653976416
Short name T462
Test name
Test status
Simulation time 6605689464 ps
CPU time 9.65 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:33:49 PM PST 23
Peak memory 198464 kb
Host smart-c4cfd1e5-21ac-45b0-8ac7-fe86da7aebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653976416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2653976416
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3043282606
Short name T821
Test name
Test status
Simulation time 159531013380 ps
CPU time 56.31 seconds
Started Dec 24 01:33:33 PM PST 23
Finished Dec 24 01:34:31 PM PST 23
Peak memory 198944 kb
Host smart-54514bf9-8304-417e-92b5-b81ae3563b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043282606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3043282606
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.431905764
Short name T723
Test name
Test status
Simulation time 28225935167 ps
CPU time 382.17 seconds
Started Dec 24 01:33:34 PM PST 23
Finished Dec 24 01:39:58 PM PST 23
Peak memory 200100 kb
Host smart-6c1b22f0-9429-4853-9b15-2aef6f291a7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431905764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.431905764
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3596232346
Short name T1118
Test name
Test status
Simulation time 2767506146 ps
CPU time 5.18 seconds
Started Dec 24 01:33:36 PM PST 23
Finished Dec 24 01:33:42 PM PST 23
Peak memory 198500 kb
Host smart-0aae1610-89e8-4d81-8ed7-d032a4b4f6b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596232346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3596232346
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.7572213
Short name T699
Test name
Test status
Simulation time 149096874074 ps
CPU time 59.08 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:34:35 PM PST 23
Peak memory 199304 kb
Host smart-e48241ae-b05c-4d7a-8432-5420347bd0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7572213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.7572213
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3287493844
Short name T904
Test name
Test status
Simulation time 1435745572 ps
CPU time 1.15 seconds
Started Dec 24 01:33:41 PM PST 23
Finished Dec 24 01:33:43 PM PST 23
Peak memory 195948 kb
Host smart-b24d5591-2f17-49d8-ba61-480111ce86de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287493844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3287493844
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2252449690
Short name T1023
Test name
Test status
Simulation time 958108562 ps
CPU time 2.05 seconds
Started Dec 24 01:33:32 PM PST 23
Finished Dec 24 01:33:36 PM PST 23
Peak memory 198676 kb
Host smart-a63290ba-5008-49d6-a569-3293a9c22a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252449690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2252449690
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.832159623
Short name T753
Test name
Test status
Simulation time 58157232077 ps
CPU time 90.98 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:37:12 PM PST 23
Peak memory 199660 kb
Host smart-fa55038e-cef8-4733-af77-84781499e12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832159623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.832159623
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.80834958
Short name T1231
Test name
Test status
Simulation time 1058655877 ps
CPU time 1.85 seconds
Started Dec 24 01:33:33 PM PST 23
Finished Dec 24 01:33:36 PM PST 23
Peak memory 199344 kb
Host smart-2a8e212f-c4c8-4571-9830-7eeb8ca046a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80834958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.80834958
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3054338134
Short name T566
Test name
Test status
Simulation time 41313492392 ps
CPU time 23.26 seconds
Started Dec 24 01:33:40 PM PST 23
Finished Dec 24 01:34:04 PM PST 23
Peak memory 200164 kb
Host smart-c1eb3fb5-8262-45a1-8e48-ab0967b7dede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054338134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3054338134
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3698596510
Short name T888
Test name
Test status
Simulation time 316699454727 ps
CPU time 51.33 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:39:25 PM PST 23
Peak memory 200208 kb
Host smart-8550b4dc-f729-4999-852c-f61866af2266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698596510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3698596510
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2505009266
Short name T638
Test name
Test status
Simulation time 34936029593 ps
CPU time 53.29 seconds
Started Dec 24 01:38:47 PM PST 23
Finished Dec 24 01:39:41 PM PST 23
Peak memory 200284 kb
Host smart-67939e0f-0ae5-4d92-a5bc-f7a578539202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505009266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2505009266
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2604405582
Short name T588
Test name
Test status
Simulation time 82070501157 ps
CPU time 66.94 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:39:40 PM PST 23
Peak memory 199980 kb
Host smart-d2a17f2e-8604-469f-bc4e-e3d5933b28c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604405582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2604405582
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1359753764
Short name T237
Test name
Test status
Simulation time 41506515520 ps
CPU time 62.09 seconds
Started Dec 24 01:38:33 PM PST 23
Finished Dec 24 01:39:36 PM PST 23
Peak memory 200204 kb
Host smart-be85fc90-cfa8-44ab-a401-c0de153a0619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359753764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1359753764
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3982000757
Short name T1124
Test name
Test status
Simulation time 52764757657 ps
CPU time 42.76 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:38 PM PST 23
Peak memory 200172 kb
Host smart-0829687a-cd3e-45b5-8f25-346f11c6f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982000757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3982000757
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4083408672
Short name T105
Test name
Test status
Simulation time 25949625598 ps
CPU time 38.52 seconds
Started Dec 24 01:38:47 PM PST 23
Finished Dec 24 01:39:26 PM PST 23
Peak memory 200208 kb
Host smart-01365dc5-f6d3-4519-a83e-f708c76a812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083408672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4083408672
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3382691595
Short name T136
Test name
Test status
Simulation time 99287209294 ps
CPU time 161.67 seconds
Started Dec 24 01:38:33 PM PST 23
Finished Dec 24 01:41:16 PM PST 23
Peak memory 200252 kb
Host smart-79bb1fdb-4ae9-4c13-bdd3-040933a6ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382691595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3382691595
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2553500098
Short name T1185
Test name
Test status
Simulation time 56770431126 ps
CPU time 26.65 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:39:16 PM PST 23
Peak memory 200008 kb
Host smart-c8bc0a3c-8853-414d-968b-59815349a668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553500098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2553500098
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3650121445
Short name T608
Test name
Test status
Simulation time 23284717 ps
CPU time 0.54 seconds
Started Dec 24 01:33:40 PM PST 23
Finished Dec 24 01:33:42 PM PST 23
Peak memory 194660 kb
Host smart-8c912a9e-2c09-4842-9705-71f799f5d68d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650121445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3650121445
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2062650978
Short name T272
Test name
Test status
Simulation time 77203546009 ps
CPU time 125.12 seconds
Started Dec 24 01:33:43 PM PST 23
Finished Dec 24 01:35:50 PM PST 23
Peak memory 200232 kb
Host smart-d1cfe580-6ceb-4c27-8d18-2bfd8cc1356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062650978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2062650978
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.700514136
Short name T427
Test name
Test status
Simulation time 98898845291 ps
CPU time 169.98 seconds
Started Dec 24 01:33:36 PM PST 23
Finished Dec 24 01:36:28 PM PST 23
Peak memory 200244 kb
Host smart-c53fb185-24b1-4c06-96ee-6dccad75d957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700514136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.700514136
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1732189396
Short name T1178
Test name
Test status
Simulation time 116909363222 ps
CPU time 33.32 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:34:13 PM PST 23
Peak memory 198704 kb
Host smart-14647b2b-0226-405b-ac7a-06cdec49469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732189396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1732189396
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1001910440
Short name T649
Test name
Test status
Simulation time 97940194905 ps
CPU time 102.79 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:35:20 PM PST 23
Peak memory 200220 kb
Host smart-d596e0f5-3ae0-41e8-b4b7-6352a5aa045c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001910440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1001910440
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3732449549
Short name T864
Test name
Test status
Simulation time 39900835934 ps
CPU time 171.73 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:36:32 PM PST 23
Peak memory 200160 kb
Host smart-96bb72af-fc82-4f58-ad54-022218061781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732449549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3732449549
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3639946937
Short name T572
Test name
Test status
Simulation time 4287392423 ps
CPU time 8.89 seconds
Started Dec 24 01:33:47 PM PST 23
Finished Dec 24 01:33:57 PM PST 23
Peak memory 198820 kb
Host smart-30a265db-78f2-408a-97f7-1d1e4bac9f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639946937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3639946937
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2052726277
Short name T1097
Test name
Test status
Simulation time 39203150766 ps
CPU time 172.31 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:38:33 PM PST 23
Peak memory 199204 kb
Host smart-867a8957-0a6c-4c62-8fb9-523a394d8a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052726277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2052726277
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2563314827
Short name T931
Test name
Test status
Simulation time 12848273516 ps
CPU time 589.23 seconds
Started Dec 24 01:33:36 PM PST 23
Finished Dec 24 01:43:27 PM PST 23
Peak memory 200176 kb
Host smart-f583650e-e3dc-480c-9918-cc172a4b819b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2563314827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2563314827
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3942073902
Short name T937
Test name
Test status
Simulation time 165852886 ps
CPU time 0.68 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:33:41 PM PST 23
Peak memory 195704 kb
Host smart-9100ebad-40ac-416b-989c-c9f300266317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942073902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3942073902
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.413020253
Short name T595
Test name
Test status
Simulation time 5305345116 ps
CPU time 2.64 seconds
Started Dec 24 01:35:14 PM PST 23
Finished Dec 24 01:35:18 PM PST 23
Peak memory 193824 kb
Host smart-5819b1b6-f01d-4bd1-913b-96dc49628220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413020253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.413020253
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2606846635
Short name T570
Test name
Test status
Simulation time 120297455 ps
CPU time 0.75 seconds
Started Dec 24 01:33:41 PM PST 23
Finished Dec 24 01:33:42 PM PST 23
Peak memory 197048 kb
Host smart-2ac29abb-cecf-49a7-a9dc-9e2464b210dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606846635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2606846635
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.689545807
Short name T1165
Test name
Test status
Simulation time 6699296347 ps
CPU time 9.58 seconds
Started Dec 24 01:33:39 PM PST 23
Finished Dec 24 01:33:50 PM PST 23
Peak memory 199792 kb
Host smart-7546294a-7a66-4bd3-a589-4dc32e7c6760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689545807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.689545807
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2924948648
Short name T827
Test name
Test status
Simulation time 16148312847 ps
CPU time 24.64 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:34:01 PM PST 23
Peak memory 200272 kb
Host smart-f07e67fa-b31a-4cb6-aab7-83df4aae2b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924948648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2924948648
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.337269625
Short name T243
Test name
Test status
Simulation time 39945330055 ps
CPU time 17.84 seconds
Started Dec 24 01:38:48 PM PST 23
Finished Dec 24 01:39:06 PM PST 23
Peak memory 200124 kb
Host smart-6dd84b83-e876-435f-9e58-7ee42d1d4ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337269625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.337269625
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2051113392
Short name T680
Test name
Test status
Simulation time 186053581619 ps
CPU time 302.32 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:43:35 PM PST 23
Peak memory 199968 kb
Host smart-f60c2711-e5fa-40cf-ad25-1538a50c2773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051113392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2051113392
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3352244682
Short name T291
Test name
Test status
Simulation time 63062927106 ps
CPU time 100.78 seconds
Started Dec 24 01:38:51 PM PST 23
Finished Dec 24 01:40:32 PM PST 23
Peak memory 200188 kb
Host smart-81593e49-963b-43f6-8a42-2b21238c9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352244682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3352244682
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3079418184
Short name T535
Test name
Test status
Simulation time 308859535089 ps
CPU time 81.64 seconds
Started Dec 24 01:38:34 PM PST 23
Finished Dec 24 01:39:57 PM PST 23
Peak memory 199404 kb
Host smart-85992c4d-0cd5-4aaa-97bf-875003f37ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079418184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3079418184
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1441230889
Short name T217
Test name
Test status
Simulation time 49163577508 ps
CPU time 20.58 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 01:39:11 PM PST 23
Peak memory 200008 kb
Host smart-7c49d147-3144-400a-9e69-099268db21d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441230889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1441230889
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1298029798
Short name T244
Test name
Test status
Simulation time 44910322805 ps
CPU time 75.07 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:40:04 PM PST 23
Peak memory 199208 kb
Host smart-1f027b91-6ca6-4a53-a131-6bc28e1d2f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298029798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1298029798
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2099799777
Short name T519
Test name
Test status
Simulation time 26977474 ps
CPU time 0.56 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:35:41 PM PST 23
Peak memory 194408 kb
Host smart-e7e3a394-0687-4540-b17c-c59e506d9f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099799777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2099799777
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3369402186
Short name T687
Test name
Test status
Simulation time 17412530943 ps
CPU time 24.25 seconds
Started Dec 24 01:33:42 PM PST 23
Finished Dec 24 01:34:08 PM PST 23
Peak memory 199764 kb
Host smart-008119d8-494b-4c8d-b671-8f31947caaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369402186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3369402186
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.2932744785
Short name T998
Test name
Test status
Simulation time 115169450888 ps
CPU time 173.84 seconds
Started Dec 24 01:33:34 PM PST 23
Finished Dec 24 01:36:29 PM PST 23
Peak memory 198708 kb
Host smart-46a10936-6867-45d5-be30-fa587588d11f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932744785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2932744785
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1434484783
Short name T1059
Test name
Test status
Simulation time 76059068085 ps
CPU time 143.05 seconds
Started Dec 24 01:33:34 PM PST 23
Finished Dec 24 01:35:58 PM PST 23
Peak memory 200200 kb
Host smart-481a74cc-b15a-45f3-89fe-67bd90209a13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434484783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1434484783
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1455969036
Short name T971
Test name
Test status
Simulation time 10662996226 ps
CPU time 12.22 seconds
Started Dec 24 01:35:14 PM PST 23
Finished Dec 24 01:35:28 PM PST 23
Peak memory 197140 kb
Host smart-94c870cd-7378-4e6f-b5f8-c872ab751ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455969036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1455969036
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.4219549754
Short name T688
Test name
Test status
Simulation time 67488857184 ps
CPU time 32.14 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:34:08 PM PST 23
Peak memory 198044 kb
Host smart-cc051ceb-1c16-41b8-8567-d25b4b4a36c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219549754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.4219549754
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.914624
Short name T257
Test name
Test status
Simulation time 5060091968 ps
CPU time 39.05 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:36:20 PM PST 23
Peak memory 199928 kb
Host smart-ad400640-08a8-42b3-b2ed-1c6afccd04c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.914624
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1223197887
Short name T896
Test name
Test status
Simulation time 2683558787 ps
CPU time 6.99 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:33:43 PM PST 23
Peak memory 198724 kb
Host smart-5d01a6f6-aeff-49c0-85ef-46e6dcdc8a47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223197887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1223197887
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2736324377
Short name T1206
Test name
Test status
Simulation time 91500998062 ps
CPU time 41.04 seconds
Started Dec 24 01:33:43 PM PST 23
Finished Dec 24 01:34:26 PM PST 23
Peak memory 200204 kb
Host smart-ca0bf21d-d55c-4c66-8a61-0f1d951096fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736324377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2736324377
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3946299984
Short name T1161
Test name
Test status
Simulation time 3181507854 ps
CPU time 3.11 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:35:44 PM PST 23
Peak memory 195244 kb
Host smart-da0f0d10-d661-4cf3-8443-823b5cd5e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946299984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3946299984
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2786869407
Short name T626
Test name
Test status
Simulation time 105712603 ps
CPU time 0.83 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:35:42 PM PST 23
Peak memory 196584 kb
Host smart-8445db9d-c388-4d9c-a11b-e8b6eb297be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786869407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2786869407
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2355478394
Short name T1096
Test name
Test status
Simulation time 12386256394 ps
CPU time 135.74 seconds
Started Dec 24 01:35:40 PM PST 23
Finished Dec 24 01:37:57 PM PST 23
Peak memory 215520 kb
Host smart-3049a198-0dcc-43b0-9f20-711e768ac643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355478394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2355478394
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3092578869
Short name T644
Test name
Test status
Simulation time 917468325 ps
CPU time 2.14 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:33:42 PM PST 23
Peak memory 198180 kb
Host smart-dac2f8bb-be70-4117-885c-72676496fb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092578869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3092578869
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3578397130
Short name T1221
Test name
Test status
Simulation time 31736003861 ps
CPU time 49.98 seconds
Started Dec 24 01:33:34 PM PST 23
Finished Dec 24 01:34:26 PM PST 23
Peak memory 200200 kb
Host smart-fe132272-0199-478f-8d1f-f674378b9788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578397130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3578397130
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2984793685
Short name T696
Test name
Test status
Simulation time 148688448564 ps
CPU time 114.26 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:40:44 PM PST 23
Peak memory 199872 kb
Host smart-7a0096c8-1497-4315-a3a8-158049c5b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984793685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2984793685
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2190578475
Short name T219
Test name
Test status
Simulation time 176904512719 ps
CPU time 40.95 seconds
Started Dec 24 01:38:31 PM PST 23
Finished Dec 24 01:39:13 PM PST 23
Peak memory 200168 kb
Host smart-3906f9c4-1aba-42d8-a32b-9118f412c6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190578475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2190578475
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1225689854
Short name T897
Test name
Test status
Simulation time 26385723911 ps
CPU time 28.62 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 01:39:19 PM PST 23
Peak memory 199984 kb
Host smart-6969b703-c6e7-4ae2-ada4-41e22e73754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225689854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1225689854
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2057472829
Short name T1069
Test name
Test status
Simulation time 86615960628 ps
CPU time 21.24 seconds
Started Dec 24 01:38:36 PM PST 23
Finished Dec 24 01:38:58 PM PST 23
Peak memory 200220 kb
Host smart-cb20bbdd-0dd2-4a50-8195-26d6d297b6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057472829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2057472829
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2312150675
Short name T1192
Test name
Test status
Simulation time 33134675511 ps
CPU time 20.37 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:38:54 PM PST 23
Peak memory 200180 kb
Host smart-a61c1213-d62e-439e-a90e-cf74aff6edca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312150675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2312150675
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.970410626
Short name T22
Test name
Test status
Simulation time 177409836266 ps
CPU time 302.91 seconds
Started Dec 24 01:38:48 PM PST 23
Finished Dec 24 01:43:52 PM PST 23
Peak memory 200184 kb
Host smart-c60dc291-7a66-4346-b764-914b5a51bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970410626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.970410626
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3495683594
Short name T181
Test name
Test status
Simulation time 114352268213 ps
CPU time 167.07 seconds
Started Dec 24 01:38:53 PM PST 23
Finished Dec 24 01:41:41 PM PST 23
Peak memory 200052 kb
Host smart-d9071fad-3c5c-4cf2-93bd-faaa64a75fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495683594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3495683594
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2169848329
Short name T778
Test name
Test status
Simulation time 42620135533 ps
CPU time 36.72 seconds
Started Dec 24 01:38:52 PM PST 23
Finished Dec 24 01:39:30 PM PST 23
Peak memory 200232 kb
Host smart-e7d51922-f71c-47b8-ba8e-5dab8a107471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169848329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2169848329
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.754828134
Short name T619
Test name
Test status
Simulation time 44890657 ps
CPU time 0.55 seconds
Started Dec 24 01:33:53 PM PST 23
Finished Dec 24 01:33:56 PM PST 23
Peak memory 195692 kb
Host smart-d9ec4d2b-7a91-4934-bd61-066f600addf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754828134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.754828134
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2124388947
Short name T594
Test name
Test status
Simulation time 6371920953 ps
CPU time 10.17 seconds
Started Dec 24 01:33:42 PM PST 23
Finished Dec 24 01:33:53 PM PST 23
Peak memory 198492 kb
Host smart-d545798c-57a1-4230-9cda-dc85490a6e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124388947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2124388947
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3481119125
Short name T1079
Test name
Test status
Simulation time 53377033285 ps
CPU time 19.27 seconds
Started Dec 24 01:33:43 PM PST 23
Finished Dec 24 01:34:04 PM PST 23
Peak memory 200280 kb
Host smart-3d2ccce1-cf76-44b7-bd1e-6d99934ed445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481119125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3481119125
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2243774344
Short name T383
Test name
Test status
Simulation time 103236271369 ps
CPU time 69.73 seconds
Started Dec 24 01:33:42 PM PST 23
Finished Dec 24 01:34:53 PM PST 23
Peak memory 200180 kb
Host smart-b330397d-a553-4027-8799-64b2e8f55a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243774344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2243774344
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.591690996
Short name T24
Test name
Test status
Simulation time 73449147125 ps
CPU time 46.61 seconds
Started Dec 24 01:33:41 PM PST 23
Finished Dec 24 01:34:28 PM PST 23
Peak memory 200208 kb
Host smart-79ad176e-9bfa-46ca-88af-179f2d3a4732
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591690996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.591690996
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2342814158
Short name T520
Test name
Test status
Simulation time 294529053193 ps
CPU time 345.12 seconds
Started Dec 24 01:34:03 PM PST 23
Finished Dec 24 01:39:52 PM PST 23
Peak memory 200224 kb
Host smart-900dd36e-7179-48b8-b876-00ad27015c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342814158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2342814158
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2361596361
Short name T972
Test name
Test status
Simulation time 9516051564 ps
CPU time 4.77 seconds
Started Dec 24 01:33:55 PM PST 23
Finished Dec 24 01:34:04 PM PST 23
Peak memory 199456 kb
Host smart-9a6c8caa-309d-4776-b201-7a9b94e186f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361596361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2361596361
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2911041767
Short name T1076
Test name
Test status
Simulation time 71773190817 ps
CPU time 160.78 seconds
Started Dec 24 01:33:37 PM PST 23
Finished Dec 24 01:36:19 PM PST 23
Peak memory 200108 kb
Host smart-a8bc31f7-c456-4723-b24f-1cd47cf7da4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911041767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2911041767
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.4101083499
Short name T994
Test name
Test status
Simulation time 15851802530 ps
CPU time 107.57 seconds
Started Dec 24 01:33:52 PM PST 23
Finished Dec 24 01:35:44 PM PST 23
Peak memory 200216 kb
Host smart-b4a39fce-244f-4cec-a651-b584bb1a2220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101083499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.4101083499
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.918251719
Short name T628
Test name
Test status
Simulation time 23958992310 ps
CPU time 40.04 seconds
Started Dec 24 01:33:59 PM PST 23
Finished Dec 24 01:34:46 PM PST 23
Peak memory 200048 kb
Host smart-119afac4-09e5-4093-a7d7-c75dc61741ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918251719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.918251719
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1964591091
Short name T932
Test name
Test status
Simulation time 5132784893 ps
CPU time 2.43 seconds
Started Dec 24 01:33:36 PM PST 23
Finished Dec 24 01:33:40 PM PST 23
Peak memory 196000 kb
Host smart-ede88e84-1442-42b1-8850-00483a0b8c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964591091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1964591091
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.420936972
Short name T817
Test name
Test status
Simulation time 115004309 ps
CPU time 0.88 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:33:40 PM PST 23
Peak memory 196836 kb
Host smart-d566cfa1-a984-409c-89a8-7501786435c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420936972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.420936972
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1449294475
Short name T358
Test name
Test status
Simulation time 104430351326 ps
CPU time 413.77 seconds
Started Dec 24 01:34:03 PM PST 23
Finished Dec 24 01:41:00 PM PST 23
Peak memory 200184 kb
Host smart-f131d2bc-193f-43d4-9867-a9679c7ca01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449294475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1449294475
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2666153940
Short name T1131
Test name
Test status
Simulation time 61342115360 ps
CPU time 747 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:46:26 PM PST 23
Peak memory 216696 kb
Host smart-47106934-6881-4d1b-b5c4-b138bb9f55d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666153940 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2666153940
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1433800356
Short name T865
Test name
Test status
Simulation time 6924028780 ps
CPU time 23.01 seconds
Started Dec 24 01:33:53 PM PST 23
Finished Dec 24 01:34:20 PM PST 23
Peak memory 199928 kb
Host smart-eb56938a-f95f-416a-9f83-2b3f893bfdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433800356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1433800356
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3183873596
Short name T1018
Test name
Test status
Simulation time 69857374611 ps
CPU time 69.41 seconds
Started Dec 24 01:33:43 PM PST 23
Finished Dec 24 01:34:54 PM PST 23
Peak memory 200216 kb
Host smart-9aada83d-df68-44c9-994b-8fd52d966236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183873596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3183873596
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.731301718
Short name T819
Test name
Test status
Simulation time 71933654549 ps
CPU time 33.24 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:39:23 PM PST 23
Peak memory 200220 kb
Host smart-b0067148-cfe4-43b6-8937-4d23e5acc45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731301718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.731301718
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2605064140
Short name T18
Test name
Test status
Simulation time 76788491834 ps
CPU time 53.21 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:39:43 PM PST 23
Peak memory 200028 kb
Host smart-81c7f912-39c7-48e2-a836-91c0bf702d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605064140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2605064140
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2246837635
Short name T1128
Test name
Test status
Simulation time 66077399937 ps
CPU time 31.85 seconds
Started Dec 24 01:38:53 PM PST 23
Finished Dec 24 01:39:26 PM PST 23
Peak memory 200268 kb
Host smart-2969e7f6-c1bd-4dbc-ae89-13d0a1ac09d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246837635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2246837635
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2063573465
Short name T1050
Test name
Test status
Simulation time 106237946190 ps
CPU time 214.49 seconds
Started Dec 24 01:38:34 PM PST 23
Finished Dec 24 01:42:09 PM PST 23
Peak memory 200268 kb
Host smart-7078e36e-ae5e-4f5a-ba28-f1a90523f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063573465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2063573465
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1944071774
Short name T718
Test name
Test status
Simulation time 50960795308 ps
CPU time 40.5 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:39:14 PM PST 23
Peak memory 200220 kb
Host smart-621ddda3-5c72-4256-8f23-a477233cd8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944071774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1944071774
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4226191116
Short name T360
Test name
Test status
Simulation time 39969213770 ps
CPU time 16.06 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:39:05 PM PST 23
Peak memory 200232 kb
Host smart-c2f1a917-3341-4081-9df9-ddf48ab5ffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226191116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4226191116
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3375925966
Short name T933
Test name
Test status
Simulation time 22021326665 ps
CPU time 27.23 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 01:39:18 PM PST 23
Peak memory 200244 kb
Host smart-39e66841-f9bb-4d75-b467-a2cc847103b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375925966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3375925966
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1554005061
Short name T323
Test name
Test status
Simulation time 22500032134 ps
CPU time 33.38 seconds
Started Dec 24 01:38:31 PM PST 23
Finished Dec 24 01:39:06 PM PST 23
Peak memory 200240 kb
Host smart-1f2252f0-97a1-43e5-8987-d3156199614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554005061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1554005061
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4162900888
Short name T663
Test name
Test status
Simulation time 36230200 ps
CPU time 0.56 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:34:00 PM PST 23
Peak memory 195672 kb
Host smart-32f2ef87-2f05-45d4-89da-6362159bd62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162900888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4162900888
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1903508820
Short name T1048
Test name
Test status
Simulation time 156522610112 ps
CPU time 61.42 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:35:01 PM PST 23
Peak memory 200004 kb
Host smart-1be05186-205b-4f2e-b88c-57be5ca668e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903508820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1903508820
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.535008810
Short name T924
Test name
Test status
Simulation time 73594608781 ps
CPU time 78.67 seconds
Started Dec 24 01:33:56 PM PST 23
Finished Dec 24 01:35:21 PM PST 23
Peak memory 199220 kb
Host smart-7955ed02-d45c-4d7a-89f6-466fe6792532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535008810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.535008810
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1736975274
Short name T681
Test name
Test status
Simulation time 20721046083 ps
CPU time 32.57 seconds
Started Dec 24 01:33:57 PM PST 23
Finished Dec 24 01:34:36 PM PST 23
Peak memory 199616 kb
Host smart-dee7a8be-844f-426a-a208-f85c36ff381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736975274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1736975274
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1747073450
Short name T1139
Test name
Test status
Simulation time 376808475212 ps
CPU time 164.24 seconds
Started Dec 24 01:34:03 PM PST 23
Finished Dec 24 01:36:51 PM PST 23
Peak memory 199924 kb
Host smart-3453dd50-b4ca-4e5d-b79f-352a171a4143
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747073450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1747073450
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.341284943
Short name T686
Test name
Test status
Simulation time 156019484012 ps
CPU time 806.29 seconds
Started Dec 24 01:33:52 PM PST 23
Finished Dec 24 01:47:22 PM PST 23
Peak memory 200224 kb
Host smart-ab83b4e1-f509-4afb-acae-beb5cc94d1e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=341284943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.341284943
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_noise_filter.4025613490
Short name T776
Test name
Test status
Simulation time 76324976312 ps
CPU time 59.01 seconds
Started Dec 24 01:33:55 PM PST 23
Finished Dec 24 01:34:59 PM PST 23
Peak memory 199676 kb
Host smart-8977c43c-0a19-40ba-80d3-d0d97de5ceee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025613490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4025613490
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.4203088068
Short name T747
Test name
Test status
Simulation time 14084112374 ps
CPU time 196.96 seconds
Started Dec 24 01:33:56 PM PST 23
Finished Dec 24 01:37:20 PM PST 23
Peak memory 200228 kb
Host smart-45ad0251-3728-4275-87ba-5d2494111e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203088068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4203088068
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1251306849
Short name T823
Test name
Test status
Simulation time 96654433182 ps
CPU time 143.63 seconds
Started Dec 24 01:33:52 PM PST 23
Finished Dec 24 01:36:20 PM PST 23
Peak memory 199152 kb
Host smart-62d5d66f-b90c-4f71-89c3-69173aa2cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251306849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1251306849
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.665516111
Short name T453
Test name
Test status
Simulation time 538217672 ps
CPU time 1.44 seconds
Started Dec 24 01:34:03 PM PST 23
Finished Dec 24 01:34:08 PM PST 23
Peak memory 195612 kb
Host smart-011c8422-ed4a-4398-a0a9-367fe4ca0236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665516111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.665516111
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.866410702
Short name T975
Test name
Test status
Simulation time 469936446 ps
CPU time 2.56 seconds
Started Dec 24 01:33:59 PM PST 23
Finished Dec 24 01:34:08 PM PST 23
Peak memory 199760 kb
Host smart-520ce076-9613-48e3-80ab-519a71e879b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866410702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.866410702
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1779460967
Short name T1035
Test name
Test status
Simulation time 5884088114 ps
CPU time 99.45 seconds
Started Dec 24 01:33:53 PM PST 23
Finished Dec 24 01:35:35 PM PST 23
Peak memory 200204 kb
Host smart-6b2dca2f-96fe-4328-a4e7-28b4499b1544
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779460967 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1779460967
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.640272529
Short name T537
Test name
Test status
Simulation time 1662654813 ps
CPU time 2.3 seconds
Started Dec 24 01:33:53 PM PST 23
Finished Dec 24 01:33:58 PM PST 23
Peak memory 198756 kb
Host smart-38dd9f76-5bf1-49fd-a33d-35d61ca8df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640272529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.640272529
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3255586374
Short name T16
Test name
Test status
Simulation time 78637343586 ps
CPU time 35.32 seconds
Started Dec 24 01:33:53 PM PST 23
Finished Dec 24 01:34:31 PM PST 23
Peak memory 200216 kb
Host smart-19b58858-2fbb-437c-920a-945c9e943693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255586374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3255586374
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.216381533
Short name T250
Test name
Test status
Simulation time 16810110222 ps
CPU time 14.16 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:38:47 PM PST 23
Peak memory 199768 kb
Host smart-db9d0901-4577-4f02-bd11-957155327113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216381533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.216381533
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.405300914
Short name T329
Test name
Test status
Simulation time 16885195553 ps
CPU time 14.35 seconds
Started Dec 24 01:38:33 PM PST 23
Finished Dec 24 01:38:49 PM PST 23
Peak memory 199828 kb
Host smart-08b39427-d516-4ef0-bd2a-29de60bd69ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405300914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.405300914
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1999960987
Short name T627
Test name
Test status
Simulation time 164903005095 ps
CPU time 96.28 seconds
Started Dec 24 01:38:51 PM PST 23
Finished Dec 24 01:40:28 PM PST 23
Peak memory 200224 kb
Host smart-cde49ac3-7528-4dfc-b8ba-653fc45a102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999960987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1999960987
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3753199830
Short name T700
Test name
Test status
Simulation time 56200919231 ps
CPU time 94.78 seconds
Started Dec 24 01:38:55 PM PST 23
Finished Dec 24 01:40:31 PM PST 23
Peak memory 199540 kb
Host smart-c41ff48d-ec8e-48a8-8134-786276794990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753199830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3753199830
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4225356519
Short name T248
Test name
Test status
Simulation time 13931366020 ps
CPU time 22.87 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:17 PM PST 23
Peak memory 199668 kb
Host smart-fe61209b-bbbb-4a43-b3dc-97a846c67f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225356519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4225356519
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.598206880
Short name T274
Test name
Test status
Simulation time 24001000016 ps
CPU time 9.74 seconds
Started Dec 24 01:38:53 PM PST 23
Finished Dec 24 01:39:04 PM PST 23
Peak memory 200144 kb
Host smart-2d42d65a-c4e4-4769-a114-0f61a6e6077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598206880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.598206880
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1774301820
Short name T919
Test name
Test status
Simulation time 29979885966 ps
CPU time 18.97 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:14 PM PST 23
Peak memory 200156 kb
Host smart-3a1bdc16-68df-4c4d-be63-7a754048c181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774301820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1774301820
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1721416900
Short name T852
Test name
Test status
Simulation time 102075244 ps
CPU time 0.52 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:20 PM PST 23
Peak memory 194668 kb
Host smart-eb739a79-9a08-41c7-8c60-da5ec0090352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721416900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1721416900
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2714924099
Short name T623
Test name
Test status
Simulation time 18302504141 ps
CPU time 28.69 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:34:26 PM PST 23
Peak memory 200252 kb
Host smart-217468a5-1f58-4e6b-9b9a-603ee4df07f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714924099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2714924099
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2789078015
Short name T611
Test name
Test status
Simulation time 250503956705 ps
CPU time 81.13 seconds
Started Dec 24 01:33:53 PM PST 23
Finished Dec 24 01:35:17 PM PST 23
Peak memory 200168 kb
Host smart-33a990c5-6245-441b-b214-4ceb9dcd47ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789078015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2789078015
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1550789327
Short name T1042
Test name
Test status
Simulation time 172552939667 ps
CPU time 323.08 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:39:22 PM PST 23
Peak memory 200156 kb
Host smart-51810c6e-3569-4c43-828e-4334dd992bb9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550789327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1550789327
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.642191236
Short name T1052
Test name
Test status
Simulation time 33730903656 ps
CPU time 258.91 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:38:41 PM PST 23
Peak memory 200160 kb
Host smart-d81fd808-f63f-4235-b8d0-93fbe24b223e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642191236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.642191236
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.656142331
Short name T542
Test name
Test status
Simulation time 10157912389 ps
CPU time 21.49 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:34:21 PM PST 23
Peak memory 200036 kb
Host smart-441f9c3c-7834-448c-95b2-8d8c455bd37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656142331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.656142331
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3197114566
Short name T1046
Test name
Test status
Simulation time 75919087222 ps
CPU time 107.95 seconds
Started Dec 24 01:33:55 PM PST 23
Finished Dec 24 01:35:48 PM PST 23
Peak memory 199312 kb
Host smart-a28dc55c-38ba-4168-ab96-4812d615972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197114566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3197114566
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.980332313
Short name T733
Test name
Test status
Simulation time 11872145366 ps
CPU time 718.01 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:46:18 PM PST 23
Peak memory 200212 kb
Host smart-4bb921c8-f1ba-47df-8e57-e31b2b13d7ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980332313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.980332313
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3474421710
Short name T1177
Test name
Test status
Simulation time 128245839 ps
CPU time 1.02 seconds
Started Dec 24 01:34:02 PM PST 23
Finished Dec 24 01:34:07 PM PST 23
Peak memory 198116 kb
Host smart-52391550-0e17-4edf-bbb2-141031c720b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474421710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3474421710
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3089109460
Short name T428
Test name
Test status
Simulation time 27942865138 ps
CPU time 22.57 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:34:21 PM PST 23
Peak memory 200248 kb
Host smart-b93a34bc-c8fd-423f-8104-553f306e0afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089109460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3089109460
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2015141701
Short name T1060
Test name
Test status
Simulation time 37106041791 ps
CPU time 18.2 seconds
Started Dec 24 01:33:55 PM PST 23
Finished Dec 24 01:34:18 PM PST 23
Peak memory 195996 kb
Host smart-1e0b70ef-3d0e-42fa-b4d8-a20feac983fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015141701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2015141701
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.344704210
Short name T714
Test name
Test status
Simulation time 714693403 ps
CPU time 4.14 seconds
Started Dec 24 01:33:54 PM PST 23
Finished Dec 24 01:34:02 PM PST 23
Peak memory 198076 kb
Host smart-5c661490-3666-45af-8b48-e3992314182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344704210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.344704210
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1695447130
Short name T1041
Test name
Test status
Simulation time 211501145196 ps
CPU time 322.78 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:40:02 PM PST 23
Peak memory 200252 kb
Host smart-d739967a-0ccf-4f03-9639-a83ecf90adf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695447130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1695447130
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3718782738
Short name T713
Test name
Test status
Simulation time 24046716240 ps
CPU time 287.14 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:39:06 PM PST 23
Peak memory 216584 kb
Host smart-1862a3fb-c004-4762-b0d7-667266bee783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718782738 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3718782738
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2041216717
Short name T1145
Test name
Test status
Simulation time 1377438779 ps
CPU time 2.42 seconds
Started Dec 24 01:33:55 PM PST 23
Finished Dec 24 01:34:02 PM PST 23
Peak memory 198764 kb
Host smart-81d5b2d3-bf6d-44c1-8e0b-cd0cb7e99444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041216717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2041216717
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.428630607
Short name T168
Test name
Test status
Simulation time 14204412446 ps
CPU time 25.8 seconds
Started Dec 24 01:34:03 PM PST 23
Finished Dec 24 01:34:32 PM PST 23
Peak memory 200248 kb
Host smart-c10ba70e-76c4-4438-97f8-388c12ad56bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428630607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.428630607
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.527662624
Short name T1213
Test name
Test status
Simulation time 20453818454 ps
CPU time 38.37 seconds
Started Dec 24 01:38:53 PM PST 23
Finished Dec 24 01:39:32 PM PST 23
Peak memory 200188 kb
Host smart-33af75b5-b7b7-4487-9f11-ba03b39d6e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527662624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.527662624
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3235368485
Short name T959
Test name
Test status
Simulation time 99112138728 ps
CPU time 175 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:41:50 PM PST 23
Peak memory 199792 kb
Host smart-5051fa80-9e89-4637-8401-f75bab6781fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235368485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3235368485
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.328398404
Short name T203
Test name
Test status
Simulation time 29272420040 ps
CPU time 49.86 seconds
Started Dec 24 01:38:56 PM PST 23
Finished Dec 24 01:39:47 PM PST 23
Peak memory 200204 kb
Host smart-84394f89-738a-442c-adb5-62b24591159c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328398404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.328398404
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3089697666
Short name T401
Test name
Test status
Simulation time 72127336321 ps
CPU time 29.5 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:24 PM PST 23
Peak memory 200092 kb
Host smart-89fb4a0d-3122-41c0-9fbf-d078fd4731de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089697666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3089697666
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2240131576
Short name T298
Test name
Test status
Simulation time 119018271464 ps
CPU time 181.23 seconds
Started Dec 24 01:38:55 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 200168 kb
Host smart-d529ae17-6f79-49b7-ae10-1194a74383d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240131576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2240131576
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.440258838
Short name T955
Test name
Test status
Simulation time 53764657928 ps
CPU time 91.76 seconds
Started Dec 24 01:38:56 PM PST 23
Finished Dec 24 01:40:29 PM PST 23
Peak memory 199772 kb
Host smart-988cfcd6-ecce-48b9-8cc5-229e24eed5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440258838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.440258838
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3923447888
Short name T384
Test name
Test status
Simulation time 149442710208 ps
CPU time 378.13 seconds
Started Dec 24 01:38:51 PM PST 23
Finished Dec 24 01:45:10 PM PST 23
Peak memory 200032 kb
Host smart-5869bc9a-5abb-4c64-b971-52cda1d06bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923447888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3923447888
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3150267619
Short name T150
Test name
Test status
Simulation time 28690777072 ps
CPU time 43.62 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:39 PM PST 23
Peak memory 200116 kb
Host smart-80fc6d6e-dc95-4474-9a38-dd2558d8456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150267619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3150267619
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3973116164
Short name T1136
Test name
Test status
Simulation time 12880208 ps
CPU time 0.6 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:34:20 PM PST 23
Peak memory 195660 kb
Host smart-451dc1b6-398e-40d7-8046-bd9ff2bf4e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973116164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3973116164
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2713560222
Short name T684
Test name
Test status
Simulation time 120436877143 ps
CPU time 103.62 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:36:27 PM PST 23
Peak memory 200204 kb
Host smart-45cdaba3-0fd4-4837-a754-3e4cfd2ac602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713560222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2713560222
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1022207754
Short name T775
Test name
Test status
Simulation time 19183458576 ps
CPU time 20.05 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:40 PM PST 23
Peak memory 200144 kb
Host smart-956aee97-86d7-4576-93f7-cd4c01c59a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022207754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1022207754
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.2730320491
Short name T513
Test name
Test status
Simulation time 25732340938 ps
CPU time 11.33 seconds
Started Dec 24 01:34:32 PM PST 23
Finished Dec 24 01:34:44 PM PST 23
Peak memory 196700 kb
Host smart-3f0d5a9b-ea97-460a-a953-197174778a4e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730320491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2730320491
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.585801725
Short name T756
Test name
Test status
Simulation time 138156429748 ps
CPU time 217.42 seconds
Started Dec 24 01:34:43 PM PST 23
Finished Dec 24 01:38:22 PM PST 23
Peak memory 200204 kb
Host smart-3d154567-6c53-4925-b23a-487a6a060866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585801725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.585801725
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_noise_filter.472325904
Short name T862
Test name
Test status
Simulation time 17613269742 ps
CPU time 29.81 seconds
Started Dec 24 01:34:41 PM PST 23
Finished Dec 24 01:35:12 PM PST 23
Peak memory 197020 kb
Host smart-59aa6b37-7042-4497-b1a0-159957faeac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472325904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.472325904
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4141362039
Short name T1011
Test name
Test status
Simulation time 17722006208 ps
CPU time 511.46 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:42:52 PM PST 23
Peak memory 200028 kb
Host smart-105f85a3-fc9e-46de-838c-ee5afec9ef76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4141362039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4141362039
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.691942414
Short name T871
Test name
Test status
Simulation time 576939810 ps
CPU time 1.59 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:34:21 PM PST 23
Peak memory 198052 kb
Host smart-c2afe587-e124-4e8f-a9ab-23e7d65a4f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691942414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.691942414
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.829408650
Short name T648
Test name
Test status
Simulation time 41065244529 ps
CPU time 31.04 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:53 PM PST 23
Peak memory 200208 kb
Host smart-3981fea8-cf7e-41be-808f-492b21d4bc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829408650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.829408650
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.133766917
Short name T1104
Test name
Test status
Simulation time 39088154851 ps
CPU time 30.22 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:34:52 PM PST 23
Peak memory 195960 kb
Host smart-c66b180a-b115-4138-aa11-4985ae4feb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133766917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.133766917
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2965669532
Short name T538
Test name
Test status
Simulation time 324634184 ps
CPU time 0.99 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:34:23 PM PST 23
Peak memory 198208 kb
Host smart-ae119195-9426-4f37-b7b8-71f65afcbc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965669532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2965669532
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.387153034
Short name T110
Test name
Test status
Simulation time 103178908761 ps
CPU time 116.1 seconds
Started Dec 24 01:35:57 PM PST 23
Finished Dec 24 01:37:55 PM PST 23
Peak memory 198300 kb
Host smart-d24b4b1d-93f6-4aa7-a767-845440698659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387153034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.387153034
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2960825942
Short name T79
Test name
Test status
Simulation time 153453488753 ps
CPU time 338.62 seconds
Started Dec 24 01:34:34 PM PST 23
Finished Dec 24 01:40:14 PM PST 23
Peak memory 216940 kb
Host smart-949439c0-451c-4e1c-80e9-0547deea9eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960825942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2960825942
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.614117821
Short name T757
Test name
Test status
Simulation time 1640542563 ps
CPU time 2.04 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:24 PM PST 23
Peak memory 198992 kb
Host smart-decc5d1f-6fa2-42a5-a07e-4a0eea6768b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614117821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.614117821
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3997299890
Short name T41
Test name
Test status
Simulation time 40554864709 ps
CPU time 6.45 seconds
Started Dec 24 01:34:40 PM PST 23
Finished Dec 24 01:34:48 PM PST 23
Peak memory 197280 kb
Host smart-42532b4d-bb57-4038-894f-a6102231ca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997299890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3997299890
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.910903615
Short name T256
Test name
Test status
Simulation time 164465415316 ps
CPU time 82.31 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:40:17 PM PST 23
Peak memory 200168 kb
Host smart-5748f453-060f-4053-8f0f-fe9580654a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910903615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.910903615
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3062621705
Short name T186
Test name
Test status
Simulation time 46413148760 ps
CPU time 74.13 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 01:40:05 PM PST 23
Peak memory 200068 kb
Host smart-d23de31d-9505-4c05-b600-7a7519b537d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062621705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3062621705
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3143123442
Short name T332
Test name
Test status
Simulation time 28778894897 ps
CPU time 45.08 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:40 PM PST 23
Peak memory 199804 kb
Host smart-f491ea6d-a9b3-4870-8ff9-9fa2a58335e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143123442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3143123442
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2061207143
Short name T276
Test name
Test status
Simulation time 190105816405 ps
CPU time 80.96 seconds
Started Dec 24 01:38:52 PM PST 23
Finished Dec 24 01:40:13 PM PST 23
Peak memory 200180 kb
Host smart-2fed5ee0-4113-4f1c-8ccb-cc65be1d7ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061207143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2061207143
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.561622357
Short name T1058
Test name
Test status
Simulation time 269753177452 ps
CPU time 100.91 seconds
Started Dec 24 01:38:56 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 200044 kb
Host smart-e7ce1812-da22-4342-b1e4-79eaad46b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561622357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.561622357
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2963416843
Short name T283
Test name
Test status
Simulation time 41837302395 ps
CPU time 67.15 seconds
Started Dec 24 01:38:55 PM PST 23
Finished Dec 24 01:40:03 PM PST 23
Peak memory 200024 kb
Host smart-909d39f2-11c8-4b21-a571-c808146130ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963416843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2963416843
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.808507345
Short name T694
Test name
Test status
Simulation time 125590841855 ps
CPU time 70.15 seconds
Started Dec 24 01:38:51 PM PST 23
Finished Dec 24 01:40:02 PM PST 23
Peak memory 200264 kb
Host smart-3aa31360-bffe-460c-8595-3d4519c4fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808507345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.808507345
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3431065001
Short name T1087
Test name
Test status
Simulation time 35207181906 ps
CPU time 13.61 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:09 PM PST 23
Peak memory 198552 kb
Host smart-c38af7d0-dfdf-4bd7-9794-a33063eb6dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431065001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3431065001
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3099254815
Short name T522
Test name
Test status
Simulation time 19369956 ps
CPU time 0.53 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:22 PM PST 23
Peak memory 195600 kb
Host smart-731a7bc1-1b39-46ff-90c5-60e95cae3df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099254815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3099254815
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3956588207
Short name T335
Test name
Test status
Simulation time 138611632096 ps
CPU time 228.48 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:38:09 PM PST 23
Peak memory 200208 kb
Host smart-ac8ca552-6ea6-4ac6-a25f-1a8df7095c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956588207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3956588207
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3879489544
Short name T20
Test name
Test status
Simulation time 28627692875 ps
CPU time 22.27 seconds
Started Dec 24 01:34:40 PM PST 23
Finished Dec 24 01:35:04 PM PST 23
Peak memory 199068 kb
Host smart-e018dbf7-428a-4202-94ff-996f3b583c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879489544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3879489544
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.2720710811
Short name T620
Test name
Test status
Simulation time 251499089608 ps
CPU time 197.03 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:37:38 PM PST 23
Peak memory 200136 kb
Host smart-5366ba20-1dc7-40e7-94ea-5bdbc86bdb55
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720710811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2720710811
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2045518526
Short name T774
Test name
Test status
Simulation time 177405248258 ps
CPU time 884.62 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:49:25 PM PST 23
Peak memory 200228 kb
Host smart-e0efa117-116f-45f1-ad04-5064c87cb52c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045518526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2045518526
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2189333232
Short name T978
Test name
Test status
Simulation time 48084415893 ps
CPU time 36.86 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:34:59 PM PST 23
Peak memory 199648 kb
Host smart-7bed4d3f-c09e-4229-83bd-42fbc748fabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189333232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2189333232
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2800375245
Short name T414
Test name
Test status
Simulation time 21660936306 ps
CPU time 551.76 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:43:33 PM PST 23
Peak memory 200036 kb
Host smart-d56c8e78-233a-4237-8918-8bbef96bfdbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2800375245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2800375245
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1883201820
Short name T837
Test name
Test status
Simulation time 130804346 ps
CPU time 0.74 seconds
Started Dec 24 01:34:40 PM PST 23
Finished Dec 24 01:34:43 PM PST 23
Peak memory 195576 kb
Host smart-275df9ed-2107-4a7f-a28e-306563c333e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883201820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1883201820
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.214820781
Short name T656
Test name
Test status
Simulation time 33708868795 ps
CPU time 4.85 seconds
Started Dec 24 01:34:39 PM PST 23
Finished Dec 24 01:34:45 PM PST 23
Peak memory 195888 kb
Host smart-1a63fcee-4d30-4ada-8b7c-b7a87fdde99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214820781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.214820781
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2055020544
Short name T514
Test name
Test status
Simulation time 508542237 ps
CPU time 1.21 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:34:20 PM PST 23
Peak memory 199140 kb
Host smart-ea21a820-973a-4a00-9598-6672e435b78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055020544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2055020544
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1086053673
Short name T651
Test name
Test status
Simulation time 1192975337 ps
CPU time 1.33 seconds
Started Dec 24 01:34:21 PM PST 23
Finished Dec 24 01:34:24 PM PST 23
Peak memory 198464 kb
Host smart-33a1728f-c17b-45ad-bdd4-5bea879e5d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086053673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1086053673
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3368654115
Short name T423
Test name
Test status
Simulation time 47350354328 ps
CPU time 86.18 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:36:06 PM PST 23
Peak memory 200164 kb
Host smart-4b4d33a4-4375-4484-848e-594c4a302b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368654115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3368654115
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.203614326
Short name T1157
Test name
Test status
Simulation time 31146984306 ps
CPU time 14.97 seconds
Started Dec 24 01:38:56 PM PST 23
Finished Dec 24 01:39:12 PM PST 23
Peak memory 198944 kb
Host smart-4a2652be-afeb-40e3-ae70-5dcdddd62e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203614326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.203614326
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.301941502
Short name T1227
Test name
Test status
Simulation time 63714124172 ps
CPU time 107.22 seconds
Started Dec 24 01:38:52 PM PST 23
Finished Dec 24 01:40:40 PM PST 23
Peak memory 200184 kb
Host smart-0bf6412c-332b-4be7-b379-faf1f23781e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301941502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.301941502
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3827155184
Short name T1107
Test name
Test status
Simulation time 29835524727 ps
CPU time 13 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:39:08 PM PST 23
Peak memory 198780 kb
Host smart-dff822e6-fae2-4f80-aea6-d50f7b0a4df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827155184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3827155184
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2345432384
Short name T267
Test name
Test status
Simulation time 131865150306 ps
CPU time 55.02 seconds
Started Dec 24 01:38:55 PM PST 23
Finished Dec 24 01:39:51 PM PST 23
Peak memory 200208 kb
Host smart-cc1483ca-67aa-4482-9a5a-0d2decf54ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345432384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2345432384
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3727658410
Short name T1080
Test name
Test status
Simulation time 27512208178 ps
CPU time 46.94 seconds
Started Dec 24 01:38:52 PM PST 23
Finished Dec 24 01:39:39 PM PST 23
Peak memory 199836 kb
Host smart-753bc363-e036-49e0-977d-b3b214227f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727658410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3727658410
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1907767099
Short name T107
Test name
Test status
Simulation time 36837423395 ps
CPU time 56.76 seconds
Started Dec 24 01:38:55 PM PST 23
Finished Dec 24 01:39:53 PM PST 23
Peak memory 200244 kb
Host smart-73c20355-6fe3-4bfe-a31b-15769d56ba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907767099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1907767099
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2364077791
Short name T809
Test name
Test status
Simulation time 45984350123 ps
CPU time 22.79 seconds
Started Dec 24 01:38:51 PM PST 23
Finished Dec 24 01:39:15 PM PST 23
Peak memory 200228 kb
Host smart-2fdfe9dc-a31c-40f6-b8b9-35933e5f39db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364077791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2364077791
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3655297771
Short name T1102
Test name
Test status
Simulation time 138868862808 ps
CPU time 315.94 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 200144 kb
Host smart-a7cb2c82-df6a-44a6-8727-7f54dd184d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655297771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3655297771
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3201623629
Short name T435
Test name
Test status
Simulation time 332040837241 ps
CPU time 33.39 seconds
Started Dec 24 01:38:56 PM PST 23
Finished Dec 24 01:39:30 PM PST 23
Peak memory 199920 kb
Host smart-e5092563-c102-4046-a792-11ebd53db8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201623629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3201623629
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.124335263
Short name T659
Test name
Test status
Simulation time 28420238 ps
CPU time 0.55 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:21 PM PST 23
Peak memory 195600 kb
Host smart-703c2378-447f-4a56-8133-9ac377cbe317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124335263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.124335263
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1356995668
Short name T708
Test name
Test status
Simulation time 25061611392 ps
CPU time 38.15 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:35:00 PM PST 23
Peak memory 200204 kb
Host smart-9236c98d-34aa-4050-8b87-bafadfce6777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356995668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1356995668
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2560862443
Short name T772
Test name
Test status
Simulation time 244785281743 ps
CPU time 29.07 seconds
Started Dec 24 01:34:39 PM PST 23
Finished Dec 24 01:35:10 PM PST 23
Peak memory 200240 kb
Host smart-cc1155fd-d257-43f5-a3da-57da94b827c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560862443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2560862443
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.282037028
Short name T1144
Test name
Test status
Simulation time 1567496641820 ps
CPU time 621.9 seconds
Started Dec 24 01:34:40 PM PST 23
Finished Dec 24 01:45:04 PM PST 23
Peak memory 199568 kb
Host smart-2b4587b5-0a68-4b35-87e4-b93a4377d5e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282037028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.282037028
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3999858883
Short name T624
Test name
Test status
Simulation time 110137033714 ps
CPU time 280.72 seconds
Started Dec 24 01:34:39 PM PST 23
Finished Dec 24 01:39:22 PM PST 23
Peak memory 200128 kb
Host smart-cb87b0db-ace8-4335-bb7c-b2da5ce0ff1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999858883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3999858883
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2675934084
Short name T516
Test name
Test status
Simulation time 6002968785 ps
CPU time 4.48 seconds
Started Dec 24 01:34:41 PM PST 23
Finished Dec 24 01:34:47 PM PST 23
Peak memory 199716 kb
Host smart-bcaa99c7-9f94-4e8f-acb3-27e06ef24578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675934084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2675934084
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3139229877
Short name T239
Test name
Test status
Simulation time 94778397430 ps
CPU time 60.04 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:35:40 PM PST 23
Peak memory 199500 kb
Host smart-7df068cb-4ce5-4096-99a0-877f62c9da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139229877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3139229877
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2599372217
Short name T583
Test name
Test status
Simulation time 25010867047 ps
CPU time 649.08 seconds
Started Dec 24 01:34:39 PM PST 23
Finished Dec 24 01:45:30 PM PST 23
Peak memory 200156 kb
Host smart-96f6c628-7478-4066-97d2-b13054d83665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599372217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2599372217
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.76125845
Short name T523
Test name
Test status
Simulation time 2526505493 ps
CPU time 4.37 seconds
Started Dec 24 01:34:40 PM PST 23
Finished Dec 24 01:34:46 PM PST 23
Peak memory 198204 kb
Host smart-cbe6f35b-bbaa-4482-9dcd-b8c993e9d010
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76125845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.76125845
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3535189222
Short name T112
Test name
Test status
Simulation time 48188573136 ps
CPU time 17.35 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:38 PM PST 23
Peak memory 198992 kb
Host smart-cfb0ab41-b3ad-4f71-9e8c-88eaa143690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535189222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3535189222
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.939982608
Short name T544
Test name
Test status
Simulation time 4636412721 ps
CPU time 2.38 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:34:42 PM PST 23
Peak memory 195772 kb
Host smart-7a99bf15-a4e9-4eae-8905-07cb0207190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939982608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.939982608
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2185292043
Short name T413
Test name
Test status
Simulation time 10552954699 ps
CPU time 22.68 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:44 PM PST 23
Peak memory 199420 kb
Host smart-b4f3ff4d-c7a4-46ea-ac21-747301c00c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185292043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2185292043
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2172024191
Short name T970
Test name
Test status
Simulation time 319436660376 ps
CPU time 533.19 seconds
Started Dec 24 01:36:13 PM PST 23
Finished Dec 24 01:45:07 PM PST 23
Peak memory 199724 kb
Host smart-c89f7ea7-9f40-45e4-95f2-873fb75473f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172024191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2172024191
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2354071063
Short name T675
Test name
Test status
Simulation time 223896948495 ps
CPU time 607.53 seconds
Started Dec 24 01:34:17 PM PST 23
Finished Dec 24 01:44:26 PM PST 23
Peak memory 215624 kb
Host smart-b6311c75-dd94-407e-a630-be64e90e37a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354071063 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2354071063
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3964823474
Short name T848
Test name
Test status
Simulation time 448787214 ps
CPU time 1.9 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:34:22 PM PST 23
Peak memory 198588 kb
Host smart-bc9b6eb3-683f-4b6b-ae40-ab6b7d75db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964823474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3964823474
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4033828586
Short name T262
Test name
Test status
Simulation time 15848956743 ps
CPU time 26.84 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:48 PM PST 23
Peak memory 200096 kb
Host smart-e5d33a2e-7037-4877-8d7c-747430e67bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033828586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4033828586
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4231389322
Short name T338
Test name
Test status
Simulation time 104478512215 ps
CPU time 85.12 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:40:20 PM PST 23
Peak memory 200292 kb
Host smart-2bce4071-5fe0-4341-b90d-1debf3d9b52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231389322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4231389322
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.623076760
Short name T213
Test name
Test status
Simulation time 116573645307 ps
CPU time 202.5 seconds
Started Dec 24 01:38:54 PM PST 23
Finished Dec 24 01:42:17 PM PST 23
Peak memory 200060 kb
Host smart-34b67077-c85c-467c-8615-44a49b4f746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623076760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.623076760
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.4000332991
Short name T355
Test name
Test status
Simulation time 53026876625 ps
CPU time 21.14 seconds
Started Dec 24 01:38:56 PM PST 23
Finished Dec 24 01:39:18 PM PST 23
Peak memory 199536 kb
Host smart-5c398219-aae1-4192-ae06-58436cb45b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000332991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.4000332991
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.4010669574
Short name T609
Test name
Test status
Simulation time 180021627400 ps
CPU time 19.66 seconds
Started Dec 24 01:38:55 PM PST 23
Finished Dec 24 01:39:15 PM PST 23
Peak memory 200220 kb
Host smart-3b889dbf-b2d8-41ea-a886-a05cd8871fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010669574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.4010669574
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.731837544
Short name T235
Test name
Test status
Simulation time 22931786091 ps
CPU time 32.89 seconds
Started Dec 24 01:38:57 PM PST 23
Finished Dec 24 01:39:30 PM PST 23
Peak memory 199868 kb
Host smart-432974d7-89d2-475f-9a9f-339c66d1e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731837544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.731837544
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2045160960
Short name T948
Test name
Test status
Simulation time 29651824720 ps
CPU time 11.8 seconds
Started Dec 24 01:38:53 PM PST 23
Finished Dec 24 01:39:05 PM PST 23
Peak memory 200272 kb
Host smart-952a36ed-4749-4560-b793-bb096e4f8b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045160960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2045160960
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3870556257
Short name T1113
Test name
Test status
Simulation time 43019766354 ps
CPU time 83.79 seconds
Started Dec 24 01:39:30 PM PST 23
Finished Dec 24 01:40:55 PM PST 23
Peak memory 199964 kb
Host smart-84a149db-f9c1-41f5-8ee5-a565f60c9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870556257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3870556257
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.385895791
Short name T891
Test name
Test status
Simulation time 110348021840 ps
CPU time 258.05 seconds
Started Dec 24 01:38:58 PM PST 23
Finished Dec 24 01:43:17 PM PST 23
Peak memory 200220 kb
Host smart-fb8dbbe9-a805-4273-9658-9e3b938a680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385895791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.385895791
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.626439891
Short name T631
Test name
Test status
Simulation time 166870235 ps
CPU time 0.56 seconds
Started Dec 24 01:32:22 PM PST 23
Finished Dec 24 01:32:24 PM PST 23
Peak memory 195544 kb
Host smart-13372a42-5c3b-4018-ad31-ae1ded53a322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626439891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.626439891
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3281030808
Short name T349
Test name
Test status
Simulation time 56383359418 ps
CPU time 52.38 seconds
Started Dec 24 01:32:40 PM PST 23
Finished Dec 24 01:33:33 PM PST 23
Peak memory 200220 kb
Host smart-0d7d035f-859c-4bb0-9171-3ff3eb7aece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281030808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3281030808
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3552263192
Short name T221
Test name
Test status
Simulation time 111323713163 ps
CPU time 164.54 seconds
Started Dec 24 01:32:40 PM PST 23
Finished Dec 24 01:35:27 PM PST 23
Peak memory 199732 kb
Host smart-06b93b4c-5b05-42c9-839d-2ceb909dc874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552263192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3552263192
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.856748916
Short name T916
Test name
Test status
Simulation time 14755437460 ps
CPU time 11.59 seconds
Started Dec 24 01:32:19 PM PST 23
Finished Dec 24 01:32:32 PM PST 23
Peak memory 199572 kb
Host smart-81a466cd-4b3a-4aae-9f1c-87b473b73661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856748916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.856748916
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1482247379
Short name T989
Test name
Test status
Simulation time 663865408108 ps
CPU time 692.27 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:44:00 PM PST 23
Peak memory 200228 kb
Host smart-449ca762-968d-46f8-814d-63b10742eea4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482247379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1482247379
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_loopback.2398957953
Short name T1039
Test name
Test status
Simulation time 9119187935 ps
CPU time 12.19 seconds
Started Dec 24 01:32:52 PM PST 23
Finished Dec 24 01:33:04 PM PST 23
Peak memory 199796 kb
Host smart-4b8e3f9a-2b27-4a53-b4a1-b0d4f764307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398957953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2398957953
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.839590879
Short name T711
Test name
Test status
Simulation time 46554275186 ps
CPU time 82.78 seconds
Started Dec 24 01:32:28 PM PST 23
Finished Dec 24 01:33:52 PM PST 23
Peak memory 199664 kb
Host smart-d9a43400-2e29-4bc3-bc7b-194ab4ce670e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839590879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.839590879
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3377184950
Short name T655
Test name
Test status
Simulation time 20227956425 ps
CPU time 407.48 seconds
Started Dec 24 01:32:26 PM PST 23
Finished Dec 24 01:39:14 PM PST 23
Peak memory 200176 kb
Host smart-e9996be7-756a-4a63-950c-e732525e125c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377184950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3377184950
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2621781125
Short name T899
Test name
Test status
Simulation time 921763443 ps
CPU time 3.2 seconds
Started Dec 24 01:32:18 PM PST 23
Finished Dec 24 01:32:24 PM PST 23
Peak memory 197916 kb
Host smart-10b5e80c-8f2d-4d4f-8bc2-4974f41ee311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621781125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2621781125
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1261869926
Short name T449
Test name
Test status
Simulation time 100148789765 ps
CPU time 142.29 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:34:51 PM PST 23
Peak memory 198896 kb
Host smart-cb79fd1a-441f-487f-8e00-ae52febe775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261869926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1261869926
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2908124421
Short name T39
Test name
Test status
Simulation time 2041245658 ps
CPU time 1.92 seconds
Started Dec 24 01:32:28 PM PST 23
Finished Dec 24 01:32:31 PM PST 23
Peak memory 195512 kb
Host smart-f39ae071-f239-4065-804c-8669dc7d5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908124421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2908124421
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1382824489
Short name T103
Test name
Test status
Simulation time 128191756 ps
CPU time 0.79 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:32:29 PM PST 23
Peak memory 218752 kb
Host smart-2a3063ad-a9c2-45b1-a442-2c4ee52f1793
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382824489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1382824489
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3061939787
Short name T616
Test name
Test status
Simulation time 272428383 ps
CPU time 1.11 seconds
Started Dec 24 01:31:56 PM PST 23
Finished Dec 24 01:31:58 PM PST 23
Peak memory 198384 kb
Host smart-0a05ccba-e1f7-4041-9d64-6c7603278efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061939787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3061939787
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1417649465
Short name T29
Test name
Test status
Simulation time 178976707108 ps
CPU time 71.15 seconds
Started Dec 24 01:32:20 PM PST 23
Finished Dec 24 01:33:34 PM PST 23
Peak memory 200244 kb
Host smart-c27cd47f-f7e3-4206-89b0-77770806d052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417649465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1417649465
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3237119366
Short name T915
Test name
Test status
Simulation time 116149095941 ps
CPU time 459.37 seconds
Started Dec 24 01:32:31 PM PST 23
Finished Dec 24 01:40:12 PM PST 23
Peak memory 211224 kb
Host smart-95978129-0c9e-44f5-b4b6-543ef79e9af2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237119366 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3237119366
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1942221426
Short name T679
Test name
Test status
Simulation time 6386495153 ps
CPU time 12.14 seconds
Started Dec 24 01:32:28 PM PST 23
Finished Dec 24 01:32:41 PM PST 23
Peak memory 199664 kb
Host smart-c0b54d93-9980-4baa-833c-1d242e890f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942221426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1942221426
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3618312317
Short name T737
Test name
Test status
Simulation time 118350624176 ps
CPU time 101.71 seconds
Started Dec 24 01:32:05 PM PST 23
Finished Dec 24 01:33:48 PM PST 23
Peak memory 200244 kb
Host smart-deef2e6e-c04e-4d0a-9ac8-046f3c8c48e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618312317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3618312317
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.161143035
Short name T719
Test name
Test status
Simulation time 15532918 ps
CPU time 0.57 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:34:20 PM PST 23
Peak memory 195608 kb
Host smart-49250b3f-9b5b-433e-89ef-e371a2f1306d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161143035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.161143035
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1200216329
Short name T1073
Test name
Test status
Simulation time 203113475353 ps
CPU time 323.49 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:39:46 PM PST 23
Peak memory 200152 kb
Host smart-29b181fe-ce0f-48c9-a910-881a669e6531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200216329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1200216329
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2571561367
Short name T533
Test name
Test status
Simulation time 90977127501 ps
CPU time 62.21 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:35:24 PM PST 23
Peak memory 199616 kb
Host smart-0e003fec-d58e-4bce-bbd8-ea8df3abd916
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571561367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2571561367
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1434228411
Short name T532
Test name
Test status
Simulation time 188530227221 ps
CPU time 292.72 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:39:33 PM PST 23
Peak memory 200232 kb
Host smart-c5b2602a-5453-4928-942e-444a5fc92b9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434228411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1434228411
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1501094925
Short name T1175
Test name
Test status
Simulation time 1622951172 ps
CPU time 0.91 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:34:41 PM PST 23
Peak memory 195880 kb
Host smart-b4890b66-3f1d-4118-ab0e-03dd9e1759f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501094925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1501094925
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1510860820
Short name T936
Test name
Test status
Simulation time 133291792294 ps
CPU time 68.82 seconds
Started Dec 24 01:35:57 PM PST 23
Finished Dec 24 01:37:07 PM PST 23
Peak memory 198620 kb
Host smart-61d5b6ce-8552-49c5-b175-f283bebe27a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510860820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1510860820
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2378700584
Short name T1197
Test name
Test status
Simulation time 9692361445 ps
CPU time 563.8 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:43:46 PM PST 23
Peak memory 199968 kb
Host smart-cac6b879-3dce-490a-b1ed-5d37dc38c437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378700584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2378700584
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2716545546
Short name T736
Test name
Test status
Simulation time 25032360229 ps
CPU time 14.61 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:34:58 PM PST 23
Peak memory 199976 kb
Host smart-a949d385-22f4-4516-916a-959479c0bc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716545546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2716545546
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.88331351
Short name T721
Test name
Test status
Simulation time 43059765083 ps
CPU time 61.23 seconds
Started Dec 24 01:34:34 PM PST 23
Finished Dec 24 01:35:36 PM PST 23
Peak memory 195812 kb
Host smart-ad28abfe-680f-4bb5-83aa-f7b445e6acbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88331351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.88331351
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3181414763
Short name T647
Test name
Test status
Simulation time 855911955 ps
CPU time 2.62 seconds
Started Dec 24 01:34:38 PM PST 23
Finished Dec 24 01:34:43 PM PST 23
Peak memory 198712 kb
Host smart-e3150951-c8a6-4ed6-aacd-836552bd80b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181414763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3181414763
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.154035092
Short name T716
Test name
Test status
Simulation time 155068278890 ps
CPU time 688.59 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:45:50 PM PST 23
Peak memory 200484 kb
Host smart-57f47fbd-fd1c-4681-b877-edc3d1c5da28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154035092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.154035092
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.166123318
Short name T26
Test name
Test status
Simulation time 7160843892 ps
CPU time 93.91 seconds
Started Dec 24 01:34:37 PM PST 23
Finished Dec 24 01:36:13 PM PST 23
Peak memory 200180 kb
Host smart-d0f4727b-a50a-4acf-a267-f0e327f299a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166123318 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.166123318
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1828587347
Short name T643
Test name
Test status
Simulation time 7051433067 ps
CPU time 13.33 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:34 PM PST 23
Peak memory 200172 kb
Host smart-4effe88d-f5a1-46ed-9582-6d861513ed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828587347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1828587347
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3515308039
Short name T1168
Test name
Test status
Simulation time 18711868926 ps
CPU time 27.74 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:34:50 PM PST 23
Peak memory 200164 kb
Host smart-f052cabe-9463-43b2-afdf-20232bf706cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515308039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3515308039
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3303503545
Short name T135
Test name
Test status
Simulation time 164763845141 ps
CPU time 258.03 seconds
Started Dec 24 01:39:30 PM PST 23
Finished Dec 24 01:43:50 PM PST 23
Peak memory 199648 kb
Host smart-3b67a16e-6d4a-4183-a67d-0ddeb3888ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303503545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3303503545
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3713583333
Short name T176
Test name
Test status
Simulation time 143443489416 ps
CPU time 59.85 seconds
Started Dec 24 01:39:17 PM PST 23
Finished Dec 24 01:40:18 PM PST 23
Peak memory 200160 kb
Host smart-6fe9d3c1-f71a-47e8-bc8e-0c374fda1c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713583333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3713583333
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1915853487
Short name T874
Test name
Test status
Simulation time 22116814430 ps
CPU time 45.99 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:40:06 PM PST 23
Peak memory 200176 kb
Host smart-a08c0d6c-0976-4b4d-b18d-7cd0046bef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915853487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1915853487
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1138679360
Short name T147
Test name
Test status
Simulation time 15919476051 ps
CPU time 27.37 seconds
Started Dec 24 01:39:15 PM PST 23
Finished Dec 24 01:39:43 PM PST 23
Peak memory 200144 kb
Host smart-6f1ced89-dce7-460d-a83a-215c6822555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138679360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1138679360
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3086345043
Short name T1019
Test name
Test status
Simulation time 84702065981 ps
CPU time 61.15 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:40:21 PM PST 23
Peak memory 199760 kb
Host smart-18cab426-ed96-4bdd-a90c-aff37d7d0574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086345043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3086345043
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2007982579
Short name T701
Test name
Test status
Simulation time 86159826603 ps
CPU time 133.4 seconds
Started Dec 24 01:39:31 PM PST 23
Finished Dec 24 01:41:49 PM PST 23
Peak memory 200044 kb
Host smart-d583c2dc-8ca9-4c53-b05d-77b641a3afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007982579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2007982579
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1110095464
Short name T266
Test name
Test status
Simulation time 61524760802 ps
CPU time 96.84 seconds
Started Dec 24 01:38:57 PM PST 23
Finished Dec 24 01:40:35 PM PST 23
Peak memory 200164 kb
Host smart-8dbc4ec4-8bad-43cc-bbd4-111960ac9006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110095464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1110095464
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2505048985
Short name T1012
Test name
Test status
Simulation time 36366941 ps
CPU time 0.53 seconds
Started Dec 24 01:34:45 PM PST 23
Finished Dec 24 01:34:47 PM PST 23
Peak memory 195592 kb
Host smart-37683eb1-4f19-4050-b6cf-0a73567b49ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505048985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2505048985
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2518891711
Short name T1210
Test name
Test status
Simulation time 65564226405 ps
CPU time 18.25 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:35:02 PM PST 23
Peak memory 200196 kb
Host smart-a21df95d-f349-4853-a398-3faf8a86b814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518891711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2518891711
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.440017060
Short name T980
Test name
Test status
Simulation time 30631462275 ps
CPU time 11.65 seconds
Started Dec 24 01:34:40 PM PST 23
Finished Dec 24 01:34:54 PM PST 23
Peak memory 199120 kb
Host smart-e9cd54e8-f924-4abd-bafa-196430786b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440017060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.440017060
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.480471817
Short name T240
Test name
Test status
Simulation time 16556717621 ps
CPU time 29.37 seconds
Started Dec 24 01:34:19 PM PST 23
Finished Dec 24 01:34:50 PM PST 23
Peak memory 200160 kb
Host smart-b0ce7c33-c369-4144-aee9-26c6223416b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480471817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.480471817
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1357056771
Short name T968
Test name
Test status
Simulation time 1363002584303 ps
CPU time 1315.8 seconds
Started Dec 24 01:34:18 PM PST 23
Finished Dec 24 01:56:15 PM PST 23
Peak memory 200172 kb
Host smart-06d66964-9889-48b0-a00c-f7d785d21aa2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357056771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1357056771
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.897238447
Short name T1006
Test name
Test status
Simulation time 111941203858 ps
CPU time 659.37 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:45:43 PM PST 23
Peak memory 200276 kb
Host smart-812dba94-11b4-4593-a994-c005ab3bb72e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=897238447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.897238447
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1907797646
Short name T825
Test name
Test status
Simulation time 2084988558 ps
CPU time 2.75 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:34:25 PM PST 23
Peak memory 197100 kb
Host smart-7c01c770-54bf-40b4-b4b7-87cb80a4f881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907797646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1907797646
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.4061539298
Short name T725
Test name
Test status
Simulation time 243968706480 ps
CPU time 43.83 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:35:27 PM PST 23
Peak memory 199204 kb
Host smart-5d1b3be9-5021-4f31-9ffe-fabf12a861cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061539298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4061539298
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.873214356
Short name T877
Test name
Test status
Simulation time 23121941284 ps
CPU time 1333.74 seconds
Started Dec 24 01:34:43 PM PST 23
Finished Dec 24 01:56:58 PM PST 23
Peak memory 200200 kb
Host smart-6e56f517-5ef9-4989-9a01-80007ef740eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873214356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.873214356
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2173340870
Short name T1218
Test name
Test status
Simulation time 269463289 ps
CPU time 0.86 seconds
Started Dec 24 01:35:57 PM PST 23
Finished Dec 24 01:35:59 PM PST 23
Peak memory 194904 kb
Host smart-e53c8d62-99b5-4f6e-a59a-b7ab2a8b3992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173340870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2173340870
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3968867789
Short name T943
Test name
Test status
Simulation time 211630740260 ps
CPU time 790.78 seconds
Started Dec 24 01:34:40 PM PST 23
Finished Dec 24 01:47:53 PM PST 23
Peak memory 200312 kb
Host smart-ce90d98c-5bcd-422e-b572-0babaf2011e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968867789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3968867789
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1520708260
Short name T665
Test name
Test status
Simulation time 4642248809 ps
CPU time 7.3 seconds
Started Dec 24 01:34:35 PM PST 23
Finished Dec 24 01:34:44 PM PST 23
Peak memory 195996 kb
Host smart-9f9f6a4d-e341-4d05-af06-d35ea3b43ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520708260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1520708260
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1585530464
Short name T761
Test name
Test status
Simulation time 470764907 ps
CPU time 2.59 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:34:25 PM PST 23
Peak memory 197940 kb
Host smart-d1e6101f-916e-455c-8611-633b5f2778b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585530464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1585530464
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2792913113
Short name T300
Test name
Test status
Simulation time 589119244557 ps
CPU time 631.95 seconds
Started Dec 24 01:36:42 PM PST 23
Finished Dec 24 01:47:16 PM PST 23
Peak memory 199924 kb
Host smart-1bb803a2-570b-452a-99c7-8d3752a6e8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792913113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2792913113
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.322615802
Short name T404
Test name
Test status
Simulation time 96150823549 ps
CPU time 720.48 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:46:44 PM PST 23
Peak memory 227680 kb
Host smart-0e05214d-77c3-4cb3-92bc-73faa65f8641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322615802 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.322615802
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1039994898
Short name T671
Test name
Test status
Simulation time 302736891 ps
CPU time 1.4 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:34:24 PM PST 23
Peak memory 198272 kb
Host smart-a0e99cfe-4b52-4ba0-8cb2-6d2f86853a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039994898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1039994898
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3244897769
Short name T991
Test name
Test status
Simulation time 65588721160 ps
CPU time 29.98 seconds
Started Dec 24 01:34:20 PM PST 23
Finished Dec 24 01:34:52 PM PST 23
Peak memory 200152 kb
Host smart-02a33546-fae7-474b-b584-637374e23dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244897769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3244897769
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1283829223
Short name T212
Test name
Test status
Simulation time 65790909595 ps
CPU time 120.01 seconds
Started Dec 24 01:39:25 PM PST 23
Finished Dec 24 01:41:26 PM PST 23
Peak memory 200120 kb
Host smart-97c1c3bb-3454-4633-8f8d-3ca659e73986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283829223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1283829223
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1226452938
Short name T591
Test name
Test status
Simulation time 142369214837 ps
CPU time 31.31 seconds
Started Dec 24 01:39:22 PM PST 23
Finished Dec 24 01:39:54 PM PST 23
Peak memory 199480 kb
Host smart-a06d647e-c244-4b51-ba48-a6445267033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226452938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1226452938
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.590922872
Short name T393
Test name
Test status
Simulation time 99794352291 ps
CPU time 127.64 seconds
Started Dec 24 01:39:21 PM PST 23
Finished Dec 24 01:41:29 PM PST 23
Peak memory 200120 kb
Host smart-ffa078fe-14b3-4a6e-8060-7812babeb093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590922872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.590922872
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1237579498
Short name T318
Test name
Test status
Simulation time 20372161992 ps
CPU time 32.88 seconds
Started Dec 24 01:39:23 PM PST 23
Finished Dec 24 01:39:57 PM PST 23
Peak memory 199644 kb
Host smart-ed8c2ff6-749f-4a24-85a4-c73cabba3de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237579498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1237579498
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2439706259
Short name T854
Test name
Test status
Simulation time 159867424173 ps
CPU time 32.98 seconds
Started Dec 24 01:39:36 PM PST 23
Finished Dec 24 01:40:18 PM PST 23
Peak memory 199820 kb
Host smart-e716e082-7b51-4def-ac4a-021b9634aefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439706259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2439706259
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1842484356
Short name T1215
Test name
Test status
Simulation time 35448879590 ps
CPU time 56.28 seconds
Started Dec 24 01:39:23 PM PST 23
Finished Dec 24 01:40:20 PM PST 23
Peak memory 200112 kb
Host smart-40c2851e-86d4-4b4c-8a5f-8e6710976f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842484356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1842484356
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2098680864
Short name T129
Test name
Test status
Simulation time 47271629321 ps
CPU time 36.65 seconds
Started Dec 24 01:39:35 PM PST 23
Finished Dec 24 01:40:18 PM PST 23
Peak memory 200248 kb
Host smart-34681d99-3290-4ab3-b5a1-8e97708d0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098680864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2098680864
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2830148615
Short name T296
Test name
Test status
Simulation time 18199487693 ps
CPU time 29.44 seconds
Started Dec 24 01:39:35 PM PST 23
Finished Dec 24 01:40:11 PM PST 23
Peak memory 199292 kb
Host smart-7b6c3f0f-4e14-444d-ac8d-17b2913c5870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830148615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2830148615
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.326561621
Short name T850
Test name
Test status
Simulation time 107251329 ps
CPU time 0.56 seconds
Started Dec 24 01:34:43 PM PST 23
Finished Dec 24 01:34:44 PM PST 23
Peak memory 194600 kb
Host smart-3bd2d865-5996-4a51-9870-8f8640ddfbba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326561621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.326561621
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.4020134847
Short name T939
Test name
Test status
Simulation time 300972323160 ps
CPU time 301.39 seconds
Started Dec 24 01:36:42 PM PST 23
Finished Dec 24 01:41:46 PM PST 23
Peak memory 199852 kb
Host smart-db1053f1-5044-4d85-b6a5-4cf7284b49aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020134847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4020134847
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.544346764
Short name T403
Test name
Test status
Simulation time 31449208249 ps
CPU time 47.63 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:35:31 PM PST 23
Peak memory 200184 kb
Host smart-63e723a1-0343-4172-9f3e-d841d28987ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544346764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.544346764
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2549900863
Short name T1153
Test name
Test status
Simulation time 254761222288 ps
CPU time 101.4 seconds
Started Dec 24 01:36:42 PM PST 23
Finished Dec 24 01:38:26 PM PST 23
Peak memory 199572 kb
Host smart-337dd54a-62e6-4b65-942f-a2845351542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549900863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2549900863
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2624428055
Short name T1117
Test name
Test status
Simulation time 50579105440 ps
CPU time 89.78 seconds
Started Dec 24 01:34:41 PM PST 23
Finished Dec 24 01:36:13 PM PST 23
Peak memory 200064 kb
Host smart-bc62966c-e0f1-4e5d-b7b9-1763b3082ce2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624428055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2624428055
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3176667126
Short name T11
Test name
Test status
Simulation time 86634435148 ps
CPU time 108.26 seconds
Started Dec 24 01:34:44 PM PST 23
Finished Dec 24 01:36:33 PM PST 23
Peak memory 200156 kb
Host smart-a5497ba7-6827-4906-9fec-3c4d7e89044b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176667126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3176667126
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3611360350
Short name T553
Test name
Test status
Simulation time 10394882002 ps
CPU time 24.5 seconds
Started Dec 24 01:36:17 PM PST 23
Finished Dec 24 01:36:43 PM PST 23
Peak memory 197100 kb
Host smart-fb0e72fc-d4d9-41ab-a27c-a211bad7aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611360350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3611360350
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2644836678
Short name T634
Test name
Test status
Simulation time 74024015547 ps
CPU time 122.62 seconds
Started Dec 24 01:34:43 PM PST 23
Finished Dec 24 01:36:47 PM PST 23
Peak memory 208728 kb
Host smart-38dc7af5-35cb-44ff-b105-732ccb5e5750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644836678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2644836678
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1734876020
Short name T605
Test name
Test status
Simulation time 10787030945 ps
CPU time 478.7 seconds
Started Dec 24 01:36:42 PM PST 23
Finished Dec 24 01:44:42 PM PST 23
Peak memory 199956 kb
Host smart-8320edd1-d4d2-4812-8fa4-2883a38ce12e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734876020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1734876020
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3281884665
Short name T1032
Test name
Test status
Simulation time 3623468377 ps
CPU time 37.36 seconds
Started Dec 24 01:34:43 PM PST 23
Finished Dec 24 01:35:22 PM PST 23
Peak memory 199088 kb
Host smart-6f0b0937-02c6-449e-93a2-3b24a8b8515b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281884665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3281884665
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3701044441
Short name T389
Test name
Test status
Simulation time 27032986717 ps
CPU time 40.86 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:35:24 PM PST 23
Peak memory 200192 kb
Host smart-50368dc0-9b08-4bc0-b306-4f46a837d7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701044441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3701044441
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3330461425
Short name T793
Test name
Test status
Simulation time 4800384666 ps
CPU time 4.72 seconds
Started Dec 24 01:36:17 PM PST 23
Finished Dec 24 01:36:23 PM PST 23
Peak memory 193520 kb
Host smart-4a4496c5-155b-4403-90f8-18ead60d79de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330461425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3330461425
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.817615570
Short name T525
Test name
Test status
Simulation time 741411609 ps
CPU time 1.43 seconds
Started Dec 24 01:36:42 PM PST 23
Finished Dec 24 01:36:45 PM PST 23
Peak memory 198412 kb
Host smart-7544d626-8c36-4ba5-9b7f-bf9d69c42972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817615570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.817615570
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1015130913
Short name T769
Test name
Test status
Simulation time 38349707284 ps
CPU time 252.69 seconds
Started Dec 24 01:34:43 PM PST 23
Finished Dec 24 01:38:57 PM PST 23
Peak memory 216332 kb
Host smart-60f20818-e83f-4a71-b585-4231fc6c78c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015130913 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1015130913
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.913203389
Short name T801
Test name
Test status
Simulation time 3453821185 ps
CPU time 2.3 seconds
Started Dec 24 01:36:42 PM PST 23
Finished Dec 24 01:36:47 PM PST 23
Peak memory 198140 kb
Host smart-1f5b1fbc-37d2-48e1-b136-a4f11b0d0bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913203389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.913203389
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2033842708
Short name T1181
Test name
Test status
Simulation time 68765638960 ps
CPU time 36.21 seconds
Started Dec 24 01:34:45 PM PST 23
Finished Dec 24 01:35:22 PM PST 23
Peak memory 200108 kb
Host smart-97befd13-5bcf-47f2-ac16-f1ea72ba27d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033842708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2033842708
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.4161133203
Short name T165
Test name
Test status
Simulation time 14898428772 ps
CPU time 23.23 seconds
Started Dec 24 01:39:15 PM PST 23
Finished Dec 24 01:39:39 PM PST 23
Peak memory 200280 kb
Host smart-aedc1597-6f76-403f-a51b-afd2968ccd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161133203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4161133203
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.11726619
Short name T265
Test name
Test status
Simulation time 34002531919 ps
CPU time 45.3 seconds
Started Dec 24 01:39:17 PM PST 23
Finished Dec 24 01:40:03 PM PST 23
Peak memory 199716 kb
Host smart-f696cf2f-b20d-453e-b27c-0f5458e788f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11726619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.11726619
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4261026268
Short name T184
Test name
Test status
Simulation time 61315779806 ps
CPU time 26.09 seconds
Started Dec 24 01:39:18 PM PST 23
Finished Dec 24 01:39:45 PM PST 23
Peak memory 200176 kb
Host smart-b2106c57-f42e-4e2b-80b2-d6bf4de76b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261026268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4261026268
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3893673390
Short name T347
Test name
Test status
Simulation time 55597843611 ps
CPU time 29.53 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:39:50 PM PST 23
Peak memory 200228 kb
Host smart-a5bfb32f-258b-47a5-b280-652815eaf214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893673390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3893673390
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2398658756
Short name T324
Test name
Test status
Simulation time 148127475600 ps
CPU time 45.94 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:40:06 PM PST 23
Peak memory 200236 kb
Host smart-7784e1f6-f4a6-4d9d-9c75-c8be3ea8cd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398658756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2398658756
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.944136355
Short name T264
Test name
Test status
Simulation time 62366246688 ps
CPU time 107.49 seconds
Started Dec 24 01:39:20 PM PST 23
Finished Dec 24 01:41:09 PM PST 23
Peak memory 199968 kb
Host smart-53c211a5-a93f-4bc6-b8b3-6d7d6fe2f33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944136355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.944136355
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2258877421
Short name T1054
Test name
Test status
Simulation time 16756598777 ps
CPU time 23.39 seconds
Started Dec 24 01:39:22 PM PST 23
Finished Dec 24 01:39:47 PM PST 23
Peak memory 200212 kb
Host smart-351b6267-3644-42b5-8b6d-848b213a7492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258877421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2258877421
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2132016904
Short name T142
Test name
Test status
Simulation time 19206445523 ps
CPU time 14.65 seconds
Started Dec 24 01:39:20 PM PST 23
Finished Dec 24 01:39:36 PM PST 23
Peak memory 200292 kb
Host smart-ccca5091-521b-40f4-b359-d57172202c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132016904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2132016904
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1121035377
Short name T269
Test name
Test status
Simulation time 122042131580 ps
CPU time 101.32 seconds
Started Dec 24 01:39:18 PM PST 23
Finished Dec 24 01:41:00 PM PST 23
Peak memory 200140 kb
Host smart-f6f905e4-935c-4919-96ea-baa71a7871f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121035377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1121035377
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.83119931
Short name T1142
Test name
Test status
Simulation time 57211186 ps
CPU time 0.56 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:34:57 PM PST 23
Peak memory 195616 kb
Host smart-3d9ef5b0-3a75-4efa-aef0-21b0c94945de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83119931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.83119931
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.4239439098
Short name T1030
Test name
Test status
Simulation time 218233858519 ps
CPU time 23.8 seconds
Started Dec 24 01:34:44 PM PST 23
Finished Dec 24 01:35:09 PM PST 23
Peak memory 200340 kb
Host smart-83ee796c-bdab-4b1d-a716-ee0e781f34dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239439098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.4239439098
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2393445916
Short name T171
Test name
Test status
Simulation time 166356111150 ps
CPU time 78.91 seconds
Started Dec 24 01:34:44 PM PST 23
Finished Dec 24 01:36:04 PM PST 23
Peak memory 200216 kb
Host smart-6ab5d7bc-0272-4d99-9da7-a45a3972a176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393445916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2393445916
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.623443700
Short name T1020
Test name
Test status
Simulation time 620887673098 ps
CPU time 814.84 seconds
Started Dec 24 01:36:42 PM PST 23
Finished Dec 24 01:50:19 PM PST 23
Peak memory 199772 kb
Host smart-ae4bfdf8-a1f8-49db-ba29-1e01ea5f6f2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623443700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.623443700
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3644240929
Short name T796
Test name
Test status
Simulation time 44264788661 ps
CPU time 294.99 seconds
Started Dec 24 01:34:53 PM PST 23
Finished Dec 24 01:39:56 PM PST 23
Peak memory 200076 kb
Host smart-794ce2ad-e3f0-4b1d-a804-07796eec03e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644240929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3644240929
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3199890410
Short name T814
Test name
Test status
Simulation time 2266762424 ps
CPU time 1.7 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:34:58 PM PST 23
Peak memory 196888 kb
Host smart-1404dea6-7257-44ff-9de8-bb89515e67dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199890410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3199890410
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1073694622
Short name T1143
Test name
Test status
Simulation time 181961289226 ps
CPU time 169.87 seconds
Started Dec 24 01:34:44 PM PST 23
Finished Dec 24 01:37:34 PM PST 23
Peak memory 200464 kb
Host smart-e7ed0b4b-feca-42f0-9d43-22ab540c1df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073694622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1073694622
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3063765990
Short name T120
Test name
Test status
Simulation time 14509394443 ps
CPU time 420.18 seconds
Started Dec 24 01:35:11 PM PST 23
Finished Dec 24 01:42:12 PM PST 23
Peak memory 200184 kb
Host smart-34d12486-a0f3-43e2-9cde-87094fb762cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063765990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3063765990
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2328914374
Short name T587
Test name
Test status
Simulation time 1507559179 ps
CPU time 2.49 seconds
Started Dec 24 01:34:45 PM PST 23
Finished Dec 24 01:34:49 PM PST 23
Peak memory 198060 kb
Host smart-04f96f65-cd20-4a27-92ff-d0665ef2f293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328914374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2328914374
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2329706697
Short name T441
Test name
Test status
Simulation time 178515806228 ps
CPU time 266.26 seconds
Started Dec 24 01:34:45 PM PST 23
Finished Dec 24 01:39:12 PM PST 23
Peak memory 200176 kb
Host smart-1ce2e37d-335c-48be-b211-4b07aa5dd44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329706697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2329706697
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3537228645
Short name T879
Test name
Test status
Simulation time 2908631831 ps
CPU time 5.28 seconds
Started Dec 24 01:34:42 PM PST 23
Finished Dec 24 01:34:49 PM PST 23
Peak memory 195676 kb
Host smart-93afc99f-d784-4825-b1f5-a1c639a9529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537228645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3537228645
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3455143729
Short name T1180
Test name
Test status
Simulation time 429898072 ps
CPU time 1.14 seconds
Started Dec 24 01:34:44 PM PST 23
Finished Dec 24 01:34:46 PM PST 23
Peak memory 197992 kb
Host smart-5ce61091-b0ca-4121-8bbe-db8e20d0ec0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455143729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3455143729
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3554904834
Short name T1114
Test name
Test status
Simulation time 49719103483 ps
CPU time 572.11 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:44:24 PM PST 23
Peak memory 216684 kb
Host smart-3e66190d-98d3-438a-967f-ceb066be456e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554904834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3554904834
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2346433042
Short name T517
Test name
Test status
Simulation time 671591283 ps
CPU time 2.52 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:34:59 PM PST 23
Peak memory 198296 kb
Host smart-54d47c77-f356-4205-8d76-b8754a302f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346433042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2346433042
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3619001026
Short name T938
Test name
Test status
Simulation time 42303695761 ps
CPU time 15.16 seconds
Started Dec 24 01:34:40 PM PST 23
Finished Dec 24 01:34:57 PM PST 23
Peak memory 197048 kb
Host smart-7582a3fa-e0c4-4af5-8449-99afa9a15c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619001026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3619001026
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.643082724
Short name T126
Test name
Test status
Simulation time 95750968120 ps
CPU time 132.07 seconds
Started Dec 24 01:39:15 PM PST 23
Finished Dec 24 01:41:27 PM PST 23
Peak memory 200140 kb
Host smart-0b8816e2-76a8-4ccb-964d-3e8a344bffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643082724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.643082724
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1305130296
Short name T208
Test name
Test status
Simulation time 123443111340 ps
CPU time 29.54 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:39:50 PM PST 23
Peak memory 200228 kb
Host smart-988438b3-5a7f-406c-9d89-034a4a11c45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305130296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1305130296
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.750580692
Short name T803
Test name
Test status
Simulation time 31826405223 ps
CPU time 12.93 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:39:32 PM PST 23
Peak memory 200192 kb
Host smart-f71dffaa-aee9-45f1-8fa8-65331512cb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750580692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.750580692
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2233387144
Short name T707
Test name
Test status
Simulation time 48821295229 ps
CPU time 83.85 seconds
Started Dec 24 01:39:18 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 200192 kb
Host smart-ae89753f-33bd-4422-bebf-121c2d9f7fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233387144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2233387144
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2447324489
Short name T278
Test name
Test status
Simulation time 70405180798 ps
CPU time 33.92 seconds
Started Dec 24 01:39:16 PM PST 23
Finished Dec 24 01:39:51 PM PST 23
Peak memory 200180 kb
Host smart-895152e7-4fd1-4ff0-8497-ee5137824d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447324489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2447324489
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3867688323
Short name T1179
Test name
Test status
Simulation time 15899331995 ps
CPU time 23.14 seconds
Started Dec 24 01:39:15 PM PST 23
Finished Dec 24 01:39:39 PM PST 23
Peak memory 199980 kb
Host smart-61e9ff4c-cf74-4708-971b-7891b15bbdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867688323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3867688323
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2571820725
Short name T832
Test name
Test status
Simulation time 24190309253 ps
CPU time 13.74 seconds
Started Dec 24 01:39:17 PM PST 23
Finished Dec 24 01:39:31 PM PST 23
Peak memory 200204 kb
Host smart-a3a6c5b8-1e3b-4035-a956-55ad9413e82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571820725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2571820725
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1239078
Short name T155
Test name
Test status
Simulation time 50675575096 ps
CPU time 173.64 seconds
Started Dec 24 01:39:23 PM PST 23
Finished Dec 24 01:42:18 PM PST 23
Peak memory 200096 kb
Host smart-21b47840-2418-4886-ac6c-67a07673163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1239078
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2526598101
Short name T789
Test name
Test status
Simulation time 18620329 ps
CPU time 0.55 seconds
Started Dec 24 01:34:55 PM PST 23
Finished Dec 24 01:35:02 PM PST 23
Peak memory 194700 kb
Host smart-eae90306-44a5-49e8-823b-c64ff8ab725d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526598101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2526598101
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1734074941
Short name T543
Test name
Test status
Simulation time 21372759958 ps
CPU time 9.21 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:35:05 PM PST 23
Peak memory 199332 kb
Host smart-c9062061-df48-4c9a-8e76-d99820911633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734074941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1734074941
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2723797286
Short name T993
Test name
Test status
Simulation time 145584930891 ps
CPU time 240.24 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:38:52 PM PST 23
Peak memory 200152 kb
Host smart-9cda8fc7-e9fa-49f5-9271-25e53ae5ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723797286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2723797286
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.882516686
Short name T670
Test name
Test status
Simulation time 28717145467 ps
CPU time 12.23 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:35:06 PM PST 23
Peak memory 200192 kb
Host smart-dcec9e9e-6be2-4cf3-b27b-6b68ac0b2aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882516686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.882516686
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3660716703
Short name T731
Test name
Test status
Simulation time 461972178232 ps
CPU time 227.28 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:38:43 PM PST 23
Peak memory 200064 kb
Host smart-8be14445-d30c-4d2b-ab35-249bca884017
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660716703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3660716703
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.936453909
Short name T677
Test name
Test status
Simulation time 188399504185 ps
CPU time 251.34 seconds
Started Dec 24 01:34:50 PM PST 23
Finished Dec 24 01:39:02 PM PST 23
Peak memory 200288 kb
Host smart-61fbdb1e-ab54-4c04-81e1-f327a5e87d52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936453909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.936453909
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3003754584
Short name T895
Test name
Test status
Simulation time 3308892883 ps
CPU time 7.17 seconds
Started Dec 24 01:35:10 PM PST 23
Finished Dec 24 01:35:18 PM PST 23
Peak memory 199324 kb
Host smart-31d9cfb2-9cf5-42b4-b6db-c7495ebea333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003754584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3003754584
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3860243115
Short name T593
Test name
Test status
Simulation time 169497792149 ps
CPU time 68.02 seconds
Started Dec 24 01:36:42 PM PST 23
Finished Dec 24 01:37:52 PM PST 23
Peak memory 199760 kb
Host smart-40163f0a-6273-4db4-96fe-9d1fd0427498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860243115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3860243115
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.186217994
Short name T806
Test name
Test status
Simulation time 6731407586 ps
CPU time 163.77 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:37:36 PM PST 23
Peak memory 200200 kb
Host smart-67990cf9-56d6-4923-8b62-2425d83f3a7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186217994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.186217994
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1545429637
Short name T1195
Test name
Test status
Simulation time 1480334432 ps
CPU time 2.91 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:34:59 PM PST 23
Peak memory 197696 kb
Host smart-8c172ad4-d2ec-444f-8f5e-e09e3b4afce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545429637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1545429637
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2109451314
Short name T834
Test name
Test status
Simulation time 504960145302 ps
CPU time 74.7 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:36:11 PM PST 23
Peak memory 200016 kb
Host smart-7865952e-28ef-470e-9258-a88b4dad1d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109451314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2109451314
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.246833894
Short name T835
Test name
Test status
Simulation time 40362462651 ps
CPU time 18.18 seconds
Started Dec 24 01:34:50 PM PST 23
Finished Dec 24 01:35:10 PM PST 23
Peak memory 195916 kb
Host smart-7d2e641a-0248-4eef-b6ff-5d41649bfec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246833894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.246833894
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.122225757
Short name T1222
Test name
Test status
Simulation time 685970755 ps
CPU time 1.7 seconds
Started Dec 24 01:34:53 PM PST 23
Finished Dec 24 01:35:03 PM PST 23
Peak memory 198584 kb
Host smart-21073c76-7452-4b61-acf0-6b110cbfa257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122225757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.122225757
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.4069091970
Short name T909
Test name
Test status
Simulation time 333347283084 ps
CPU time 158.7 seconds
Started Dec 24 01:35:09 PM PST 23
Finished Dec 24 01:37:49 PM PST 23
Peak memory 200236 kb
Host smart-39061ddf-4f73-4aa9-b31a-27803b62a62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069091970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.4069091970
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4086633888
Short name T69
Test name
Test status
Simulation time 19911470305 ps
CPU time 170.86 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:37:43 PM PST 23
Peak memory 216524 kb
Host smart-c9afd1a3-7d3d-430a-b494-53d3531ceacf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086633888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4086633888
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.449407164
Short name T1009
Test name
Test status
Simulation time 6672762594 ps
CPU time 24.78 seconds
Started Dec 24 01:34:50 PM PST 23
Finished Dec 24 01:35:16 PM PST 23
Peak memory 199848 kb
Host smart-4a72c2b7-ae98-4481-849f-4c3ebce273b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449407164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.449407164
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3961356736
Short name T1160
Test name
Test status
Simulation time 33134373946 ps
CPU time 50.95 seconds
Started Dec 24 01:36:17 PM PST 23
Finished Dec 24 01:37:09 PM PST 23
Peak memory 197552 kb
Host smart-290390e0-f99d-4000-966d-aacf47e015f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961356736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3961356736
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.195870957
Short name T339
Test name
Test status
Simulation time 21987440836 ps
CPU time 19.3 seconds
Started Dec 24 01:39:17 PM PST 23
Finished Dec 24 01:39:37 PM PST 23
Peak memory 200228 kb
Host smart-a37d09f5-83af-4b8b-86c8-576c52ce65e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195870957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.195870957
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.603768252
Short name T599
Test name
Test status
Simulation time 161438252257 ps
CPU time 150.64 seconds
Started Dec 24 01:39:18 PM PST 23
Finished Dec 24 01:41:49 PM PST 23
Peak memory 200220 kb
Host smart-58e8be97-3b6b-4705-ab55-22a21f8d6aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603768252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.603768252
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2193972334
Short name T365
Test name
Test status
Simulation time 98140159066 ps
CPU time 25.27 seconds
Started Dec 24 01:39:18 PM PST 23
Finished Dec 24 01:39:44 PM PST 23
Peak memory 200232 kb
Host smart-fd6619ff-9bef-40cd-b075-37d8a0f476db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193972334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2193972334
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1039626238
Short name T140
Test name
Test status
Simulation time 228865161358 ps
CPU time 48.56 seconds
Started Dec 24 01:39:30 PM PST 23
Finished Dec 24 01:40:20 PM PST 23
Peak memory 199920 kb
Host smart-0b43f402-5a31-464f-afca-3db8c72b1e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039626238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1039626238
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2497541014
Short name T674
Test name
Test status
Simulation time 127225514539 ps
CPU time 116.63 seconds
Started Dec 24 01:39:31 PM PST 23
Finished Dec 24 01:41:28 PM PST 23
Peak memory 199984 kb
Host smart-ff9e835e-ba6f-4e3d-88c3-db8cabc1948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497541014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2497541014
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.626895395
Short name T172
Test name
Test status
Simulation time 96329437571 ps
CPU time 170.96 seconds
Started Dec 24 01:39:31 PM PST 23
Finished Dec 24 01:42:23 PM PST 23
Peak memory 200032 kb
Host smart-58cbded7-c577-4283-8521-ed9eb739e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626895395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.626895395
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2097864004
Short name T805
Test name
Test status
Simulation time 100542837589 ps
CPU time 180.76 seconds
Started Dec 24 01:39:36 PM PST 23
Finished Dec 24 01:42:45 PM PST 23
Peak memory 199636 kb
Host smart-150a95f0-7749-4659-ab92-0aed9601cb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097864004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2097864004
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3453854958
Short name T698
Test name
Test status
Simulation time 43192252 ps
CPU time 0.56 seconds
Started Dec 24 01:35:01 PM PST 23
Finished Dec 24 01:35:05 PM PST 23
Peak memory 195648 kb
Host smart-19ec14ba-1735-4a24-a2d1-ba9a567690b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453854958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3453854958
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.965053172
Short name T963
Test name
Test status
Simulation time 17130109332 ps
CPU time 30.46 seconds
Started Dec 24 01:34:50 PM PST 23
Finished Dec 24 01:35:22 PM PST 23
Peak memory 200040 kb
Host smart-6d61bb8c-18ea-46c0-b1e9-b36f412192a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965053172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.965053172
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1943407130
Short name T109
Test name
Test status
Simulation time 15615266307 ps
CPU time 25.5 seconds
Started Dec 24 01:35:09 PM PST 23
Finished Dec 24 01:35:36 PM PST 23
Peak memory 198768 kb
Host smart-00d92b13-9ca1-4847-809d-a22ca0c84042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943407130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1943407130
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1192188557
Short name T207
Test name
Test status
Simulation time 65925109811 ps
CPU time 14.6 seconds
Started Dec 24 01:34:55 PM PST 23
Finished Dec 24 01:35:16 PM PST 23
Peak memory 200192 kb
Host smart-911e4202-5ef5-4aa4-927f-d5844478d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192188557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1192188557
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3332358703
Short name T546
Test name
Test status
Simulation time 140632649656 ps
CPU time 189.79 seconds
Started Dec 24 01:35:00 PM PST 23
Finished Dec 24 01:38:15 PM PST 23
Peak memory 200276 kb
Host smart-12e88c12-bc9c-4a45-83bf-f532a6b4367f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332358703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3332358703
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3537575084
Short name T813
Test name
Test status
Simulation time 162177351929 ps
CPU time 1307.11 seconds
Started Dec 24 01:34:53 PM PST 23
Finished Dec 24 01:56:49 PM PST 23
Peak memory 200208 kb
Host smart-042a143a-024e-4a41-8858-0076e97431f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537575084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3537575084
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.899667571
Short name T502
Test name
Test status
Simulation time 2936151428 ps
CPU time 4.7 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:35:04 PM PST 23
Peak memory 195892 kb
Host smart-2856af72-ac65-4d89-96f3-4043039f1799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899667571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.899667571
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.31987711
Short name T759
Test name
Test status
Simulation time 24847229268 ps
CPU time 38.63 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:35:35 PM PST 23
Peak memory 198224 kb
Host smart-3263b275-66b1-439f-8e3b-87d4d9829b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31987711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.31987711
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1617618841
Short name T685
Test name
Test status
Simulation time 24928239430 ps
CPU time 1195.59 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:54:48 PM PST 23
Peak memory 200196 kb
Host smart-bd4130f0-0dc2-4168-b8b1-7d0949861e93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617618841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1617618841
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3236494809
Short name T1225
Test name
Test status
Simulation time 102603394524 ps
CPU time 205.16 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:38:21 PM PST 23
Peak memory 199680 kb
Host smart-99c602e8-f3e1-4418-a533-1c09e1cc7530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236494809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3236494809
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3839396650
Short name T751
Test name
Test status
Simulation time 4159217169 ps
CPU time 2.3 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:34:58 PM PST 23
Peak memory 196112 kb
Host smart-e21dd6f8-9e9e-4edc-a876-0ab24eeaf515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839396650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3839396650
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.274271075
Short name T1191
Test name
Test status
Simulation time 897328750 ps
CPU time 4 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:34:57 PM PST 23
Peak memory 198580 kb
Host smart-00dc0bab-f7b5-40d9-8d33-48722c72a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274271075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.274271075
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.4170704939
Short name T1040
Test name
Test status
Simulation time 237372850083 ps
CPU time 94.96 seconds
Started Dec 24 01:35:08 PM PST 23
Finished Dec 24 01:36:44 PM PST 23
Peak memory 200200 kb
Host smart-33636f4d-a801-41e0-9351-17ae753535d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170704939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.4170704939
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1085753657
Short name T446
Test name
Test status
Simulation time 126542031542 ps
CPU time 307.72 seconds
Started Dec 24 01:35:09 PM PST 23
Finished Dec 24 01:40:17 PM PST 23
Peak memory 208712 kb
Host smart-c12ece61-fb1c-4c66-9e27-406e124674e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085753657 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1085753657
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4233442007
Short name T562
Test name
Test status
Simulation time 998534344 ps
CPU time 2.53 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:34:57 PM PST 23
Peak memory 199528 kb
Host smart-83f6d36a-9c18-4ba5-8528-55f3fde93a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233442007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4233442007
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.436882835
Short name T463
Test name
Test status
Simulation time 14038141704 ps
CPU time 10.82 seconds
Started Dec 24 01:34:51 PM PST 23
Finished Dec 24 01:35:03 PM PST 23
Peak memory 196916 kb
Host smart-c9237948-60d3-4443-a10c-91f177853f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436882835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.436882835
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1431247472
Short name T271
Test name
Test status
Simulation time 33941893437 ps
CPU time 16.1 seconds
Started Dec 24 01:39:22 PM PST 23
Finished Dec 24 01:39:39 PM PST 23
Peak memory 199296 kb
Host smart-85ac6109-a3d1-4608-a297-4df4b70a0efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431247472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1431247472
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2291190349
Short name T127
Test name
Test status
Simulation time 22697141448 ps
CPU time 40.87 seconds
Started Dec 24 01:39:35 PM PST 23
Finished Dec 24 01:40:23 PM PST 23
Peak memory 200124 kb
Host smart-8dcb547e-f11f-488f-a19f-fa2ca8a0738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291190349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2291190349
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.930976278
Short name T224
Test name
Test status
Simulation time 104605851548 ps
CPU time 30 seconds
Started Dec 24 01:39:24 PM PST 23
Finished Dec 24 01:39:55 PM PST 23
Peak memory 200120 kb
Host smart-741053e8-0730-4d86-962c-70b78369b155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930976278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.930976278
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.503362408
Short name T690
Test name
Test status
Simulation time 224675538241 ps
CPU time 68.57 seconds
Started Dec 24 01:39:35 PM PST 23
Finished Dec 24 01:40:51 PM PST 23
Peak memory 200184 kb
Host smart-a56f83b7-b003-40fd-b4c1-b6427df9242d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503362408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.503362408
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.852832580
Short name T870
Test name
Test status
Simulation time 173073022917 ps
CPU time 56.24 seconds
Started Dec 24 01:39:35 PM PST 23
Finished Dec 24 01:40:38 PM PST 23
Peak memory 200168 kb
Host smart-bcd9f205-6e64-4725-90e3-7f7b92ce0239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852832580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.852832580
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3970642285
Short name T346
Test name
Test status
Simulation time 42693961722 ps
CPU time 17.33 seconds
Started Dec 24 01:39:23 PM PST 23
Finished Dec 24 01:39:41 PM PST 23
Peak memory 199904 kb
Host smart-a638c3ff-1ac1-4f2c-9621-6280db864dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970642285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3970642285
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.344789656
Short name T152
Test name
Test status
Simulation time 179143173183 ps
CPU time 396.49 seconds
Started Dec 24 01:39:37 PM PST 23
Finished Dec 24 01:46:22 PM PST 23
Peak memory 200228 kb
Host smart-3160baf0-4be1-4a0b-9843-af46e73a0b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344789656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.344789656
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1968570761
Short name T1016
Test name
Test status
Simulation time 103171056 ps
CPU time 0.55 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:35:28 PM PST 23
Peak memory 194700 kb
Host smart-6291a7d0-bd7c-4756-b445-82873e061f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968570761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1968570761
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3693924657
Short name T754
Test name
Test status
Simulation time 101902460148 ps
CPU time 28.36 seconds
Started Dec 24 01:35:11 PM PST 23
Finished Dec 24 01:35:40 PM PST 23
Peak memory 200248 kb
Host smart-75f98afd-35b5-4cee-ac85-dd10aa048778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693924657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3693924657
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1342225841
Short name T550
Test name
Test status
Simulation time 31683211259 ps
CPU time 18.68 seconds
Started Dec 24 01:34:55 PM PST 23
Finished Dec 24 01:35:20 PM PST 23
Peak memory 200144 kb
Host smart-728c8bf2-f6cf-4c2e-8664-e5ef665e51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342225841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1342225841
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1849747577
Short name T378
Test name
Test status
Simulation time 29970947492 ps
CPU time 28 seconds
Started Dec 24 01:34:53 PM PST 23
Finished Dec 24 01:35:28 PM PST 23
Peak memory 200268 kb
Host smart-79b995c0-2332-45ec-8e74-6f7e34fbf58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849747577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1849747577
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2802343035
Short name T999
Test name
Test status
Simulation time 1200584089788 ps
CPU time 1038.39 seconds
Started Dec 24 01:34:55 PM PST 23
Finished Dec 24 01:52:20 PM PST 23
Peak memory 200184 kb
Host smart-926af7b9-3d3b-4a2d-ab85-f95ded49708b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802343035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2802343035
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2453957900
Short name T917
Test name
Test status
Simulation time 100963485637 ps
CPU time 270.61 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:39:58 PM PST 23
Peak memory 200156 kb
Host smart-9e70a476-f58d-466a-b465-94a7afc51b16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453957900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2453957900
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4016818079
Short name T779
Test name
Test status
Simulation time 8477043299 ps
CPU time 15.68 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:35:12 PM PST 23
Peak memory 200188 kb
Host smart-aa366311-b7f1-4bf9-8b60-26ea255f60a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016818079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4016818079
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1611165470
Short name T1126
Test name
Test status
Simulation time 125895681046 ps
CPU time 301.9 seconds
Started Dec 24 01:34:54 PM PST 23
Finished Dec 24 01:40:04 PM PST 23
Peak memory 208632 kb
Host smart-7302681d-2779-4a29-ab61-eecc3a9e0ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611165470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1611165470
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2953207290
Short name T902
Test name
Test status
Simulation time 25715081680 ps
CPU time 329.52 seconds
Started Dec 24 01:34:54 PM PST 23
Finished Dec 24 01:40:31 PM PST 23
Peak memory 200152 kb
Host smart-196aeb0b-7e5b-4d1f-b0dd-0b02be3e6fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953207290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2953207290
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1102221162
Short name T195
Test name
Test status
Simulation time 147708567249 ps
CPU time 72.7 seconds
Started Dec 24 01:34:53 PM PST 23
Finished Dec 24 01:36:14 PM PST 23
Peak memory 200372 kb
Host smart-29566c45-2320-456b-a703-d419c98299b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102221162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1102221162
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3970093701
Short name T788
Test name
Test status
Simulation time 4508138317 ps
CPU time 3.04 seconds
Started Dec 24 01:35:08 PM PST 23
Finished Dec 24 01:35:12 PM PST 23
Peak memory 196104 kb
Host smart-e3d49951-cbc2-4d8e-9e3a-ecc5fd0caad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970093701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3970093701
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.53996919
Short name T667
Test name
Test status
Simulation time 679069095 ps
CPU time 1.34 seconds
Started Dec 24 01:34:53 PM PST 23
Finished Dec 24 01:35:03 PM PST 23
Peak memory 199096 kb
Host smart-d6357b26-550d-400a-87c3-27ce6815b13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53996919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.53996919
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2821822419
Short name T1217
Test name
Test status
Simulation time 244512966382 ps
CPU time 305.23 seconds
Started Dec 24 01:35:42 PM PST 23
Finished Dec 24 01:40:48 PM PST 23
Peak memory 208664 kb
Host smart-874938c9-891c-4f70-a0af-15659a7250df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821822419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2821822419
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.664076521
Short name T1109
Test name
Test status
Simulation time 204558191898 ps
CPU time 1026.67 seconds
Started Dec 24 01:35:27 PM PST 23
Finished Dec 24 01:52:36 PM PST 23
Peak memory 226196 kb
Host smart-b9a573a8-9147-44f7-8674-5c9847656cd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664076521 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.664076521
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.779824374
Short name T692
Test name
Test status
Simulation time 1783730457 ps
CPU time 2.18 seconds
Started Dec 24 01:34:52 PM PST 23
Finished Dec 24 01:34:59 PM PST 23
Peak memory 199568 kb
Host smart-05509748-3fc7-4bae-a639-e6521690f497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779824374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.779824374
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1030614314
Short name T461
Test name
Test status
Simulation time 23479798866 ps
CPU time 21.78 seconds
Started Dec 24 01:34:56 PM PST 23
Finished Dec 24 01:35:24 PM PST 23
Peak memory 200308 kb
Host smart-1cf18cd6-ce85-4254-bf44-1f57dac1761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030614314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1030614314
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.4255024452
Short name T983
Test name
Test status
Simulation time 18710687102 ps
CPU time 18.23 seconds
Started Dec 24 01:39:35 PM PST 23
Finished Dec 24 01:40:00 PM PST 23
Peak memory 200204 kb
Host smart-3d1fb50e-2c05-44ac-bbfa-ffe59678c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255024452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.4255024452
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3543839836
Short name T170
Test name
Test status
Simulation time 47446327712 ps
CPU time 65.64 seconds
Started Dec 24 01:39:34 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 200120 kb
Host smart-3dcb8f51-9ee0-4071-afff-e80ce52f1a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543839836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3543839836
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3182306325
Short name T209
Test name
Test status
Simulation time 136332998999 ps
CPU time 92.88 seconds
Started Dec 24 01:39:34 PM PST 23
Finished Dec 24 01:41:14 PM PST 23
Peak memory 200220 kb
Host smart-4da5200a-cfc7-4156-a63b-a394d1a2bf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182306325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3182306325
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2393238367
Short name T182
Test name
Test status
Simulation time 131828547837 ps
CPU time 58.4 seconds
Started Dec 24 01:39:38 PM PST 23
Finished Dec 24 01:40:43 PM PST 23
Peak memory 200204 kb
Host smart-ba9766c3-320b-4bd6-a222-9dedb2ab3b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393238367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2393238367
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.834452479
Short name T984
Test name
Test status
Simulation time 78272945135 ps
CPU time 48.25 seconds
Started Dec 24 01:39:38 PM PST 23
Finished Dec 24 01:40:33 PM PST 23
Peak memory 200208 kb
Host smart-d6b9821d-03fd-4ac2-8654-8de8828ef440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834452479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.834452479
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3495365431
Short name T204
Test name
Test status
Simulation time 19919995466 ps
CPU time 34.18 seconds
Started Dec 24 01:39:36 PM PST 23
Finished Dec 24 01:40:19 PM PST 23
Peak memory 200240 kb
Host smart-697b7fd7-cf42-406b-98ea-1805c098078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495365431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3495365431
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2597722198
Short name T123
Test name
Test status
Simulation time 173479695562 ps
CPU time 75.3 seconds
Started Dec 24 01:39:37 PM PST 23
Finished Dec 24 01:41:00 PM PST 23
Peak memory 200184 kb
Host smart-1a78cef7-6671-418a-bdcb-cba8385a906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597722198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2597722198
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.628425701
Short name T705
Test name
Test status
Simulation time 11603154107 ps
CPU time 20.62 seconds
Started Dec 24 01:39:37 PM PST 23
Finished Dec 24 01:40:06 PM PST 23
Peak memory 200228 kb
Host smart-b2e413cd-55c9-4995-8ab3-410ea044749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628425701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.628425701
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1548889199
Short name T849
Test name
Test status
Simulation time 49030535103 ps
CPU time 75.19 seconds
Started Dec 24 01:40:14 PM PST 23
Finished Dec 24 01:41:36 PM PST 23
Peak memory 200124 kb
Host smart-d0cd198e-3a67-4501-a8e9-29451c45f538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548889199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1548889199
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2363837950
Short name T600
Test name
Test status
Simulation time 24237651 ps
CPU time 0.57 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:35:29 PM PST 23
Peak memory 195632 kb
Host smart-b48f647f-86bc-459b-b258-364f11ab1049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363837950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2363837950
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3570252074
Short name T372
Test name
Test status
Simulation time 45642372122 ps
CPU time 36.82 seconds
Started Dec 24 01:35:24 PM PST 23
Finished Dec 24 01:36:02 PM PST 23
Peak memory 199980 kb
Host smart-4fd713d4-7603-4fbb-9f0f-5ec16b82830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570252074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3570252074
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3716515389
Short name T890
Test name
Test status
Simulation time 179495297366 ps
CPU time 82.71 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:36:48 PM PST 23
Peak memory 200264 kb
Host smart-ab9aa4d0-73aa-4c71-b7a1-4f9cdedd2dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716515389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3716515389
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3356691119
Short name T1194
Test name
Test status
Simulation time 14163020285 ps
CPU time 31.28 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:35:57 PM PST 23
Peak memory 200056 kb
Host smart-0b8bda25-5065-4076-a828-5b18ef5b7d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356691119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3356691119
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1819185661
Short name T465
Test name
Test status
Simulation time 1665392410384 ps
CPU time 1315.73 seconds
Started Dec 24 01:35:43 PM PST 23
Finished Dec 24 01:57:40 PM PST 23
Peak memory 200240 kb
Host smart-71797752-1109-441e-bac1-e1cdee5359e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819185661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1819185661
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1982129933
Short name T549
Test name
Test status
Simulation time 148167693229 ps
CPU time 392.11 seconds
Started Dec 24 01:35:24 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 200172 kb
Host smart-11c5d0df-b1e5-4232-9095-11861dd334e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982129933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1982129933
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1874274247
Short name T606
Test name
Test status
Simulation time 1948035518 ps
CPU time 1.6 seconds
Started Dec 24 01:35:28 PM PST 23
Finished Dec 24 01:35:31 PM PST 23
Peak memory 197008 kb
Host smart-f0597bf8-df63-4ad1-987d-5f512a33da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874274247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1874274247
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.418836246
Short name T920
Test name
Test status
Simulation time 37419898319 ps
CPU time 67.34 seconds
Started Dec 24 01:35:27 PM PST 23
Finished Dec 24 01:36:36 PM PST 23
Peak memory 200488 kb
Host smart-639e59cf-5058-4a8e-8589-2a3f82d24906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418836246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.418836246
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.707372853
Short name T742
Test name
Test status
Simulation time 79853361581 ps
CPU time 39.17 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:36:05 PM PST 23
Peak memory 200168 kb
Host smart-29c07cfa-aec6-48dc-9d08-d01b2ca0a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707372853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.707372853
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3232628177
Short name T1202
Test name
Test status
Simulation time 544828619 ps
CPU time 1.17 seconds
Started Dec 24 01:35:27 PM PST 23
Finished Dec 24 01:35:30 PM PST 23
Peak memory 195628 kb
Host smart-783e8a16-ea76-4438-87a2-4d4fa5628742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232628177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3232628177
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.4288770325
Short name T822
Test name
Test status
Simulation time 113888601 ps
CPU time 0.93 seconds
Started Dec 24 01:35:27 PM PST 23
Finished Dec 24 01:35:30 PM PST 23
Peak memory 198072 kb
Host smart-51c76447-89f4-44f9-b6c0-1846fd45176f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288770325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4288770325
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1192345490
Short name T941
Test name
Test status
Simulation time 133687193108 ps
CPU time 133.85 seconds
Started Dec 24 01:35:28 PM PST 23
Finished Dec 24 01:37:43 PM PST 23
Peak memory 200236 kb
Host smart-5dd7dfc6-4b51-4b11-82e8-7142869a8ef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192345490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1192345490
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.704163987
Short name T1017
Test name
Test status
Simulation time 4265156117 ps
CPU time 1.41 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:35:27 PM PST 23
Peak memory 198488 kb
Host smart-914fa4cd-d8c5-4fc0-a44e-7bb5fead18d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704163987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.704163987
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.738809756
Short name T460
Test name
Test status
Simulation time 42032531460 ps
CPU time 47.92 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:36:16 PM PST 23
Peak memory 200248 kb
Host smart-3e9fc7e1-74a1-4f12-a1c1-8a1af3afcbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738809756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.738809756
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.209921630
Short name T1014
Test name
Test status
Simulation time 71215204330 ps
CPU time 57.79 seconds
Started Dec 24 01:40:33 PM PST 23
Finished Dec 24 01:41:32 PM PST 23
Peak memory 200204 kb
Host smart-d2610973-bc91-454a-9f42-54266b1cbe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209921630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.209921630
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2028839851
Short name T307
Test name
Test status
Simulation time 65947287723 ps
CPU time 49.64 seconds
Started Dec 24 01:39:40 PM PST 23
Finished Dec 24 01:40:35 PM PST 23
Peak memory 200180 kb
Host smart-9235ddb6-7b71-4b6f-8022-06982eef74cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028839851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2028839851
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1995974817
Short name T253
Test name
Test status
Simulation time 18685330230 ps
CPU time 16.09 seconds
Started Dec 24 01:40:37 PM PST 23
Finished Dec 24 01:40:55 PM PST 23
Peak memory 199592 kb
Host smart-1595de83-3003-4e69-887c-a4a6e5da7623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995974817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1995974817
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2432169487
Short name T341
Test name
Test status
Simulation time 115708546830 ps
CPU time 58.39 seconds
Started Dec 24 01:40:11 PM PST 23
Finished Dec 24 01:41:19 PM PST 23
Peak memory 200216 kb
Host smart-71607b6c-9f25-4822-8bae-bb0243c4e20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432169487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2432169487
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.4009497575
Short name T340
Test name
Test status
Simulation time 203644782397 ps
CPU time 38.95 seconds
Started Dec 24 01:39:39 PM PST 23
Finished Dec 24 01:40:24 PM PST 23
Peak memory 199656 kb
Host smart-9aaa93e2-6eb5-422d-8bee-6cfa44f1f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009497575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4009497575
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2825984513
Short name T200
Test name
Test status
Simulation time 168849775360 ps
CPU time 142.55 seconds
Started Dec 24 01:39:38 PM PST 23
Finished Dec 24 01:42:08 PM PST 23
Peak memory 199900 kb
Host smart-c039da18-0460-4cd5-8a25-c76c14638b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825984513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2825984513
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.4086964093
Short name T185
Test name
Test status
Simulation time 36036448709 ps
CPU time 50.29 seconds
Started Dec 24 01:39:40 PM PST 23
Finished Dec 24 01:40:36 PM PST 23
Peak memory 199912 kb
Host smart-f7a34812-29e7-4159-a21e-a1480a707f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086964093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.4086964093
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3566843951
Short name T921
Test name
Test status
Simulation time 21574454 ps
CPU time 0.53 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:35:26 PM PST 23
Peak memory 195636 kb
Host smart-42231cd3-5816-4990-ac8d-08858a1906b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566843951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3566843951
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1473757817
Short name T1123
Test name
Test status
Simulation time 42658871871 ps
CPU time 9.88 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:35:36 PM PST 23
Peak memory 200208 kb
Host smart-4599d4ad-c9b7-4abb-9ded-6abb4cb7122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473757817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1473757817
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1961431526
Short name T945
Test name
Test status
Simulation time 53535975428 ps
CPU time 78.69 seconds
Started Dec 24 01:35:42 PM PST 23
Finished Dec 24 01:37:01 PM PST 23
Peak memory 200152 kb
Host smart-f6241b59-3c64-4529-855e-20e9961afae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961431526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1961431526
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2256980077
Short name T162
Test name
Test status
Simulation time 60022321577 ps
CPU time 101.08 seconds
Started Dec 24 01:35:28 PM PST 23
Finished Dec 24 01:37:11 PM PST 23
Peak memory 200144 kb
Host smart-6901aa3c-7fb6-4173-81f5-234356eb4ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256980077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2256980077
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2315257296
Short name T863
Test name
Test status
Simulation time 213742968000 ps
CPU time 224.07 seconds
Started Dec 24 01:35:41 PM PST 23
Finished Dec 24 01:39:26 PM PST 23
Peak memory 200212 kb
Host smart-19d8753f-0726-4684-ac55-9eaf782fcd57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2315257296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2315257296
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2919502236
Short name T540
Test name
Test status
Simulation time 1518010232 ps
CPU time 2.96 seconds
Started Dec 24 01:35:42 PM PST 23
Finished Dec 24 01:35:45 PM PST 23
Peak memory 195608 kb
Host smart-f3fc64d8-0164-48bd-8d10-17b3e1a76bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919502236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2919502236
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.670657277
Short name T633
Test name
Test status
Simulation time 63313422189 ps
CPU time 68.18 seconds
Started Dec 24 01:35:41 PM PST 23
Finished Dec 24 01:36:50 PM PST 23
Peak memory 199072 kb
Host smart-8da855f1-b411-473f-98d9-cc6884278338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670657277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.670657277
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3151419626
Short name T201
Test name
Test status
Simulation time 17508639185 ps
CPU time 397 seconds
Started Dec 24 01:35:43 PM PST 23
Finished Dec 24 01:42:20 PM PST 23
Peak memory 200248 kb
Host smart-e8dea55a-f541-41cb-8acb-5d595e851fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151419626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3151419626
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1410711155
Short name T615
Test name
Test status
Simulation time 4232158410 ps
CPU time 17.91 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:35:46 PM PST 23
Peak memory 199084 kb
Host smart-53d46ce0-c4c7-4511-940f-2613a2d292f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410711155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1410711155
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1520869285
Short name T622
Test name
Test status
Simulation time 44589703022 ps
CPU time 4.09 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:35:33 PM PST 23
Peak memory 195996 kb
Host smart-d9c79652-af4d-46a2-bde8-1223ffd3f8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520869285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1520869285
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2201096292
Short name T953
Test name
Test status
Simulation time 477903909 ps
CPU time 1.86 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:35:30 PM PST 23
Peak memory 197964 kb
Host smart-6ff5b742-bc7f-4d6a-b14a-0a611b5ef639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201096292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2201096292
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.893750710
Short name T375
Test name
Test status
Simulation time 333833359832 ps
CPU time 1064.52 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:53:10 PM PST 23
Peak memory 200232 kb
Host smart-6a9f178a-147d-42ac-b1ab-6a257f9eabc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893750710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.893750710
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.757908232
Short name T1208
Test name
Test status
Simulation time 203076882497 ps
CPU time 1256.08 seconds
Started Dec 24 01:35:42 PM PST 23
Finished Dec 24 01:56:39 PM PST 23
Peak memory 216868 kb
Host smart-4382ab7a-7c6d-44b6-8afc-9cb8b7b691dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757908232 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.757908232
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.399149299
Short name T580
Test name
Test status
Simulation time 2977796481 ps
CPU time 1.85 seconds
Started Dec 24 01:35:24 PM PST 23
Finished Dec 24 01:35:27 PM PST 23
Peak memory 198240 kb
Host smart-2ff64998-e2ba-43cb-85c6-7d1ad51bbf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399149299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.399149299
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.4232832072
Short name T530
Test name
Test status
Simulation time 105960983829 ps
CPU time 15.32 seconds
Started Dec 24 01:35:29 PM PST 23
Finished Dec 24 01:35:45 PM PST 23
Peak memory 200164 kb
Host smart-3729fe07-a8c0-4d6d-9515-f4bd0f3eed47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232832072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4232832072
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4091962861
Short name T1078
Test name
Test status
Simulation time 72120202186 ps
CPU time 117.35 seconds
Started Dec 24 01:39:40 PM PST 23
Finished Dec 24 01:41:43 PM PST 23
Peak memory 200220 kb
Host smart-ad375f5c-c4bb-4d37-9882-f2699c49305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091962861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4091962861
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3420893467
Short name T111
Test name
Test status
Simulation time 25281087876 ps
CPU time 19.98 seconds
Started Dec 24 01:39:39 PM PST 23
Finished Dec 24 01:40:05 PM PST 23
Peak memory 197848 kb
Host smart-f2566ef0-2e08-47d4-953d-158668d41a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420893467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3420893467
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3656276853
Short name T188
Test name
Test status
Simulation time 113977601474 ps
CPU time 23.55 seconds
Started Dec 24 01:40:14 PM PST 23
Finished Dec 24 01:40:44 PM PST 23
Peak memory 200048 kb
Host smart-fc07526b-0182-465a-a832-9a479a302a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656276853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3656276853
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1058531675
Short name T167
Test name
Test status
Simulation time 51279701104 ps
CPU time 44.46 seconds
Started Dec 24 01:39:18 PM PST 23
Finished Dec 24 01:40:03 PM PST 23
Peak memory 200244 kb
Host smart-705a87ae-dfc9-4daf-a593-78d297d672da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058531675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1058531675
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.219691711
Short name T337
Test name
Test status
Simulation time 37732556445 ps
CPU time 65.33 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:40:26 PM PST 23
Peak memory 200276 kb
Host smart-8d106c8b-6da3-4661-be4f-a064c6639918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219691711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.219691711
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2540056117
Short name T299
Test name
Test status
Simulation time 23765532389 ps
CPU time 36.11 seconds
Started Dec 24 01:39:22 PM PST 23
Finished Dec 24 01:39:59 PM PST 23
Peak memory 200180 kb
Host smart-ca58a7b7-3077-45c7-bbf7-78506bda0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540056117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2540056117
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2452269503
Short name T668
Test name
Test status
Simulation time 57257362142 ps
CPU time 21.85 seconds
Started Dec 24 01:39:20 PM PST 23
Finished Dec 24 01:39:42 PM PST 23
Peak memory 200176 kb
Host smart-dabc4f71-1805-4dd9-9962-dd6fec15af3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452269503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2452269503
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3453115510
Short name T234
Test name
Test status
Simulation time 76526775658 ps
CPU time 36.84 seconds
Started Dec 24 01:39:20 PM PST 23
Finished Dec 24 01:39:58 PM PST 23
Peak memory 200196 kb
Host smart-8566d6b6-1657-4808-b434-5095ddb488ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453115510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3453115510
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2874908806
Short name T1167
Test name
Test status
Simulation time 36790659 ps
CPU time 0.54 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:36:06 PM PST 23
Peak memory 194672 kb
Host smart-51114290-3804-4e79-88af-2051ff8c5016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874908806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2874908806
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1008744983
Short name T288
Test name
Test status
Simulation time 123425151304 ps
CPU time 172.7 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:38:21 PM PST 23
Peak memory 200028 kb
Host smart-403696bf-d626-4a19-a085-2fd1f5e6ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008744983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1008744983
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.415843340
Short name T950
Test name
Test status
Simulation time 242991670269 ps
CPU time 109.25 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:37:16 PM PST 23
Peak memory 199476 kb
Host smart-aba9f67e-236e-408d-8020-2d322b9f4841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415843340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.415843340
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.3141731030
Short name T27
Test name
Test status
Simulation time 560414544295 ps
CPU time 215.68 seconds
Started Dec 24 01:35:28 PM PST 23
Finished Dec 24 01:39:05 PM PST 23
Peak memory 200020 kb
Host smart-66be0f5c-9c90-44d7-be59-9bd3330813cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141731030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3141731030
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3835353905
Short name T1053
Test name
Test status
Simulation time 233697195752 ps
CPU time 164.19 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:38:12 PM PST 23
Peak memory 200220 kb
Host smart-248ce8c9-cbf2-409c-a746-334fb8aa4835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835353905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3835353905
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3756216488
Short name T785
Test name
Test status
Simulation time 13668438619 ps
CPU time 4.44 seconds
Started Dec 24 01:35:28 PM PST 23
Finished Dec 24 01:35:34 PM PST 23
Peak memory 199324 kb
Host smart-e4a3356b-916c-447e-92e0-6e63f2b80b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756216488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3756216488
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2985952519
Short name T952
Test name
Test status
Simulation time 52749706972 ps
CPU time 28.5 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:35:56 PM PST 23
Peak memory 199424 kb
Host smart-f2df40e2-0c49-4631-9fbf-d4a315e28bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985952519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2985952519
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2930867886
Short name T976
Test name
Test status
Simulation time 4358926872 ps
CPU time 49.92 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:36:55 PM PST 23
Peak memory 200228 kb
Host smart-27efae4d-98b9-4f5c-86e1-bbc3b2731bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930867886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2930867886
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1255347305
Short name T518
Test name
Test status
Simulation time 2533372231 ps
CPU time 5.22 seconds
Started Dec 24 01:35:25 PM PST 23
Finished Dec 24 01:35:32 PM PST 23
Peak memory 198828 kb
Host smart-9b1091f3-9149-4006-b2e4-f93f58888c9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255347305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1255347305
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1938786686
Short name T1086
Test name
Test status
Simulation time 54311238293 ps
CPU time 87.73 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:36:55 PM PST 23
Peak memory 199536 kb
Host smart-e6d2daff-fc12-4861-b6b7-a930ed9c25c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938786686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1938786686
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1738082161
Short name T447
Test name
Test status
Simulation time 2349481263 ps
CPU time 1.34 seconds
Started Dec 24 01:35:27 PM PST 23
Finished Dec 24 01:35:30 PM PST 23
Peak memory 195704 kb
Host smart-d7de74f8-0a19-445d-8f23-39370ac768d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738082161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1738082161
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3966442081
Short name T1029
Test name
Test status
Simulation time 690412909 ps
CPU time 1.44 seconds
Started Dec 24 01:35:27 PM PST 23
Finished Dec 24 01:35:30 PM PST 23
Peak memory 198532 kb
Host smart-2c8b165d-5070-4b9b-a991-bf82b180e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966442081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3966442081
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.261762703
Short name T781
Test name
Test status
Simulation time 33209798155 ps
CPU time 200.31 seconds
Started Dec 24 01:36:00 PM PST 23
Finished Dec 24 01:39:22 PM PST 23
Peak memory 215768 kb
Host smart-a61c094b-2469-4e20-aac5-2d7265b25858
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261762703 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.261762703
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2740941514
Short name T32
Test name
Test status
Simulation time 4818895132 ps
CPU time 2.15 seconds
Started Dec 24 01:35:43 PM PST 23
Finished Dec 24 01:35:46 PM PST 23
Peak memory 199468 kb
Host smart-373cd689-626b-4fa0-8d50-e0d3bf0d71f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740941514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2740941514
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1395259462
Short name T437
Test name
Test status
Simulation time 69315122760 ps
CPU time 38.08 seconds
Started Dec 24 01:35:26 PM PST 23
Finished Dec 24 01:36:07 PM PST 23
Peak memory 200200 kb
Host smart-88f97858-1cb3-4e73-8a98-a7aa55f474ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395259462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1395259462
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1783356811
Short name T745
Test name
Test status
Simulation time 83717821591 ps
CPU time 75.43 seconds
Started Dec 24 01:39:19 PM PST 23
Finished Dec 24 01:40:35 PM PST 23
Peak memory 200276 kb
Host smart-7e67ad6d-a570-442b-b7aa-0ef7350b4f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783356811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1783356811
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3587895839
Short name T289
Test name
Test status
Simulation time 101752298295 ps
CPU time 99.36 seconds
Started Dec 24 01:39:30 PM PST 23
Finished Dec 24 01:41:11 PM PST 23
Peak memory 199960 kb
Host smart-41a955e0-f485-487f-88e8-bf2b7c0b2878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587895839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3587895839
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4249412467
Short name T362
Test name
Test status
Simulation time 37630910403 ps
CPU time 17.09 seconds
Started Dec 24 01:39:16 PM PST 23
Finished Dec 24 01:39:34 PM PST 23
Peak memory 200188 kb
Host smart-00996ba9-571a-48eb-8081-cffc5d80320d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249412467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4249412467
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2792182085
Short name T676
Test name
Test status
Simulation time 16026165759 ps
CPU time 25.38 seconds
Started Dec 24 01:39:31 PM PST 23
Finished Dec 24 01:39:57 PM PST 23
Peak memory 199756 kb
Host smart-ea89e665-b088-4f38-95c6-462d03af3c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792182085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2792182085
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3599378808
Short name T1038
Test name
Test status
Simulation time 133453326985 ps
CPU time 91.67 seconds
Started Dec 24 01:40:38 PM PST 23
Finished Dec 24 01:42:12 PM PST 23
Peak memory 200284 kb
Host smart-52aedea0-f8f4-436c-a889-b142aad4916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599378808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3599378808
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3717689632
Short name T133
Test name
Test status
Simulation time 22765105185 ps
CPU time 40.19 seconds
Started Dec 24 01:39:38 PM PST 23
Finished Dec 24 01:40:25 PM PST 23
Peak memory 200212 kb
Host smart-e5ce9e6a-e5c6-4ed6-bc6e-1c2c131bea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717689632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3717689632
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3875689206
Short name T125
Test name
Test status
Simulation time 60727524364 ps
CPU time 51.57 seconds
Started Dec 24 01:39:54 PM PST 23
Finished Dec 24 01:40:47 PM PST 23
Peak memory 199244 kb
Host smart-2c357981-c37a-4551-b062-8035a2a67cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875689206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3875689206
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2807878653
Short name T1089
Test name
Test status
Simulation time 13461150 ps
CPU time 0.56 seconds
Started Dec 24 01:32:18 PM PST 23
Finished Dec 24 01:32:21 PM PST 23
Peak memory 194660 kb
Host smart-1a86ae1d-5422-4d61-a83b-29dfcacf45c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807878653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2807878653
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.747735065
Short name T238
Test name
Test status
Simulation time 12441746918 ps
CPU time 11.69 seconds
Started Dec 24 01:32:41 PM PST 23
Finished Dec 24 01:32:54 PM PST 23
Peak memory 199072 kb
Host smart-b315e95d-12bc-4bb4-9405-26cc6814b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747735065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.747735065
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.204550831
Short name T750
Test name
Test status
Simulation time 48435789671 ps
CPU time 75.55 seconds
Started Dec 24 01:32:18 PM PST 23
Finished Dec 24 01:33:36 PM PST 23
Peak memory 200132 kb
Host smart-4f61fb8f-0773-43e8-bbe9-336ebd06f04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204550831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.204550831
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3466759476
Short name T1057
Test name
Test status
Simulation time 111443599403 ps
CPU time 45.46 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:33:13 PM PST 23
Peak memory 200248 kb
Host smart-2abf64da-4940-4f1d-876a-8430c4922af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466759476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3466759476
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2079980860
Short name T726
Test name
Test status
Simulation time 1482536987574 ps
CPU time 1248.34 seconds
Started Dec 24 01:32:26 PM PST 23
Finished Dec 24 01:53:15 PM PST 23
Peak memory 200152 kb
Host smart-1099830c-2a86-4805-a29e-512dcba5b254
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079980860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2079980860
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2180061286
Short name T824
Test name
Test status
Simulation time 124801144709 ps
CPU time 272.05 seconds
Started Dec 24 01:32:16 PM PST 23
Finished Dec 24 01:36:52 PM PST 23
Peak memory 200284 kb
Host smart-835582bd-1623-486a-9f2d-063a1324a771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180061286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2180061286
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2859625471
Short name T528
Test name
Test status
Simulation time 8508360531 ps
CPU time 4.86 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:32:32 PM PST 23
Peak memory 200152 kb
Host smart-ad5b4919-7be6-4d1b-ad2f-12356f67727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859625471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2859625471
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1872587680
Short name T766
Test name
Test status
Simulation time 144726377378 ps
CPU time 210.75 seconds
Started Dec 24 01:32:21 PM PST 23
Finished Dec 24 01:35:54 PM PST 23
Peak memory 208736 kb
Host smart-5ef32475-0afa-4382-adfd-34b50402f381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872587680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1872587680
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.114914804
Short name T777
Test name
Test status
Simulation time 18458139145 ps
CPU time 1042.41 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:49:50 PM PST 23
Peak memory 200232 kb
Host smart-bea2ef01-5d0a-46ac-8359-270474b907bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114914804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.114914804
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1900281283
Short name T669
Test name
Test status
Simulation time 3231737539 ps
CPU time 7.58 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:32:36 PM PST 23
Peak memory 198408 kb
Host smart-b500196f-f583-4fa4-8322-dce37336e0e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900281283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1900281283
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1722458280
Short name T156
Test name
Test status
Simulation time 91112736128 ps
CPU time 70.87 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:33:38 PM PST 23
Peak memory 199408 kb
Host smart-511fb858-0d55-419c-87f1-560e5134bfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722458280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1722458280
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2268689741
Short name T1108
Test name
Test status
Simulation time 3661321084 ps
CPU time 7.11 seconds
Started Dec 24 01:32:28 PM PST 23
Finished Dec 24 01:32:37 PM PST 23
Peak memory 196044 kb
Host smart-f9c9f7ee-829a-45dd-883e-dba8aa3a15ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268689741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2268689741
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.947822075
Short name T104
Test name
Test status
Simulation time 200482789 ps
CPU time 0.82 seconds
Started Dec 24 01:32:28 PM PST 23
Finished Dec 24 01:32:30 PM PST 23
Peak memory 217688 kb
Host smart-e548b8af-49ac-4449-aa4c-62d2e107d237
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947822075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.947822075
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.4219492229
Short name T1233
Test name
Test status
Simulation time 649940088 ps
CPU time 1.87 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:32:30 PM PST 23
Peak memory 197984 kb
Host smart-4e74dcca-fac3-4367-a04d-8fe526070dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219492229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4219492229
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2772781631
Short name T380
Test name
Test status
Simulation time 411673542040 ps
CPU time 220.77 seconds
Started Dec 24 01:32:21 PM PST 23
Finished Dec 24 01:36:04 PM PST 23
Peak memory 208484 kb
Host smart-5a0560ee-1adc-4528-9dbc-e54816f75d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772781631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2772781631
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2410420114
Short name T1120
Test name
Test status
Simulation time 178248531214 ps
CPU time 978.89 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:48:46 PM PST 23
Peak memory 216664 kb
Host smart-623df544-8faf-4102-9638-065c5e4f2e53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410420114 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2410420114
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2220041821
Short name T1037
Test name
Test status
Simulation time 8494361781 ps
CPU time 15.28 seconds
Started Dec 24 01:32:41 PM PST 23
Finished Dec 24 01:32:58 PM PST 23
Peak memory 199316 kb
Host smart-319d12fb-8f46-4fcf-9a1a-b2619fa6c5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220041821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2220041821
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3507653888
Short name T905
Test name
Test status
Simulation time 72348186913 ps
CPU time 22.92 seconds
Started Dec 24 01:32:26 PM PST 23
Finished Dec 24 01:32:50 PM PST 23
Peak memory 197312 kb
Host smart-7b1be6dc-2ce4-4f10-b900-44b1e01edb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507653888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3507653888
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1030650160
Short name T844
Test name
Test status
Simulation time 24350620 ps
CPU time 0.54 seconds
Started Dec 24 01:36:03 PM PST 23
Finished Dec 24 01:36:04 PM PST 23
Peak memory 195620 kb
Host smart-68608de5-df19-4d34-a8b5-3712546b5457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030650160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1030650160
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3623639845
Short name T780
Test name
Test status
Simulation time 48302340374 ps
CPU time 71.17 seconds
Started Dec 24 01:36:00 PM PST 23
Finished Dec 24 01:37:12 PM PST 23
Peak memory 200044 kb
Host smart-e37aad98-4980-4f24-982a-70963a6f7442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623639845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3623639845
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3438368888
Short name T333
Test name
Test status
Simulation time 166480502095 ps
CPU time 27.95 seconds
Started Dec 24 01:35:58 PM PST 23
Finished Dec 24 01:36:26 PM PST 23
Peak memory 199880 kb
Host smart-f6faedde-8c15-49e9-b23c-71e40c516aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438368888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3438368888
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2611524977
Short name T1116
Test name
Test status
Simulation time 13950602993 ps
CPU time 16.89 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:36:22 PM PST 23
Peak memory 200140 kb
Host smart-8533db0d-e882-45bc-a772-ca44e67a6c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611524977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2611524977
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2892758848
Short name T853
Test name
Test status
Simulation time 446693639908 ps
CPU time 303.05 seconds
Started Dec 24 01:36:00 PM PST 23
Finished Dec 24 01:41:04 PM PST 23
Peak memory 200060 kb
Host smart-5d95dc72-1bc1-4913-9c7e-c81a25e63693
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892758848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2892758848
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2806970029
Short name T1176
Test name
Test status
Simulation time 120888037002 ps
CPU time 823.05 seconds
Started Dec 24 01:35:45 PM PST 23
Finished Dec 24 01:49:29 PM PST 23
Peak memory 199972 kb
Host smart-c7c1cff3-db98-4f69-9d59-cc7fe4bda6b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806970029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2806970029
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2143208517
Short name T632
Test name
Test status
Simulation time 5016178839 ps
CPU time 5.24 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:36:14 PM PST 23
Peak memory 197728 kb
Host smart-9b6b43b3-408d-42ac-a9bf-dc054e5d98b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143208517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2143208517
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2107156927
Short name T967
Test name
Test status
Simulation time 143693636470 ps
CPU time 158.41 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:38:46 PM PST 23
Peak memory 200456 kb
Host smart-b6ca5f7e-b533-43e4-8322-5e723e2453fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107156927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2107156927
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.767612374
Short name T564
Test name
Test status
Simulation time 29288523345 ps
CPU time 1531.86 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 02:01:36 PM PST 23
Peak memory 200192 kb
Host smart-5ab2b422-79f8-4171-ba0a-352ed83940d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767612374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.767612374
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4084719055
Short name T840
Test name
Test status
Simulation time 2393817702 ps
CPU time 15.97 seconds
Started Dec 24 01:35:46 PM PST 23
Finished Dec 24 01:36:03 PM PST 23
Peak memory 198744 kb
Host smart-f4a8dd36-6360-47a5-8d42-c340e9acf0b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084719055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4084719055
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3663842420
Short name T1045
Test name
Test status
Simulation time 19314587095 ps
CPU time 22.9 seconds
Started Dec 24 01:36:03 PM PST 23
Finished Dec 24 01:36:27 PM PST 23
Peak memory 200124 kb
Host smart-358c5645-934d-4ac6-9ab8-daf12ca5ce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663842420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3663842420
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2335653501
Short name T880
Test name
Test status
Simulation time 1859931616 ps
CPU time 3.52 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:36:10 PM PST 23
Peak memory 195696 kb
Host smart-f96a92d5-5dd7-4efe-a420-e9c624b81d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335653501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2335653501
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.57570575
Short name T652
Test name
Test status
Simulation time 6077626071 ps
CPU time 12.73 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:36:17 PM PST 23
Peak memory 199884 kb
Host smart-1ee27909-96d1-4f7f-8202-697d5d69de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57570575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.57570575
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1641522730
Short name T466
Test name
Test status
Simulation time 271256249244 ps
CPU time 781.59 seconds
Started Dec 24 01:36:03 PM PST 23
Finished Dec 24 01:49:06 PM PST 23
Peak memory 208640 kb
Host smart-152cb5e1-038d-4e4e-b332-9fa3746b413e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641522730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1641522730
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1844712695
Short name T592
Test name
Test status
Simulation time 787128573 ps
CPU time 1.4 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:36:10 PM PST 23
Peak memory 198584 kb
Host smart-57e8a098-e30f-4c0b-844e-6272641df512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844712695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1844712695
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3340772763
Short name T678
Test name
Test status
Simulation time 18860624182 ps
CPU time 15.79 seconds
Started Dec 24 01:36:02 PM PST 23
Finished Dec 24 01:36:18 PM PST 23
Peak memory 200164 kb
Host smart-d62e72ba-29c3-446e-9a0f-2adb7abf90c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340772763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3340772763
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3141674379
Short name T1166
Test name
Test status
Simulation time 32738533 ps
CPU time 0.57 seconds
Started Dec 24 01:36:00 PM PST 23
Finished Dec 24 01:36:02 PM PST 23
Peak memory 195588 kb
Host smart-638a4771-4149-47d9-923e-e84e3745fcb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141674379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3141674379
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.4149697309
Short name T303
Test name
Test status
Simulation time 211292889349 ps
CPU time 201.48 seconds
Started Dec 24 01:35:48 PM PST 23
Finished Dec 24 01:39:10 PM PST 23
Peak memory 200272 kb
Host smart-57c1d212-5afe-4961-a519-7a270c2d493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149697309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.4149697309
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.749161768
Short name T940
Test name
Test status
Simulation time 133265921832 ps
CPU time 181.31 seconds
Started Dec 24 01:36:03 PM PST 23
Finished Dec 24 01:39:05 PM PST 23
Peak memory 200172 kb
Host smart-39a79d17-ff6b-4bd9-a566-a208576b2b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749161768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.749161768
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3782220957
Short name T645
Test name
Test status
Simulation time 29503306147 ps
CPU time 14.12 seconds
Started Dec 24 01:36:01 PM PST 23
Finished Dec 24 01:36:16 PM PST 23
Peak memory 199888 kb
Host smart-549200ca-e6f4-4a5e-bf04-8adddc760dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782220957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3782220957
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1176476108
Short name T14
Test name
Test status
Simulation time 151829911342 ps
CPU time 379.3 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:42:24 PM PST 23
Peak memory 200228 kb
Host smart-f1585291-32d3-473a-92a9-262bba582c21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176476108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1176476108
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.225909364
Short name T724
Test name
Test status
Simulation time 4507471520 ps
CPU time 5.57 seconds
Started Dec 24 01:36:01 PM PST 23
Finished Dec 24 01:36:07 PM PST 23
Peak memory 199104 kb
Host smart-572c7d11-1ca7-4a2d-8db1-965b12ed7f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225909364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.225909364
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1878727943
Short name T947
Test name
Test status
Simulation time 64932193141 ps
CPU time 47.68 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:36:54 PM PST 23
Peak memory 199852 kb
Host smart-d88db35a-b13d-405e-87c3-a678c74bfe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878727943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1878727943
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.652583092
Short name T828
Test name
Test status
Simulation time 12371456989 ps
CPU time 123.7 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:38:11 PM PST 23
Peak memory 200192 kb
Host smart-4c996489-5945-4c5e-b1f6-4f13dc0ae729
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652583092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.652583092
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3205211192
Short name T997
Test name
Test status
Simulation time 2583025341 ps
CPU time 16.93 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:36:22 PM PST 23
Peak memory 198692 kb
Host smart-cff2a7c6-2a77-4144-b678-28c83a3dbce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205211192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3205211192
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3092336316
Short name T344
Test name
Test status
Simulation time 14754081685 ps
CPU time 29.62 seconds
Started Dec 24 01:36:01 PM PST 23
Finished Dec 24 01:36:32 PM PST 23
Peak memory 200172 kb
Host smart-3c39e073-329b-4319-910e-bdcbfee0ca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092336316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3092336316
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3281544134
Short name T1049
Test name
Test status
Simulation time 3580364814 ps
CPU time 5.63 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:36:11 PM PST 23
Peak memory 195912 kb
Host smart-8106c2d0-cf0d-4e54-bdbf-d3ec4258b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281544134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3281544134
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2900253987
Short name T1075
Test name
Test status
Simulation time 447204814 ps
CPU time 2.78 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:36:08 PM PST 23
Peak memory 198604 kb
Host smart-bcd9b9e2-5bd7-4293-b6f1-082c7bbd02a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900253987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2900253987
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.564672605
Short name T146
Test name
Test status
Simulation time 315318128285 ps
CPU time 345.31 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 200152 kb
Host smart-70fc7b1f-fb55-45da-a4a7-4a9f34dd4234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564672605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.564672605
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1981976730
Short name T730
Test name
Test status
Simulation time 279555834362 ps
CPU time 1298.19 seconds
Started Dec 24 01:36:03 PM PST 23
Finished Dec 24 01:57:43 PM PST 23
Peak memory 225432 kb
Host smart-21bc037c-f78d-4f5d-9fc9-bd129a9cf99c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981976730 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1981976730
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1059954362
Short name T710
Test name
Test status
Simulation time 2946564392 ps
CPU time 2.59 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:36:08 PM PST 23
Peak memory 198464 kb
Host smart-d47ec647-482a-40b3-9cd8-c2d491a19f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059954362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1059954362
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3480808313
Short name T782
Test name
Test status
Simulation time 34865242260 ps
CPU time 64.13 seconds
Started Dec 24 01:35:44 PM PST 23
Finished Dec 24 01:36:49 PM PST 23
Peak memory 200192 kb
Host smart-3dc852c1-41f8-45ac-90d7-ce0e662ee9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480808313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3480808313
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1824031409
Short name T506
Test name
Test status
Simulation time 12939123 ps
CPU time 0.54 seconds
Started Dec 24 01:35:42 PM PST 23
Finished Dec 24 01:35:43 PM PST 23
Peak memory 195608 kb
Host smart-0baed247-6a5a-4a5c-b7cf-03501b9efeaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824031409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1824031409
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2509182394
Short name T331
Test name
Test status
Simulation time 86748868388 ps
CPU time 35.42 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:36:42 PM PST 23
Peak memory 200260 kb
Host smart-56511318-123c-481b-82d6-129f9c2226dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509182394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2509182394
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2254330875
Short name T381
Test name
Test status
Simulation time 115378243768 ps
CPU time 14.12 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:36:22 PM PST 23
Peak memory 198924 kb
Host smart-a861a1db-883b-4b61-af53-149ca6a17c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254330875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2254330875
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2107433715
Short name T145
Test name
Test status
Simulation time 70996588348 ps
CPU time 73.47 seconds
Started Dec 24 01:35:45 PM PST 23
Finished Dec 24 01:36:59 PM PST 23
Peak memory 200160 kb
Host smart-28862abd-d162-4c9d-9e09-e7c44a7bf668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107433715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2107433715
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.44212026
Short name T927
Test name
Test status
Simulation time 1502802799060 ps
CPU time 1099.67 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 200156 kb
Host smart-7e6a49c1-3967-44e9-9a5d-aeac338cd076
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44212026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.44212026
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.549486375
Short name T322
Test name
Test status
Simulation time 51289828657 ps
CPU time 64.66 seconds
Started Dec 24 01:36:00 PM PST 23
Finished Dec 24 01:37:06 PM PST 23
Peak memory 200188 kb
Host smart-d43d6760-b532-40a9-b89d-cf6b877c8707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549486375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.549486375
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1202429015
Short name T787
Test name
Test status
Simulation time 8463457512 ps
CPU time 20.08 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:36:29 PM PST 23
Peak memory 199236 kb
Host smart-4fde59ca-d1d0-456b-bd3c-0aff924179b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202429015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1202429015
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.861140881
Short name T898
Test name
Test status
Simulation time 57444576139 ps
CPU time 33.25 seconds
Started Dec 24 01:35:47 PM PST 23
Finished Dec 24 01:36:21 PM PST 23
Peak memory 199900 kb
Host smart-71ba6677-0e2f-4d00-a9f4-65f67f8a3a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861140881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.861140881
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2472192811
Short name T590
Test name
Test status
Simulation time 20505942230 ps
CPU time 757.23 seconds
Started Dec 24 01:36:00 PM PST 23
Finished Dec 24 01:48:38 PM PST 23
Peak memory 200196 kb
Host smart-5b6f9c90-072f-463c-8348-f90398b18045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472192811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2472192811
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.71038584
Short name T1115
Test name
Test status
Simulation time 4055509567 ps
CPU time 17 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:36:22 PM PST 23
Peak memory 198976 kb
Host smart-10b9cb92-c8bf-4670-8623-2e3ec07305a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71038584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.71038584
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.542719749
Short name T552
Test name
Test status
Simulation time 132940831257 ps
CPU time 204.78 seconds
Started Dec 24 01:36:04 PM PST 23
Finished Dec 24 01:39:30 PM PST 23
Peak memory 200264 kb
Host smart-f61e2dcd-1cc5-47ff-ab17-4f4ca52207ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542719749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.542719749
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2702888415
Short name T534
Test name
Test status
Simulation time 3707639786 ps
CPU time 2.04 seconds
Started Dec 24 01:36:03 PM PST 23
Finished Dec 24 01:36:06 PM PST 23
Peak memory 195960 kb
Host smart-f0f794a3-0a51-4337-8b2a-084fe371392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702888415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2702888415
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.760889169
Short name T818
Test name
Test status
Simulation time 606422913 ps
CPU time 2.61 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:36:10 PM PST 23
Peak memory 198536 kb
Host smart-be53d1fc-0ca0-492b-8d39-e05389ba07a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760889169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.760889169
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.605672353
Short name T727
Test name
Test status
Simulation time 196458872937 ps
CPU time 661.98 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:47:07 PM PST 23
Peak memory 200228 kb
Host smart-66510702-8e58-4fc1-8d75-0b2c9a008f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605672353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.605672353
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2356850473
Short name T1027
Test name
Test status
Simulation time 38330932539 ps
CPU time 452.32 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:43:38 PM PST 23
Peak memory 217056 kb
Host smart-7f916317-8f8d-4d53-8c25-3707bd91a084
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356850473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2356850473
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1495506440
Short name T1051
Test name
Test status
Simulation time 3289071300 ps
CPU time 1.72 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:36:10 PM PST 23
Peak memory 198528 kb
Host smart-aabee66a-d2fe-4094-bedb-8e7f17424aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495506440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1495506440
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2015878381
Short name T804
Test name
Test status
Simulation time 75591535266 ps
CPU time 41.37 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:36:50 PM PST 23
Peak memory 200180 kb
Host smart-87d39d58-f45a-40e0-b26b-8694692bf142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015878381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2015878381
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1122064641
Short name T783
Test name
Test status
Simulation time 22100949 ps
CPU time 0.55 seconds
Started Dec 24 01:36:19 PM PST 23
Finished Dec 24 01:36:20 PM PST 23
Peak memory 194748 kb
Host smart-76a3875b-81d2-4458-9d6a-4bfbf0afa5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122064641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1122064641
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.76847548
Short name T851
Test name
Test status
Simulation time 169324188037 ps
CPU time 65.55 seconds
Started Dec 24 01:36:00 PM PST 23
Finished Dec 24 01:37:06 PM PST 23
Peak memory 200288 kb
Host smart-e44dad02-e2b6-4792-aedf-147195c54cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76847548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.76847548
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2039661255
Short name T407
Test name
Test status
Simulation time 87077507222 ps
CPU time 32.7 seconds
Started Dec 24 01:36:00 PM PST 23
Finished Dec 24 01:36:34 PM PST 23
Peak memory 199304 kb
Host smart-d07d72d7-9b96-493c-b22c-28b849276889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039661255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2039661255
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2189090949
Short name T1028
Test name
Test status
Simulation time 22678368594 ps
CPU time 34.93 seconds
Started Dec 24 01:35:45 PM PST 23
Finished Dec 24 01:36:21 PM PST 23
Peak memory 200176 kb
Host smart-cb93d97d-2c4f-44e1-82a8-85678177b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189090949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2189090949
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1971669222
Short name T990
Test name
Test status
Simulation time 72511366361 ps
CPU time 48.13 seconds
Started Dec 24 01:36:05 PM PST 23
Finished Dec 24 01:36:55 PM PST 23
Peak memory 200256 kb
Host smart-6ee70174-018f-4e4e-bb33-e9fbf829a93d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971669222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1971669222
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.980675166
Short name T1211
Test name
Test status
Simulation time 115995778998 ps
CPU time 528.54 seconds
Started Dec 24 01:36:17 PM PST 23
Finished Dec 24 01:45:07 PM PST 23
Peak memory 200048 kb
Host smart-ca13a487-ed1a-478a-9a84-9ca097157d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980675166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.980675166
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.876121819
Short name T786
Test name
Test status
Simulation time 298540320 ps
CPU time 1.15 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:36:09 PM PST 23
Peak memory 197680 kb
Host smart-c8bd0427-2811-4e8b-9416-404b92ba4348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876121819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.876121819
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3746172184
Short name T914
Test name
Test status
Simulation time 199451692730 ps
CPU time 118.08 seconds
Started Dec 24 01:35:59 PM PST 23
Finished Dec 24 01:37:58 PM PST 23
Peak memory 208728 kb
Host smart-788f1bf5-802c-47d9-9a76-e7a24206c570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746172184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3746172184
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.607577270
Short name T885
Test name
Test status
Simulation time 7434105636 ps
CPU time 400.44 seconds
Started Dec 24 01:36:08 PM PST 23
Finished Dec 24 01:42:50 PM PST 23
Peak memory 200192 kb
Host smart-3bbb98bf-b935-4f7a-a9cd-00ba03e6c624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607577270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.607577270
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.659871829
Short name T954
Test name
Test status
Simulation time 55389190373 ps
CPU time 21.11 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:36:30 PM PST 23
Peak memory 199428 kb
Host smart-b07aa248-3e6c-4d9c-8e99-9acb38cee958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659871829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.659871829
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.4091941291
Short name T1188
Test name
Test status
Simulation time 1571451312 ps
CPU time 2.47 seconds
Started Dec 24 01:35:44 PM PST 23
Finished Dec 24 01:35:48 PM PST 23
Peak memory 195536 kb
Host smart-fca6a837-48d2-45dc-a403-f427179e208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091941291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4091941291
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2048680054
Short name T1198
Test name
Test status
Simulation time 961478716 ps
CPU time 2.05 seconds
Started Dec 24 01:36:01 PM PST 23
Finished Dec 24 01:36:04 PM PST 23
Peak memory 198900 kb
Host smart-562503f1-0da3-45d3-a89b-4d533ee80ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048680054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2048680054
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2611557953
Short name T1164
Test name
Test status
Simulation time 37591558676 ps
CPU time 424.67 seconds
Started Dec 24 01:36:08 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 216944 kb
Host smart-320799bf-a18f-4279-a75e-eccb392b0c4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611557953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2611557953
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.474787737
Short name T561
Test name
Test status
Simulation time 7216803055 ps
CPU time 2 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:36:29 PM PST 23
Peak memory 199024 kb
Host smart-103b6a39-97d6-459e-a6d9-5465fbd57094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474787737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.474787737
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2879212950
Short name T768
Test name
Test status
Simulation time 85316486511 ps
CPU time 38.23 seconds
Started Dec 24 01:35:45 PM PST 23
Finished Dec 24 01:36:24 PM PST 23
Peak memory 200180 kb
Host smart-96f96fcb-e786-4b06-9d24-79c9f03fef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879212950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2879212950
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2747617557
Short name T509
Test name
Test status
Simulation time 13770282 ps
CPU time 0.57 seconds
Started Dec 24 01:36:17 PM PST 23
Finished Dec 24 01:36:18 PM PST 23
Peak memory 195604 kb
Host smart-3faa8e10-0cc6-4917-862d-7b7a6237b4ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747617557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2747617557
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1056191512
Short name T811
Test name
Test status
Simulation time 68009573543 ps
CPU time 32.33 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:36:41 PM PST 23
Peak memory 200220 kb
Host smart-c4a7b10d-d144-4e8f-8566-9c92b1f6f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056191512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1056191512
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_intr.3531039963
Short name T1064
Test name
Test status
Simulation time 1328957864757 ps
CPU time 585.13 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:45:54 PM PST 23
Peak memory 200132 kb
Host smart-02ccc617-cdaa-46e6-92ee-a262e2ed39db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531039963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3531039963
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1322340166
Short name T640
Test name
Test status
Simulation time 66934734131 ps
CPU time 27.97 seconds
Started Dec 24 01:36:08 PM PST 23
Finished Dec 24 01:36:37 PM PST 23
Peak memory 199160 kb
Host smart-fc9b63a9-1526-43d5-ae42-0e75ac447eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322340166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1322340166
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.270094897
Short name T703
Test name
Test status
Simulation time 22469609009 ps
CPU time 1353.08 seconds
Started Dec 24 01:36:07 PM PST 23
Finished Dec 24 01:58:42 PM PST 23
Peak memory 200200 kb
Host smart-620cb125-37a7-46dc-ba1c-a55821192579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270094897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.270094897
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2515023806
Short name T923
Test name
Test status
Simulation time 2345387475 ps
CPU time 16.21 seconds
Started Dec 24 01:36:22 PM PST 23
Finished Dec 24 01:36:39 PM PST 23
Peak memory 198204 kb
Host smart-0a74610c-76db-4831-9a92-b85d37f89aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515023806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2515023806
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1447542483
Short name T1159
Test name
Test status
Simulation time 209311744354 ps
CPU time 75.26 seconds
Started Dec 24 01:36:17 PM PST 23
Finished Dec 24 01:37:34 PM PST 23
Peak memory 200004 kb
Host smart-d1e5120c-e08e-45bd-acc8-73efa37f7677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447542483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1447542483
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3130019453
Short name T728
Test name
Test status
Simulation time 69951114998 ps
CPU time 100.66 seconds
Started Dec 24 01:36:17 PM PST 23
Finished Dec 24 01:37:58 PM PST 23
Peak memory 195796 kb
Host smart-ef3d47d1-9121-46fd-ad20-d43d30e02447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130019453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3130019453
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2646496094
Short name T1174
Test name
Test status
Simulation time 461420465 ps
CPU time 2.09 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:36:10 PM PST 23
Peak memory 198156 kb
Host smart-688b0c41-69e6-4533-a296-b06aebf3ce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646496094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2646496094
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2387943287
Short name T277
Test name
Test status
Simulation time 14740316829 ps
CPU time 123.69 seconds
Started Dec 24 01:36:16 PM PST 23
Finished Dec 24 01:38:21 PM PST 23
Peak memory 200080 kb
Host smart-48e3ef96-5b24-4126-80a5-42d9afd60a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387943287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2387943287
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.568180542
Short name T581
Test name
Test status
Simulation time 113462816610 ps
CPU time 315.53 seconds
Started Dec 24 01:36:19 PM PST 23
Finished Dec 24 01:41:36 PM PST 23
Peak memory 215960 kb
Host smart-951cd869-ccb1-41eb-aa1e-fed26fdb9973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568180542 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.568180542
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.4256726924
Short name T1232
Test name
Test status
Simulation time 1705535742 ps
CPU time 1.5 seconds
Started Dec 24 01:36:08 PM PST 23
Finished Dec 24 01:36:11 PM PST 23
Peak memory 198156 kb
Host smart-14ce68ed-975d-430a-8dea-118710140701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256726924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.4256726924
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1930190887
Short name T985
Test name
Test status
Simulation time 122756206748 ps
CPU time 63.55 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:37:30 PM PST 23
Peak memory 200192 kb
Host smart-e9ae0fda-3c92-46df-ac96-1dce4d68127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930190887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1930190887
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2712120227
Short name T102
Test name
Test status
Simulation time 137204810 ps
CPU time 0.56 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:36:28 PM PST 23
Peak memory 195584 kb
Host smart-b845a663-8e61-4365-9494-ff03e50c9cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712120227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2712120227
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2683200927
Short name T1209
Test name
Test status
Simulation time 185148179346 ps
CPU time 23.03 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:36:31 PM PST 23
Peak memory 200228 kb
Host smart-4329b668-6a80-4957-9742-d69637af1d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683200927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2683200927
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1158480825
Short name T179
Test name
Test status
Simulation time 110801559909 ps
CPU time 155.96 seconds
Started Dec 24 01:36:19 PM PST 23
Finished Dec 24 01:38:57 PM PST 23
Peak memory 200080 kb
Host smart-0b5791d1-2d1a-4e42-a65c-f68af8811d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158480825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1158480825
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2387056969
Short name T1214
Test name
Test status
Simulation time 145037047203 ps
CPU time 68.49 seconds
Started Dec 24 01:36:19 PM PST 23
Finished Dec 24 01:37:29 PM PST 23
Peak memory 200168 kb
Host smart-4633c8ec-02ca-4f98-8353-9d0b12e96401
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387056969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2387056969
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2973407609
Short name T1007
Test name
Test status
Simulation time 123673767239 ps
CPU time 196.07 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:39:43 PM PST 23
Peak memory 200224 kb
Host smart-d27afb99-d1aa-4c83-9c99-3516efb55691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973407609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2973407609
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.426836926
Short name T515
Test name
Test status
Simulation time 3445828786 ps
CPU time 3.76 seconds
Started Dec 24 01:36:33 PM PST 23
Finished Dec 24 01:36:37 PM PST 23
Peak memory 194524 kb
Host smart-272fd84b-61ab-49df-b0e9-bff8179ce415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426836926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.426836926
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2234852277
Short name T604
Test name
Test status
Simulation time 55803725887 ps
CPU time 88.8 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:37:58 PM PST 23
Peak memory 200096 kb
Host smart-17d3fb6e-1bbc-4acc-b1e3-174bc488377e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234852277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2234852277
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1707245140
Short name T893
Test name
Test status
Simulation time 18146409091 ps
CPU time 264.57 seconds
Started Dec 24 01:36:24 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 200204 kb
Host smart-51627f31-b96c-4e0f-8bb2-35b3a1a98976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707245140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1707245140
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2754902279
Short name T531
Test name
Test status
Simulation time 2390129937 ps
CPU time 3.82 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:36:11 PM PST 23
Peak memory 198588 kb
Host smart-4314f9f0-bfc4-4c69-b7cc-ae838758014c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754902279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2754902279
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2810938546
Short name T697
Test name
Test status
Simulation time 94318806596 ps
CPU time 37.64 seconds
Started Dec 24 01:36:19 PM PST 23
Finished Dec 24 01:36:57 PM PST 23
Peak memory 199300 kb
Host smart-5af78844-c9fe-4d9d-86e0-4d7fff4635d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810938546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2810938546
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2401901882
Short name T794
Test name
Test status
Simulation time 38005434852 ps
CPU time 26.74 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:36:56 PM PST 23
Peak memory 195988 kb
Host smart-3e52b8a1-bcbe-4f44-ad84-81f15dfe4ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401901882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2401901882
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3631472839
Short name T901
Test name
Test status
Simulation time 767426769 ps
CPU time 1.19 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:36:27 PM PST 23
Peak memory 198724 kb
Host smart-e2fa641c-96bf-4e14-b8aa-4f37779484f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631472839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3631472839
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.603524249
Short name T93
Test name
Test status
Simulation time 482679657730 ps
CPU time 163.03 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:39:10 PM PST 23
Peak memory 208756 kb
Host smart-52560fe9-4bf1-4a68-9a13-2ac229562090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603524249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.603524249
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2068533059
Short name T729
Test name
Test status
Simulation time 7417981927 ps
CPU time 8.65 seconds
Started Dec 24 01:36:24 PM PST 23
Finished Dec 24 01:36:33 PM PST 23
Peak memory 199324 kb
Host smart-0104ed94-1bfd-4185-89ff-448ded7938a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068533059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2068533059
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1796710462
Short name T42
Test name
Test status
Simulation time 51743960939 ps
CPU time 89.74 seconds
Started Dec 24 01:36:06 PM PST 23
Finished Dec 24 01:37:37 PM PST 23
Peak memory 200292 kb
Host smart-2cec2c78-a39c-41f3-af3c-f1b726413b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796710462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1796710462
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2624590238
Short name T512
Test name
Test status
Simulation time 13551600 ps
CPU time 0.55 seconds
Started Dec 24 01:36:19 PM PST 23
Finished Dec 24 01:36:20 PM PST 23
Peak memory 194728 kb
Host smart-14fa35db-d63c-406e-8f80-40ac33456052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624590238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2624590238
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2760849391
Short name T934
Test name
Test status
Simulation time 27487812272 ps
CPU time 45.77 seconds
Started Dec 24 01:36:20 PM PST 23
Finished Dec 24 01:37:07 PM PST 23
Peak memory 200164 kb
Host smart-6b2e83f3-ad28-4332-8147-e212a1e56b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760849391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2760849391
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2174766670
Short name T926
Test name
Test status
Simulation time 32941883045 ps
CPU time 50.71 seconds
Started Dec 24 01:36:24 PM PST 23
Finished Dec 24 01:37:15 PM PST 23
Peak memory 200188 kb
Host smart-51b0a7fb-95c8-4d91-aa8d-ec1cb9324d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174766670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2174766670
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1237290115
Short name T965
Test name
Test status
Simulation time 126004424703 ps
CPU time 205.78 seconds
Started Dec 24 01:36:33 PM PST 23
Finished Dec 24 01:39:59 PM PST 23
Peak memory 199600 kb
Host smart-d632808e-d701-4a53-bb8b-c7c757c4f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237290115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1237290115
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3970773885
Short name T910
Test name
Test status
Simulation time 692110803357 ps
CPU time 1465.26 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 02:00:53 PM PST 23
Peak memory 200236 kb
Host smart-a5d1e0f3-887f-4ddc-9240-7d9acb7d5622
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970773885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3970773885
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.619252526
Short name T839
Test name
Test status
Simulation time 134877366395 ps
CPU time 942.81 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:52:10 PM PST 23
Peak memory 200120 kb
Host smart-9808602a-957e-407a-9145-951a37c6e495
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619252526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.619252526
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3851824830
Short name T521
Test name
Test status
Simulation time 6601726280 ps
CPU time 13.47 seconds
Started Dec 24 01:36:20 PM PST 23
Finished Dec 24 01:36:35 PM PST 23
Peak memory 199272 kb
Host smart-8a8fb508-0c04-4826-92db-e6a1c772f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851824830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3851824830
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3228894935
Short name T618
Test name
Test status
Simulation time 53158576813 ps
CPU time 84.58 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:37:54 PM PST 23
Peak memory 199116 kb
Host smart-46719f8e-f39d-4ffa-89d4-3952019e713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228894935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3228894935
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.743162358
Short name T1061
Test name
Test status
Simulation time 1584168041 ps
CPU time 15.89 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:36:42 PM PST 23
Peak memory 198180 kb
Host smart-4ab392f4-cc12-4703-bf41-8c4e8995bee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743162358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.743162358
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3900509330
Short name T367
Test name
Test status
Simulation time 71372562460 ps
CPU time 31.71 seconds
Started Dec 24 01:36:24 PM PST 23
Finished Dec 24 01:36:56 PM PST 23
Peak memory 199928 kb
Host smart-405f2d86-b688-400e-8f9a-340ade2bcdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900509330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3900509330
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3494808532
Short name T682
Test name
Test status
Simulation time 6246879746 ps
CPU time 3.28 seconds
Started Dec 24 01:36:24 PM PST 23
Finished Dec 24 01:36:28 PM PST 23
Peak memory 195972 kb
Host smart-38da985d-b5f2-441c-99cc-d78a2defc2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494808532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3494808532
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3097491720
Short name T996
Test name
Test status
Simulation time 492020677 ps
CPU time 1.27 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:36:31 PM PST 23
Peak memory 198120 kb
Host smart-6e567301-6750-40e8-b8b4-fe0066693c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097491720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3097491720
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2293672616
Short name T830
Test name
Test status
Simulation time 148956558813 ps
CPU time 66.93 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:37:35 PM PST 23
Peak memory 200496 kb
Host smart-2e57ddfd-9347-4bed-81e0-acddb14cb13c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293672616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2293672616
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2424580921
Short name T457
Test name
Test status
Simulation time 249552489844 ps
CPU time 735.99 seconds
Started Dec 24 01:36:33 PM PST 23
Finished Dec 24 01:48:50 PM PST 23
Peak memory 216164 kb
Host smart-fc212648-405c-4f52-ac42-0dfe27fd3e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424580921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2424580921
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.584545950
Short name T1147
Test name
Test status
Simulation time 1570629781 ps
CPU time 2.03 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:36:29 PM PST 23
Peak memory 198732 kb
Host smart-629d4a08-62a9-443a-8e83-5869bf133365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584545950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.584545950
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1893725883
Short name T431
Test name
Test status
Simulation time 94269013031 ps
CPU time 36.91 seconds
Started Dec 24 01:36:19 PM PST 23
Finished Dec 24 01:36:56 PM PST 23
Peak memory 200148 kb
Host smart-0b6cfcf5-bd76-4816-be19-315f051cd986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893725883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1893725883
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2579365567
Short name T987
Test name
Test status
Simulation time 10471852 ps
CPU time 0.57 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:36:27 PM PST 23
Peak memory 194776 kb
Host smart-d78ff0e6-533f-49ed-9347-211003f9b602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579365567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2579365567
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3486481929
Short name T450
Test name
Test status
Simulation time 45110251935 ps
CPU time 69.8 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:37:39 PM PST 23
Peak memory 200192 kb
Host smart-1affc18a-ae4a-41c4-9b4e-4cc0069ae54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486481929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3486481929
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2165398315
Short name T1070
Test name
Test status
Simulation time 122504431808 ps
CPU time 61.05 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:37:31 PM PST 23
Peak memory 200232 kb
Host smart-70c3708c-9d6b-4055-89df-dca3313157e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165398315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2165398315
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.380430815
Short name T860
Test name
Test status
Simulation time 449741948516 ps
CPU time 195.17 seconds
Started Dec 24 01:36:29 PM PST 23
Finished Dec 24 01:39:45 PM PST 23
Peak memory 200168 kb
Host smart-6ec548ba-d7b4-4d7c-a25e-b7b3343cad1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380430815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.380430815
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3215996082
Short name T1162
Test name
Test status
Simulation time 242389832515 ps
CPU time 228.88 seconds
Started Dec 24 01:36:24 PM PST 23
Finished Dec 24 01:40:13 PM PST 23
Peak memory 200204 kb
Host smart-49b42986-a696-4a0c-89f4-f55949e77857
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215996082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3215996082
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1689650741
Short name T1043
Test name
Test status
Simulation time 5595440032 ps
CPU time 6.86 seconds
Started Dec 24 01:36:33 PM PST 23
Finished Dec 24 01:36:40 PM PST 23
Peak memory 198496 kb
Host smart-228ae4cb-7805-4ec4-b22c-a911d709bcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689650741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1689650741
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.336133579
Short name T1000
Test name
Test status
Simulation time 7615041519 ps
CPU time 12.91 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:36:40 PM PST 23
Peak memory 196008 kb
Host smart-609ed8b6-d63f-4e98-ac9c-6748919b749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336133579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.336133579
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1189594238
Short name T527
Test name
Test status
Simulation time 20144745530 ps
CPU time 98.99 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:38:05 PM PST 23
Peak memory 200220 kb
Host smart-de2d3a65-e1b1-4f6a-8037-91c14a8ad382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189594238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1189594238
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2378264301
Short name T911
Test name
Test status
Simulation time 4128929387 ps
CPU time 8.25 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:36:36 PM PST 23
Peak memory 198712 kb
Host smart-22513f39-77d2-46ad-97f7-c92184fd0b89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378264301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2378264301
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.609422585
Short name T464
Test name
Test status
Simulation time 36324388302 ps
CPU time 52.31 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:37:20 PM PST 23
Peak memory 200120 kb
Host smart-310c69f8-a575-46ba-80f5-ad02c190e083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609422585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.609422585
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2517936931
Short name T434
Test name
Test status
Simulation time 1272715496 ps
CPU time 2.81 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:36:31 PM PST 23
Peak memory 195528 kb
Host smart-0f93f426-f050-41e7-9617-c95ac36bb575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517936931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2517936931
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2957996412
Short name T709
Test name
Test status
Simulation time 265428105 ps
CPU time 1.35 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:36:30 PM PST 23
Peak memory 198452 kb
Host smart-6e5bfe76-ee37-47f8-a63b-60f6ef19a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957996412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2957996412
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2845191545
Short name T70
Test name
Test status
Simulation time 47616647084 ps
CPU time 711.87 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:48:20 PM PST 23
Peak memory 217036 kb
Host smart-5c77e54e-2d70-4e77-8b06-903148ab8fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845191545 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2845191545
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4216438894
Short name T444
Test name
Test status
Simulation time 6064623477 ps
CPU time 12.66 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:36:41 PM PST 23
Peak memory 199660 kb
Host smart-738cc7ca-1920-46ab-99b8-635dd3924405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216438894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4216438894
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3323608985
Short name T935
Test name
Test status
Simulation time 27424669530 ps
CPU time 13.15 seconds
Started Dec 24 01:36:16 PM PST 23
Finished Dec 24 01:36:30 PM PST 23
Peak memory 200220 kb
Host smart-26364ffc-81e4-4226-9dc4-5b2012472741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323608985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3323608985
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3159008098
Short name T629
Test name
Test status
Simulation time 14440401 ps
CPU time 0.55 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:36:30 PM PST 23
Peak memory 195652 kb
Host smart-33299862-b1b4-4d8d-b5a5-80fff320977c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159008098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3159008098
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3232294572
Short name T536
Test name
Test status
Simulation time 59277895562 ps
CPU time 83.04 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:37:52 PM PST 23
Peak memory 199384 kb
Host smart-4e90a970-3e9d-4db9-bc8e-d5b3211f2550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232294572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3232294572
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3722488364
Short name T873
Test name
Test status
Simulation time 47989128191 ps
CPU time 17.91 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:36:46 PM PST 23
Peak memory 199348 kb
Host smart-d7e73c7d-b9c7-415e-9859-97d98a7f42a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722488364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3722488364
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3999673378
Short name T373
Test name
Test status
Simulation time 65948031728 ps
CPU time 19.74 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:36:46 PM PST 23
Peak memory 200196 kb
Host smart-45f10960-2adc-4566-b323-30e3f74a4b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999673378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3999673378
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3586298822
Short name T1036
Test name
Test status
Simulation time 474375570745 ps
CPU time 320.3 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:41:49 PM PST 23
Peak memory 200000 kb
Host smart-b3231c21-8f2a-4930-917c-0ffb11c1886c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586298822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3586298822
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1077765142
Short name T1229
Test name
Test status
Simulation time 44163200155 ps
CPU time 189.32 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:39:39 PM PST 23
Peak memory 200260 kb
Host smart-1c2d077b-4ed2-44e1-9f95-71ffbcd8d0e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077765142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1077765142
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1482896305
Short name T846
Test name
Test status
Simulation time 1821170257 ps
CPU time 1.34 seconds
Started Dec 24 01:36:29 PM PST 23
Finished Dec 24 01:36:32 PM PST 23
Peak memory 195636 kb
Host smart-6579185f-bc10-4e55-8f8f-7f8f95991a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482896305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1482896305
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.232716029
Short name T1092
Test name
Test status
Simulation time 68824803987 ps
CPU time 57.91 seconds
Started Dec 24 01:36:24 PM PST 23
Finished Dec 24 01:37:23 PM PST 23
Peak memory 199012 kb
Host smart-f9257c6d-10a3-451d-8a20-faba22ec9be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232716029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.232716029
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1976492271
Short name T192
Test name
Test status
Simulation time 15653756162 ps
CPU time 904.33 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:51:37 PM PST 23
Peak memory 200184 kb
Host smart-55cbe514-68d9-4df7-bdc3-52874f8086b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976492271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1976492271
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.765370797
Short name T1093
Test name
Test status
Simulation time 2455255105 ps
CPU time 4.77 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:36:32 PM PST 23
Peak memory 198748 kb
Host smart-4c62f4dd-acfd-47ca-91eb-74caf68be152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765370797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.765370797
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.998716069
Short name T1100
Test name
Test status
Simulation time 316638081680 ps
CPU time 44.8 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:37:14 PM PST 23
Peak memory 200252 kb
Host smart-b1233687-8703-4426-883f-eb5232ef5916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998716069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.998716069
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1031136815
Short name T1084
Test name
Test status
Simulation time 27762420376 ps
CPU time 44.21 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:37:13 PM PST 23
Peak memory 195692 kb
Host smart-1c879c8f-c7c0-4f5f-aace-643eaa360ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031136815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1031136815
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.736123043
Short name T842
Test name
Test status
Simulation time 312021414 ps
CPU time 1.56 seconds
Started Dec 24 01:36:24 PM PST 23
Finished Dec 24 01:36:26 PM PST 23
Peak memory 198608 kb
Host smart-7924ae39-32f6-4e7e-8356-fe96ff7524b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736123043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.736123043
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2273852310
Short name T836
Test name
Test status
Simulation time 105562321400 ps
CPU time 166.33 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:39:16 PM PST 23
Peak memory 199096 kb
Host smart-ef2b90fe-c4b5-4c7c-b96c-f5dcdcfdb784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273852310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2273852310
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.957983071
Short name T816
Test name
Test status
Simulation time 204879473156 ps
CPU time 657.29 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:47:27 PM PST 23
Peak memory 225128 kb
Host smart-bd4fe45b-3a43-4eaa-8090-0157b47750ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957983071 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.957983071
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1909698579
Short name T720
Test name
Test status
Simulation time 6340552184 ps
CPU time 18.03 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:36:44 PM PST 23
Peak memory 199224 kb
Host smart-a8756aa2-d25f-4310-b931-887837651664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909698579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1909698579
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1772428222
Short name T577
Test name
Test status
Simulation time 10259419249 ps
CPU time 5.13 seconds
Started Dec 24 01:36:29 PM PST 23
Finished Dec 24 01:36:35 PM PST 23
Peak memory 198164 kb
Host smart-d6182746-604f-45be-8aa1-7613ab070980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772428222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1772428222
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3796957043
Short name T551
Test name
Test status
Simulation time 20005422 ps
CPU time 0.55 seconds
Started Dec 24 01:36:35 PM PST 23
Finished Dec 24 01:36:36 PM PST 23
Peak memory 195704 kb
Host smart-f48f98cc-ed3d-4737-ab97-db682819486e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796957043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3796957043
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2794703965
Short name T569
Test name
Test status
Simulation time 51297970488 ps
CPU time 72.73 seconds
Started Dec 24 01:36:33 PM PST 23
Finished Dec 24 01:37:46 PM PST 23
Peak memory 199280 kb
Host smart-588c6fbc-9a2d-4929-8ef7-b4c5fe52e892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794703965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2794703965
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3203857357
Short name T397
Test name
Test status
Simulation time 9978971896 ps
CPU time 9.58 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:36:38 PM PST 23
Peak memory 199064 kb
Host smart-16a74932-24d0-4a05-9177-8b64356ad657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203857357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3203857357
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1600749247
Short name T326
Test name
Test status
Simulation time 160544381820 ps
CPU time 249.54 seconds
Started Dec 24 01:36:28 PM PST 23
Finished Dec 24 01:40:39 PM PST 23
Peak memory 199912 kb
Host smart-68cfea31-bb32-46c6-b9dd-ab23cdcab218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600749247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1600749247
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1441896329
Short name T748
Test name
Test status
Simulation time 2218430898478 ps
CPU time 3001.26 seconds
Started Dec 24 01:36:31 PM PST 23
Finished Dec 24 02:26:33 PM PST 23
Peak memory 198560 kb
Host smart-2ccd9302-20df-46eb-abbe-d18f2bdcb44e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441896329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1441896329
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3311713089
Short name T598
Test name
Test status
Simulation time 160363522442 ps
CPU time 447.42 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:44:00 PM PST 23
Peak memory 200140 kb
Host smart-38178463-c345-4338-8812-24451c5835b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311713089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3311713089
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4213275365
Short name T858
Test name
Test status
Simulation time 2230414728 ps
CPU time 4.27 seconds
Started Dec 24 01:36:30 PM PST 23
Finished Dec 24 01:36:35 PM PST 23
Peak memory 197068 kb
Host smart-7ba22f23-2a17-44f1-aa3d-b1254a007fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213275365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4213275365
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3641287339
Short name T451
Test name
Test status
Simulation time 74740871015 ps
CPU time 133.83 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:38:46 PM PST 23
Peak memory 199944 kb
Host smart-56859138-c15e-467f-894b-0649594b55eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641287339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3641287339
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1988565318
Short name T1111
Test name
Test status
Simulation time 18477454371 ps
CPU time 52.67 seconds
Started Dec 24 01:36:30 PM PST 23
Finished Dec 24 01:37:23 PM PST 23
Peak memory 200184 kb
Host smart-aca6ea40-8805-454c-99d6-78e1b8eb7bd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988565318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1988565318
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2811120358
Short name T704
Test name
Test status
Simulation time 879607958 ps
CPU time 7.86 seconds
Started Dec 24 01:36:30 PM PST 23
Finished Dec 24 01:36:39 PM PST 23
Peak memory 197780 kb
Host smart-a43da6e5-3241-43e9-b52a-b4e67c777ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811120358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2811120358
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1103836940
Short name T1125
Test name
Test status
Simulation time 88971173410 ps
CPU time 72.01 seconds
Started Dec 24 01:36:29 PM PST 23
Finished Dec 24 01:37:42 PM PST 23
Peak memory 198916 kb
Host smart-7e6145c1-dc4b-4c8e-bfc7-0f83201157f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103836940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1103836940
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2979112489
Short name T425
Test name
Test status
Simulation time 4786963260 ps
CPU time 3.95 seconds
Started Dec 24 01:36:31 PM PST 23
Finished Dec 24 01:36:36 PM PST 23
Peak memory 196040 kb
Host smart-69bc78da-3963-4baf-aa8c-8f8d2e0b84ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979112489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2979112489
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2072721067
Short name T555
Test name
Test status
Simulation time 680988629 ps
CPU time 1.96 seconds
Started Dec 24 01:36:25 PM PST 23
Finished Dec 24 01:36:28 PM PST 23
Peak memory 198624 kb
Host smart-c25b2734-d891-4fcd-a6e5-7908f8941de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072721067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2072721067
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1647710567
Short name T578
Test name
Test status
Simulation time 232890984855 ps
CPU time 244.82 seconds
Started Dec 24 01:36:46 PM PST 23
Finished Dec 24 01:40:52 PM PST 23
Peak memory 200212 kb
Host smart-19e1700d-35c0-41f9-bd39-9abe49b7d568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647710567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1647710567
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3174529377
Short name T800
Test name
Test status
Simulation time 26959811226 ps
CPU time 320.69 seconds
Started Dec 24 01:36:30 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 216904 kb
Host smart-0a6d2dad-2ea9-4449-8279-82d141a8e931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174529377 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3174529377
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2851549317
Short name T1158
Test name
Test status
Simulation time 775386705 ps
CPU time 1.86 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:36:30 PM PST 23
Peak memory 198604 kb
Host smart-7eeda375-05d8-4eac-8da7-98a815e2ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851549317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2851549317
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3779872888
Short name T657
Test name
Test status
Simulation time 36203621678 ps
CPU time 70.14 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:37:43 PM PST 23
Peak memory 200204 kb
Host smart-34ef55f7-4648-4253-9dc4-b9bde76af4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779872888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3779872888
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3582260910
Short name T918
Test name
Test status
Simulation time 21239483 ps
CPU time 0.56 seconds
Started Dec 24 01:32:52 PM PST 23
Finished Dec 24 01:32:54 PM PST 23
Peak memory 195648 kb
Host smart-2de5996e-9f0c-46a2-b48a-4f0f54285441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582260910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3582260910
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3878571043
Short name T868
Test name
Test status
Simulation time 148814435106 ps
CPU time 63.55 seconds
Started Dec 24 01:32:27 PM PST 23
Finished Dec 24 01:33:32 PM PST 23
Peak memory 199368 kb
Host smart-f8bbc85d-5dc7-45be-91fc-54dca690338a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878571043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3878571043
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3578553030
Short name T1090
Test name
Test status
Simulation time 97391508138 ps
CPU time 37.7 seconds
Started Dec 24 01:32:50 PM PST 23
Finished Dec 24 01:33:29 PM PST 23
Peak memory 198412 kb
Host smart-6c9fbe39-5f65-456a-88a1-1ea6f708409d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578553030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3578553030
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1370475112
Short name T1200
Test name
Test status
Simulation time 144117336998 ps
CPU time 55.47 seconds
Started Dec 24 01:33:25 PM PST 23
Finished Dec 24 01:34:22 PM PST 23
Peak memory 200268 kb
Host smart-d70b1db4-f5e7-42fb-929f-4d2f9d68bfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370475112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1370475112
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3745259542
Short name T894
Test name
Test status
Simulation time 1708062884865 ps
CPU time 2726.25 seconds
Started Dec 24 01:32:49 PM PST 23
Finished Dec 24 02:18:17 PM PST 23
Peak memory 199212 kb
Host smart-f8258324-2c60-4794-8879-d79d92930fa9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745259542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3745259542
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3810827908
Short name T452
Test name
Test status
Simulation time 66142400327 ps
CPU time 246.33 seconds
Started Dec 24 01:32:42 PM PST 23
Finished Dec 24 01:36:49 PM PST 23
Peak memory 200296 kb
Host smart-e75295c5-49f5-47fa-af92-fe50fcadf98a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810827908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3810827908
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2936798668
Short name T637
Test name
Test status
Simulation time 2550920879 ps
CPU time 4.69 seconds
Started Dec 24 01:32:49 PM PST 23
Finished Dec 24 01:32:55 PM PST 23
Peak memory 197532 kb
Host smart-bd0057c1-b7f8-48a2-ae42-1cb8c5fd3991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936798668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2936798668
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2243502837
Short name T1002
Test name
Test status
Simulation time 119158692320 ps
CPU time 67.08 seconds
Started Dec 24 01:32:41 PM PST 23
Finished Dec 24 01:33:50 PM PST 23
Peak memory 199728 kb
Host smart-f700b969-5c81-4cda-bf2d-8d8c8c677d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243502837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2243502837
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3430456299
Short name T1154
Test name
Test status
Simulation time 7305508618 ps
CPU time 214.59 seconds
Started Dec 24 01:32:40 PM PST 23
Finished Dec 24 01:36:16 PM PST 23
Peak memory 200032 kb
Host smart-57a1eb8c-b839-4476-94d7-071776f6f919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3430456299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3430456299
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3276363986
Short name T763
Test name
Test status
Simulation time 2115690283 ps
CPU time 10.06 seconds
Started Dec 24 01:33:28 PM PST 23
Finished Dec 24 01:33:39 PM PST 23
Peak memory 198332 kb
Host smart-2f442703-0d44-453d-89bd-47de54b4952c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276363986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3276363986
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.938484141
Short name T439
Test name
Test status
Simulation time 3498426446 ps
CPU time 1.56 seconds
Started Dec 24 01:32:53 PM PST 23
Finished Dec 24 01:32:55 PM PST 23
Peak memory 195768 kb
Host smart-f423ad32-e60e-42eb-89d0-7a54ed143bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938484141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.938484141
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3997029118
Short name T91
Test name
Test status
Simulation time 59707514 ps
CPU time 0.89 seconds
Started Dec 24 01:32:42 PM PST 23
Finished Dec 24 01:32:44 PM PST 23
Peak memory 217736 kb
Host smart-1eec6d97-daf4-4a9a-b1b8-ed72c2ccd2bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997029118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3997029118
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.247982508
Short name T1163
Test name
Test status
Simulation time 930020038 ps
CPU time 3.46 seconds
Started Dec 24 01:32:52 PM PST 23
Finished Dec 24 01:32:56 PM PST 23
Peak memory 199596 kb
Host smart-0f9af8ee-5d1b-4537-ad2c-2994668584ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247982508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.247982508
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.593146570
Short name T139
Test name
Test status
Simulation time 54597202020 ps
CPU time 193.95 seconds
Started Dec 24 01:33:26 PM PST 23
Finished Dec 24 01:36:41 PM PST 23
Peak memory 200200 kb
Host smart-bd406fd0-83f0-4d03-98fc-f90918a201a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593146570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.593146570
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.109548889
Short name T764
Test name
Test status
Simulation time 74379325142 ps
CPU time 616.45 seconds
Started Dec 24 01:32:49 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 225084 kb
Host smart-5a14aac2-f10e-4704-97e0-a531e356d684
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109548889 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.109548889
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1547307410
Short name T607
Test name
Test status
Simulation time 7054198536 ps
CPU time 19.94 seconds
Started Dec 24 01:32:51 PM PST 23
Finished Dec 24 01:33:12 PM PST 23
Peak memory 199132 kb
Host smart-481e3958-eef2-4708-a553-266590804236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547307410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1547307410
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.614485669
Short name T889
Test name
Test status
Simulation time 53286346498 ps
CPU time 52.83 seconds
Started Dec 24 01:32:40 PM PST 23
Finished Dec 24 01:33:34 PM PST 23
Peak memory 200228 kb
Host smart-96e13ffa-8382-4645-8127-15a62cc3a4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614485669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.614485669
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.864015201
Short name T526
Test name
Test status
Simulation time 44696062 ps
CPU time 0.59 seconds
Started Dec 24 01:36:49 PM PST 23
Finished Dec 24 01:36:51 PM PST 23
Peak memory 195416 kb
Host smart-391cdc38-16ae-436f-8534-cc10232ac4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864015201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.864015201
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3110378830
Short name T436
Test name
Test status
Simulation time 133633673779 ps
CPU time 23.22 seconds
Started Dec 24 01:36:31 PM PST 23
Finished Dec 24 01:36:55 PM PST 23
Peak memory 200144 kb
Host smart-bf1677cd-bb43-435d-ba75-eb9aa1f16a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110378830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3110378830
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3465295193
Short name T962
Test name
Test status
Simulation time 11252614613 ps
CPU time 16.93 seconds
Started Dec 24 01:36:30 PM PST 23
Finished Dec 24 01:36:48 PM PST 23
Peak memory 199728 kb
Host smart-50378c59-e02c-4fcd-847d-33887763d771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465295193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3465295193
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3794247804
Short name T1230
Test name
Test status
Simulation time 2417504323079 ps
CPU time 3107.51 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 02:28:21 PM PST 23
Peak memory 200244 kb
Host smart-58af494c-1fd3-4005-8ef7-bb26581f62be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794247804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3794247804
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.4096927023
Short name T641
Test name
Test status
Simulation time 79868313563 ps
CPU time 108.81 seconds
Started Dec 24 01:36:46 PM PST 23
Finished Dec 24 01:38:35 PM PST 23
Peak memory 200244 kb
Host smart-ec2efe53-d43b-464d-94df-8330b4df1512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4096927023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.4096927023
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_noise_filter.486254284
Short name T1203
Test name
Test status
Simulation time 99443084741 ps
CPU time 45.42 seconds
Started Dec 24 01:36:36 PM PST 23
Finished Dec 24 01:37:22 PM PST 23
Peak memory 199336 kb
Host smart-d55d60ca-05b8-4b0e-8c50-534c625e9c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486254284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.486254284
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3690835352
Short name T511
Test name
Test status
Simulation time 14849128666 ps
CPU time 218.8 seconds
Started Dec 24 01:36:27 PM PST 23
Finished Dec 24 01:40:07 PM PST 23
Peak memory 200256 kb
Host smart-f396d5f0-e863-413a-bc11-30fcb02bc820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3690835352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3690835352
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2291685276
Short name T892
Test name
Test status
Simulation time 125057207337 ps
CPU time 100.29 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:38:13 PM PST 23
Peak memory 200272 kb
Host smart-f6c2fb5f-5b3e-4350-85ea-868a7ccf78e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291685276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2291685276
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2542640399
Short name T650
Test name
Test status
Simulation time 6977051251 ps
CPU time 5.85 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:36:38 PM PST 23
Peak memory 195960 kb
Host smart-bb0d2fcc-83fe-4ff7-a33b-c35dc9398b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542640399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2542640399
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.571326258
Short name T922
Test name
Test status
Simulation time 501549108 ps
CPU time 1.55 seconds
Started Dec 24 01:36:26 PM PST 23
Finished Dec 24 01:36:30 PM PST 23
Peak memory 197920 kb
Host smart-8c41490c-c5d0-4baa-a5fc-a71978266cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571326258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.571326258
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.445463131
Short name T1067
Test name
Test status
Simulation time 36650343392 ps
CPU time 688.07 seconds
Started Dec 24 01:36:48 PM PST 23
Finished Dec 24 01:48:17 PM PST 23
Peak memory 225040 kb
Host smart-75416c94-6162-45ee-bc1c-5e9bc89f2c60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445463131 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.445463131
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.662522185
Short name T1132
Test name
Test status
Simulation time 9057536009 ps
CPU time 4.83 seconds
Started Dec 24 01:36:47 PM PST 23
Finished Dec 24 01:36:52 PM PST 23
Peak memory 198868 kb
Host smart-50795d19-cd38-4cdf-8b01-fc236de3fb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662522185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.662522185
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.346010028
Short name T574
Test name
Test status
Simulation time 9154969883 ps
CPU time 14.88 seconds
Started Dec 24 01:36:31 PM PST 23
Finished Dec 24 01:36:47 PM PST 23
Peak memory 198320 kb
Host smart-33452b3e-c5eb-463b-820d-930428fc1de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346010028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.346010028
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3596165984
Short name T1003
Test name
Test status
Simulation time 40265006 ps
CPU time 0.55 seconds
Started Dec 24 01:37:12 PM PST 23
Finished Dec 24 01:37:15 PM PST 23
Peak memory 195608 kb
Host smart-2d5127a9-6958-44e5-92da-42dfa9989b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596165984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3596165984
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1436899773
Short name T585
Test name
Test status
Simulation time 165678376439 ps
CPU time 69.88 seconds
Started Dec 24 01:36:57 PM PST 23
Finished Dec 24 01:38:15 PM PST 23
Peak memory 200204 kb
Host smart-49c2846a-d850-405d-a94e-2bc976b68232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436899773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1436899773
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2873381977
Short name T386
Test name
Test status
Simulation time 153357141819 ps
CPU time 345.08 seconds
Started Dec 24 01:36:58 PM PST 23
Finished Dec 24 01:42:50 PM PST 23
Peak memory 200008 kb
Host smart-b204d6e0-1680-4f3f-9aa9-bbf48b719f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873381977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2873381977
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1446196081
Short name T573
Test name
Test status
Simulation time 73304455576 ps
CPU time 6.8 seconds
Started Dec 24 01:36:56 PM PST 23
Finished Dec 24 01:37:12 PM PST 23
Peak memory 200004 kb
Host smart-01d4b2c8-437f-4a9e-bc9b-678ee62776d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446196081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1446196081
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3633773058
Short name T866
Test name
Test status
Simulation time 6213104972 ps
CPU time 5.59 seconds
Started Dec 24 01:36:46 PM PST 23
Finished Dec 24 01:36:53 PM PST 23
Peak memory 195968 kb
Host smart-60dbd603-60d3-4a2d-af3b-78cbc8d8a49a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633773058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3633773058
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2717406108
Short name T1066
Test name
Test status
Simulation time 57006986078 ps
CPU time 114.1 seconds
Started Dec 24 01:37:11 PM PST 23
Finished Dec 24 01:39:08 PM PST 23
Peak memory 200140 kb
Host smart-1de9b326-55e3-4be2-b3e9-6e52599527db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2717406108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2717406108
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1351116168
Short name T571
Test name
Test status
Simulation time 12620543127 ps
CPU time 22.85 seconds
Started Dec 24 01:36:32 PM PST 23
Finished Dec 24 01:36:55 PM PST 23
Peak memory 198732 kb
Host smart-4d965492-40e0-49c7-ae8a-ad45c161f4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351116168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1351116168
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2424753578
Short name T961
Test name
Test status
Simulation time 11652642446 ps
CPU time 338.77 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:42:59 PM PST 23
Peak memory 200256 kb
Host smart-1cbddadd-b8f7-43c6-81f1-fc1fe9f98ad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424753578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2424753578
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4003206697
Short name T738
Test name
Test status
Simulation time 140532517913 ps
CPU time 331.55 seconds
Started Dec 24 01:37:12 PM PST 23
Finished Dec 24 01:42:46 PM PST 23
Peak memory 200264 kb
Host smart-37f7b985-eac0-4c26-96a2-4668650c9e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003206697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4003206697
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3672826466
Short name T833
Test name
Test status
Simulation time 4223052360 ps
CPU time 1.62 seconds
Started Dec 24 01:37:11 PM PST 23
Finished Dec 24 01:37:15 PM PST 23
Peak memory 196016 kb
Host smart-229534c3-a059-4aff-8de4-4c97d3b4406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672826466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3672826466
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.693721206
Short name T843
Test name
Test status
Simulation time 314892694 ps
CPU time 1.23 seconds
Started Dec 24 01:36:31 PM PST 23
Finished Dec 24 01:36:33 PM PST 23
Peak memory 198492 kb
Host smart-573ce0e8-4e89-4b00-b7d3-9ec9ddab684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693721206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.693721206
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.805443338
Short name T334
Test name
Test status
Simulation time 917364121024 ps
CPU time 1221.42 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:57:42 PM PST 23
Peak memory 224880 kb
Host smart-5ba04077-179d-456d-8514-04ea4bdff4be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805443338 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.805443338
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2127698087
Short name T913
Test name
Test status
Simulation time 6503384933 ps
CPU time 1.61 seconds
Started Dec 24 01:37:17 PM PST 23
Finished Dec 24 01:37:20 PM PST 23
Peak memory 199188 kb
Host smart-1f14c487-527f-4784-9645-f9707783d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127698087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2127698087
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2420089717
Short name T986
Test name
Test status
Simulation time 27246475976 ps
CPU time 52.66 seconds
Started Dec 24 01:36:55 PM PST 23
Finished Dec 24 01:37:56 PM PST 23
Peak memory 200124 kb
Host smart-707e41b2-7474-47a1-943e-b8ff2e9b4ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420089717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2420089717
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3267441129
Short name T1081
Test name
Test status
Simulation time 39065048 ps
CPU time 0.54 seconds
Started Dec 24 01:37:01 PM PST 23
Finished Dec 24 01:37:07 PM PST 23
Peak memory 195480 kb
Host smart-324dbd85-db38-45a6-8c7c-a20f31d2f9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267441129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3267441129
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3168359610
Short name T790
Test name
Test status
Simulation time 227255312134 ps
CPU time 215.7 seconds
Started Dec 24 01:37:11 PM PST 23
Finished Dec 24 01:40:50 PM PST 23
Peak memory 200292 kb
Host smart-d385f89c-2786-4cbd-b125-cf0829a4362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168359610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3168359610
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3165555338
Short name T363
Test name
Test status
Simulation time 35211032240 ps
CPU time 31.12 seconds
Started Dec 24 01:37:12 PM PST 23
Finished Dec 24 01:37:45 PM PST 23
Peak memory 200052 kb
Host smart-143ff3df-1f4a-473b-9d47-8c1bc0053180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165555338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3165555338
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2669291479
Short name T273
Test name
Test status
Simulation time 40461309472 ps
CPU time 17.49 seconds
Started Dec 24 01:37:03 PM PST 23
Finished Dec 24 01:37:25 PM PST 23
Peak memory 200192 kb
Host smart-86961a0f-ec7f-4960-8b97-ad91342a9191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669291479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2669291479
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.362209146
Short name T722
Test name
Test status
Simulation time 456108746826 ps
CPU time 168.79 seconds
Started Dec 24 01:37:12 PM PST 23
Finished Dec 24 01:40:03 PM PST 23
Peak memory 199336 kb
Host smart-87a2aa91-d62f-4e53-b14c-5453678e2f74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362209146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.362209146
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.825045251
Short name T808
Test name
Test status
Simulation time 101694252176 ps
CPU time 291.32 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:42:12 PM PST 23
Peak memory 200228 kb
Host smart-ba61dba1-cf27-44ad-885f-99f3a1f1b01e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825045251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.825045251
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1972317058
Short name T812
Test name
Test status
Simulation time 7216038736 ps
CPU time 11.85 seconds
Started Dec 24 01:37:17 PM PST 23
Finished Dec 24 01:37:31 PM PST 23
Peak memory 198056 kb
Host smart-d429a5b9-d4e0-48ff-b382-4f6bd2faa417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972317058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1972317058
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.814676269
Short name T810
Test name
Test status
Simulation time 185767078534 ps
CPU time 98.5 seconds
Started Dec 24 01:37:11 PM PST 23
Finished Dec 24 01:38:52 PM PST 23
Peak memory 199688 kb
Host smart-9deca5d9-a3b0-4f19-8750-d20d51080cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814676269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.814676269
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2123306852
Short name T424
Test name
Test status
Simulation time 4763391589 ps
CPU time 69.65 seconds
Started Dec 24 01:37:12 PM PST 23
Finished Dec 24 01:38:24 PM PST 23
Peak memory 200232 kb
Host smart-fa66bccf-2172-4844-b7aa-aa8696de0892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2123306852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2123306852
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.4064152690
Short name T981
Test name
Test status
Simulation time 3553993927 ps
CPU time 39.04 seconds
Started Dec 24 01:37:13 PM PST 23
Finished Dec 24 01:37:54 PM PST 23
Peak memory 198468 kb
Host smart-4adbc617-aa89-4edf-bf2d-09816373fdf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064152690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.4064152690
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2563864572
Short name T236
Test name
Test status
Simulation time 24546085307 ps
CPU time 54.72 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:38:15 PM PST 23
Peak memory 199448 kb
Host smart-75a593b0-19c1-4ae5-a0de-1d4e24329513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563864572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2563864572
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1398889359
Short name T601
Test name
Test status
Simulation time 42931742639 ps
CPU time 36.5 seconds
Started Dec 24 01:37:19 PM PST 23
Finished Dec 24 01:37:58 PM PST 23
Peak memory 195964 kb
Host smart-2856b92d-b23a-4330-a5e4-b65d2f88f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398889359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1398889359
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2530296983
Short name T426
Test name
Test status
Simulation time 502537639 ps
CPU time 1.62 seconds
Started Dec 24 01:37:11 PM PST 23
Finished Dec 24 01:37:15 PM PST 23
Peak memory 198372 kb
Host smart-fc1defd4-8105-4ad9-868e-3b77c8b48462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530296983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2530296983
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2501211302
Short name T241
Test name
Test status
Simulation time 55977581935 ps
CPU time 995.87 seconds
Started Dec 24 01:37:19 PM PST 23
Finished Dec 24 01:53:57 PM PST 23
Peak memory 216892 kb
Host smart-e5092bad-e87c-473a-af84-e31ee82fd839
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501211302 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2501211302
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2925352151
Short name T974
Test name
Test status
Simulation time 1130330640 ps
CPU time 4.85 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:37:24 PM PST 23
Peak memory 198848 kb
Host smart-0b7921d3-1d70-42a3-a039-28e26269ef70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925352151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2925352151
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3135342083
Short name T148
Test name
Test status
Simulation time 62544863165 ps
CPU time 11.06 seconds
Started Dec 24 01:37:10 PM PST 23
Finished Dec 24 01:37:25 PM PST 23
Peak memory 200180 kb
Host smart-f8c96cf9-635f-4fd7-9693-f5e73ca7b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135342083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3135342083
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2618098561
Short name T508
Test name
Test status
Simulation time 42384851 ps
CPU time 0.54 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:34 PM PST 23
Peak memory 195640 kb
Host smart-2e03c0f4-fa5f-4855-88e0-bef38236cce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618098561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2618098561
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3308248143
Short name T317
Test name
Test status
Simulation time 29119968429 ps
CPU time 47.23 seconds
Started Dec 24 01:37:02 PM PST 23
Finished Dec 24 01:37:54 PM PST 23
Peak memory 200016 kb
Host smart-f220c86e-3d4a-4b8a-bace-35792aebacaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308248143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3308248143
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3708043265
Short name T755
Test name
Test status
Simulation time 21083107449 ps
CPU time 38.14 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:37:59 PM PST 23
Peak memory 199628 kb
Host smart-d5f612e3-46e8-49ac-80a4-59cfa2c46630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708043265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3708043265
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_intr.2536578116
Short name T1234
Test name
Test status
Simulation time 14753131057 ps
CPU time 6.72 seconds
Started Dec 24 01:37:10 PM PST 23
Finished Dec 24 01:37:20 PM PST 23
Peak memory 195872 kb
Host smart-30d969b7-ac77-410b-a7c3-e1525549ec5a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536578116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2536578116
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3020178761
Short name T1127
Test name
Test status
Simulation time 54040188541 ps
CPU time 369.36 seconds
Started Dec 24 01:37:27 PM PST 23
Finished Dec 24 01:43:38 PM PST 23
Peak memory 200212 kb
Host smart-4b8e5ef5-94bb-4e8c-9373-7d75ee9418f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020178761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3020178761
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.129886308
Short name T1156
Test name
Test status
Simulation time 6196041401 ps
CPU time 8.09 seconds
Started Dec 24 01:37:16 PM PST 23
Finished Dec 24 01:37:25 PM PST 23
Peak memory 200116 kb
Host smart-69a720c6-9b75-4f5f-adb4-7f23fec445bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129886308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.129886308
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1715024305
Short name T666
Test name
Test status
Simulation time 221124307525 ps
CPU time 179.84 seconds
Started Dec 24 01:37:17 PM PST 23
Finished Dec 24 01:40:18 PM PST 23
Peak memory 200212 kb
Host smart-a3fc9c66-dd9e-4db0-89a6-f72d066b51a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715024305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1715024305
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3343038809
Short name T969
Test name
Test status
Simulation time 19181113086 ps
CPU time 1039.96 seconds
Started Dec 24 01:37:33 PM PST 23
Finished Dec 24 01:54:58 PM PST 23
Peak memory 200252 kb
Host smart-304dc647-216e-4f8e-a489-1be1bb2cc683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343038809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3343038809
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.430252670
Short name T1044
Test name
Test status
Simulation time 1728651988 ps
CPU time 8.63 seconds
Started Dec 24 01:37:12 PM PST 23
Finished Dec 24 01:37:23 PM PST 23
Peak memory 197836 kb
Host smart-ea55578e-693c-4284-b591-9399b114e6a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430252670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.430252670
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3056571528
Short name T847
Test name
Test status
Simulation time 93210153357 ps
CPU time 40.52 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:13 PM PST 23
Peak memory 200096 kb
Host smart-44d711a8-6730-422f-a286-3834ad619b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056571528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3056571528
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2254474290
Short name T21
Test name
Test status
Simulation time 38927047182 ps
CPU time 15.7 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:50 PM PST 23
Peak memory 196044 kb
Host smart-eab58c4b-8b63-4500-8ded-394fc4306c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254474290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2254474290
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.591525208
Short name T654
Test name
Test status
Simulation time 6062602814 ps
CPU time 28.46 seconds
Started Dec 24 01:37:17 PM PST 23
Finished Dec 24 01:37:47 PM PST 23
Peak memory 199632 kb
Host smart-f9d3cd6b-2557-4491-85d3-8b1b64c22b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591525208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.591525208
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3477121368
Short name T1201
Test name
Test status
Simulation time 98836841426 ps
CPU time 698.01 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:48:58 PM PST 23
Peak memory 200268 kb
Host smart-8cc3c88f-2b87-48cd-8d66-72002d345f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477121368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3477121368
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.404947821
Short name T297
Test name
Test status
Simulation time 44357228421 ps
CPU time 486.75 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:45:36 PM PST 23
Peak memory 216692 kb
Host smart-3814e157-8313-40f8-98a0-f332aac9cf85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404947821 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.404947821
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2002789090
Short name T1190
Test name
Test status
Simulation time 2057986337 ps
CPU time 1.67 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:37:31 PM PST 23
Peak memory 198104 kb
Host smart-6e38973f-c132-49c6-9989-2b68691a1824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002789090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2002789090
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.98583766
Short name T1062
Test name
Test status
Simulation time 68659912850 ps
CPU time 133.54 seconds
Started Dec 24 01:37:11 PM PST 23
Finished Dec 24 01:39:28 PM PST 23
Peak memory 200168 kb
Host smart-78d1634b-9049-49ae-87ee-d5783d82d38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98583766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.98583766
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.4123049476
Short name T613
Test name
Test status
Simulation time 15274960 ps
CPU time 0.56 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:37:36 PM PST 23
Peak memory 195616 kb
Host smart-72849d76-3631-4499-80ed-c903ad404d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123049476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.4123049476
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.22662981
Short name T1228
Test name
Test status
Simulation time 280485717967 ps
CPU time 322.89 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:42:59 PM PST 23
Peak memory 200252 kb
Host smart-b938fcd8-29b9-4bfc-9c34-c1ae0f8c8cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22662981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.22662981
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3757188279
Short name T1134
Test name
Test status
Simulation time 122448994297 ps
CPU time 59.5 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:38:35 PM PST 23
Peak memory 199956 kb
Host smart-f4141c03-1b0d-4855-9daf-8c51f65b1173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757188279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3757188279
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2514665828
Short name T122
Test name
Test status
Simulation time 89978742856 ps
CPU time 26.96 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:59 PM PST 23
Peak memory 199984 kb
Host smart-5cbe31df-5208-4e9a-8c9c-a629bc4ad817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514665828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2514665828
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3023502245
Short name T1005
Test name
Test status
Simulation time 494404293532 ps
CPU time 226 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:41:16 PM PST 23
Peak memory 199988 kb
Host smart-92f8873b-c66c-474c-82f1-3969811d866e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023502245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3023502245
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2526059761
Short name T845
Test name
Test status
Simulation time 113207479143 ps
CPU time 439.52 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:44:55 PM PST 23
Peak memory 200204 kb
Host smart-8b0b8b81-5fc0-40ec-93d6-ee291f39c8c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526059761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2526059761
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1430256502
Short name T1112
Test name
Test status
Simulation time 1486583761 ps
CPU time 3.22 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:34 PM PST 23
Peak memory 195744 kb
Host smart-283e1c5e-7ba4-4574-bdc9-54708914674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430256502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1430256502
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3386381617
Short name T445
Test name
Test status
Simulation time 66595774254 ps
CPU time 36.09 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:10 PM PST 23
Peak memory 199832 kb
Host smart-611d2b99-6d79-4b67-98c5-9b15674b1650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386381617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3386381617
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1909798131
Short name T312
Test name
Test status
Simulation time 13009885599 ps
CPU time 788.53 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:50:38 PM PST 23
Peak memory 200096 kb
Host smart-77e37dac-beef-4520-8c0c-a1fdcea54e36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909798131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1909798131
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3485712125
Short name T503
Test name
Test status
Simulation time 1305345001 ps
CPU time 3.28 seconds
Started Dec 24 01:37:27 PM PST 23
Finished Dec 24 01:37:32 PM PST 23
Peak memory 197796 kb
Host smart-24f76fcb-e5fa-4b8a-9657-895648ca3436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485712125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3485712125
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1417985225
Short name T977
Test name
Test status
Simulation time 47431120538 ps
CPU time 80.38 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:38:51 PM PST 23
Peak memory 200220 kb
Host smart-2a115dfb-56e5-4087-90e1-74e3b78aa7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417985225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1417985225
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.341404593
Short name T758
Test name
Test status
Simulation time 1468041018 ps
CPU time 2.87 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:37:23 PM PST 23
Peak memory 195712 kb
Host smart-13c1eac8-f9ec-4a91-b664-19f480157b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341404593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.341404593
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2020473378
Short name T1055
Test name
Test status
Simulation time 840020134 ps
CPU time 3.37 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:37:34 PM PST 23
Peak memory 198792 kb
Host smart-b797205e-2278-4eeb-ba08-7c01f7544f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020473378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2020473378
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2735376502
Short name T884
Test name
Test status
Simulation time 202833341174 ps
CPU time 671.9 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:48:42 PM PST 23
Peak memory 208708 kb
Host smart-50653b54-7107-465b-a801-1b9cebaa03b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735376502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2735376502
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3840926140
Short name T233
Test name
Test status
Simulation time 121036244426 ps
CPU time 508.63 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:46:01 PM PST 23
Peak memory 216908 kb
Host smart-3293b216-27fc-4bc8-9bed-9b10f7ea73a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840926140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3840926140
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.580893716
Short name T1094
Test name
Test status
Simulation time 3193741635 ps
CPU time 2.93 seconds
Started Dec 24 01:37:17 PM PST 23
Finished Dec 24 01:37:22 PM PST 23
Peak memory 198448 kb
Host smart-6f7bbfb3-c083-4f7c-b4fd-298fde70493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580893716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.580893716
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2755911944
Short name T617
Test name
Test status
Simulation time 21024365734 ps
CPU time 34.56 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:38:04 PM PST 23
Peak memory 200196 kb
Host smart-7ae4388d-95a8-4f7e-9674-5b4351fe9a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755911944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2755911944
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3771342094
Short name T548
Test name
Test status
Simulation time 13477395 ps
CPU time 0.56 seconds
Started Dec 24 01:37:27 PM PST 23
Finished Dec 24 01:37:29 PM PST 23
Peak memory 195592 kb
Host smart-5b1c42f4-b183-4579-9475-fbc3119d8f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771342094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3771342094
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.145036665
Short name T658
Test name
Test status
Simulation time 49758892478 ps
CPU time 8.73 seconds
Started Dec 24 01:37:35 PM PST 23
Finished Dec 24 01:37:48 PM PST 23
Peak memory 199812 kb
Host smart-720590a7-709a-4b10-8b67-cb851cb7670e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145036665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.145036665
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.520189287
Short name T280
Test name
Test status
Simulation time 119446644656 ps
CPU time 46.92 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:38:23 PM PST 23
Peak memory 199544 kb
Host smart-4cf3b213-be53-4a73-8ba5-8918b97415be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520189287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.520189287
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.373141323
Short name T15
Test name
Test status
Simulation time 10984552552 ps
CPU time 5.14 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:40 PM PST 23
Peak memory 195780 kb
Host smart-deff6490-e05b-44a6-8b57-b5f6956e1990
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373141323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.373141323
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.274439282
Short name T310
Test name
Test status
Simulation time 105960480899 ps
CPU time 224.26 seconds
Started Dec 24 01:37:18 PM PST 23
Finished Dec 24 01:41:04 PM PST 23
Peak memory 200168 kb
Host smart-abd027ae-e108-4f33-8ba1-f2e9a2051863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=274439282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.274439282
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2836232568
Short name T1186
Test name
Test status
Simulation time 8506978163 ps
CPU time 9.32 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:44 PM PST 23
Peak memory 199736 kb
Host smart-c6289ec4-d372-4fd2-a1ee-70432a58b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836232568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2836232568
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1913297405
Short name T855
Test name
Test status
Simulation time 172912028229 ps
CPU time 70.76 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:38:46 PM PST 23
Peak memory 200476 kb
Host smart-8d11e661-d25a-46df-966e-bb6fd9a44be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913297405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1913297405
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.92908043
Short name T547
Test name
Test status
Simulation time 24811773828 ps
CPU time 1093.02 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:55:46 PM PST 23
Peak memory 200176 kb
Host smart-4337d5e9-ff4b-4b51-a63a-cb953dc51061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92908043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.92908043
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2162224683
Short name T740
Test name
Test status
Simulation time 562913807 ps
CPU time 1.73 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:35 PM PST 23
Peak memory 198456 kb
Host smart-bcce0cfa-1bc3-45d7-83ba-34282b34776f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162224683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2162224683
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.207728843
Short name T859
Test name
Test status
Simulation time 163775868237 ps
CPU time 57.39 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:38:32 PM PST 23
Peak memory 199620 kb
Host smart-79d43a08-4083-49ad-8204-084fbc94b9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207728843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.207728843
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3479041854
Short name T1021
Test name
Test status
Simulation time 5289079178 ps
CPU time 4.81 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:37:41 PM PST 23
Peak memory 196104 kb
Host smart-2fb38acf-1713-40d4-9689-1114da9e2b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479041854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3479041854
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2722552756
Short name T1220
Test name
Test status
Simulation time 499307016 ps
CPU time 1.29 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:37 PM PST 23
Peak memory 198508 kb
Host smart-f97dfe9f-ff9f-4226-bdda-2e5bfd12aa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722552756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2722552756
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3148873988
Short name T161
Test name
Test status
Simulation time 433246937792 ps
CPU time 273.34 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 200196 kb
Host smart-fb6fbe81-fff1-467d-a0d0-64819ce62c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148873988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3148873988
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1196680864
Short name T1031
Test name
Test status
Simulation time 36840114390 ps
CPU time 450.13 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:45:00 PM PST 23
Peak memory 216668 kb
Host smart-172cd388-588a-4f9d-8752-e8465c3015c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196680864 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1196680864
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2250211526
Short name T596
Test name
Test status
Simulation time 7824978836 ps
CPU time 17.77 seconds
Started Dec 24 01:37:27 PM PST 23
Finished Dec 24 01:37:46 PM PST 23
Peak memory 199680 kb
Host smart-05d79045-33bd-4e63-9d8e-83008ced1f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250211526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2250211526
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1494734707
Short name T664
Test name
Test status
Simulation time 35240548322 ps
CPU time 10.57 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:44 PM PST 23
Peak memory 198320 kb
Host smart-795be555-59ef-47d6-a691-7aa16c0915ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494734707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1494734707
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3622838760
Short name T925
Test name
Test status
Simulation time 39930569 ps
CPU time 0.56 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:33 PM PST 23
Peak memory 195612 kb
Host smart-2be2154e-62dd-47a5-b2b4-436d50b14129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622838760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3622838760
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3690867919
Short name T1004
Test name
Test status
Simulation time 117224966596 ps
CPU time 33.01 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:07 PM PST 23
Peak memory 200168 kb
Host smart-c4b0349d-cf07-4ba7-82b6-c20bca746f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690867919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3690867919
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.541521029
Short name T1169
Test name
Test status
Simulation time 141836013648 ps
CPU time 310.76 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:42:47 PM PST 23
Peak memory 200268 kb
Host smart-58fd02b0-c9a6-4b17-8c03-1ed0545f110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541521029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.541521029
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3086588335
Short name T149
Test name
Test status
Simulation time 144160874638 ps
CPU time 66.38 seconds
Started Dec 24 01:37:27 PM PST 23
Finished Dec 24 01:38:34 PM PST 23
Peak memory 200220 kb
Host smart-79eb9a96-6f19-4ad7-8c94-d027606e3c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086588335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3086588335
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3882304455
Short name T432
Test name
Test status
Simulation time 72335267634 ps
CPU time 82.78 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:55 PM PST 23
Peak memory 200172 kb
Host smart-9dd4a7b3-3a9c-4120-9fc6-87645314a8eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882304455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3882304455
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.437148528
Short name T799
Test name
Test status
Simulation time 39836212965 ps
CPU time 352.36 seconds
Started Dec 24 01:37:33 PM PST 23
Finished Dec 24 01:43:30 PM PST 23
Peak memory 200188 kb
Host smart-6312384d-bf82-4304-ab5b-e8cd037a19de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437148528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.437148528
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3160172058
Short name T744
Test name
Test status
Simulation time 4844158574 ps
CPU time 8.91 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:45 PM PST 23
Peak memory 198736 kb
Host smart-380092ef-458b-4fb5-8d6f-f0e5e25227a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160172058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3160172058
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4264219261
Short name T949
Test name
Test status
Simulation time 104686534245 ps
CPU time 66.06 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:39 PM PST 23
Peak memory 200396 kb
Host smart-a859dd64-7739-4849-94cb-a546b8263597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264219261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4264219261
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.616467061
Short name T193
Test name
Test status
Simulation time 13153692038 ps
CPU time 71.44 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:38:40 PM PST 23
Peak memory 200136 kb
Host smart-1a945897-a1f8-451d-85f7-ca1925fbcc91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616467061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.616467061
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.752069729
Short name T560
Test name
Test status
Simulation time 2067861186 ps
CPU time 2.73 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:38 PM PST 23
Peak memory 197760 kb
Host smart-e81afe7b-3440-4645-87cd-32f1e6813632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=752069729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.752069729
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2787600804
Short name T178
Test name
Test status
Simulation time 24776253319 ps
CPU time 22.54 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:56 PM PST 23
Peak memory 199768 kb
Host smart-535b7ae2-7fe6-4198-9080-e697a549ef4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787600804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2787600804
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2633067056
Short name T683
Test name
Test status
Simulation time 3977963480 ps
CPU time 7.07 seconds
Started Dec 24 01:37:32 PM PST 23
Finished Dec 24 01:37:44 PM PST 23
Peak memory 196148 kb
Host smart-5ddef9e9-8ab7-4a3c-a1fa-3ddf71ee37d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633067056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2633067056
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1711580052
Short name T771
Test name
Test status
Simulation time 466545758 ps
CPU time 2.17 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:37 PM PST 23
Peak memory 198712 kb
Host smart-b2c5a28c-5b39-46c1-8fde-6baf4d4a23b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711580052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1711580052
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3128703925
Short name T886
Test name
Test status
Simulation time 98106336040 ps
CPU time 37.19 seconds
Started Dec 24 01:37:35 PM PST 23
Finished Dec 24 01:38:16 PM PST 23
Peak memory 199968 kb
Host smart-1ff05343-4410-4df0-88bd-1d13bc6b6895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128703925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3128703925
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.395713418
Short name T420
Test name
Test status
Simulation time 61702289448 ps
CPU time 669.54 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:48:45 PM PST 23
Peak memory 216700 kb
Host smart-92bd493a-0eee-4151-afa9-3eadb37b8cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395713418 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.395713418
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2446285849
Short name T557
Test name
Test status
Simulation time 890062221 ps
CPU time 1.37 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:37 PM PST 23
Peak memory 198156 kb
Host smart-177ce074-828f-4934-8e37-1a5bb0cc17cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446285849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2446285849
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3891211984
Short name T421
Test name
Test status
Simulation time 55594281766 ps
CPU time 113.19 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:39:30 PM PST 23
Peak memory 200224 kb
Host smart-c6277ab1-f8af-4f19-a40c-b72ae912a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891211984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3891211984
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3192333539
Short name T100
Test name
Test status
Simulation time 18918131 ps
CPU time 0.59 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:36 PM PST 23
Peak memory 195680 kb
Host smart-e8f04669-c895-416d-83b8-402a87019249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192333539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3192333539
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2911126268
Short name T642
Test name
Test status
Simulation time 13420570460 ps
CPU time 22.76 seconds
Started Dec 24 01:37:38 PM PST 23
Finished Dec 24 01:38:07 PM PST 23
Peak memory 200124 kb
Host smart-1eb36684-c2af-4888-b8d8-55ef5f18da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911126268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2911126268
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3199792350
Short name T1204
Test name
Test status
Simulation time 93378988077 ps
CPU time 74.14 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:45 PM PST 23
Peak memory 199928 kb
Host smart-8b8af4d8-4c1b-4f91-8365-ed8e3f9f4660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199792350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3199792350
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1665061741
Short name T1170
Test name
Test status
Simulation time 313552421905 ps
CPU time 30.2 seconds
Started Dec 24 01:37:33 PM PST 23
Finished Dec 24 01:38:09 PM PST 23
Peak memory 199884 kb
Host smart-4e6d0025-1b54-4c76-9328-90e0a5b80ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665061741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1665061741
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4119829368
Short name T565
Test name
Test status
Simulation time 38557435368 ps
CPU time 50.59 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:38:27 PM PST 23
Peak memory 195760 kb
Host smart-2e066dbc-68f7-4d97-9380-058c45a5152b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119829368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4119829368
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2540274905
Short name T1034
Test name
Test status
Simulation time 39217237742 ps
CPU time 291.61 seconds
Started Dec 24 01:37:34 PM PST 23
Finished Dec 24 01:42:30 PM PST 23
Peak memory 200192 kb
Host smart-c85a35bd-a8f9-4940-aa1d-0791f315ae51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540274905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2540274905
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1884307136
Short name T689
Test name
Test status
Simulation time 43237281209 ps
CPU time 67.1 seconds
Started Dec 24 01:37:39 PM PST 23
Finished Dec 24 01:38:52 PM PST 23
Peak memory 199360 kb
Host smart-2a348143-97a9-4839-bd7d-ca381c0eaff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884307136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1884307136
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2642890554
Short name T660
Test name
Test status
Simulation time 23464513805 ps
CPU time 1244.35 seconds
Started Dec 24 01:37:34 PM PST 23
Finished Dec 24 01:58:23 PM PST 23
Peak memory 200200 kb
Host smart-10a49c30-e7aa-48cf-8d17-1a40335b35be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642890554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2642890554
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3138809202
Short name T1083
Test name
Test status
Simulation time 4101104309 ps
CPU time 3.79 seconds
Started Dec 24 01:37:39 PM PST 23
Finished Dec 24 01:37:50 PM PST 23
Peak memory 198220 kb
Host smart-51fdf490-970c-49b6-be9e-9e8a4cf43863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138809202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3138809202
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2710580078
Short name T946
Test name
Test status
Simulation time 78331924157 ps
CPU time 116.49 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:39:32 PM PST 23
Peak memory 199892 kb
Host smart-2014c380-e736-4adb-a207-645d24b0d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710580078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2710580078
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.952466165
Short name T1063
Test name
Test status
Simulation time 3496068405 ps
CPU time 2.01 seconds
Started Dec 24 01:37:40 PM PST 23
Finished Dec 24 01:37:48 PM PST 23
Peak memory 195944 kb
Host smart-72709e51-0cd6-4cf4-af0e-4b7d705d60ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952466165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.952466165
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3675854437
Short name T765
Test name
Test status
Simulation time 514547095 ps
CPU time 1.19 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:36 PM PST 23
Peak memory 198204 kb
Host smart-b9312de1-a175-4d35-a824-a6c8208a017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675854437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3675854437
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1169771219
Short name T797
Test name
Test status
Simulation time 682034534071 ps
CPU time 370.58 seconds
Started Dec 24 01:37:35 PM PST 23
Finished Dec 24 01:43:50 PM PST 23
Peak memory 200296 kb
Host smart-1c29bf79-c641-40ab-bc97-2a189205890b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169771219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1169771219
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2404150657
Short name T907
Test name
Test status
Simulation time 2288564087 ps
CPU time 2.07 seconds
Started Dec 24 01:37:33 PM PST 23
Finished Dec 24 01:37:40 PM PST 23
Peak memory 198396 kb
Host smart-1643973e-d57d-41c6-af23-7165e04b1051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404150657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2404150657
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3562587210
Short name T966
Test name
Test status
Simulation time 36883894929 ps
CPU time 32.13 seconds
Started Dec 24 01:37:35 PM PST 23
Finished Dec 24 01:38:11 PM PST 23
Peak memory 199832 kb
Host smart-219ec3cc-14ed-41ee-8633-f754fe125545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562587210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3562587210
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2296719575
Short name T792
Test name
Test status
Simulation time 33752186 ps
CPU time 0.55 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:37:37 PM PST 23
Peak memory 194560 kb
Host smart-72df4904-96ed-4503-96cd-abddfeb37057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296719575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2296719575
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.55990086
Short name T211
Test name
Test status
Simulation time 31539867848 ps
CPU time 41.89 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:38:18 PM PST 23
Peak memory 200244 kb
Host smart-6f3745b3-b2ab-44aa-b97b-868e26bc9f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55990086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.55990086
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2790317231
Short name T390
Test name
Test status
Simulation time 107537757135 ps
CPU time 41.64 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:14 PM PST 23
Peak memory 199492 kb
Host smart-619f0183-5fdb-44ff-812e-2c5dfb3b0811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790317231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2790317231
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2396676775
Short name T603
Test name
Test status
Simulation time 123947028784 ps
CPU time 57.28 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:38:26 PM PST 23
Peak memory 200180 kb
Host smart-9ca19906-92dc-4dad-8fc1-16fa4dcfe383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396676775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2396676775
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2545281460
Short name T752
Test name
Test status
Simulation time 130966870795 ps
CPU time 56.47 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:38:26 PM PST 23
Peak memory 199156 kb
Host smart-9211045b-7a43-4749-9fec-4d4466b1939c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545281460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2545281460
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2123125139
Short name T673
Test name
Test status
Simulation time 117880854355 ps
CPU time 977.47 seconds
Started Dec 24 01:37:27 PM PST 23
Finished Dec 24 01:53:45 PM PST 23
Peak memory 200076 kb
Host smart-1e94a050-89fb-461e-9555-d595fb8cfe75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2123125139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2123125139
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1416878172
Short name T510
Test name
Test status
Simulation time 2049227203 ps
CPU time 1.59 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:37:33 PM PST 23
Peak memory 195860 kb
Host smart-8866e5f0-ffed-4e09-a0e8-2a08f37bbfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416878172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1416878172
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.4122100234
Short name T1148
Test name
Test status
Simulation time 34927922832 ps
CPU time 8 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:44 PM PST 23
Peak memory 194964 kb
Host smart-f85181ae-7dc8-4912-84d9-56d45bc53f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122100234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.4122100234
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2197074506
Short name T887
Test name
Test status
Simulation time 17152714009 ps
CPU time 877 seconds
Started Dec 24 01:37:32 PM PST 23
Finished Dec 24 01:52:14 PM PST 23
Peak memory 199552 kb
Host smart-9cb211bf-3e09-49d4-b78b-b3d52b32c219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197074506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2197074506
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3309006912
Short name T12
Test name
Test status
Simulation time 3577489183 ps
CPU time 13.18 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:37:43 PM PST 23
Peak memory 198656 kb
Host smart-f1c5d996-5f3b-4572-bdd9-385e9cddff67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309006912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3309006912
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3636752420
Short name T1082
Test name
Test status
Simulation time 55706816812 ps
CPU time 14.55 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:37:51 PM PST 23
Peak memory 197500 kb
Host smart-a500569b-e887-412b-b3f8-0e652ebb5357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636752420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3636752420
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2434914688
Short name T1013
Test name
Test status
Simulation time 4585054752 ps
CPU time 2.24 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:38 PM PST 23
Peak memory 195976 kb
Host smart-f337b46d-b549-4e7a-83cc-1e4859a45661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434914688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2434914688
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3863338487
Short name T630
Test name
Test status
Simulation time 5860748150 ps
CPU time 18.1 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:54 PM PST 23
Peak memory 199636 kb
Host smart-123321ef-df0c-4714-9f31-2010a1b36881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863338487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3863338487
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1838142716
Short name T258
Test name
Test status
Simulation time 138801734406 ps
CPU time 386.32 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:44:00 PM PST 23
Peak memory 200236 kb
Host smart-7e37ccb5-1233-4b69-ba4e-47730f0ccf17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838142716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1838142716
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3990046100
Short name T1105
Test name
Test status
Simulation time 17684338601 ps
CPU time 191.56 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:40:41 PM PST 23
Peak memory 208884 kb
Host smart-778b7a70-317f-44a7-9964-19850a756cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990046100 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3990046100
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2405235332
Short name T440
Test name
Test status
Simulation time 1879570271 ps
CPU time 1.62 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:37:37 PM PST 23
Peak memory 197944 kb
Host smart-dcb9e8bb-1b21-40b5-aebf-95f98f9bdab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405235332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2405235332
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2473067257
Short name T584
Test name
Test status
Simulation time 57554968431 ps
CPU time 110.78 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:39:27 PM PST 23
Peak memory 200272 kb
Host smart-d6a16055-f25b-4d0a-b456-28623f694564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473067257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2473067257
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.383456231
Short name T507
Test name
Test status
Simulation time 145698259 ps
CPU time 0.53 seconds
Started Dec 24 01:37:35 PM PST 23
Finished Dec 24 01:37:40 PM PST 23
Peak memory 195424 kb
Host smart-b53d59a1-6508-4871-9b43-0cfd732fc9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383456231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.383456231
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.332638222
Short name T869
Test name
Test status
Simulation time 61679218944 ps
CPU time 31.38 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:05 PM PST 23
Peak memory 200264 kb
Host smart-313af227-e1d6-4abd-aa72-066f8fe5744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332638222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.332638222
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3484329434
Short name T416
Test name
Test status
Simulation time 258036202341 ps
CPU time 97.04 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:39:12 PM PST 23
Peak memory 199788 kb
Host smart-6ad2a9e3-5093-4ac8-8fec-0c1711fd871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484329434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3484329434
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.1703054285
Short name T1199
Test name
Test status
Simulation time 549162465455 ps
CPU time 258.47 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 200096 kb
Host smart-96badcda-bac9-43e5-b00a-c364f5682848
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703054285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1703054285
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.868771123
Short name T1173
Test name
Test status
Simulation time 52503912131 ps
CPU time 305.49 seconds
Started Dec 24 01:37:28 PM PST 23
Finished Dec 24 01:42:35 PM PST 23
Peak memory 200216 kb
Host smart-c0b7f265-e762-4d5b-863e-2e1b535e66e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868771123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.868771123
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1165431279
Short name T1022
Test name
Test status
Simulation time 3630077767 ps
CPU time 7.6 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:37:43 PM PST 23
Peak memory 198584 kb
Host smart-658b01a9-b7f1-413a-af7c-63ba449f636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165431279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1165431279
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1778645606
Short name T417
Test name
Test status
Simulation time 206689744670 ps
CPU time 123.23 seconds
Started Dec 24 01:37:32 PM PST 23
Finished Dec 24 01:39:41 PM PST 23
Peak memory 200468 kb
Host smart-cf36abf0-44e5-40fd-a528-d09291d659da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778645606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1778645606
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3630653488
Short name T857
Test name
Test status
Simulation time 19056956390 ps
CPU time 336.4 seconds
Started Dec 24 01:37:32 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 199568 kb
Host smart-a7ccb8b8-9529-4a92-b1b9-6ec9087e70f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630653488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3630653488
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1909341400
Short name T798
Test name
Test status
Simulation time 4316550656 ps
CPU time 36.78 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:38:09 PM PST 23
Peak memory 198864 kb
Host smart-8dac20ce-5190-4d2d-a9d2-75f5cc9b0fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909341400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1909341400
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2271102385
Short name T951
Test name
Test status
Simulation time 125263483519 ps
CPU time 1043.82 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:54:59 PM PST 23
Peak memory 200208 kb
Host smart-1832c2b8-606c-48a5-99e4-decef0ca7ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271102385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2271102385
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2500962308
Short name T1184
Test name
Test status
Simulation time 5686494810 ps
CPU time 2.86 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:37:39 PM PST 23
Peak memory 195864 kb
Host smart-965cb22e-1dd0-40cc-ba7a-89fe5c2c3339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500962308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2500962308
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.318507849
Short name T912
Test name
Test status
Simulation time 6324918526 ps
CPU time 11.8 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:37:45 PM PST 23
Peak memory 199168 kb
Host smart-4bd382f9-6315-4643-b1fd-3d12fb735373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318507849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.318507849
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.747746612
Short name T1121
Test name
Test status
Simulation time 306660694107 ps
CPU time 287.75 seconds
Started Dec 24 01:37:30 PM PST 23
Finished Dec 24 01:42:23 PM PST 23
Peak memory 199964 kb
Host smart-eeaafe1a-f201-4ac3-a713-d7545b2f7301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747746612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.747746612
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3027597466
Short name T743
Test name
Test status
Simulation time 47001168190 ps
CPU time 427.91 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:44:44 PM PST 23
Peak memory 209492 kb
Host smart-3dfa6761-8fac-43fd-9911-de3dfa780a0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027597466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3027597466
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3417560505
Short name T575
Test name
Test status
Simulation time 652494621 ps
CPU time 2.59 seconds
Started Dec 24 01:37:27 PM PST 23
Finished Dec 24 01:37:31 PM PST 23
Peak memory 198184 kb
Host smart-7dd47000-7940-4e5c-82c2-4c926f4786f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417560505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3417560505
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2732885962
Short name T448
Test name
Test status
Simulation time 66208075642 ps
CPU time 111.91 seconds
Started Dec 24 01:37:29 PM PST 23
Finished Dec 24 01:39:24 PM PST 23
Peak memory 200196 kb
Host smart-4afb9475-b618-478f-804f-0f66f13e3aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732885962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2732885962
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3518843406
Short name T900
Test name
Test status
Simulation time 17460951 ps
CPU time 0.53 seconds
Started Dec 24 01:33:30 PM PST 23
Finished Dec 24 01:33:32 PM PST 23
Peak memory 195576 kb
Host smart-94ee3105-6745-49f3-a820-5cb4fb2058de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518843406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3518843406
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3716128497
Short name T956
Test name
Test status
Simulation time 403836044650 ps
CPU time 66.56 seconds
Started Dec 24 01:32:51 PM PST 23
Finished Dec 24 01:33:58 PM PST 23
Peak memory 200164 kb
Host smart-067cf8d7-a2a3-4d1c-a1e3-12a28c710eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716128497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3716128497
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3726948392
Short name T1071
Test name
Test status
Simulation time 191917360622 ps
CPU time 409.37 seconds
Started Dec 24 01:33:28 PM PST 23
Finished Dec 24 01:40:18 PM PST 23
Peak memory 200244 kb
Host smart-94b7858f-8828-4f52-96da-d4b94b8df393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726948392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3726948392
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.4237395579
Short name T191
Test name
Test status
Simulation time 134074455798 ps
CPU time 52.09 seconds
Started Dec 24 01:33:08 PM PST 23
Finished Dec 24 01:34:01 PM PST 23
Peak memory 200204 kb
Host smart-dcf43955-3adc-460b-9a1f-e090acf42a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237395579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.4237395579
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1331060104
Short name T732
Test name
Test status
Simulation time 232824047307 ps
CPU time 203.01 seconds
Started Dec 24 01:33:13 PM PST 23
Finished Dec 24 01:36:37 PM PST 23
Peak memory 198508 kb
Host smart-14166947-030b-4068-893e-d806c05989a0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331060104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1331060104
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1465006911
Short name T661
Test name
Test status
Simulation time 148148576270 ps
CPU time 305.94 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:38:38 PM PST 23
Peak memory 200132 kb
Host smart-0103eccd-efaf-4e61-890d-ce5d1cdc0361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465006911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1465006911
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1656495690
Short name T529
Test name
Test status
Simulation time 6133124067 ps
CPU time 4.72 seconds
Started Dec 24 01:33:26 PM PST 23
Finished Dec 24 01:33:32 PM PST 23
Peak memory 198932 kb
Host smart-33f62790-5063-4c6a-90d4-3801ed1508f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656495690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1656495690
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.533571642
Short name T1033
Test name
Test status
Simulation time 124277631440 ps
CPU time 33.2 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:33:47 PM PST 23
Peak memory 200448 kb
Host smart-2055c3d9-6924-4353-a3c5-8d1374f0c689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533571642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.533571642
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3753488808
Short name T1068
Test name
Test status
Simulation time 10781981689 ps
CPU time 294.34 seconds
Started Dec 24 01:33:37 PM PST 23
Finished Dec 24 01:38:33 PM PST 23
Peak memory 200232 kb
Host smart-c6ceec89-682e-456c-b3e5-6a1fbd42111d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753488808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3753488808
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2051813150
Short name T1025
Test name
Test status
Simulation time 4290234859 ps
CPU time 8.14 seconds
Started Dec 24 01:33:06 PM PST 23
Finished Dec 24 01:33:15 PM PST 23
Peak memory 198696 kb
Host smart-b1ece8fd-534a-4ad4-b84c-f4bbe6341ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051813150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2051813150
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.432256136
Short name T377
Test name
Test status
Simulation time 152434407353 ps
CPU time 33.17 seconds
Started Dec 24 01:33:27 PM PST 23
Finished Dec 24 01:34:01 PM PST 23
Peak memory 200272 kb
Host smart-243bee84-b91b-4ce5-8278-3fa3c68d36fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432256136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.432256136
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.4031207625
Short name T1072
Test name
Test status
Simulation time 43190023049 ps
CPU time 26.25 seconds
Started Dec 24 01:33:13 PM PST 23
Finished Dec 24 01:33:41 PM PST 23
Peak memory 195860 kb
Host smart-b4452f01-8cec-44bd-a9f1-a5bda97dfb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031207625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4031207625
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2046629747
Short name T944
Test name
Test status
Simulation time 909154262 ps
CPU time 2.41 seconds
Started Dec 24 01:32:50 PM PST 23
Finished Dec 24 01:32:54 PM PST 23
Peak memory 198168 kb
Host smart-2c80b841-d072-4361-b5e4-77b3ccd4c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046629747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2046629747
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1483250390
Short name T174
Test name
Test status
Simulation time 93468689959 ps
CPU time 434.01 seconds
Started Dec 24 01:33:30 PM PST 23
Finished Dec 24 01:40:45 PM PST 23
Peak memory 200224 kb
Host smart-79cf1de9-5e76-4f0a-859d-1088b7295112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483250390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1483250390
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3906041962
Short name T1219
Test name
Test status
Simulation time 127747102658 ps
CPU time 337.55 seconds
Started Dec 24 01:33:42 PM PST 23
Finished Dec 24 01:39:21 PM PST 23
Peak memory 225216 kb
Host smart-acb74068-a9ae-4a86-bee6-973d95cd3f7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906041962 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3906041962
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1127667989
Short name T672
Test name
Test status
Simulation time 1095841420 ps
CPU time 2.41 seconds
Started Dec 24 01:33:26 PM PST 23
Finished Dec 24 01:33:30 PM PST 23
Peak memory 198728 kb
Host smart-84b76c6e-d7d1-43ef-972a-8bbf0f12775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127667989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1127667989
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3281195778
Short name T197
Test name
Test status
Simulation time 66786089336 ps
CPU time 31.08 seconds
Started Dec 24 01:32:40 PM PST 23
Finished Dec 24 01:33:12 PM PST 23
Peak memory 200224 kb
Host smart-5b03b199-eb27-47d9-bef4-a969941d17a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281195778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3281195778
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1194885900
Short name T226
Test name
Test status
Simulation time 46110024581 ps
CPU time 257.79 seconds
Started Dec 24 01:37:32 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 200148 kb
Host smart-4bd43a9b-0d16-4c0a-8814-f1c1dd1ba52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194885900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1194885900
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.576949258
Short name T458
Test name
Test status
Simulation time 393565495828 ps
CPU time 343.29 seconds
Started Dec 24 01:37:34 PM PST 23
Finished Dec 24 01:43:22 PM PST 23
Peak memory 210604 kb
Host smart-5a93f14e-4df5-446b-bef5-8e9a682afc93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576949258 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.576949258
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3408874456
Short name T1026
Test name
Test status
Simulation time 41303647507 ps
CPU time 19.82 seconds
Started Dec 24 01:37:33 PM PST 23
Finished Dec 24 01:37:58 PM PST 23
Peak memory 200184 kb
Host smart-5933a336-a6ea-468b-bf6a-47e47473470f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408874456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3408874456
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.4122632889
Short name T1151
Test name
Test status
Simulation time 120181446507 ps
CPU time 592.26 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:47:29 PM PST 23
Peak memory 225100 kb
Host smart-c4e80d12-a147-4122-91a2-961d3aaf4bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122632889 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.4122632889
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2354373891
Short name T973
Test name
Test status
Simulation time 21604169623 ps
CPU time 34.26 seconds
Started Dec 24 01:37:32 PM PST 23
Finished Dec 24 01:38:12 PM PST 23
Peak memory 199668 kb
Host smart-7617adc0-732e-48d4-ba71-11d851ee0479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354373891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2354373891
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1164240753
Short name T388
Test name
Test status
Simulation time 48258361988 ps
CPU time 555.53 seconds
Started Dec 24 01:37:41 PM PST 23
Finished Dec 24 01:47:02 PM PST 23
Peak memory 217124 kb
Host smart-6e69c6de-d3db-4014-86eb-f7d9beb1ffff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164240753 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1164240753
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.4256882711
Short name T210
Test name
Test status
Simulation time 32414060653 ps
CPU time 14.51 seconds
Started Dec 24 01:37:34 PM PST 23
Finished Dec 24 01:37:53 PM PST 23
Peak memory 200196 kb
Host smart-7c3bd380-2ad1-40c5-a9f4-fa7aebf3253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256882711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4256882711
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3573077836
Short name T86
Test name
Test status
Simulation time 28528649804 ps
CPU time 559.65 seconds
Started Dec 24 01:37:33 PM PST 23
Finished Dec 24 01:46:58 PM PST 23
Peak memory 216348 kb
Host smart-16e331e6-d25d-48bc-86b9-228cdee0077a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573077836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3573077836
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.230331555
Short name T992
Test name
Test status
Simulation time 56389146326 ps
CPU time 33.05 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:38:10 PM PST 23
Peak memory 200312 kb
Host smart-ab65a01f-fd23-45e2-9667-311e105981b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230331555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.230331555
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1167399131
Short name T1095
Test name
Test status
Simulation time 18827703229 ps
CPU time 213.86 seconds
Started Dec 24 01:37:31 PM PST 23
Finished Dec 24 01:41:11 PM PST 23
Peak memory 208732 kb
Host smart-a4f7bd22-ffe6-4a5f-be10-5ae58403e765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167399131 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1167399131
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.173931625
Short name T279
Test name
Test status
Simulation time 127787054834 ps
CPU time 34.79 seconds
Started Dec 24 01:37:36 PM PST 23
Finished Dec 24 01:38:18 PM PST 23
Peak memory 200228 kb
Host smart-d9ddd07d-0dee-40d6-a9be-8e5ca8b309d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173931625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.173931625
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2414069343
Short name T348
Test name
Test status
Simulation time 47181169428 ps
CPU time 477.73 seconds
Started Dec 24 01:37:33 PM PST 23
Finished Dec 24 01:45:36 PM PST 23
Peak memory 216708 kb
Host smart-ff8342dc-e315-41f4-941a-8f17f49c65c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414069343 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2414069343
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2724905276
Short name T215
Test name
Test status
Simulation time 21786455209 ps
CPU time 16.66 seconds
Started Dec 24 01:37:40 PM PST 23
Finished Dec 24 01:38:03 PM PST 23
Peak memory 200188 kb
Host smart-2c67068e-ce02-443e-9832-25465f1c0d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724905276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2724905276
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3098330488
Short name T929
Test name
Test status
Simulation time 5598326590 ps
CPU time 69.72 seconds
Started Dec 24 01:37:35 PM PST 23
Finished Dec 24 01:38:49 PM PST 23
Peak memory 215900 kb
Host smart-ea2aec0f-4f24-4ce4-9740-f3c3bf0d7908
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098330488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3098330488
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3328780399
Short name T1196
Test name
Test status
Simulation time 69745481255 ps
CPU time 104.45 seconds
Started Dec 24 01:37:34 PM PST 23
Finished Dec 24 01:39:23 PM PST 23
Peak memory 199988 kb
Host smart-b66fec3d-7550-477b-85a9-d96da4a5f7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328780399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3328780399
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1584912861
Short name T826
Test name
Test status
Simulation time 477273204523 ps
CPU time 1483.27 seconds
Started Dec 24 01:37:51 PM PST 23
Finished Dec 24 02:02:36 PM PST 23
Peak memory 232276 kb
Host smart-ef2b5b4b-eaa7-4250-a9c6-41f6034aa8e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584912861 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1584912861
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1059955575
Short name T169
Test name
Test status
Simulation time 222068014846 ps
CPU time 44.91 seconds
Started Dec 24 01:37:40 PM PST 23
Finished Dec 24 01:38:31 PM PST 23
Peak memory 199500 kb
Host smart-8996b17e-96a7-4941-8bf2-1f7a39255628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059955575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1059955575
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1942193899
Short name T255
Test name
Test status
Simulation time 30794070829 ps
CPU time 282.8 seconds
Started Dec 24 01:37:40 PM PST 23
Finished Dec 24 01:42:29 PM PST 23
Peak memory 208524 kb
Host smart-9b2177a2-c8d9-4efc-814b-5bb764e7f9d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942193899 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1942193899
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.569082018
Short name T556
Test name
Test status
Simulation time 71861755 ps
CPU time 0.56 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:33:14 PM PST 23
Peak memory 195612 kb
Host smart-55fc5f50-4490-4f44-b0e0-461695853f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569082018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.569082018
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.4174046838
Short name T336
Test name
Test status
Simulation time 81882590761 ps
CPU time 158.42 seconds
Started Dec 24 01:33:32 PM PST 23
Finished Dec 24 01:36:12 PM PST 23
Peak memory 200260 kb
Host smart-230abf09-6fb3-4c4c-8c92-b4dd64443de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174046838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4174046838
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3600385329
Short name T856
Test name
Test status
Simulation time 320100272921 ps
CPU time 135.05 seconds
Started Dec 24 01:33:30 PM PST 23
Finished Dec 24 01:35:47 PM PST 23
Peak memory 200168 kb
Host smart-01fa567b-30cc-4e26-9f75-35eee17bf4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600385329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3600385329
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1490737180
Short name T908
Test name
Test status
Simulation time 141933890599 ps
CPU time 221.54 seconds
Started Dec 24 01:33:16 PM PST 23
Finished Dec 24 01:36:58 PM PST 23
Peak memory 200260 kb
Host smart-80fd040c-4cb3-491c-aa6c-f22bef25ec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490737180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1490737180
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1717732385
Short name T875
Test name
Test status
Simulation time 491317048711 ps
CPU time 405.97 seconds
Started Dec 24 01:33:11 PM PST 23
Finished Dec 24 01:39:57 PM PST 23
Peak memory 199984 kb
Host smart-a6b6a877-de89-4590-adb4-229a4ce2788f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717732385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1717732385
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1815545282
Short name T770
Test name
Test status
Simulation time 52931488868 ps
CPU time 217.38 seconds
Started Dec 24 01:33:33 PM PST 23
Finished Dec 24 01:37:12 PM PST 23
Peak memory 200176 kb
Host smart-569994b4-51f2-4336-b244-6b485f53ead8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815545282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1815545282
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3681988979
Short name T1223
Test name
Test status
Simulation time 5387517943 ps
CPU time 3.52 seconds
Started Dec 24 01:33:30 PM PST 23
Finished Dec 24 01:33:35 PM PST 23
Peak memory 199036 kb
Host smart-dd0cbffc-8594-4d99-84ec-2c2ac2252a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681988979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3681988979
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2366063303
Short name T576
Test name
Test status
Simulation time 29853217997 ps
CPU time 63.96 seconds
Started Dec 24 01:33:32 PM PST 23
Finished Dec 24 01:34:37 PM PST 23
Peak memory 200168 kb
Host smart-2b9d1be4-fbc7-44fd-808d-13ca1cf3fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366063303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2366063303
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2177894927
Short name T597
Test name
Test status
Simulation time 13287039799 ps
CPU time 352.43 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:39:29 PM PST 23
Peak memory 200228 kb
Host smart-96d37deb-aa32-45ad-9f33-485619242f56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177894927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2177894927
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.764683581
Short name T541
Test name
Test status
Simulation time 30986767927 ps
CPU time 35.95 seconds
Started Dec 24 01:33:13 PM PST 23
Finished Dec 24 01:33:51 PM PST 23
Peak memory 200196 kb
Host smart-aa63926f-aee5-45cc-9885-b42bff859b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764683581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.764683581
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1551919304
Short name T1205
Test name
Test status
Simulation time 3759498287 ps
CPU time 6.69 seconds
Started Dec 24 01:33:06 PM PST 23
Finished Dec 24 01:33:14 PM PST 23
Peak memory 196116 kb
Host smart-0b00ccef-0b7e-454f-bcb9-f1b7973d26d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551919304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1551919304
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.325119239
Short name T635
Test name
Test status
Simulation time 977254199 ps
CPU time 4.04 seconds
Started Dec 24 01:33:38 PM PST 23
Finished Dec 24 01:33:43 PM PST 23
Peak memory 198732 kb
Host smart-ef12eb37-b887-4f21-9256-df66d173cde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325119239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.325119239
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1193170556
Short name T151
Test name
Test status
Simulation time 98050306683 ps
CPU time 209.98 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:36:43 PM PST 23
Peak memory 216616 kb
Host smart-2aa5e944-1d1f-4c3a-99d5-e1eb9bd82208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193170556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1193170556
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2947426317
Short name T639
Test name
Test status
Simulation time 2132194032 ps
CPU time 1.82 seconds
Started Dec 24 01:33:32 PM PST 23
Finished Dec 24 01:33:35 PM PST 23
Peak memory 198168 kb
Host smart-27718f77-1cfe-4ba4-bd01-5a11c575777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947426317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2947426317
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2542205608
Short name T589
Test name
Test status
Simulation time 7912752115 ps
CPU time 2.27 seconds
Started Dec 24 01:33:29 PM PST 23
Finished Dec 24 01:33:33 PM PST 23
Peak memory 198916 kb
Host smart-ca8cfc3d-370f-467e-98c4-d5a8d543ca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542205608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2542205608
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3680521835
Short name T1119
Test name
Test status
Simulation time 8424380192 ps
CPU time 12.73 seconds
Started Dec 24 01:37:40 PM PST 23
Finished Dec 24 01:37:59 PM PST 23
Peak memory 199656 kb
Host smart-673f22ec-bac7-464b-9650-6819f9e433c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680521835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3680521835
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3192867881
Short name T1140
Test name
Test status
Simulation time 86439627927 ps
CPU time 138.69 seconds
Started Dec 24 01:37:39 PM PST 23
Finished Dec 24 01:40:05 PM PST 23
Peak memory 200232 kb
Host smart-1885266b-5b23-4956-b327-88744907464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192867881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3192867881
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.68680601
Short name T85
Test name
Test status
Simulation time 93435670013 ps
CPU time 504.77 seconds
Started Dec 24 01:37:46 PM PST 23
Finished Dec 24 01:46:15 PM PST 23
Peak memory 212024 kb
Host smart-fc41bf2d-3d5b-43ec-9274-36ff5d95cb3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68680601 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.68680601
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2411008567
Short name T293
Test name
Test status
Simulation time 22693195667 ps
CPU time 38.39 seconds
Started Dec 24 01:37:44 PM PST 23
Finished Dec 24 01:38:25 PM PST 23
Peak memory 200240 kb
Host smart-c934a32f-7ed5-43d6-8439-0d744b8f18a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411008567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2411008567
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1438277695
Short name T712
Test name
Test status
Simulation time 89290992484 ps
CPU time 549.36 seconds
Started Dec 24 01:37:39 PM PST 23
Finished Dec 24 01:46:56 PM PST 23
Peak memory 216696 kb
Host smart-bdb62e73-fcae-4210-af71-4c8f36c17246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438277695 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1438277695
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3134718127
Short name T175
Test name
Test status
Simulation time 135872775001 ps
CPU time 45.29 seconds
Started Dec 24 01:37:48 PM PST 23
Finished Dec 24 01:38:36 PM PST 23
Peak memory 200372 kb
Host smart-2445c454-7bf7-4e01-89ba-53326a2f24ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134718127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3134718127
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2564346450
Short name T741
Test name
Test status
Simulation time 58008547929 ps
CPU time 799.09 seconds
Started Dec 24 01:37:57 PM PST 23
Finished Dec 24 01:51:17 PM PST 23
Peak memory 213960 kb
Host smart-fd57bf8b-65b3-4ca9-8a09-9548e8977733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564346450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2564346450
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.176107791
Short name T330
Test name
Test status
Simulation time 72976359483 ps
CPU time 62.27 seconds
Started Dec 24 01:37:48 PM PST 23
Finished Dec 24 01:38:53 PM PST 23
Peak memory 200284 kb
Host smart-4d362ad6-ad92-4828-8548-648c8f6ef8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176107791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.176107791
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2543812159
Short name T882
Test name
Test status
Simulation time 98988810981 ps
CPU time 212.94 seconds
Started Dec 24 01:37:48 PM PST 23
Finished Dec 24 01:41:24 PM PST 23
Peak memory 200424 kb
Host smart-ee20c491-a9ae-4d06-a177-c6c7ab0d0930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543812159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2543812159
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1514546748
Short name T1106
Test name
Test status
Simulation time 157122382628 ps
CPU time 57.26 seconds
Started Dec 24 01:37:48 PM PST 23
Finished Dec 24 01:38:48 PM PST 23
Peak memory 199616 kb
Host smart-47614d17-66a0-414a-8105-4fc1d10e7330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514546748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1514546748
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2611107686
Short name T820
Test name
Test status
Simulation time 160255849020 ps
CPU time 519.24 seconds
Started Dec 24 01:37:53 PM PST 23
Finished Dec 24 01:46:33 PM PST 23
Peak memory 216896 kb
Host smart-b8c4e147-2df0-478d-9651-bb58b2ef13c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611107686 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2611107686
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2008263790
Short name T350
Test name
Test status
Simulation time 14819698461 ps
CPU time 28.49 seconds
Started Dec 24 01:38:04 PM PST 23
Finished Dec 24 01:38:34 PM PST 23
Peak memory 200116 kb
Host smart-2d95732b-ae8f-44ce-8b8a-84a61bf23c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008263790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2008263790
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2056358318
Short name T1172
Test name
Test status
Simulation time 250358611116 ps
CPU time 1071.65 seconds
Started Dec 24 01:38:04 PM PST 23
Finished Dec 24 01:55:57 PM PST 23
Peak memory 216660 kb
Host smart-bad494a2-1724-489b-a0a7-f333f2962cba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056358318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2056358318
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.4280346242
Short name T838
Test name
Test status
Simulation time 92467117745 ps
CPU time 247.76 seconds
Started Dec 24 01:38:05 PM PST 23
Finished Dec 24 01:42:13 PM PST 23
Peak memory 208732 kb
Host smart-2a4caf48-82e8-48ef-964d-99173bb774ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280346242 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.4280346242
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3748718098
Short name T1149
Test name
Test status
Simulation time 19660892 ps
CPU time 0.55 seconds
Started Dec 24 01:33:13 PM PST 23
Finished Dec 24 01:33:15 PM PST 23
Peak memory 195472 kb
Host smart-27b3498c-6dd8-4180-a33e-88d435cedf7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748718098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3748718098
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3279137491
Short name T1135
Test name
Test status
Simulation time 98808374121 ps
CPU time 48.36 seconds
Started Dec 24 01:33:27 PM PST 23
Finished Dec 24 01:34:17 PM PST 23
Peak memory 198396 kb
Host smart-6303d4cc-c13a-4cf3-ac16-735dd4fecea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279137491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3279137491
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2201766901
Short name T395
Test name
Test status
Simulation time 57502534197 ps
CPU time 91.19 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:35:03 PM PST 23
Peak memory 200268 kb
Host smart-76661993-7753-4b1a-b3c3-40eaa3512f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201766901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2201766901
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1563565901
Short name T382
Test name
Test status
Simulation time 26355855789 ps
CPU time 12.32 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:33:26 PM PST 23
Peak memory 199928 kb
Host smart-6c9ed3ea-f15b-475e-809b-8859677527ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563565901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1563565901
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1010171255
Short name T883
Test name
Test status
Simulation time 505116863921 ps
CPU time 396.09 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:39:50 PM PST 23
Peak memory 200208 kb
Host smart-7fbf0ac5-2460-4339-872e-cd6870bf47ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010171255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1010171255
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3754405653
Short name T422
Test name
Test status
Simulation time 136788864235 ps
CPU time 413.89 seconds
Started Dec 24 01:33:27 PM PST 23
Finished Dec 24 01:40:22 PM PST 23
Peak memory 200204 kb
Host smart-475bd515-9f6e-417e-ae63-8281aef95240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754405653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3754405653
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3133102975
Short name T1224
Test name
Test status
Simulation time 8058462065 ps
CPU time 15.34 seconds
Started Dec 24 01:33:15 PM PST 23
Finished Dec 24 01:33:31 PM PST 23
Peak memory 198860 kb
Host smart-a0fbeb28-63b5-4acc-86ae-d4625bc3e671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133102975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3133102975
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3573433119
Short name T438
Test name
Test status
Simulation time 58358421712 ps
CPU time 31.35 seconds
Started Dec 24 01:33:07 PM PST 23
Finished Dec 24 01:33:39 PM PST 23
Peak memory 199532 kb
Host smart-f894de22-1aec-41f3-aff9-ac3d9f5562a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573433119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3573433119
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.781596179
Short name T415
Test name
Test status
Simulation time 22167987832 ps
CPU time 165.86 seconds
Started Dec 24 01:33:06 PM PST 23
Finished Dec 24 01:35:53 PM PST 23
Peak memory 200196 kb
Host smart-69836e5d-0189-4c82-a43e-f884e7ec44e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781596179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.781596179
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3099799308
Short name T505
Test name
Test status
Simulation time 3638275222 ps
CPU time 9.83 seconds
Started Dec 24 01:33:11 PM PST 23
Finished Dec 24 01:33:23 PM PST 23
Peak memory 198936 kb
Host smart-cf7ad81c-6ed3-4ea3-bc8a-d4828896f295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099799308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3099799308
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1932187377
Short name T735
Test name
Test status
Simulation time 51292891272 ps
CPU time 100.08 seconds
Started Dec 24 01:33:28 PM PST 23
Finished Dec 24 01:35:09 PM PST 23
Peak memory 200188 kb
Host smart-0c87c0c2-15d4-410d-99f4-a9bdef291778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932187377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1932187377
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.696004754
Short name T829
Test name
Test status
Simulation time 652434477 ps
CPU time 1.77 seconds
Started Dec 24 01:33:15 PM PST 23
Finished Dec 24 01:33:17 PM PST 23
Peak memory 195468 kb
Host smart-572ed4a4-5667-41a5-8af2-28d54a11f43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696004754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.696004754
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3164472857
Short name T1182
Test name
Test status
Simulation time 5489097251 ps
CPU time 15.64 seconds
Started Dec 24 01:33:28 PM PST 23
Finished Dec 24 01:33:44 PM PST 23
Peak memory 199964 kb
Host smart-4d4a96b7-4f47-483f-886f-ff34c4a4e085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164472857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3164472857
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.501875679
Short name T760
Test name
Test status
Simulation time 385481543360 ps
CPU time 138.89 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:35:32 PM PST 23
Peak memory 200140 kb
Host smart-eacc42fd-4ec6-48c0-a4e4-fb80838ad733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501875679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.501875679
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3901185167
Short name T867
Test name
Test status
Simulation time 46368157330 ps
CPU time 587.2 seconds
Started Dec 24 01:33:13 PM PST 23
Finished Dec 24 01:43:02 PM PST 23
Peak memory 214348 kb
Host smart-fed8590e-d007-455f-a9e5-e3cc36e005cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901185167 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3901185167
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3759066361
Short name T1085
Test name
Test status
Simulation time 661491587 ps
CPU time 1.89 seconds
Started Dec 24 01:33:25 PM PST 23
Finished Dec 24 01:33:29 PM PST 23
Peak memory 199176 kb
Host smart-f0e7735d-69c4-4f07-9685-e9ec649e1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759066361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3759066361
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.253535033
Short name T612
Test name
Test status
Simulation time 10386516780 ps
CPU time 4.33 seconds
Started Dec 24 01:33:29 PM PST 23
Finished Dec 24 01:33:35 PM PST 23
Peak memory 198712 kb
Host smart-c08a471f-0149-467b-9eaf-3e32b31f37fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253535033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.253535033
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1707628418
Short name T610
Test name
Test status
Simulation time 87661159639 ps
CPU time 68.15 seconds
Started Dec 24 01:38:03 PM PST 23
Finished Dec 24 01:39:13 PM PST 23
Peak memory 200116 kb
Host smart-6811e574-b34f-4648-a011-7344945586cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707628418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1707628418
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3091768933
Short name T636
Test name
Test status
Simulation time 139873672682 ps
CPU time 400.31 seconds
Started Dec 24 01:37:49 PM PST 23
Finished Dec 24 01:44:32 PM PST 23
Peak memory 216928 kb
Host smart-7fd8db3f-7a58-413e-b575-fc1d5c491a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091768933 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3091768933
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.754524627
Short name T802
Test name
Test status
Simulation time 50360893344 ps
CPU time 11.34 seconds
Started Dec 24 01:38:01 PM PST 23
Finished Dec 24 01:38:13 PM PST 23
Peak memory 200112 kb
Host smart-b71e8a01-04e0-427e-98fd-b7905c4c0cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754524627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.754524627
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.175896167
Short name T1138
Test name
Test status
Simulation time 104379024609 ps
CPU time 1064.24 seconds
Started Dec 24 01:37:42 PM PST 23
Finished Dec 24 01:55:31 PM PST 23
Peak memory 224852 kb
Host smart-887eaa3a-abc0-40a5-a377-25be9fd8eb76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175896167 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.175896167
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2965488573
Short name T1091
Test name
Test status
Simulation time 138121727247 ps
CPU time 301.79 seconds
Started Dec 24 01:37:43 PM PST 23
Finished Dec 24 01:42:48 PM PST 23
Peak memory 200196 kb
Host smart-ac5d4e6f-4553-4dc1-8a14-aed0f72cf491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965488573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2965488573
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2997758650
Short name T1129
Test name
Test status
Simulation time 658234052440 ps
CPU time 1086.83 seconds
Started Dec 24 01:37:49 PM PST 23
Finished Dec 24 01:55:58 PM PST 23
Peak memory 216872 kb
Host smart-1f63e5a8-9958-4741-92c8-f51103c0b357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997758650 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2997758650
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.4016672711
Short name T138
Test name
Test status
Simulation time 15579236742 ps
CPU time 15.99 seconds
Started Dec 24 01:38:00 PM PST 23
Finished Dec 24 01:38:17 PM PST 23
Peak memory 198728 kb
Host smart-1f4be463-ae10-45ed-a4c9-9d57117e698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016672711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4016672711
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.617835341
Short name T400
Test name
Test status
Simulation time 67940208502 ps
CPU time 31.5 seconds
Started Dec 24 01:37:43 PM PST 23
Finished Dec 24 01:38:18 PM PST 23
Peak memory 199216 kb
Host smart-715aa6f7-d21d-4df5-8613-ad12e2670f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617835341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.617835341
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3468576971
Short name T784
Test name
Test status
Simulation time 169574337938 ps
CPU time 378.35 seconds
Started Dec 24 01:38:01 PM PST 23
Finished Dec 24 01:44:20 PM PST 23
Peak memory 220508 kb
Host smart-fbeef070-40a6-42d5-a4a1-dc298a33d9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468576971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3468576971
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1992798539
Short name T1141
Test name
Test status
Simulation time 72968300568 ps
CPU time 122.7 seconds
Started Dec 24 01:38:18 PM PST 23
Finished Dec 24 01:40:22 PM PST 23
Peak memory 200220 kb
Host smart-33502b7b-404b-49e5-bcae-b09cded38794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992798539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1992798539
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3607841146
Short name T749
Test name
Test status
Simulation time 15027483567 ps
CPU time 190.36 seconds
Started Dec 24 01:38:04 PM PST 23
Finished Dec 24 01:41:15 PM PST 23
Peak memory 215944 kb
Host smart-444206ff-b6f4-4831-ae2c-a047e6b22e1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607841146 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3607841146
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3603659287
Short name T251
Test name
Test status
Simulation time 281394937778 ps
CPU time 26.39 seconds
Started Dec 24 01:38:19 PM PST 23
Finished Dec 24 01:38:47 PM PST 23
Peak memory 200048 kb
Host smart-550d5ffa-8c0f-4469-9e34-2a37db66b30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603659287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3603659287
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2997311178
Short name T88
Test name
Test status
Simulation time 71697647698 ps
CPU time 1422.33 seconds
Started Dec 24 01:38:14 PM PST 23
Finished Dec 24 02:01:57 PM PST 23
Peak memory 216800 kb
Host smart-069f7c89-2647-49bd-8ae7-d55c8b505ef8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997311178 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2997311178
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1840720479
Short name T281
Test name
Test status
Simulation time 109790274344 ps
CPU time 160.33 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:41:02 PM PST 23
Peak memory 200172 kb
Host smart-4b2c32fe-8725-4129-a8a6-f449621b11f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840720479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1840720479
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1492448368
Short name T87
Test name
Test status
Simulation time 201951534878 ps
CPU time 1007.82 seconds
Started Dec 24 01:38:13 PM PST 23
Finished Dec 24 01:55:02 PM PST 23
Peak memory 226328 kb
Host smart-6da686d7-9dfe-45d4-9f9f-0af69dccc980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492448368 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1492448368
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1420841874
Short name T715
Test name
Test status
Simulation time 112824212914 ps
CPU time 50.95 seconds
Started Dec 24 01:38:19 PM PST 23
Finished Dec 24 01:39:12 PM PST 23
Peak memory 200136 kb
Host smart-76ac8761-d659-42e5-bf9d-8bbdef652ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420841874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1420841874
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.744130734
Short name T662
Test name
Test status
Simulation time 61422245156 ps
CPU time 357.54 seconds
Started Dec 24 01:38:15 PM PST 23
Finished Dec 24 01:44:13 PM PST 23
Peak memory 213448 kb
Host smart-be3b951f-ccad-4b1f-9ce2-2199376a2812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744130734 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.744130734
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.292720163
Short name T539
Test name
Test status
Simulation time 23848904 ps
CPU time 0.55 seconds
Started Dec 24 01:33:30 PM PST 23
Finished Dec 24 01:33:32 PM PST 23
Peak memory 194552 kb
Host smart-ae3a1560-1da9-4983-9313-d40aa0405927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292720163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.292720163
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.797379247
Short name T625
Test name
Test status
Simulation time 40699042696 ps
CPU time 15.75 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:33:53 PM PST 23
Peak memory 200192 kb
Host smart-fb20787c-f7bc-4cc7-91d6-c3f07c697a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797379247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.797379247
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2157693708
Short name T691
Test name
Test status
Simulation time 16291663937 ps
CPU time 24.67 seconds
Started Dec 24 01:33:30 PM PST 23
Finished Dec 24 01:33:56 PM PST 23
Peak memory 200228 kb
Host smart-71b9a84d-5407-4cbb-aa08-216a7b5e5915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157693708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2157693708
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.4200170572
Short name T960
Test name
Test status
Simulation time 173478216120 ps
CPU time 1359.33 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:55:52 PM PST 23
Peak memory 200208 kb
Host smart-e2d4f549-b27e-4d8e-9cf3-737cd54f2c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4200170572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4200170572
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1260454414
Short name T807
Test name
Test status
Simulation time 4163853006 ps
CPU time 3.4 seconds
Started Dec 24 01:33:28 PM PST 23
Finished Dec 24 01:33:32 PM PST 23
Peak memory 197892 kb
Host smart-3bfac548-f7f7-4375-a43b-07e9297f0ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260454414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1260454414
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2998390376
Short name T164
Test name
Test status
Simulation time 71545938373 ps
CPU time 126.19 seconds
Started Dec 24 01:33:07 PM PST 23
Finished Dec 24 01:35:14 PM PST 23
Peak memory 198920 kb
Host smart-96ecbe28-2fda-4bbb-a421-97c291f1cea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998390376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2998390376
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3736854917
Short name T930
Test name
Test status
Simulation time 11539739109 ps
CPU time 527.74 seconds
Started Dec 24 01:33:24 PM PST 23
Finished Dec 24 01:42:12 PM PST 23
Peak memory 200152 kb
Host smart-d6eca542-84f4-4b24-9293-4db9b677fd31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3736854917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3736854917
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2138787282
Short name T1047
Test name
Test status
Simulation time 5075571362 ps
CPU time 20.73 seconds
Started Dec 24 01:33:28 PM PST 23
Finished Dec 24 01:33:50 PM PST 23
Peak memory 199176 kb
Host smart-a7590a7c-fd8e-4cf5-af1a-fa5013db130e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138787282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2138787282
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3968011591
Short name T1103
Test name
Test status
Simulation time 28319061870 ps
CPU time 12.28 seconds
Started Dec 24 01:33:05 PM PST 23
Finished Dec 24 01:33:18 PM PST 23
Peak memory 199512 kb
Host smart-0fe413cd-ef21-4774-ba11-6d473f09997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968011591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3968011591
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3164673011
Short name T903
Test name
Test status
Simulation time 45239905648 ps
CPU time 19.97 seconds
Started Dec 24 01:33:26 PM PST 23
Finished Dec 24 01:33:47 PM PST 23
Peak memory 195624 kb
Host smart-54c2cfcd-7bfd-47e2-8fc8-a3af1dec2419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164673011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3164673011
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.179266774
Short name T646
Test name
Test status
Simulation time 263779508 ps
CPU time 1.48 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:33:34 PM PST 23
Peak memory 199092 kb
Host smart-ef307018-1a33-4879-b59e-e06b51bf1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179266774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.179266774
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2285003428
Short name T128
Test name
Test status
Simulation time 284122012178 ps
CPU time 1880.13 seconds
Started Dec 24 01:33:30 PM PST 23
Finished Dec 24 02:04:52 PM PST 23
Peak memory 200252 kb
Host smart-9ba34b37-b667-4b06-8530-0d0bc3a2e9df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285003428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2285003428
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2109659381
Short name T861
Test name
Test status
Simulation time 162305180048 ps
CPU time 1006.98 seconds
Started Dec 24 01:33:26 PM PST 23
Finished Dec 24 01:50:14 PM PST 23
Peak memory 226236 kb
Host smart-2aec24e5-d721-46e1-adb2-6efaac5d966d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109659381 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2109659381
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3893605239
Short name T1056
Test name
Test status
Simulation time 8121222767 ps
CPU time 5.77 seconds
Started Dec 24 01:33:25 PM PST 23
Finished Dec 24 01:33:32 PM PST 23
Peak memory 199196 kb
Host smart-7f884eaf-79c6-446f-aee3-daabaf118412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893605239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3893605239
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1385195060
Short name T586
Test name
Test status
Simulation time 70745675238 ps
CPU time 64.62 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:34:18 PM PST 23
Peak memory 200108 kb
Host smart-bc3a3063-51e1-462f-a107-47f7c3dccfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385195060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1385195060
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3240943959
Short name T130
Test name
Test status
Simulation time 128109022866 ps
CPU time 191.83 seconds
Started Dec 24 01:38:31 PM PST 23
Finished Dec 24 01:41:44 PM PST 23
Peak memory 200020 kb
Host smart-7a7aca61-992b-4a89-b559-900100fd0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240943959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3240943959
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1413117061
Short name T78
Test name
Test status
Simulation time 103509155283 ps
CPU time 903.95 seconds
Started Dec 24 01:38:26 PM PST 23
Finished Dec 24 01:53:31 PM PST 23
Peak memory 216896 kb
Host smart-cd32315f-9281-441e-b439-e75c5f181a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413117061 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1413117061
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1436159286
Short name T1074
Test name
Test status
Simulation time 96924520566 ps
CPU time 172.86 seconds
Started Dec 24 01:38:12 PM PST 23
Finished Dec 24 01:41:06 PM PST 23
Peak memory 200224 kb
Host smart-77607a84-58fc-4516-8498-9647cdc85796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436159286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1436159286
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2528830997
Short name T328
Test name
Test status
Simulation time 52540250450 ps
CPU time 128.68 seconds
Started Dec 24 01:38:19 PM PST 23
Finished Dec 24 01:40:30 PM PST 23
Peak memory 208476 kb
Host smart-d39e1f31-4165-4f3e-ad93-5971a1712476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528830997 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2528830997
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.251866243
Short name T1152
Test name
Test status
Simulation time 20701078136 ps
CPU time 31.51 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:38:53 PM PST 23
Peak memory 200168 kb
Host smart-dda9302e-5705-469c-8514-7848fdebfb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251866243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.251866243
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.4002519316
Short name T342
Test name
Test status
Simulation time 214667015062 ps
CPU time 365.53 seconds
Started Dec 24 01:38:14 PM PST 23
Finished Dec 24 01:44:21 PM PST 23
Peak memory 225120 kb
Host smart-743f036f-9908-4c76-8a8c-a4affb9d4a48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002519316 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.4002519316
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.577693512
Short name T166
Test name
Test status
Simulation time 67679883323 ps
CPU time 30.69 seconds
Started Dec 24 01:38:21 PM PST 23
Finished Dec 24 01:38:53 PM PST 23
Peak memory 200196 kb
Host smart-7c95c022-2904-44e5-925a-ff86ca03ce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577693512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.577693512
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3652970800
Short name T1226
Test name
Test status
Simulation time 84291575412 ps
CPU time 169.58 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:41:12 PM PST 23
Peak memory 208468 kb
Host smart-974ec902-a6ce-42fc-8fe1-2bb0f1b2712b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652970800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3652970800
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2567227238
Short name T1101
Test name
Test status
Simulation time 83600183156 ps
CPU time 33.79 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:38:56 PM PST 23
Peak memory 200140 kb
Host smart-1d59dd7c-e547-411e-bad2-2617a45f44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567227238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2567227238
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1243126837
Short name T454
Test name
Test status
Simulation time 15439772439 ps
CPU time 188.8 seconds
Started Dec 24 01:38:03 PM PST 23
Finished Dec 24 01:41:13 PM PST 23
Peak memory 216364 kb
Host smart-adfd1952-4b75-4fda-b83b-1e1465185856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243126837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1243126837
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1038657024
Short name T183
Test name
Test status
Simulation time 17060441559 ps
CPU time 26.65 seconds
Started Dec 24 01:38:19 PM PST 23
Finished Dec 24 01:38:47 PM PST 23
Peak memory 200112 kb
Host smart-bf62e31b-9a96-4e1f-b487-ffb1a4e274b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038657024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1038657024
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.21034576
Short name T285
Test name
Test status
Simulation time 364821223515 ps
CPU time 1206.54 seconds
Started Dec 24 01:38:12 PM PST 23
Finished Dec 24 01:58:20 PM PST 23
Peak memory 226704 kb
Host smart-4e1d846e-ec4a-4dcd-ac30-562470ab66c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21034576 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.21034576
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1672870145
Short name T791
Test name
Test status
Simulation time 116814892473 ps
CPU time 151.18 seconds
Started Dec 24 01:38:13 PM PST 23
Finished Dec 24 01:40:45 PM PST 23
Peak memory 200264 kb
Host smart-5e890f65-0f07-4e8b-9747-046d8823196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672870145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1672870145
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.218025360
Short name T89
Test name
Test status
Simulation time 135268251207 ps
CPU time 865.64 seconds
Started Dec 24 01:38:21 PM PST 23
Finished Dec 24 01:52:48 PM PST 23
Peak memory 225092 kb
Host smart-1f91c9a4-38f6-467e-9f98-95ce53832f39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218025360 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.218025360
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1449724502
Short name T739
Test name
Test status
Simulation time 40211662401 ps
CPU time 70.19 seconds
Started Dec 24 01:38:13 PM PST 23
Finished Dec 24 01:39:25 PM PST 23
Peak memory 200220 kb
Host smart-a9c73fd9-a844-4f29-8f3a-f54da0507be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449724502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1449724502
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3049999786
Short name T419
Test name
Test status
Simulation time 30560479523 ps
CPU time 378.65 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:44:41 PM PST 23
Peak memory 210660 kb
Host smart-0691953f-be45-49b2-953c-54cba66da929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049999786 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3049999786
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1613367164
Short name T247
Test name
Test status
Simulation time 57548587514 ps
CPU time 19.78 seconds
Started Dec 24 01:38:16 PM PST 23
Finished Dec 24 01:38:36 PM PST 23
Peak memory 200168 kb
Host smart-a1851ab3-9d94-470a-8905-ec5e82f00746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613367164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1613367164
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.899468892
Short name T995
Test name
Test status
Simulation time 99334201338 ps
CPU time 667.73 seconds
Started Dec 24 01:38:19 PM PST 23
Finished Dec 24 01:49:27 PM PST 23
Peak memory 216672 kb
Host smart-fd8c2148-756b-4c44-aaba-893ecb668525
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899468892 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.899468892
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.840384138
Short name T1155
Test name
Test status
Simulation time 14833673 ps
CPU time 0.6 seconds
Started Dec 24 01:33:12 PM PST 23
Finished Dec 24 01:33:14 PM PST 23
Peak memory 195588 kb
Host smart-4e28b2dd-bd45-4931-82e7-62d2e5e055e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840384138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.840384138
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2782731789
Short name T113
Test name
Test status
Simulation time 301459273870 ps
CPU time 239.85 seconds
Started Dec 24 01:33:15 PM PST 23
Finished Dec 24 01:37:16 PM PST 23
Peak memory 200316 kb
Host smart-b65afa82-7fde-4584-a054-117e86533d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782731789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2782731789
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1182507717
Short name T881
Test name
Test status
Simulation time 39976439591 ps
CPU time 36.44 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:34:09 PM PST 23
Peak memory 199300 kb
Host smart-964bbd5d-daa1-4540-b755-1f1c2897d5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182507717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1182507717
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2770246153
Short name T567
Test name
Test status
Simulation time 72064672253 ps
CPU time 25.36 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:33:57 PM PST 23
Peak memory 198216 kb
Host smart-3366400a-ae19-4051-bb8b-041a545b68f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770246153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2770246153
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.719095000
Short name T982
Test name
Test status
Simulation time 12864113076 ps
CPU time 11.11 seconds
Started Dec 24 01:33:32 PM PST 23
Finished Dec 24 01:33:45 PM PST 23
Peak memory 196636 kb
Host smart-f2fc4b11-4cd7-48ee-b138-d2de24b44f07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719095000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.719095000
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1433052607
Short name T563
Test name
Test status
Simulation time 90388627549 ps
CPU time 734.94 seconds
Started Dec 24 01:33:14 PM PST 23
Finished Dec 24 01:45:30 PM PST 23
Peak memory 200220 kb
Host smart-00aa3881-5331-42f7-8541-10dd117e914c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433052607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1433052607
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1480693719
Short name T545
Test name
Test status
Simulation time 6129859787 ps
CPU time 4.42 seconds
Started Dec 24 01:33:37 PM PST 23
Finished Dec 24 01:33:43 PM PST 23
Peak memory 197996 kb
Host smart-233e5743-e213-45e0-9896-fea710f292ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480693719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1480693719
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2749123225
Short name T928
Test name
Test status
Simulation time 39346755020 ps
CPU time 14.48 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:33:51 PM PST 23
Peak memory 194000 kb
Host smart-0376c17c-d4f3-49e9-8039-1155db4b5018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749123225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2749123225
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1435880239
Short name T876
Test name
Test status
Simulation time 23138094636 ps
CPU time 108.14 seconds
Started Dec 24 01:33:33 PM PST 23
Finished Dec 24 01:35:22 PM PST 23
Peak memory 200116 kb
Host smart-02e77065-0bad-4514-be4e-f4e206e59d7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435880239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1435880239
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1910012571
Short name T773
Test name
Test status
Simulation time 1842317757 ps
CPU time 1.33 seconds
Started Dec 24 01:33:14 PM PST 23
Finished Dec 24 01:33:17 PM PST 23
Peak memory 198088 kb
Host smart-8881f47f-12c6-4e8f-80b5-ec22f431e751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910012571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1910012571
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.705683740
Short name T394
Test name
Test status
Simulation time 87723924911 ps
CPU time 29.4 seconds
Started Dec 24 01:33:29 PM PST 23
Finished Dec 24 01:34:00 PM PST 23
Peak memory 200136 kb
Host smart-a086b0f0-93f8-4aaa-ae56-8160a5103a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705683740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.705683740
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2435560258
Short name T433
Test name
Test status
Simulation time 40976204533 ps
CPU time 16.37 seconds
Started Dec 24 01:33:35 PM PST 23
Finished Dec 24 01:33:53 PM PST 23
Peak memory 195572 kb
Host smart-dfee14ab-67ae-4c69-a2cb-9dee49847ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435560258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2435560258
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3275826775
Short name T878
Test name
Test status
Simulation time 647453486 ps
CPU time 2.43 seconds
Started Dec 24 01:33:14 PM PST 23
Finished Dec 24 01:33:18 PM PST 23
Peak memory 198612 kb
Host smart-f4b3ee1d-1702-477e-918f-83f2d018a274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275826775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3275826775
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.34122002
Short name T1137
Test name
Test status
Simulation time 981743577823 ps
CPU time 1240.6 seconds
Started Dec 24 01:33:32 PM PST 23
Finished Dec 24 01:54:14 PM PST 23
Peak memory 200108 kb
Host smart-284180ed-88bb-4151-81e5-9b8802fc3e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34122002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.34122002
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3978593449
Short name T455
Test name
Test status
Simulation time 154776131092 ps
CPU time 735.01 seconds
Started Dec 24 01:33:29 PM PST 23
Finished Dec 24 01:45:45 PM PST 23
Peak memory 216660 kb
Host smart-cc545313-c740-4d27-82f2-a4677f62dc82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978593449 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3978593449
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3082876722
Short name T1122
Test name
Test status
Simulation time 1085779858 ps
CPU time 3.74 seconds
Started Dec 24 01:33:31 PM PST 23
Finished Dec 24 01:33:36 PM PST 23
Peak memory 199576 kb
Host smart-442143c4-22ae-4a9b-8fbc-b40e66ca659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082876722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3082876722
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.4281564979
Short name T964
Test name
Test status
Simulation time 109233518437 ps
CPU time 43.56 seconds
Started Dec 24 01:33:25 PM PST 23
Finished Dec 24 01:34:10 PM PST 23
Peak memory 200216 kb
Host smart-5b6d00c3-6db4-4c5b-bf4a-0e74a035ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281564979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.4281564979
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2089247318
Short name T230
Test name
Test status
Simulation time 156790422730 ps
CPU time 475.38 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:46:17 PM PST 23
Peak memory 200164 kb
Host smart-1456f8ca-b876-4525-93e2-8ef24b286377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089247318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2089247318
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.50289032
Short name T1183
Test name
Test status
Simulation time 83573046205 ps
CPU time 493.57 seconds
Started Dec 24 01:38:03 PM PST 23
Finished Dec 24 01:46:18 PM PST 23
Peak memory 209092 kb
Host smart-93631bcd-ecb4-41e7-b73c-d8abddda4afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50289032 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.50289032
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.716600277
Short name T352
Test name
Test status
Simulation time 34305589224 ps
CPU time 16.58 seconds
Started Dec 24 01:38:13 PM PST 23
Finished Dec 24 01:38:31 PM PST 23
Peak memory 200232 kb
Host smart-3adbe5d9-1380-4699-a7c3-795a061c07de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716600277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.716600277
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.20993832
Short name T379
Test name
Test status
Simulation time 118209992830 ps
CPU time 1505.62 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 02:03:56 PM PST 23
Peak memory 224480 kb
Host smart-409afd4b-568d-4672-bec4-4c0e53470a31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20993832 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.20993832
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.422355098
Short name T160
Test name
Test status
Simulation time 36405353828 ps
CPU time 26.31 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:38:48 PM PST 23
Peak memory 200220 kb
Host smart-e6e4cb5d-d4da-4acd-a34c-eb85bd4d9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422355098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.422355098
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.80279817
Short name T746
Test name
Test status
Simulation time 18956682098 ps
CPU time 154.5 seconds
Started Dec 24 01:38:33 PM PST 23
Finished Dec 24 01:41:08 PM PST 23
Peak memory 216724 kb
Host smart-bd01754c-a388-4899-be34-6ca8cfc940f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80279817 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.80279817
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3049940575
Short name T343
Test name
Test status
Simulation time 94704729833 ps
CPU time 37.8 seconds
Started Dec 24 01:38:48 PM PST 23
Finished Dec 24 01:39:27 PM PST 23
Peak memory 200208 kb
Host smart-e95dac70-a970-4c16-8b0f-69f8923d6cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049940575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3049940575
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3142753879
Short name T320
Test name
Test status
Simulation time 548761086182 ps
CPU time 1399.11 seconds
Started Dec 24 01:38:50 PM PST 23
Finished Dec 24 02:02:10 PM PST 23
Peak memory 232888 kb
Host smart-10ab5a3c-2140-4184-a970-abbc7e2b41bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142753879 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3142753879
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2537127943
Short name T988
Test name
Test status
Simulation time 66610215721 ps
CPU time 100.8 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:40:14 PM PST 23
Peak memory 199980 kb
Host smart-99873441-c6b4-483a-b59a-ede1f556c009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537127943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2537127943
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3441891295
Short name T443
Test name
Test status
Simulation time 22580078945 ps
CPU time 252.77 seconds
Started Dec 24 01:38:46 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 215920 kb
Host smart-6dbc76ae-01f7-4879-8ff6-e34a1196071f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441891295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3441891295
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2974984291
Short name T153
Test name
Test status
Simulation time 75028883467 ps
CPU time 33.83 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:39:07 PM PST 23
Peak memory 199724 kb
Host smart-8ecad39a-f55f-4860-a52e-acdcce041dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974984291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2974984291
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2371807457
Short name T227
Test name
Test status
Simulation time 230342818750 ps
CPU time 708.99 seconds
Started Dec 24 01:38:35 PM PST 23
Finished Dec 24 01:50:24 PM PST 23
Peak memory 225156 kb
Host smart-a75a2dcd-ef40-480b-8810-827aceb53795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371807457 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2371807457
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.416282561
Short name T524
Test name
Test status
Simulation time 58773967314 ps
CPU time 22.81 seconds
Started Dec 24 01:38:32 PM PST 23
Finished Dec 24 01:38:56 PM PST 23
Peak memory 199408 kb
Host smart-78837d1d-29ac-4a6e-b667-ceaf92f02b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416282561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.416282561
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1285310551
Short name T734
Test name
Test status
Simulation time 75407488697 ps
CPU time 1193.15 seconds
Started Dec 24 01:38:31 PM PST 23
Finished Dec 24 01:58:25 PM PST 23
Peak memory 216924 kb
Host smart-c24b9a17-35ae-44d1-bfa6-6592c0de4987
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285310551 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1285310551
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1256777143
Short name T134
Test name
Test status
Simulation time 328300443622 ps
CPU time 509.78 seconds
Started Dec 24 01:38:33 PM PST 23
Finished Dec 24 01:47:04 PM PST 23
Peak memory 216956 kb
Host smart-82d7d81d-11de-40f3-9fa9-3d1da4c8886b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256777143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1256777143
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1163061414
Short name T582
Test name
Test status
Simulation time 9876761788 ps
CPU time 147.02 seconds
Started Dec 24 01:38:49 PM PST 23
Finished Dec 24 01:41:16 PM PST 23
Peak memory 200320 kb
Host smart-83229bad-0008-4955-8bf6-2a5ce37db0db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163061414 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1163061414
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.300186101
Short name T173
Test name
Test status
Simulation time 53739788302 ps
CPU time 263.84 seconds
Started Dec 24 01:38:20 PM PST 23
Finished Dec 24 01:42:46 PM PST 23
Peak memory 200052 kb
Host smart-7751ee4f-0a9c-47a8-a39e-64d0b0867571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300186101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.300186101
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1857057833
Short name T717
Test name
Test status
Simulation time 234964562940 ps
CPU time 794.35 seconds
Started Dec 24 01:38:48 PM PST 23
Finished Dec 24 01:52:03 PM PST 23
Peak memory 225240 kb
Host smart-6e636539-7592-4fa4-9f2a-ca89ce8e68a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857057833 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1857057833
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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