Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	144060	1			T2	1		T3	5		T4	8
all_values[1]	144060	1			T2	1		T3	5		T4	8
all_values[2]	144060	1			T2	1		T3	5		T4	8
all_values[3]	144060	1			T2	1		T3	5		T4	8
all_values[4]	144060	1			T2	1		T3	5		T4	8
all_values[5]	144060	1			T2	1		T3	5		T4	8
all_values[6]	144060	1			T2	1		T3	5		T4	8
all_values[7]	144060	1			T2	1		T3	5		T4	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

586471

1

T2

8

T3

10

T4

35

auto[1]

566009

1

T3

30

T4

29

T8

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133634

1

T2

8

T3

32

T4

41

auto[1]

18846

1

T3

8

T4

23

T8

19

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	67782	1			T2	1		T4	4		T5	1
all_values[0]	auto[0]	auto[1]	2873	1			T3	1		T4	1		T8	2
all_values[0]	auto[1]	auto[0]	70844	1			T3	1		T4	2		T8	1
all_values[0]	auto[1]	auto[1]	2561	1			T3	3		T4	1		T8	2
all_values[1]	auto[0]	auto[0]	70396	1			T2	1		T3	4		T4	4
all_values[1]	auto[0]	auto[1]	2650	1			T4	2		T8	1		T32	1
all_values[1]	auto[1]	auto[0]	68630	1			T3	1		T4	1		T8	1
all_values[1]	auto[1]	auto[1]	2384	1			T4	1		T8	2		T32	2
all_values[2]	auto[0]	auto[0]	70848	1			T2	1		T3	1		T4	2
all_values[2]	auto[0]	auto[1]	2807	1			T4	3		T33	1		T32	1
all_values[2]	auto[1]	auto[0]	67878	1			T3	4		T4	3		T8	4
all_values[2]	auto[1]	auto[1]	2527	1			T33	1		T32	2		T100	1
all_values[3]	auto[0]	auto[0]	68113	1			T2	1		T4	1		T5	1
all_values[3]	auto[0]	auto[1]	276	1			T3	1		T4	4		T8	3
all_values[3]	auto[1]	auto[0]	75441	1			T3	4		T4	2		T8	1
all_values[3]	auto[1]	auto[1]	230	1			T4	1		T32	1		T53	2
all_values[4]	auto[0]	auto[0]	77851	1			T2	1		T3	2		T4	2
all_values[4]	auto[0]	auto[1]	498	1			T4	2		T8	2		T100	3
all_values[4]	auto[1]	auto[0]	65198	1			T3	3		T4	2		T33	1
all_values[4]	auto[1]	auto[1]	513	1			T4	2		T33	3		T32	2
all_values[5]	auto[0]	auto[0]	70348	1			T2	1		T3	1		T4	3
all_values[5]	auto[0]	auto[1]	182	1			T4	3		T8	1		T33	3
all_values[5]	auto[1]	auto[0]	73342	1			T3	4		T4	2		T8	3
all_values[5]	auto[1]	auto[1]	188	1			T8	1		T33	1		T32	3
all_values[6]	auto[0]	auto[0]	77092	1			T2	1		T4	2		T5	1
all_values[6]	auto[0]	auto[1]	207	1			T4	2		T53	4		T408	1
all_values[6]	auto[1]	auto[0]	66577	1			T3	3		T4	4		T8	3
all_values[6]	auto[1]	auto[1]	184	1			T3	2		T8	1		T33	4
all_values[7]	auto[0]	auto[0]	74174	1			T2	1		T5	1		T8	1
all_values[7]	auto[0]	auto[1]	374	1			T8	2		T33	3		T53	4
all_values[7]	auto[1]	auto[0]	69120	1			T3	4		T4	7		T32	5
all_values[7]	auto[1]	auto[1]	392	1			T3	1		T4	1		T8	2