Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2529

1

T1

2

T2

1

T3

1

auto[UartRx]

2529

1

T1

2

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4463	1			T1	4		T2	2		T3	2
values[1]	41	1			T27	2		T427	1		T344	1
values[2]	50	1			T27	2		T76	1		T55	1
values[3]	51	1			T27	1		T55	1		T210	2
values[4]	50	1			T27	2		T30	1		T26	3
values[5]	56	1			T27	1		T76	1		T427	1
values[6]	62	1			T315	2		T30	1		T26	1
values[7]	68	1			T27	2		T26	1		T55	1
values[8]	56	1			T27	1		T26	1		T210	2
values[9]	51	1			T27	1		T315	1		T30	1
values[10]	66	1			T27	2		T26	1		T427	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2309	1			T1	2		T2	1		T3	1
auto[UartTx]	values[1]	15	1			T267	1		T462	1		T145	1
auto[UartTx]	values[2]	19	1			T27	1		T210	1		T267	1
auto[UartTx]	values[3]	18	1			T267	2		T463	1		T258	1
auto[UartTx]	values[4]	18	1			T27	1		T26	1		T442	1
auto[UartTx]	values[5]	25	1			T76	1		T463	1		T329	1
auto[UartTx]	values[6]	19	1			T315	1		T427	1		T56	1
auto[UartTx]	values[7]	25	1			T27	1		T26	1		T427	1
auto[UartTx]	values[8]	21	1			T210	1		T344	1		T464	1
auto[UartTx]	values[9]	19	1			T27	1		T315	1		T344	1
auto[UartTx]	values[10]	26	1			T27	1		T427	1		T344	1
auto[UartRx]	values[0]	2154	1			T1	2		T2	1		T3	1
auto[UartRx]	values[1]	26	1			T27	2		T427	1		T344	1
auto[UartRx]	values[2]	31	1			T27	1		T76	1		T55	1
auto[UartRx]	values[3]	33	1			T27	1		T55	1		T210	2
auto[UartRx]	values[4]	32	1			T27	1		T30	1		T26	2
auto[UartRx]	values[5]	31	1			T27	1		T427	1		T56	1
auto[UartRx]	values[6]	43	1			T315	1		T30	1		T26	1
auto[UartRx]	values[7]	43	1			T27	1		T55	1		T427	2
auto[UartRx]	values[8]	35	1			T27	1		T26	1		T210	1
auto[UartRx]	values[9]	32	1			T30	1		T76	2		T462	1
auto[UartRx]	values[10]	40	1			T27	1		T26	1		T427	1