Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1912	1			T13	6		T18	2		T19	3
auto[BaudRate115200]	2158	1			T11	2		T13	3		T19	6
auto[BaudRate230400]	1917	1			T11	1		T13	6		T19	15
auto[BaudRate128Kbps]	2012	1			T11	1		T13	18		T19	15
auto[BaudRate256Kbps]	2171	1			T13	9		T19	5		T14	2
auto[BaudRate1Mbps]	1756	1			T13	9		T19	12		T14	3
auto[BaudRate1p5Mbps]	1282	1			T13	9		T17	1		T14	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1160	1			T13	60		T19	56		T20	2
freqs[25]	1410	1			T14	6		T21	10		T15	55
freqs[48]	548	1			T113	8		T185	7		T453	9
freqs[50]	703	1			T260	28		T118	10		T465	21
freqs[100]	1157	1			T22	3		T23	5		T418	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	145	1			T13	6		T19	3		T266	1
auto[BaudRate9600]	freqs[25]	203	1			T21	1		T15	5		T34	1
auto[BaudRate9600]	freqs[48]	71	1			T113	1		T453	2		T466	3
auto[BaudRate9600]	freqs[50]	98	1			T118	1		T465	3		T455	8
auto[BaudRate9600]	freqs[100]	168	1			T418	2		T315	1		T26	3
auto[BaudRate115200]	freqs[24]	188	1			T13	3		T19	6		T20	1
auto[BaudRate115200]	freqs[25]	177	1			T21	1		T15	9		T102	2
auto[BaudRate115200]	freqs[48]	86	1			T113	1		T185	1		T453	1
auto[BaudRate115200]	freqs[50]	135	1			T260	6		T118	1		T465	3
auto[BaudRate115200]	freqs[100]	149	1			T418	1		T315	5		T467	1
auto[BaudRate230400]	freqs[24]	183	1			T13	6		T19	15		T20	1
auto[BaudRate230400]	freqs[25]	229	1			T21	1		T15	11		T102	1
auto[BaudRate230400]	freqs[48]	73	1			T113	3		T453	1		T466	3
auto[BaudRate230400]	freqs[50]	75	1			T260	1		T455	4		T468	1
auto[BaudRate230400]	freqs[100]	165	1			T22	1		T26	10		T116	2
auto[BaudRate128Kbps]	freqs[24]	184	1			T13	18		T19	15		T266	1
auto[BaudRate128Kbps]	freqs[25]	237	1			T21	3		T15	9		T102	3
auto[BaudRate128Kbps]	freqs[48]	80	1			T113	2		T185	1		T453	3
auto[BaudRate128Kbps]	freqs[50]	94	1			T260	5		T118	4		T465	3
auto[BaudRate128Kbps]	freqs[100]	159	1			T315	4		T26	7		T116	2
auto[BaudRate256Kbps]	freqs[24]	168	1			T13	9		T19	5		T266	1
auto[BaudRate256Kbps]	freqs[25]	231	1			T14	2		T21	3		T15	7
auto[BaudRate256Kbps]	freqs[48]	69	1			T185	1		T453	1		T466	9
auto[BaudRate256Kbps]	freqs[50]	88	1			T260	7		T465	3		T455	9
auto[BaudRate256Kbps]	freqs[100]	185	1			T22	1		T23	1		T315	9
auto[BaudRate1Mbps]	freqs[24]	190	1			T13	9		T19	12		T266	2
auto[BaudRate1Mbps]	freqs[25]	218	1			T14	3		T21	1		T15	10
auto[BaudRate1Mbps]	freqs[48]	78	1			T466	3		T341	4		T308	2
auto[BaudRate1Mbps]	freqs[50]	103	1			T260	3		T118	2		T465	3
auto[BaudRate1Mbps]	freqs[100]	164	1			T23	2		T418	1		T315	3
auto[BaudRate1p5Mbps]	freqs[25]	115	1			T14	1		T15	4		T102	2
auto[BaudRate1p5Mbps]	freqs[48]	91	1			T113	1		T185	4		T453	1
auto[BaudRate1p5Mbps]	freqs[50]	110	1			T260	6		T118	2		T465	6
auto[BaudRate1p5Mbps]	freqs[100]	167	1			T22	1		T23	2		T418	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded