Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
0 |
8 |
100.00 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
0 |
8 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for cp_watermark_lvl
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
2464 |
1 |
|
|
T4 |
3 |
|
T8 |
3 |
|
T32 |
3 |
all_levels[1] |
435 |
1 |
|
|
T11 |
13 |
|
T21 |
2 |
|
T102 |
1 |
all_levels[2] |
449 |
1 |
|
|
T11 |
20 |
|
T24 |
4 |
|
T126 |
5 |
all_levels[3] |
314 |
1 |
|
|
T14 |
1 |
|
T15 |
1 |
|
T16 |
2 |
all_levels[4] |
455 |
1 |
|
|
T21 |
2 |
|
T25 |
5 |
|
T91 |
1 |
all_levels[5] |
388 |
1 |
|
|
T15 |
1 |
|
T140 |
1 |
|
T301 |
1 |
all_levels[6] |
330 |
1 |
|
|
T19 |
1 |
|
T103 |
1 |
|
T470 |
1 |
all_levels[7] |
188 |
1 |
|
|
T16 |
4 |
|
T103 |
2 |
|
T89 |
2 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |