Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2464 1 T4 3 T8 3 T32 3
all_levels[1] 435 1 T11 13 T21 2 T102 1
all_levels[2] 449 1 T11 20 T24 4 T126 5
all_levels[3] 314 1 T14 1 T15 1 T16 2
all_levels[4] 455 1 T21 2 T25 5 T91 1
all_levels[5] 388 1 T15 1 T140 1 T301 1
all_levels[6] 330 1 T19 1 T103 1 T470 1
all_levels[7] 188 1 T16 4 T103 2 T89 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%