Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	144060	1			T2	1		T3	5		T4	8
all_pins[1]	144060	1			T2	1		T3	5		T4	8
all_pins[2]	144060	1			T2	1		T3	5		T4	8
all_pins[3]	144060	1			T2	1		T3	5		T4	8
all_pins[4]	144060	1			T2	1		T3	5		T4	8
all_pins[5]	144060	1			T2	1		T3	5		T4	8
all_pins[6]	144060	1			T2	1		T3	5		T4	8
all_pins[7]	144060	1			T2	1		T3	5		T4	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1142600	1			T2	8		T3	34		T4	58
values[0x1]	9880	1			T3	6		T4	6		T8	8
transitions[0x0=>0x1]	8994	1			T3	4		T4	5		T8	3
transitions[0x1=>0x0]	9012	1			T3	5		T4	6		T8	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	141417	1			T2	1		T3	2		T4	7
all_pins[0]	values[0x1]	2643	1			T3	3		T4	1		T8	2
all_pins[0]	transitions[0x0=>0x1]	2402	1			T3	3		T4	1		T33	3
all_pins[0]	transitions[0x1=>0x0]	2140	1			T4	1		T32	2		T53	2
all_pins[1]	values[0x0]	141679	1			T2	1		T3	5		T4	7
all_pins[1]	values[0x1]	2381	1			T4	1		T8	2		T32	2
all_pins[1]	transitions[0x0=>0x1]	2103	1			T4	1		T8	2		T53	2
all_pins[1]	transitions[0x1=>0x0]	2333	1			T33	1		T100	1		T409	1
all_pins[2]	values[0x0]	141449	1			T2	1		T3	5		T4	8
all_pins[2]	values[0x1]	2611	1			T33	1		T32	2		T100	1
all_pins[2]	transitions[0x0=>0x1]	2559	1			T33	1		T32	2		T100	1
all_pins[2]	transitions[0x1=>0x0]	178	1			T4	1		T32	1		T53	2
all_pins[3]	values[0x0]	143830	1			T2	1		T3	5		T4	7
all_pins[3]	values[0x1]	230	1			T4	1		T32	1		T53	2
all_pins[3]	transitions[0x0=>0x1]	167	1			T4	1		T53	2		T410	2
all_pins[3]	transitions[0x1=>0x0]	450	1			T4	2		T33	3		T32	1
all_pins[4]	values[0x0]	143547	1			T2	1		T3	5		T4	6
all_pins[4]	values[0x1]	513	1			T4	2		T33	3		T32	2
all_pins[4]	transitions[0x0=>0x1]	438	1			T4	2		T33	3		T32	1
all_pins[4]	transitions[0x1=>0x0]	182	1			T8	1		T33	1		T32	2
all_pins[5]	values[0x0]	143803	1			T2	1		T3	5		T4	8
all_pins[5]	values[0x1]	257	1			T8	1		T33	1		T32	3
all_pins[5]	transitions[0x0=>0x1]	198	1			T32	3		T410	2		T409	1
all_pins[5]	transitions[0x1=>0x0]	794	1			T3	2		T33	3		T53	1
all_pins[6]	values[0x0]	143207	1			T2	1		T3	3		T4	8
all_pins[6]	values[0x1]	853	1			T3	2		T8	1		T33	4
all_pins[6]	transitions[0x0=>0x1]	805	1			T3	1		T33	3		T53	1
all_pins[6]	transitions[0x1=>0x0]	344	1			T4	1		T8	1		T53	1
all_pins[7]	values[0x0]	143668	1			T2	1		T3	4		T4	7
all_pins[7]	values[0x1]	392	1			T3	1		T4	1		T8	2
all_pins[7]	transitions[0x0=>0x1]	322	1			T8	1		T408	3		T100	3
all_pins[7]	transitions[0x1=>0x0]	2591	1			T3	3		T4	1		T8	2