Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_watermark_cg

Group : uart_env_pkg::uart_env_cov::tx_watermark_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_watermark_lvl	7	0	7	100.00	100	1	1	0

Summary for Variable cp_watermark_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_watermark_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	1672	1			T3	4		T4	2		T8	4
all_levels[1]	708	1			T24	2		T417	1		T126	1
all_levels[2]	660	1			T11	5		T21	3		T15	2
all_levels[3]	663	1			T14	2		T15	8		T16	1
all_levels[4]	711	1			T21	2		T22	1		T15	4
all_levels[5]	602	1			T19	1		T15	2		T16	1
all_levels[6]	559	1			T15	3		T102	1		T23	1