Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	792	1			T3	4		T4	7		T8	4
all_values[1]	792	1			T3	4		T4	7		T8	4
all_values[2]	792	1			T3	4		T4	7		T8	4
all_values[3]	792	1			T3	4		T4	7		T8	4
all_values[4]	792	1			T3	4		T4	7		T8	4
all_values[5]	792	1			T3	4		T4	7		T8	4
all_values[6]	792	1			T3	4		T4	7		T8	4
all_values[7]	792	1			T3	4		T4	7		T8	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3316

1

T3

9

T4

26

T8

16

auto[1]

3020

1

T3

23

T4

30

T8

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2481

1

T3

19

T4

24

T8

13

auto[1]

3855

1

T3

13

T4

32

T8

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3720

1

T3

21

T4

33

T8

19

auto[1]

2616

1

T3

11

T4

23

T8

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	170	1			T4	2		T32	2		T53	3
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T53	1		T409	1		T411	2
all_values[0]	auto[0]	auto[1]	auto[0]	133	1			T4	2		T32	1		T100	2
all_values[0]	auto[0]	auto[1]	auto[1]	69	1			T3	1		T8	1		T33	2
all_values[0]	auto[1]	auto[0]	auto[1]	185	1			T3	1		T4	1		T8	2
all_values[0]	auto[1]	auto[1]	auto[1]	142	1			T3	2		T4	2		T8	1
all_values[1]	auto[0]	auto[0]	auto[0]	188	1			T3	3		T4	2		T8	1
all_values[1]	auto[0]	auto[0]	auto[1]	62	1			T4	1		T32	1		T53	1
all_values[1]	auto[0]	auto[1]	auto[0]	138	1			T3	1		T4	1		T33	4
all_values[1]	auto[0]	auto[1]	auto[1]	71	1			T8	1		T32	1		T53	1
all_values[1]	auto[1]	auto[0]	auto[1]	185	1			T4	1		T8	1		T53	1
all_values[1]	auto[1]	auto[1]	auto[1]	148	1			T4	2		T8	1		T32	1
all_values[2]	auto[0]	auto[0]	auto[0]	153	1			T3	1		T4	2		T8	1
all_values[2]	auto[0]	auto[0]	auto[1]	74	1			T4	1		T32	1		T100	1
all_values[2]	auto[0]	auto[1]	auto[0]	147	1			T3	3		T4	1		T8	3
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T32	1		T412	2		T413	1
all_values[2]	auto[1]	auto[0]	auto[1]	152	1			T4	2		T33	2		T410	1
all_values[2]	auto[1]	auto[1]	auto[1]	174	1			T4	1		T32	1		T53	1
all_values[3]	auto[0]	auto[0]	auto[0]	153	1			T32	1		T53	2		T408	1
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T4	1		T8	1		T33	2
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T3	1		T4	1		T8	1
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T4	1		T32	1		T53	1
all_values[3]	auto[1]	auto[0]	auto[1]	181	1			T3	1		T4	3		T8	2
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T3	2		T4	1		T32	1
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T3	2		T4	1		T8	2
all_values[4]	auto[0]	auto[0]	auto[1]	62	1			T8	1		T100	1		T414	1
all_values[4]	auto[0]	auto[1]	auto[0]	164	1			T3	2		T32	1		T408	2
all_values[4]	auto[0]	auto[1]	auto[1]	89	1			T4	2		T33	1		T32	2
all_values[4]	auto[1]	auto[0]	auto[1]	158	1			T4	3		T8	1		T33	1
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T4	1		T33	1		T32	1
all_values[5]	auto[0]	auto[0]	auto[0]	184	1			T3	1		T4	1		T410	2
all_values[5]	auto[0]	auto[0]	auto[1]	75	1			T4	1		T33	2		T32	1
all_values[5]	auto[0]	auto[1]	auto[0]	132	1			T3	3		T4	2		T8	2
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T32	1		T53	1		T409	1
all_values[5]	auto[1]	auto[0]	auto[1]	172	1			T4	2		T8	1		T32	1
all_values[5]	auto[1]	auto[1]	auto[1]	159	1			T4	1		T8	1		T33	2
all_values[6]	auto[0]	auto[0]	auto[0]	154	1			T8	1		T32	2		T53	1
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T4	1		T53	3		T408	1
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T3	1		T4	5		T8	2
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T3	1		T33	1		T408	2
all_values[6]	auto[1]	auto[0]	auto[1]	183	1			T4	1		T32	1		T53	1
all_values[6]	auto[1]	auto[1]	auto[1]	148	1			T3	2		T8	1		T33	3
all_values[7]	auto[0]	auto[0]	auto[0]	161	1			T53	1		T410	1		T411	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T8	2		T33	2		T53	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T3	1		T4	4		T32	4
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T4	1		T33	1		T408	2
all_values[7]	auto[1]	auto[0]	auto[1]	157	1			T53	5		T410	1		T100	1
all_values[7]	auto[1]	auto[1]	auto[1]	170	1			T3	3		T4	2		T8	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal