Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.29 99.79 98.45 100.00 99.76 100.00 97.73


Total test records in report: 1292
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T1256 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1283218293 Dec 27 12:35:47 PM PST 23 Dec 27 12:36:22 PM PST 23 18743270 ps
T64 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1157279450 Dec 27 12:36:02 PM PST 23 Dec 27 12:36:22 PM PST 23 81834789 ps
T1257 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.957199301 Dec 27 12:36:17 PM PST 23 Dec 27 12:36:38 PM PST 23 14202259 ps
T1258 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2961883884 Dec 27 12:35:34 PM PST 23 Dec 27 12:35:47 PM PST 23 16560672 ps
T1259 /workspace/coverage/cover_reg_top/26.uart_intr_test.4226783583 Dec 27 12:36:28 PM PST 23 Dec 27 12:36:51 PM PST 23 42349696 ps
T1260 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2590051140 Dec 27 12:36:13 PM PST 23 Dec 27 12:36:34 PM PST 23 14536064 ps
T1261 /workspace/coverage/cover_reg_top/9.uart_tl_errors.787323474 Dec 27 12:36:13 PM PST 23 Dec 27 12:36:35 PM PST 23 201648220 ps
T407 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.419063272 Dec 27 12:36:25 PM PST 23 Dec 27 12:36:48 PM PST 23 90561711 ps
T1262 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3829168810 Dec 27 12:36:06 PM PST 23 Dec 27 12:36:27 PM PST 23 247600569 ps
T82 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.248844705 Dec 27 12:36:41 PM PST 23 Dec 27 12:37:12 PM PST 23 235554772 ps
T1263 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1496246226 Dec 27 12:37:17 PM PST 23 Dec 27 12:37:38 PM PST 23 43574542 ps
T1264 /workspace/coverage/cover_reg_top/15.uart_intr_test.2250607986 Dec 27 12:36:08 PM PST 23 Dec 27 12:36:30 PM PST 23 11178499 ps
T65 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1637754090 Dec 27 12:36:26 PM PST 23 Dec 27 12:36:49 PM PST 23 28304938 ps
T1265 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2261014567 Dec 27 12:36:21 PM PST 23 Dec 27 12:36:43 PM PST 23 157068820 ps
T1266 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.971040330 Dec 27 12:36:08 PM PST 23 Dec 27 12:36:29 PM PST 23 140681547 ps
T1267 /workspace/coverage/cover_reg_top/8.uart_tl_errors.526741111 Dec 27 12:36:47 PM PST 23 Dec 27 12:37:16 PM PST 23 134638432 ps
T1268 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2231001808 Dec 27 12:36:19 PM PST 23 Dec 27 12:36:39 PM PST 23 22639260 ps
T1269 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1156167604 Dec 27 12:36:02 PM PST 23 Dec 27 12:36:21 PM PST 23 14265513 ps
T1270 /workspace/coverage/cover_reg_top/27.uart_intr_test.4091595547 Dec 27 12:36:12 PM PST 23 Dec 27 12:36:33 PM PST 23 17035343 ps
T1271 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1757391396 Dec 27 12:36:24 PM PST 23 Dec 27 12:36:47 PM PST 23 153984994 ps
T1272 /workspace/coverage/cover_reg_top/42.uart_intr_test.3140194702 Dec 27 12:36:03 PM PST 23 Dec 27 12:36:22 PM PST 23 16738875 ps
T1273 /workspace/coverage/cover_reg_top/40.uart_intr_test.2198829635 Dec 27 12:36:08 PM PST 23 Dec 27 12:36:30 PM PST 23 25824195 ps
T1274 /workspace/coverage/cover_reg_top/31.uart_intr_test.2011808788 Dec 27 12:36:21 PM PST 23 Dec 27 12:36:42 PM PST 23 29702544 ps
T1275 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2889354518 Dec 27 12:36:32 PM PST 23 Dec 27 12:36:59 PM PST 23 188827931 ps
T1276 /workspace/coverage/cover_reg_top/17.uart_intr_test.3729637371 Dec 27 12:36:26 PM PST 23 Dec 27 12:36:49 PM PST 23 17169476 ps
T1277 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3946906496 Dec 27 12:36:32 PM PST 23 Dec 27 12:37:01 PM PST 23 81296247 ps
T1278 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3770642006 Dec 27 12:35:54 PM PST 23 Dec 27 12:36:13 PM PST 23 37474983 ps
T1279 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2861696484 Dec 27 12:36:31 PM PST 23 Dec 27 12:36:59 PM PST 23 116367076 ps
T1280 /workspace/coverage/cover_reg_top/41.uart_intr_test.1745602981 Dec 27 12:36:18 PM PST 23 Dec 27 12:36:39 PM PST 23 50504306 ps
T1281 /workspace/coverage/cover_reg_top/16.uart_csr_rw.534867557 Dec 27 12:35:57 PM PST 23 Dec 27 12:36:16 PM PST 23 11640802 ps
T1282 /workspace/coverage/cover_reg_top/9.uart_intr_test.3300370127 Dec 27 12:36:03 PM PST 23 Dec 27 12:36:22 PM PST 23 12540459 ps
T1283 /workspace/coverage/cover_reg_top/1.uart_intr_test.1868038237 Dec 27 12:36:09 PM PST 23 Dec 27 12:36:30 PM PST 23 27571053 ps
T1284 /workspace/coverage/cover_reg_top/9.uart_csr_rw.4067241145 Dec 27 12:36:09 PM PST 23 Dec 27 12:36:30 PM PST 23 14381770 ps
T1285 /workspace/coverage/cover_reg_top/48.uart_intr_test.3333070914 Dec 27 12:36:24 PM PST 23 Dec 27 12:36:46 PM PST 23 14849975 ps
T1286 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.968592683 Dec 27 12:37:22 PM PST 23 Dec 27 12:37:42 PM PST 23 26568560 ps
T1287 /workspace/coverage/cover_reg_top/36.uart_intr_test.4147147357 Dec 27 12:36:28 PM PST 23 Dec 27 12:36:51 PM PST 23 40060742 ps
T1288 /workspace/coverage/cover_reg_top/28.uart_intr_test.1583454933 Dec 27 12:36:26 PM PST 23 Dec 27 12:36:49 PM PST 23 127485950 ps
T1289 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.613108732 Dec 27 12:37:17 PM PST 23 Dec 27 12:37:38 PM PST 23 27226916 ps
T66 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2986129683 Dec 27 12:36:07 PM PST 23 Dec 27 12:36:29 PM PST 23 19368942 ps
T1290 /workspace/coverage/cover_reg_top/3.uart_tl_errors.4110800005 Dec 27 12:36:29 PM PST 23 Dec 27 12:36:54 PM PST 23 64824486 ps
T1291 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.451161522 Dec 27 12:35:54 PM PST 23 Dec 27 12:36:14 PM PST 23 29842773 ps
T1292 /workspace/coverage/cover_reg_top/5.uart_intr_test.1976049371 Dec 27 12:35:52 PM PST 23 Dec 27 12:36:12 PM PST 23 12708088 ps

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3886226298
Short name T1
Test name
Test status
Simulation time 28377525 ps
CPU time 0.72 seconds
Started Dec 27 12:36:35 PM PST 23
Finished Dec 27 12:37:04 PM PST 23
Peak memory 196808 kb
Host smart-9b315200-71dc-416b-b946-2f373986418d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886226298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3886226298
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1646981290
Short name T14
Test name
Test status
Simulation time 79300164452 ps
CPU time 105.22 seconds
Started Dec 27 01:03:51 PM PST 23
Finished Dec 27 01:05:46 PM PST 23
Peak memory 200276 kb
Host smart-aec92672-a2e1-49bf-b5f4-bf4b2fbd56ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646981290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1646981290
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_stress_all.468611461
Short name T15
Test name
Test status
Simulation time 615752417081 ps
CPU time 729.01 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:15:44 PM PST 23
Peak memory 215876 kb
Host smart-13aac4dd-5bad-48f8-8c19-b5cb370dc65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468611461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.468611461
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2621564268
Short name T4
Test name
Test status
Simulation time 10975515 ps
CPU time 0.61 seconds
Started Dec 27 12:35:46 PM PST 23
Finished Dec 27 12:36:06 PM PST 23
Peak memory 185092 kb
Host smart-9c472c50-d754-4373-bcfb-fcc9d223cf59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621564268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2621564268
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3804327068
Short name T30
Test name
Test status
Simulation time 483149267061 ps
CPU time 530.15 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:14:23 PM PST 23
Peak memory 216916 kb
Host smart-6f04bd12-847c-4944-aec7-bc22d9cb4a96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804327068 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3804327068
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2015911669
Short name T10
Test name
Test status
Simulation time 237397670 ps
CPU time 2.01 seconds
Started Dec 27 12:36:34 PM PST 23
Finished Dec 27 12:37:04 PM PST 23
Peak memory 199996 kb
Host smart-622a21a1-0237-4035-831e-b54e34da2706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015911669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2015911669
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/default/39.uart_stress_all.176100297
Short name T341
Test name
Test status
Simulation time 829929550739 ps
CPU time 636.66 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:15:32 PM PST 23
Peak memory 200160 kb
Host smart-00713e02-2e92-47d7-8cbc-7af9bce4a2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176100297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.176100297
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1412795020
Short name T27
Test name
Test status
Simulation time 45033337964 ps
CPU time 530.43 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:14:15 PM PST 23
Peak memory 226364 kb
Host smart-1cac7257-5273-4cd3-9c9e-b5abbd187648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412795020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1412795020
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.2088256625
Short name T119
Test name
Test status
Simulation time 162764231142 ps
CPU time 511.1 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:13:48 PM PST 23
Peak memory 200196 kb
Host smart-ec6bd7d5-ebc8-4413-8b6b-09dfef4c6a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088256625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2088256625
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3323507271
Short name T210
Test name
Test status
Simulation time 154210718274 ps
CPU time 639.57 seconds
Started Dec 27 01:05:41 PM PST 23
Finished Dec 27 01:16:23 PM PST 23
Peak memory 213400 kb
Host smart-81221847-1c44-4e5e-8074-2e36f802ee47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323507271 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3323507271
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3625827023
Short name T9
Test name
Test status
Simulation time 61926075 ps
CPU time 2.19 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:30 PM PST 23
Peak memory 197904 kb
Host smart-111743b2-d805-4d1e-a000-4aaf13474bf8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625827023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3625827023
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/default/24.uart_intr.2214437333
Short name T108
Test name
Test status
Simulation time 591390121631 ps
CPU time 809.4 seconds
Started Dec 27 01:04:07 PM PST 23
Finished Dec 27 01:17:43 PM PST 23
Peak memory 200088 kb
Host smart-3e6ef27d-6255-458f-829c-dafca3e18ba9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214437333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2214437333
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.4184807231
Short name T78
Test name
Test status
Simulation time 87565119 ps
CPU time 1.28 seconds
Started Dec 27 12:35:56 PM PST 23
Finished Dec 27 12:36:16 PM PST 23
Peak memory 199132 kb
Host smart-0617536e-fa02-41ff-9021-e4944fc2afa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184807231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.4184807231
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/default/43.uart_stress_all.2352831963
Short name T122
Test name
Test status
Simulation time 341711272874 ps
CPU time 78.01 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:06:17 PM PST 23
Peak memory 200188 kb
Host smart-b76de2d8-9e49-45e2-8198-1d687015ee67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352831963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2352831963
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all.1094781182
Short name T127
Test name
Test status
Simulation time 244609520547 ps
CPU time 1287.34 seconds
Started Dec 27 01:04:15 PM PST 23
Finished Dec 27 01:25:44 PM PST 23
Peak memory 208624 kb
Host smart-1df270bc-d003-4d8b-8460-52318a30e7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094781182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1094781182
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_fifo_full.564164498
Short name T95
Test name
Test status
Simulation time 160930529282 ps
CPU time 157.65 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:06:14 PM PST 23
Peak memory 200168 kb
Host smart-8c2f41b0-16d6-4af7-97b5-39868cee77cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564164498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.564164498
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3117168824
Short name T74
Test name
Test status
Simulation time 42198055 ps
CPU time 0.82 seconds
Started Dec 27 01:03:14 PM PST 23
Finished Dec 27 01:03:22 PM PST 23
Peak memory 217744 kb
Host smart-e397856a-0457-4494-aa8c-ea886d8fb220
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117168824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3117168824
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2497137305
Short name T113
Test name
Test status
Simulation time 119338976135 ps
CPU time 119.52 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:07:56 PM PST 23
Peak memory 200016 kb
Host smart-9dc9845c-f024-4e3c-af9f-3c9329d6b306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497137305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2497137305
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.1847810162
Short name T195
Test name
Test status
Simulation time 692775925880 ps
CPU time 517.83 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:13:44 PM PST 23
Peak memory 200440 kb
Host smart-37f778da-8d9d-49ce-962f-1202a41cbe0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847810162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1847810162
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2025292464
Short name T266
Test name
Test status
Simulation time 119760703217 ps
CPU time 42.33 seconds
Started Dec 27 01:05:31 PM PST 23
Finished Dec 27 01:06:15 PM PST 23
Peak memory 199256 kb
Host smart-234da86d-24f9-44c9-a046-2692862eff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025292464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2025292464
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.121189789
Short name T33
Test name
Test status
Simulation time 11912720 ps
CPU time 0.54 seconds
Started Dec 27 12:36:37 PM PST 23
Finished Dec 27 12:37:06 PM PST 23
Peak memory 194256 kb
Host smart-dc9eeb7e-e943-41f3-bbcb-f43477802672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121189789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.121189789
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1354866413
Short name T145
Test name
Test status
Simulation time 82494559814 ps
CPU time 763.69 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:18:09 PM PST 23
Peak memory 227588 kb
Host smart-7e9e0bd4-71b0-4f22-a552-7526bd95af98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354866413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1354866413
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1901725058
Short name T344
Test name
Test status
Simulation time 54508451472 ps
CPU time 1549.84 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:29:30 PM PST 23
Peak memory 215748 kb
Host smart-ee571491-e292-4166-a81e-ada48794d507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901725058 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1901725058
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all.3269111488
Short name T260
Test name
Test status
Simulation time 178833175129 ps
CPU time 732.77 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:17:18 PM PST 23
Peak memory 200148 kb
Host smart-33ee241e-deb0-4afe-be5f-e146d9ef4065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269111488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3269111488
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.4133440838
Short name T489
Test name
Test status
Simulation time 58795137 ps
CPU time 0.56 seconds
Started Dec 27 12:36:06 PM PST 23
Finished Dec 27 12:36:28 PM PST 23
Peak memory 194300 kb
Host smart-0bf1d240-5dc4-4778-ac8e-736498bebddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133440838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4133440838
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1942947301
Short name T111
Test name
Test status
Simulation time 77544803098 ps
CPU time 128.73 seconds
Started Dec 27 01:06:12 PM PST 23
Finished Dec 27 01:08:23 PM PST 23
Peak memory 200016 kb
Host smart-8912b40a-2c48-4c34-841b-d044d10da653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942947301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1942947301
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2080811671
Short name T132
Test name
Test status
Simulation time 206467144989 ps
CPU time 88.04 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:07:37 PM PST 23
Peak memory 200112 kb
Host smart-c43b30d3-2e43-4eee-bfdc-4186ddadea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080811671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2080811671
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_alert_test.4124763782
Short name T543
Test name
Test status
Simulation time 11479639 ps
CPU time 0.62 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:03:33 PM PST 23
Peak memory 195660 kb
Host smart-fcf54dcc-c07f-4e9c-aeb6-1665cf832ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124763782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.4124763782
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2860171504
Short name T303
Test name
Test status
Simulation time 194924011760 ps
CPU time 182.7 seconds
Started Dec 27 01:05:15 PM PST 23
Finished Dec 27 01:08:26 PM PST 23
Peak memory 200240 kb
Host smart-5783cce5-e5ee-4b08-a602-8cd5f5cf6885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860171504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2860171504
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2625957878
Short name T97
Test name
Test status
Simulation time 141447903197 ps
CPU time 192.81 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:09:07 PM PST 23
Peak memory 200152 kb
Host smart-22c13078-6ba7-421c-9434-17420e0bd5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625957878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2625957878
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3320517777
Short name T89
Test name
Test status
Simulation time 19549560986 ps
CPU time 26.76 seconds
Started Dec 27 01:05:56 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 200252 kb
Host smart-ed312914-36f8-4749-95b1-73013c021bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320517777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3320517777
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2231505580
Short name T96
Test name
Test status
Simulation time 57903434424 ps
CPU time 64.04 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:56 PM PST 23
Peak memory 200212 kb
Host smart-b58f6ba4-7efd-4414-b8b3-1595d64ecbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231505580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2231505580
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.248844705
Short name T82
Test name
Test status
Simulation time 235554772 ps
CPU time 1.25 seconds
Started Dec 27 12:36:41 PM PST 23
Finished Dec 27 12:37:12 PM PST 23
Peak memory 199116 kb
Host smart-a91e86b8-5722-4d72-b5f7-68498e2d5874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248844705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.248844705
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3457993902
Short name T53
Test name
Test status
Simulation time 38538177 ps
CPU time 0.55 seconds
Started Dec 27 12:36:41 PM PST 23
Finished Dec 27 12:37:15 PM PST 23
Peak memory 185020 kb
Host smart-e58e3d76-2a58-42c1-8bf3-01c506d421c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457993902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3457993902
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2414390052
Short name T222
Test name
Test status
Simulation time 16567825417 ps
CPU time 43.73 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:06:41 PM PST 23
Peak memory 200124 kb
Host smart-f08a1176-9f02-4540-9103-3d2d8d8c7a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414390052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2414390052
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.61858972
Short name T118
Test name
Test status
Simulation time 72391806585 ps
CPU time 62.69 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:56 PM PST 23
Peak memory 200204 kb
Host smart-59b60048-02e1-41e7-bc67-555c77ff93fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61858972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.61858972
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.4236807160
Short name T192
Test name
Test status
Simulation time 89489388431 ps
CPU time 17.49 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:08 PM PST 23
Peak memory 199776 kb
Host smart-d006c895-d6ac-4074-9c02-fa4008908709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236807160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4236807160
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1937111694
Short name T146
Test name
Test status
Simulation time 41788624803 ps
CPU time 70.34 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:07:07 PM PST 23
Peak memory 200216 kb
Host smart-30ddffb2-d102-4f1e-8c74-e20eb99e9b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937111694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1937111694
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.61487295
Short name T389
Test name
Test status
Simulation time 52889622585 ps
CPU time 29.01 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:23 PM PST 23
Peak memory 200104 kb
Host smart-87555bc6-7a0b-4ebf-9a7f-8a0648579ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61487295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.61487295
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.4144000197
Short name T233
Test name
Test status
Simulation time 35298032136 ps
CPU time 34.66 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:06:33 PM PST 23
Peak memory 200260 kb
Host smart-d6925632-8729-415b-9500-023da8c2fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144000197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4144000197
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1513598666
Short name T231
Test name
Test status
Simulation time 81955499945 ps
CPU time 131.82 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:08:07 PM PST 23
Peak memory 200136 kb
Host smart-1ecf7f50-69d8-4b57-931e-8a517dbc599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513598666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1513598666
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3563118820
Short name T285
Test name
Test status
Simulation time 8275387455 ps
CPU time 12.87 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 200220 kb
Host smart-0188fa00-41d4-4196-8075-9f2f206b7ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563118820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3563118820
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2695953868
Short name T157
Test name
Test status
Simulation time 182951693967 ps
CPU time 80.69 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:06:44 PM PST 23
Peak memory 200080 kb
Host smart-1a026a2a-e8d9-4316-95d1-74539780b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695953868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2695953868
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2826215835
Short name T256
Test name
Test status
Simulation time 158578380028 ps
CPU time 247.17 seconds
Started Dec 27 01:05:33 PM PST 23
Finished Dec 27 01:09:44 PM PST 23
Peak memory 200240 kb
Host smart-5f6d28b8-04af-46ae-ae85-9c78fc044d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826215835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2826215835
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4246540624
Short name T208
Test name
Test status
Simulation time 1726680612520 ps
CPU time 2010.86 seconds
Started Dec 27 01:05:55 PM PST 23
Finished Dec 27 01:39:30 PM PST 23
Peak memory 233328 kb
Host smart-858cd0dd-72af-4f3f-8389-3d0fe66de9bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246540624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4246540624
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3385720186
Short name T365
Test name
Test status
Simulation time 46857267876 ps
CPU time 45.88 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:38 PM PST 23
Peak memory 200224 kb
Host smart-d970f634-d181-47bf-841b-430432f52ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385720186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3385720186
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1724424453
Short name T186
Test name
Test status
Simulation time 120940062645 ps
CPU time 54.38 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:46 PM PST 23
Peak memory 200212 kb
Host smart-192490b8-f8e2-4a92-b04e-d2dd6ead8605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724424453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1724424453
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3354493608
Short name T247
Test name
Test status
Simulation time 65066420744 ps
CPU time 38.38 seconds
Started Dec 27 01:06:09 PM PST 23
Finished Dec 27 01:06:51 PM PST 23
Peak memory 200136 kb
Host smart-957932da-2693-4800-8a9c-91b0d5210309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354493608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3354493608
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1702730598
Short name T280
Test name
Test status
Simulation time 111772367428 ps
CPU time 94.37 seconds
Started Dec 27 01:03:09 PM PST 23
Finished Dec 27 01:04:54 PM PST 23
Peak memory 199840 kb
Host smart-5f5e99ef-1543-4fbc-8025-fa1bc58b31a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702730598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1702730598
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.564303663
Short name T131
Test name
Test status
Simulation time 22751233119 ps
CPU time 32.4 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 199848 kb
Host smart-a392d646-2702-4f27-9a3e-921bc744610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564303663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.564303663
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.345295754
Short name T258
Test name
Test status
Simulation time 199818415500 ps
CPU time 737.58 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:15:50 PM PST 23
Peak memory 228288 kb
Host smart-658887a4-8392-4b51-bee0-d9bbe6e5c276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345295754 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.345295754
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.87233760
Short name T236
Test name
Test status
Simulation time 65002051576 ps
CPU time 14.48 seconds
Started Dec 27 01:05:47 PM PST 23
Finished Dec 27 01:06:03 PM PST 23
Peak memory 200132 kb
Host smart-af1d62c4-bc16-4d11-83a6-8b6792e6bb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87233760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.87233760
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3844953954
Short name T374
Test name
Test status
Simulation time 94108092779 ps
CPU time 81.43 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:07:18 PM PST 23
Peak memory 199928 kb
Host smart-fc828a07-5032-48cc-ae44-bbce062a0f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844953954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3844953954
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2223688572
Short name T265
Test name
Test status
Simulation time 196189508627 ps
CPU time 63.08 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:56 PM PST 23
Peak memory 200248 kb
Host smart-0415f17b-da25-4aa7-89dc-2927c9d64d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223688572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2223688572
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2561168298
Short name T159
Test name
Test status
Simulation time 26956956936 ps
CPU time 63 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:04:44 PM PST 23
Peak memory 200164 kb
Host smart-1df5aaf8-8681-4b5a-b123-9470d44151c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561168298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2561168298
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3135248040
Short name T399
Test name
Test status
Simulation time 142592869716 ps
CPU time 67.19 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 200120 kb
Host smart-38e8ec18-2284-41f5-b594-c30a7605a32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135248040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3135248040
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3652921485
Short name T178
Test name
Test status
Simulation time 13508031489 ps
CPU time 20.79 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:13 PM PST 23
Peak memory 198628 kb
Host smart-ae1e9213-4826-4a11-be85-c8988db7ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652921485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3652921485
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.2906574361
Short name T378
Test name
Test status
Simulation time 1054685875460 ps
CPU time 1038.51 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:21:27 PM PST 23
Peak memory 200236 kb
Host smart-7aa79476-d52f-4373-8f18-1eeb556ce42c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906574361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2906574361
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.4217481173
Short name T202
Test name
Test status
Simulation time 119609915028 ps
CPU time 156.09 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:08:33 PM PST 23
Peak memory 200268 kb
Host smart-2ae3e8d5-e4c6-4c07-9fb5-f40b49efb83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217481173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4217481173
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.21671285
Short name T356
Test name
Test status
Simulation time 53764394424 ps
CPU time 24.18 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:06:33 PM PST 23
Peak memory 200304 kb
Host smart-799a4187-ea93-43c5-b7fe-6dd0ef2817d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21671285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.21671285
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1125792194
Short name T179
Test name
Test status
Simulation time 105802712344 ps
CPU time 56.13 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:07:06 PM PST 23
Peak memory 200208 kb
Host smart-fcc24984-6a84-4c32-bd25-dc08e8fddf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125792194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1125792194
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2629242963
Short name T166
Test name
Test status
Simulation time 149083650245 ps
CPU time 341.33 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:11:55 PM PST 23
Peak memory 199836 kb
Host smart-d4970143-6dcd-489d-a324-0f694d57e2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629242963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2629242963
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.416916554
Short name T56
Test name
Test status
Simulation time 52224160196 ps
CPU time 134.15 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:07:20 PM PST 23
Peak memory 208484 kb
Host smart-a5822d1a-e71d-4156-9390-d5fe67c919d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416916554 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.416916554
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2320067540
Short name T140
Test name
Test status
Simulation time 7636530466 ps
CPU time 10.03 seconds
Started Dec 27 01:05:30 PM PST 23
Finished Dec 27 01:05:43 PM PST 23
Peak memory 199800 kb
Host smart-a798a487-b1af-4e39-b254-cfef312d527d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320067540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2320067540
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3820293808
Short name T123
Test name
Test status
Simulation time 60623124636 ps
CPU time 48.77 seconds
Started Dec 27 01:05:31 PM PST 23
Finished Dec 27 01:06:22 PM PST 23
Peak memory 199760 kb
Host smart-cbf01ed6-26f6-46c3-8944-524aefe8bb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820293808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3820293808
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3990721293
Short name T408
Test name
Test status
Simulation time 14975611 ps
CPU time 0.53 seconds
Started Dec 27 12:37:21 PM PST 23
Finished Dec 27 12:37:41 PM PST 23
Peak memory 184740 kb
Host smart-991f0e42-3508-4bfe-b83e-3c44fd0c5d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990721293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3990721293
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1114338633
Short name T362
Test name
Test status
Simulation time 25527417600 ps
CPU time 12.75 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:03 PM PST 23
Peak memory 200252 kb
Host smart-84fe298c-e19d-447a-8f97-ee8922b79f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114338633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1114338633
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1592393422
Short name T168
Test name
Test status
Simulation time 23972260509 ps
CPU time 10.45 seconds
Started Dec 27 01:05:55 PM PST 23
Finished Dec 27 01:06:09 PM PST 23
Peak memory 199128 kb
Host smart-b51a85de-e3b7-4ad2-bc48-5bb3a8c7a877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592393422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1592393422
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.309901463
Short name T244
Test name
Test status
Simulation time 42048594640 ps
CPU time 57.89 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:48 PM PST 23
Peak memory 200176 kb
Host smart-427178dc-a910-42a0-9450-42e4b7c9a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309901463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.309901463
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.220757173
Short name T229
Test name
Test status
Simulation time 152293364731 ps
CPU time 62.61 seconds
Started Dec 27 01:05:54 PM PST 23
Finished Dec 27 01:07:01 PM PST 23
Peak memory 200064 kb
Host smart-eb041587-0bd3-47f8-bfbc-fc6e7096b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220757173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.220757173
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_tx_rx.36788748
Short name T535
Test name
Test status
Simulation time 108775967280 ps
CPU time 193.72 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:06:55 PM PST 23
Peak memory 200108 kb
Host smart-a2e433ce-562f-446b-9844-6e2a7c50eb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36788748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.36788748
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2395371056
Short name T183
Test name
Test status
Simulation time 115069902301 ps
CPU time 222.63 seconds
Started Dec 27 01:05:47 PM PST 23
Finished Dec 27 01:09:31 PM PST 23
Peak memory 200144 kb
Host smart-65739b42-d85d-437f-918d-b4f064435ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395371056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2395371056
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3914559187
Short name T234
Test name
Test status
Simulation time 58956309593 ps
CPU time 105.28 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:07:42 PM PST 23
Peak memory 200220 kb
Host smart-535dffa9-a6d1-4d3a-840e-3206c41b1840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914559187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3914559187
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2507246656
Short name T175
Test name
Test status
Simulation time 49021122661 ps
CPU time 19.31 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:08 PM PST 23
Peak memory 200116 kb
Host smart-70ad76d3-1854-4bbe-acb9-e83c96158113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507246656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2507246656
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all.4173917005
Short name T1020
Test name
Test status
Simulation time 191998520016 ps
CPU time 288.35 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:08:46 PM PST 23
Peak memory 200520 kb
Host smart-5a443304-deb3-4050-97ad-730beae13e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173917005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4173917005
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.325131990
Short name T241
Test name
Test status
Simulation time 67562733195 ps
CPU time 59 seconds
Started Dec 27 01:03:57 PM PST 23
Finished Dec 27 01:05:04 PM PST 23
Peak memory 199840 kb
Host smart-9b79155d-d91e-40e7-a621-5f1556e909d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325131990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.325131990
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2590185996
Short name T297
Test name
Test status
Simulation time 22540289907 ps
CPU time 17.11 seconds
Started Dec 27 01:04:00 PM PST 23
Finished Dec 27 01:04:25 PM PST 23
Peak memory 200192 kb
Host smart-789bfbf9-a67f-4a6c-ab0e-84fb36e9f900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590185996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2590185996
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2531514825
Short name T393
Test name
Test status
Simulation time 157069083850 ps
CPU time 17.74 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 200048 kb
Host smart-2d551a2c-2cfd-4cb6-a9d9-c979a33ade43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531514825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2531514825
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.398229641
Short name T102
Test name
Test status
Simulation time 24840160671 ps
CPU time 12.67 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:21 PM PST 23
Peak memory 200168 kb
Host smart-38c12f4c-ca36-4bef-9c4a-2179dbf1ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398229641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.398229641
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.89325860
Short name T1158
Test name
Test status
Simulation time 56923741563 ps
CPU time 98.4 seconds
Started Dec 27 01:06:09 PM PST 23
Finished Dec 27 01:07:50 PM PST 23
Peak memory 200216 kb
Host smart-0b179ff6-b0f9-4126-aca0-8f8b85a891dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89325860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.89325860
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1458695745
Short name T375
Test name
Test status
Simulation time 142207815126 ps
CPU time 19.21 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:06:29 PM PST 23
Peak memory 199980 kb
Host smart-3d4e44e8-8801-463e-931c-50ff8788fd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458695745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1458695745
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.4223840660
Short name T385
Test name
Test status
Simulation time 37907111406 ps
CPU time 16.15 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:05:36 PM PST 23
Peak memory 199688 kb
Host smart-897ce652-56a2-499f-a276-7bc36e1ab43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223840660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4223840660
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3664201678
Short name T198
Test name
Test status
Simulation time 82957669661 ps
CPU time 19.39 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:03 PM PST 23
Peak memory 200180 kb
Host smart-654f22de-37ac-47c2-8f9c-8846cbe40296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664201678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3664201678
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.89942808
Short name T492
Test name
Test status
Simulation time 139168479 ps
CPU time 0.86 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 198648 kb
Host smart-d3bce5db-d775-4230-87db-4af264304b90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89942808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.89942808
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.419063272
Short name T407
Test name
Test status
Simulation time 90561711 ps
CPU time 1.24 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 199264 kb
Host smart-22f95550-f26c-4847-a811-ff9e7835617d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419063272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.419063272
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_noise_filter.424770260
Short name T546
Test name
Test status
Simulation time 291509386470 ps
CPU time 82.71 seconds
Started Dec 27 01:03:16 PM PST 23
Finished Dec 27 01:04:44 PM PST 23
Peak memory 200456 kb
Host smart-3a2ac441-790a-4607-ae43-4b4d8200854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424770260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.424770260
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4267575440
Short name T103
Test name
Test status
Simulation time 61291979189 ps
CPU time 19.14 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:06:16 PM PST 23
Peak memory 200296 kb
Host smart-e435ec19-8469-4972-92fc-6e8c45c4fcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267575440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4267575440
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2879761831
Short name T173
Test name
Test status
Simulation time 124542992758 ps
CPU time 96.87 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:07:35 PM PST 23
Peak memory 200244 kb
Host smart-7c8c05a9-03d6-461a-91ba-7104a2bca27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879761831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2879761831
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1722400162
Short name T218
Test name
Test status
Simulation time 44576609924 ps
CPU time 37.45 seconds
Started Dec 27 01:05:47 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 200220 kb
Host smart-df081c28-655a-4e10-8611-9d307367b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722400162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1722400162
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3144332763
Short name T336
Test name
Test status
Simulation time 243649935159 ps
CPU time 98.98 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 200192 kb
Host smart-40507cfc-7e3b-420b-9a59-f0cbc23044dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144332763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3144332763
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3469909427
Short name T279
Test name
Test status
Simulation time 182045977882 ps
CPU time 114.44 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:07:49 PM PST 23
Peak memory 200224 kb
Host smart-190c26de-942d-4706-a945-8184d28ff9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469909427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3469909427
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.756106161
Short name T293
Test name
Test status
Simulation time 110384185345 ps
CPU time 37.93 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:28 PM PST 23
Peak memory 199512 kb
Host smart-a067d80a-774d-4fe7-8ee2-73bae5b4662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756106161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.756106161
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.272814612
Short name T251
Test name
Test status
Simulation time 48704903456 ps
CPU time 39.17 seconds
Started Dec 27 01:03:54 PM PST 23
Finished Dec 27 01:04:41 PM PST 23
Peak memory 200296 kb
Host smart-102336e7-38f9-4a39-b60f-297cb446604a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272814612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.272814612
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3035379561
Short name T276
Test name
Test status
Simulation time 131009589064 ps
CPU time 207.78 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:09:20 PM PST 23
Peak memory 200040 kb
Host smart-2183d2ad-284a-4385-9fc0-f2b29ccdf83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035379561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3035379561
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3986521721
Short name T291
Test name
Test status
Simulation time 80505107970 ps
CPU time 29.37 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:04:18 PM PST 23
Peak memory 200220 kb
Host smart-2afd7217-8246-4f8f-a3ba-f11267b3efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986521721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3986521721
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.461846193
Short name T402
Test name
Test status
Simulation time 100426625889 ps
CPU time 148.82 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:08:22 PM PST 23
Peak memory 199912 kb
Host smart-05878702-edfe-4051-87be-879038ab3197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461846193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.461846193
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.915775266
Short name T136
Test name
Test status
Simulation time 35170876789 ps
CPU time 50.14 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:06:48 PM PST 23
Peak memory 199716 kb
Host smart-8ed16f65-b064-4e0a-b7e4-78e7f957afbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915775266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.915775266
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1162470394
Short name T300
Test name
Test status
Simulation time 16960859627 ps
CPU time 8.57 seconds
Started Dec 27 01:03:52 PM PST 23
Finished Dec 27 01:04:10 PM PST 23
Peak memory 198948 kb
Host smart-11a03b61-16a3-48fe-8b7a-231736a97ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162470394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1162470394
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2916234826
Short name T124
Test name
Test status
Simulation time 28256278872 ps
CPU time 41.58 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:38 PM PST 23
Peak memory 200248 kb
Host smart-9024731d-aa34-4f14-b5e8-ccd4473bc2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916234826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2916234826
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3703488499
Short name T370
Test name
Test status
Simulation time 93621015507 ps
CPU time 73.29 seconds
Started Dec 27 01:06:02 PM PST 23
Finished Dec 27 01:07:17 PM PST 23
Peak memory 200176 kb
Host smart-caaf0b99-94d3-4bce-ae67-4bc440745389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703488499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3703488499
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1771295784
Short name T405
Test name
Test status
Simulation time 127612220720 ps
CPU time 13.55 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:06:11 PM PST 23
Peak memory 200260 kb
Host smart-55c0114e-1771-4561-81c9-8e7fbdf3e373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771295784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1771295784
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1965217411
Short name T105
Test name
Test status
Simulation time 14344859385 ps
CPU time 22.64 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:19 PM PST 23
Peak memory 200144 kb
Host smart-44bfea7f-0acf-4364-9d5f-f95176315cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965217411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1965217411
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.789243421
Short name T334
Test name
Test status
Simulation time 69933248455 ps
CPU time 30.2 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:27 PM PST 23
Peak memory 200124 kb
Host smart-b9c529a2-9077-4b4f-9acc-deb0f1149885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789243421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.789243421
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1679851301
Short name T156
Test name
Test status
Simulation time 249919535517 ps
CPU time 176.35 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:08:54 PM PST 23
Peak memory 200224 kb
Host smart-f1e6d95d-e60a-42fb-8e1e-9c7bfe902a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679851301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1679851301
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3613639926
Short name T394
Test name
Test status
Simulation time 19493539257 ps
CPU time 17.5 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:25 PM PST 23
Peak memory 200004 kb
Host smart-d07677a5-ab30-483c-8e91-636f8157fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613639926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3613639926
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1528760140
Short name T295
Test name
Test status
Simulation time 354598966377 ps
CPU time 995.81 seconds
Started Dec 27 01:03:54 PM PST 23
Finished Dec 27 01:20:37 PM PST 23
Peak memory 225148 kb
Host smart-5ea34a9e-3e36-42b3-99ad-bc96ceeacded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528760140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1528760140
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.802097398
Short name T381
Test name
Test status
Simulation time 57928090532 ps
CPU time 27.53 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:06:36 PM PST 23
Peak memory 200244 kb
Host smart-1df537cd-dc57-4e09-ab40-de5de1982058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802097398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.802097398
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2047958551
Short name T190
Test name
Test status
Simulation time 115732170141 ps
CPU time 44.7 seconds
Started Dec 27 01:04:11 PM PST 23
Finished Dec 27 01:05:01 PM PST 23
Peak memory 200192 kb
Host smart-671e6e67-4f42-4711-aa38-a1ab4abc8618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047958551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2047958551
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2396337788
Short name T366
Test name
Test status
Simulation time 1329030598908 ps
CPU time 1509.99 seconds
Started Dec 27 01:04:13 PM PST 23
Finished Dec 27 01:29:26 PM PST 23
Peak memory 216676 kb
Host smart-803b07a4-b0a1-47c6-bd04-a19b72ca4084
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396337788 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2396337788
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1213663055
Short name T321
Test name
Test status
Simulation time 41286588408 ps
CPU time 31.54 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:06:42 PM PST 23
Peak memory 199536 kb
Host smart-b13066fb-b3f3-4e6a-b880-17e2d48bf628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213663055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1213663055
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all.2274202541
Short name T323
Test name
Test status
Simulation time 35206011003 ps
CPU time 66.67 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:06:08 PM PST 23
Peak memory 200204 kb
Host smart-8619a702-8553-4661-85aa-cd91b64475cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274202541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2274202541
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3171275944
Short name T359
Test name
Test status
Simulation time 86037663901 ps
CPU time 51.92 seconds
Started Dec 27 01:04:20 PM PST 23
Finished Dec 27 01:05:13 PM PST 23
Peak memory 200184 kb
Host smart-f2c7d5ed-cdb0-466d-941a-9adb836b8fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171275944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3171275944
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1708756162
Short name T129
Test name
Test status
Simulation time 27977202770 ps
CPU time 25.61 seconds
Started Dec 27 01:06:09 PM PST 23
Finished Dec 27 01:06:38 PM PST 23
Peak memory 200144 kb
Host smart-c3afa5e9-6163-4ee8-84d2-18fc6c3bb9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708756162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1708756162
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.4291920342
Short name T348
Test name
Test status
Simulation time 36195238551 ps
CPU time 16.04 seconds
Started Dec 27 01:06:13 PM PST 23
Finished Dec 27 01:06:32 PM PST 23
Peak memory 199820 kb
Host smart-d7f395d9-5d5c-4a5a-a870-ef8dd2340de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291920342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.4291920342
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2872670930
Short name T355
Test name
Test status
Simulation time 158473753263 ps
CPU time 65.85 seconds
Started Dec 27 01:06:13 PM PST 23
Finished Dec 27 01:07:22 PM PST 23
Peak memory 200124 kb
Host smart-bd24c20d-03c8-43f9-83ab-c2f669e4b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872670930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2872670930
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3293040684
Short name T283
Test name
Test status
Simulation time 48287659635 ps
CPU time 79.56 seconds
Started Dec 27 01:06:11 PM PST 23
Finished Dec 27 01:07:33 PM PST 23
Peak memory 200148 kb
Host smart-1b8e3545-0fe6-40e2-adb4-dd047492480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293040684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3293040684
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1317436116
Short name T273
Test name
Test status
Simulation time 44681965040 ps
CPU time 19.97 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:06:31 PM PST 23
Peak memory 200292 kb
Host smart-53a64ba5-3365-4d33-a5ce-ccf4e056fa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317436116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1317436116
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.542726195
Short name T298
Test name
Test status
Simulation time 155610297200 ps
CPU time 21.8 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:25 PM PST 23
Peak memory 200156 kb
Host smart-1188cc94-be50-4b51-9d8f-ae48f8bdc12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542726195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.542726195
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_perf.3378061630
Short name T287
Test name
Test status
Simulation time 19406354034 ps
CPU time 101.53 seconds
Started Dec 27 01:04:39 PM PST 23
Finished Dec 27 01:06:31 PM PST 23
Peak memory 200160 kb
Host smart-372582c1-b2e9-4771-ac87-5c9a38109fa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378061630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3378061630
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3842974279
Short name T371
Test name
Test status
Simulation time 69740579917 ps
CPU time 52.97 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:06:11 PM PST 23
Peak memory 200216 kb
Host smart-289077ed-744f-4772-89e3-89d8b206ccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842974279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3842974279
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3019858771
Short name T404
Test name
Test status
Simulation time 86903383200 ps
CPU time 46.76 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:06:04 PM PST 23
Peak memory 200256 kb
Host smart-1188b0b3-796c-42db-9cdc-b995b9ea88ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019858771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3019858771
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2201438070
Short name T117
Test name
Test status
Simulation time 45923882839 ps
CPU time 25.66 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:05:32 PM PST 23
Peak memory 199620 kb
Host smart-a703873a-0793-450f-9c51-9bbb69c2f8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201438070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2201438070
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.4287188870
Short name T204
Test name
Test status
Simulation time 156304868031 ps
CPU time 1567.3 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:29:48 PM PST 23
Peak memory 216196 kb
Host smart-c776bfa4-168e-4531-8897-2df6fccc97d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287188870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4287188870
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2480840061
Short name T292
Test name
Test status
Simulation time 135709859947 ps
CPU time 211.27 seconds
Started Dec 27 01:03:26 PM PST 23
Finished Dec 27 01:07:01 PM PST 23
Peak memory 199896 kb
Host smart-d67b212b-6087-425e-a73d-8b9695b906ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480840061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2480840061
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2276104472
Short name T286
Test name
Test status
Simulation time 251938306997 ps
CPU time 667.35 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:16:40 PM PST 23
Peak memory 216668 kb
Host smart-cad85988-6185-4e01-a45e-983661a6c770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276104472 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2276104472
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2435522855
Short name T54
Test name
Test status
Simulation time 15069136 ps
CPU time 0.74 seconds
Started Dec 27 12:36:30 PM PST 23
Finished Dec 27 12:36:57 PM PST 23
Peak memory 196760 kb
Host smart-d3a25b63-45f9-4f05-984b-18ba2ffb9ced
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435522855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2435522855
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2794530479
Short name T1244
Test name
Test status
Simulation time 281184257 ps
CPU time 1.4 seconds
Started Dec 27 12:36:48 PM PST 23
Finished Dec 27 12:37:17 PM PST 23
Peak memory 197584 kb
Host smart-0b729810-8314-4be2-a9ec-eca71c410484
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794530479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2794530479
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.957199301
Short name T1257
Test name
Test status
Simulation time 14202259 ps
CPU time 0.56 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:36:38 PM PST 23
Peak memory 195428 kb
Host smart-d8a6f411-58d7-4cd4-bb49-410af49813f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957199301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.957199301
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.185535348
Short name T1228
Test name
Test status
Simulation time 20478634 ps
CPU time 1.01 seconds
Started Dec 27 12:35:59 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 199924 kb
Host smart-a731ee9e-ff0c-4504-b4a5-9f2cc16c5420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185535348 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.185535348
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.472942146
Short name T72
Test name
Test status
Simulation time 39186283 ps
CPU time 0.59 seconds
Started Dec 27 12:36:20 PM PST 23
Finished Dec 27 12:36:42 PM PST 23
Peak memory 195704 kb
Host smart-220f0e7b-b730-4437-9be5-c33f79778ab9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472942146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.472942146
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2631569009
Short name T68
Test name
Test status
Simulation time 39356151 ps
CPU time 0.71 seconds
Started Dec 27 12:36:15 PM PST 23
Finished Dec 27 12:36:38 PM PST 23
Peak memory 195908 kb
Host smart-f1191b88-b550-488b-8010-51fdca3b4ea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631569009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2631569009
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.294764224
Short name T490
Test name
Test status
Simulation time 124516796 ps
CPU time 1.16 seconds
Started Dec 27 12:35:46 PM PST 23
Finished Dec 27 12:36:06 PM PST 23
Peak memory 199960 kb
Host smart-5b24d947-f3c1-4327-806b-d1399373c5ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294764224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.294764224
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.514251976
Short name T46
Test name
Test status
Simulation time 55832580 ps
CPU time 0.74 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 196284 kb
Host smart-26b201df-db5e-4158-ad73-003692097a23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514251976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.514251976
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.129786096
Short name T7
Test name
Test status
Simulation time 18425361 ps
CPU time 0.58 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 195400 kb
Host smart-9800f78f-36fc-4fe4-8a5e-6798ccac853a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129786096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.129786096
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2861696484
Short name T1279
Test name
Test status
Simulation time 116367076 ps
CPU time 0.95 seconds
Started Dec 27 12:36:31 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 199804 kb
Host smart-eb5586bb-cfb4-403b-8901-a2d78cfa1c48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861696484 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2861696484
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2231001808
Short name T1268
Test name
Test status
Simulation time 22639260 ps
CPU time 0.55 seconds
Started Dec 27 12:36:19 PM PST 23
Finished Dec 27 12:36:39 PM PST 23
Peak memory 195380 kb
Host smart-9dfd0afe-43ff-4489-87c7-92afdb12a84f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231001808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2231001808
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1868038237
Short name T1283
Test name
Test status
Simulation time 27571053 ps
CPU time 0.54 seconds
Started Dec 27 12:36:09 PM PST 23
Finished Dec 27 12:36:30 PM PST 23
Peak memory 185184 kb
Host smart-b0caec1f-ca9f-4434-948b-848f2d913db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868038237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1868038237
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3864831219
Short name T479
Test name
Test status
Simulation time 59276415 ps
CPU time 0.68 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:28 PM PST 23
Peak memory 196860 kb
Host smart-a4e13025-a695-4867-99c0-9231145e5215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864831219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3864831219
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.4169543492
Short name T491
Test name
Test status
Simulation time 168178929 ps
CPU time 1.23 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 200112 kb
Host smart-7661ac3e-38dd-47d3-86f9-32e559b1230c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169543492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.4169543492
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1241481024
Short name T1229
Test name
Test status
Simulation time 166005847 ps
CPU time 1.31 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 199176 kb
Host smart-37e6b8ee-23be-42b0-84b9-ad602e35ba4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241481024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1241481024
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2520127811
Short name T1247
Test name
Test status
Simulation time 19754635 ps
CPU time 0.63 seconds
Started Dec 27 12:36:01 PM PST 23
Finished Dec 27 12:36:20 PM PST 23
Peak memory 196168 kb
Host smart-be5897e9-d98f-4a56-a668-d2dc6d6bb236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520127811 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2520127811
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2986129683
Short name T66
Test name
Test status
Simulation time 19368942 ps
CPU time 0.6 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:29 PM PST 23
Peak memory 195456 kb
Host smart-db99bec1-4ebf-48ed-94c6-2dcc4b81a693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986129683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2986129683
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1907182538
Short name T1235
Test name
Test status
Simulation time 355811813 ps
CPU time 0.77 seconds
Started Dec 27 12:36:16 PM PST 23
Finished Dec 27 12:36:38 PM PST 23
Peak memory 197016 kb
Host smart-da896800-c4a7-4c33-afd1-6602f3387144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907182538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1907182538
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2389329586
Short name T483
Test name
Test status
Simulation time 189536838 ps
CPU time 1.48 seconds
Started Dec 27 12:36:19 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 200024 kb
Host smart-7bef26e6-c609-4567-ad75-3d7500300d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389329586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2389329586
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2672085268
Short name T504
Test name
Test status
Simulation time 185632547 ps
CPU time 0.89 seconds
Started Dec 27 12:36:04 PM PST 23
Finished Dec 27 12:36:23 PM PST 23
Peak memory 198744 kb
Host smart-c3e259ec-7d92-45a7-b911-bb814c321d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672085268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2672085268
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2807066619
Short name T493
Test name
Test status
Simulation time 25818170 ps
CPU time 0.76 seconds
Started Dec 27 12:36:35 PM PST 23
Finished Dec 27 12:37:04 PM PST 23
Peak memory 198012 kb
Host smart-892c4f38-10f6-47b5-98ba-455a44b77613
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807066619 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2807066619
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3831549783
Short name T1249
Test name
Test status
Simulation time 17134863 ps
CPU time 0.6 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 195636 kb
Host smart-e64ea7f9-52b6-4789-9baf-55f51910a94e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831549783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3831549783
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1348908346
Short name T509
Test name
Test status
Simulation time 11667796 ps
CPU time 0.55 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 185040 kb
Host smart-91d362f9-6ef7-4370-bf1d-9a47230a5f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348908346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1348908346
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1311011844
Short name T69
Test name
Test status
Simulation time 26449188 ps
CPU time 0.69 seconds
Started Dec 27 12:36:18 PM PST 23
Finished Dec 27 12:36:39 PM PST 23
Peak memory 196876 kb
Host smart-76cf1d32-2826-48e6-bc91-3118a7dd2475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311011844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1311011844
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1918254940
Short name T45
Test name
Test status
Simulation time 45457274 ps
CPU time 1.45 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 200072 kb
Host smart-5b4c2357-147a-4d1d-8ed7-7f2de3f5f465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918254940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1918254940
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3926232254
Short name T38
Test name
Test status
Simulation time 60511869 ps
CPU time 0.94 seconds
Started Dec 27 12:36:40 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 198976 kb
Host smart-b1d048cb-5f27-4cdd-ade2-60a8d0abdda8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926232254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3926232254
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.111178718
Short name T484
Test name
Test status
Simulation time 31592060 ps
CPU time 0.65 seconds
Started Dec 27 12:35:53 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 196700 kb
Host smart-28f2b045-d86e-42dd-ae57-c9b64bba46ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111178718 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.111178718
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3504026681
Short name T510
Test name
Test status
Simulation time 56705867 ps
CPU time 0.59 seconds
Started Dec 27 12:36:34 PM PST 23
Finished Dec 27 12:37:02 PM PST 23
Peak memory 195640 kb
Host smart-ff540f9b-4e74-4b69-a1e4-5427f247cf10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504026681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3504026681
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.971040330
Short name T1266
Test name
Test status
Simulation time 140681547 ps
CPU time 0.61 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:36:29 PM PST 23
Peak memory 195384 kb
Host smart-cf540fd1-929c-47bb-ae4d-e783ba7ca420
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971040330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.971040330
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.968592683
Short name T1286
Test name
Test status
Simulation time 26568560 ps
CPU time 1.2 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:37:42 PM PST 23
Peak memory 199732 kb
Host smart-20859a97-15f8-4a24-9e4a-b0e3cbfaf5f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968592683 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.968592683
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.117266147
Short name T47
Test name
Test status
Simulation time 13928853 ps
CPU time 0.58 seconds
Started Dec 27 12:36:42 PM PST 23
Finished Dec 27 12:37:12 PM PST 23
Peak memory 195540 kb
Host smart-2cee98ff-6bbb-470c-bf3d-1c4dbd8ddd09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117266147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.117266147
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1281594775
Short name T488
Test name
Test status
Simulation time 93051389 ps
CPU time 0.53 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:12 PM PST 23
Peak memory 185152 kb
Host smart-9804d1ea-8429-4305-806e-13ee683d5397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281594775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1281594775
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.221895442
Short name T1230
Test name
Test status
Simulation time 25636285 ps
CPU time 0.68 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:36:36 PM PST 23
Peak memory 196952 kb
Host smart-022c4373-b42b-4d82-b4cb-ebe39bc91202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221895442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.221895442
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3946906496
Short name T1277
Test name
Test status
Simulation time 81296247 ps
CPU time 2 seconds
Started Dec 27 12:36:32 PM PST 23
Finished Dec 27 12:37:01 PM PST 23
Peak memory 200160 kb
Host smart-01e02d0b-12a7-4eb6-8974-264926fc31c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946906496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3946906496
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3161293267
Short name T1254
Test name
Test status
Simulation time 91754408 ps
CPU time 1.31 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:34 PM PST 23
Peak memory 199324 kb
Host smart-7cba31c8-40b4-46aa-be58-e3ba29741d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161293267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3161293267
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2005083378
Short name T1246
Test name
Test status
Simulation time 16783603 ps
CPU time 0.62 seconds
Started Dec 27 12:36:18 PM PST 23
Finished Dec 27 12:36:39 PM PST 23
Peak memory 197504 kb
Host smart-877de680-732c-4a84-a77c-e8c45eee609d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005083378 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2005083378
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1228827326
Short name T495
Test name
Test status
Simulation time 16325070 ps
CPU time 0.58 seconds
Started Dec 27 12:36:20 PM PST 23
Finished Dec 27 12:36:42 PM PST 23
Peak memory 195540 kb
Host smart-03130086-a6c8-4719-86af-41833ae9585d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228827326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1228827326
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3130705646
Short name T485
Test name
Test status
Simulation time 60197953 ps
CPU time 0.54 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:42 PM PST 23
Peak memory 185072 kb
Host smart-83951b81-6d0d-4c9b-b783-bf8be333f510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130705646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3130705646
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.593760191
Short name T1252
Test name
Test status
Simulation time 63599689 ps
CPU time 0.63 seconds
Started Dec 27 12:36:29 PM PST 23
Finished Dec 27 12:36:53 PM PST 23
Peak memory 195660 kb
Host smart-a191bf98-48d0-4b5a-922e-13e8501ba3e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593760191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.593760191
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.4053583296
Short name T44
Test name
Test status
Simulation time 622866658 ps
CPU time 1.34 seconds
Started Dec 27 12:36:13 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 199940 kb
Host smart-e865d0aa-5018-4f9a-9436-dd70f250f1f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053583296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.4053583296
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2852557489
Short name T500
Test name
Test status
Simulation time 87186740 ps
CPU time 1.21 seconds
Started Dec 27 12:37:52 PM PST 23
Finished Dec 27 12:37:57 PM PST 23
Peak memory 199112 kb
Host smart-f8cb7eed-4511-4839-a3e3-135fdcc6c2e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852557489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2852557489
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.613108732
Short name T1289
Test name
Test status
Simulation time 27226916 ps
CPU time 0.71 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 195040 kb
Host smart-7c8cd81d-9348-4095-b3c8-408c3cabb15d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613108732 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.613108732
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3191557385
Short name T52
Test name
Test status
Simulation time 14513867 ps
CPU time 0.56 seconds
Started Dec 27 12:36:29 PM PST 23
Finished Dec 27 12:36:53 PM PST 23
Peak memory 195388 kb
Host smart-20376921-39ee-4ddc-b598-883f79b2d2b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191557385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3191557385
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2250607986
Short name T1264
Test name
Test status
Simulation time 11178499 ps
CPU time 0.53 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:36:30 PM PST 23
Peak memory 185084 kb
Host smart-b6245af5-f922-469e-87ea-a0e730ede5d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250607986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2250607986
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.994661219
Short name T1240
Test name
Test status
Simulation time 18590043 ps
CPU time 0.7 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:33 PM PST 23
Peak memory 196564 kb
Host smart-73350653-26dc-4f35-aab7-0d4a4c07135b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994661219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.994661219
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3241264531
Short name T99
Test name
Test status
Simulation time 422821750 ps
CPU time 1.94 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:15 PM PST 23
Peak memory 200016 kb
Host smart-0a7630f9-b9bd-4d89-933b-d20f6cee6c12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241264531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3241264531
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2894514873
Short name T80
Test name
Test status
Simulation time 68322001 ps
CPU time 1.24 seconds
Started Dec 27 12:36:19 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 199256 kb
Host smart-bc0b5f9a-911b-4229-a6d2-3f2e0e140454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894514873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2894514873
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1489248395
Short name T1234
Test name
Test status
Simulation time 136511354 ps
CPU time 0.66 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:37:41 PM PST 23
Peak memory 197452 kb
Host smart-92ae2336-f694-4a3a-9af6-f16e3a695353
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489248395 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1489248395
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.534867557
Short name T1281
Test name
Test status
Simulation time 11640802 ps
CPU time 0.57 seconds
Started Dec 27 12:35:57 PM PST 23
Finished Dec 27 12:36:16 PM PST 23
Peak memory 195524 kb
Host smart-20082988-47dc-4e7c-8305-a15c547b78fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534867557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.534867557
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2870702374
Short name T1242
Test name
Test status
Simulation time 43538386 ps
CPU time 0.55 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:36:39 PM PST 23
Peak memory 185064 kb
Host smart-52e40992-9102-4f22-a16a-76f4b3328e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870702374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2870702374
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1800100747
Short name T71
Test name
Test status
Simulation time 95380215 ps
CPU time 0.67 seconds
Started Dec 27 12:36:56 PM PST 23
Finished Dec 27 12:37:22 PM PST 23
Peak memory 195664 kb
Host smart-0c4e2717-d593-48a3-af54-1017333f74d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800100747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1800100747
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.682099114
Short name T482
Test name
Test status
Simulation time 46573444 ps
CPU time 1.15 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:36:37 PM PST 23
Peak memory 199968 kb
Host smart-6e1a48ee-846c-46f0-bd62-b0b570b8d3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682099114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.682099114
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3192255487
Short name T499
Test name
Test status
Simulation time 60642714 ps
CPU time 0.96 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 199016 kb
Host smart-f53ec412-f422-44d7-98b2-36f47a641db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192255487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3192255487
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4163690265
Short name T43
Test name
Test status
Simulation time 34021968 ps
CPU time 1.59 seconds
Started Dec 27 12:36:04 PM PST 23
Finished Dec 27 12:36:24 PM PST 23
Peak memory 200084 kb
Host smart-649f148f-9794-4a6a-8c40-e0a3fd987872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163690265 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4163690265
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2590051140
Short name T1260
Test name
Test status
Simulation time 14536064 ps
CPU time 0.56 seconds
Started Dec 27 12:36:13 PM PST 23
Finished Dec 27 12:36:34 PM PST 23
Peak memory 195420 kb
Host smart-1819b571-582e-4729-94a6-5f7ba7bb180a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590051140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2590051140
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3729637371
Short name T1276
Test name
Test status
Simulation time 17169476 ps
CPU time 0.57 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 185148 kb
Host smart-09bb92fc-bce1-4688-95bd-4ddcae1821f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729637371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3729637371
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1571892721
Short name T5
Test name
Test status
Simulation time 601095014 ps
CPU time 2.54 seconds
Started Dec 27 12:36:50 PM PST 23
Finished Dec 27 12:37:19 PM PST 23
Peak memory 200068 kb
Host smart-a7f148f0-166d-4488-84f2-de884236d6d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571892721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1571892721
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3885933114
Short name T35
Test name
Test status
Simulation time 152005887 ps
CPU time 0.85 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 199792 kb
Host smart-673451df-de11-4a94-9b94-ed1114ec4b60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885933114 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3885933114
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1496246226
Short name T1263
Test name
Test status
Simulation time 43574542 ps
CPU time 0.65 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 193452 kb
Host smart-307adb13-9835-4629-a1f4-7a29fc5895a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496246226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1496246226
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3613699137
Short name T3
Test name
Test status
Simulation time 10733930 ps
CPU time 0.53 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 185112 kb
Host smart-3d61d988-5d8e-468f-b235-ec00a23f851a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613699137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3613699137
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2523515202
Short name T6
Test name
Test status
Simulation time 46249005 ps
CPU time 0.61 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 195532 kb
Host smart-946835a5-ad57-4e91-8aad-bc65e0f68c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523515202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2523515202
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2474682353
Short name T476
Test name
Test status
Simulation time 193275010 ps
CPU time 1.77 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 200060 kb
Host smart-26e0cb59-05c7-4e19-ab38-943a7029033c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474682353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2474682353
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.961410268
Short name T37
Test name
Test status
Simulation time 73427899 ps
CPU time 1.25 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:37:06 PM PST 23
Peak memory 199156 kb
Host smart-f876a6f9-c200-44b9-841d-d52694ba0e20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961410268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.961410268
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2643452685
Short name T41
Test name
Test status
Simulation time 84194236 ps
CPU time 0.87 seconds
Started Dec 27 12:36:35 PM PST 23
Finished Dec 27 12:37:04 PM PST 23
Peak memory 199816 kb
Host smart-82c56353-66b7-4e7b-a084-3f288d82e398
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643452685 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2643452685
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2078503651
Short name T1239
Test name
Test status
Simulation time 66215407 ps
CPU time 0.59 seconds
Started Dec 27 12:36:30 PM PST 23
Finished Dec 27 12:36:54 PM PST 23
Peak memory 195580 kb
Host smart-8233e47c-59ca-4baf-b7dc-206d7b8bbed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078503651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2078503651
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.265295161
Short name T486
Test name
Test status
Simulation time 12242449 ps
CPU time 0.56 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:36:38 PM PST 23
Peak memory 185200 kb
Host smart-cb2ef229-9144-426c-ad59-02036862756e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265295161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.265295161
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2161896670
Short name T1237
Test name
Test status
Simulation time 47997230 ps
CPU time 0.61 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 195820 kb
Host smart-81447682-d980-42df-aac4-ae3eb5c81124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161896670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2161896670
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1008396748
Short name T2
Test name
Test status
Simulation time 24136468 ps
CPU time 1.11 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 197548 kb
Host smart-c0a3fbfa-fdfa-4e9b-831c-f2fa4bea6c76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008396748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1008396748
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1094579677
Short name T79
Test name
Test status
Simulation time 202232129 ps
CPU time 0.96 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 196340 kb
Host smart-3004602d-0c89-4651-b925-2675bc6963aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094579677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1094579677
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1283218293
Short name T1256
Test name
Test status
Simulation time 18743270 ps
CPU time 0.67 seconds
Started Dec 27 12:35:47 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 195316 kb
Host smart-5c426491-b4a1-486a-88e7-4d16588a2ffc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283218293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1283218293
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1643424994
Short name T501
Test name
Test status
Simulation time 510520085 ps
CPU time 1.49 seconds
Started Dec 27 12:36:32 PM PST 23
Finished Dec 27 12:37:00 PM PST 23
Peak memory 197764 kb
Host smart-da7ee157-aa25-4185-9c4c-7d1be34bd1bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643424994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1643424994
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3770642006
Short name T1278
Test name
Test status
Simulation time 37474983 ps
CPU time 0.56 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 195420 kb
Host smart-23efdb90-8f0e-412b-8ba2-8e3a7918ea02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770642006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3770642006
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3829168810
Short name T1262
Test name
Test status
Simulation time 247600569 ps
CPU time 0.74 seconds
Started Dec 27 12:36:06 PM PST 23
Finished Dec 27 12:36:27 PM PST 23
Peak memory 199612 kb
Host smart-bbaba0bb-3df5-4216-b7fd-8f41712c50bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829168810 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3829168810
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2940710279
Short name T51
Test name
Test status
Simulation time 131388874 ps
CPU time 0.57 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 195376 kb
Host smart-661a562d-4d39-4d49-8fef-dedfef67f496
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940710279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2940710279
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.53973090
Short name T409
Test name
Test status
Simulation time 43124207 ps
CPU time 0.55 seconds
Started Dec 27 12:35:59 PM PST 23
Finished Dec 27 12:36:18 PM PST 23
Peak memory 194320 kb
Host smart-a65ba980-dad7-4c0d-a56f-0e3a45c4f20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53973090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.53973090
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3404241615
Short name T472
Test name
Test status
Simulation time 23953945 ps
CPU time 0.61 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:18 PM PST 23
Peak memory 195720 kb
Host smart-60c84431-886f-4a0d-ac37-48321ac9ce36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404241615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3404241615
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2328463955
Short name T507
Test name
Test status
Simulation time 26444598 ps
CPU time 1.12 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:33 PM PST 23
Peak memory 200104 kb
Host smart-61dc97a7-c042-4919-9bd4-54e551356aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328463955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2328463955
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1170291461
Short name T1245
Test name
Test status
Simulation time 168082293 ps
CPU time 0.91 seconds
Started Dec 27 12:36:27 PM PST 23
Finished Dec 27 12:36:50 PM PST 23
Peak memory 198572 kb
Host smart-f504a69f-0ba2-4d30-bdf4-94896122c09e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170291461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1170291461
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.968785607
Short name T411
Test name
Test status
Simulation time 12241372 ps
CPU time 0.53 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 185172 kb
Host smart-5ad89f46-ebe3-4ffe-867d-bae16bb299b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968785607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.968785607
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2729173805
Short name T413
Test name
Test status
Simulation time 19416001 ps
CPU time 0.56 seconds
Started Dec 27 12:36:25 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 185116 kb
Host smart-9754a05c-dab4-4a0e-bb06-6828848b134b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729173805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2729173805
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1785039091
Short name T1253
Test name
Test status
Simulation time 48157421 ps
CPU time 0.55 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 194328 kb
Host smart-3f4672ec-1bf6-4312-bd89-182003c52a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785039091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1785039091
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4258959344
Short name T414
Test name
Test status
Simulation time 124903149 ps
CPU time 0.55 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:50 PM PST 23
Peak memory 185200 kb
Host smart-bf7f471f-dd23-45a7-97a5-cbcb25bb3ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258959344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4258959344
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3199904181
Short name T100
Test name
Test status
Simulation time 47843521 ps
CPU time 0.56 seconds
Started Dec 27 12:36:03 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 194324 kb
Host smart-65a977b7-c3cf-4988-9f56-8df32ae23fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199904181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3199904181
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4226783583
Short name T1259
Test name
Test status
Simulation time 42349696 ps
CPU time 0.55 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 185096 kb
Host smart-f4a52af4-b00b-47d2-9407-672502ada2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226783583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4226783583
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4091595547
Short name T1270
Test name
Test status
Simulation time 17035343 ps
CPU time 0.6 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:33 PM PST 23
Peak memory 185052 kb
Host smart-9243f224-7f38-4ec9-a623-0fd9777f3f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091595547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4091595547
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1583454933
Short name T1288
Test name
Test status
Simulation time 127485950 ps
CPU time 0.6 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 185200 kb
Host smart-863027c6-beb8-4e36-b124-753d88a62c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583454933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1583454933
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.290077198
Short name T32
Test name
Test status
Simulation time 22181049 ps
CPU time 0.55 seconds
Started Dec 27 12:36:42 PM PST 23
Finished Dec 27 12:37:11 PM PST 23
Peak memory 185072 kb
Host smart-d93a2b60-e14f-4f04-a52d-e1f0ec197568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290077198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.290077198
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1706659803
Short name T471
Test name
Test status
Simulation time 17667851 ps
CPU time 0.64 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 194944 kb
Host smart-17382985-3c68-4791-a3c8-388b108e0b44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706659803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1706659803
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3865062988
Short name T50
Test name
Test status
Simulation time 176763373 ps
CPU time 2.47 seconds
Started Dec 27 12:36:09 PM PST 23
Finished Dec 27 12:36:32 PM PST 23
Peak memory 197636 kb
Host smart-40eb10d5-603e-42e0-a934-876b1a4ef56c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865062988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3865062988
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3260015943
Short name T1251
Test name
Test status
Simulation time 116138341 ps
CPU time 0.56 seconds
Started Dec 27 12:36:32 PM PST 23
Finished Dec 27 12:37:00 PM PST 23
Peak memory 195504 kb
Host smart-6b7c0966-48b6-49ff-847c-90ace442dbca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260015943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3260015943
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.626132004
Short name T42
Test name
Test status
Simulation time 20829162 ps
CPU time 0.93 seconds
Started Dec 27 12:36:05 PM PST 23
Finished Dec 27 12:36:26 PM PST 23
Peak memory 199784 kb
Host smart-12d1ef5d-06be-409e-bfc0-f66f239c3b8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626132004 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.626132004
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3595386782
Short name T98
Test name
Test status
Simulation time 58838053 ps
CPU time 0.58 seconds
Started Dec 27 12:36:13 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 195416 kb
Host smart-bb3cbc54-3505-4384-826f-1845447bfa09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595386782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3595386782
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2471247256
Short name T1238
Test name
Test status
Simulation time 16337945 ps
CPU time 0.57 seconds
Started Dec 27 12:35:53 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 185116 kb
Host smart-5f4de86f-d13b-4c75-9b3a-25d2a7724fa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471247256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2471247256
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2834669449
Short name T506
Test name
Test status
Simulation time 31115167 ps
CPU time 0.61 seconds
Started Dec 27 12:36:22 PM PST 23
Finished Dec 27 12:36:44 PM PST 23
Peak memory 195600 kb
Host smart-0bc61172-3dc0-4380-acfe-599da47b6fd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834669449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2834669449
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.4110800005
Short name T1290
Test name
Test status
Simulation time 64824486 ps
CPU time 1.42 seconds
Started Dec 27 12:36:29 PM PST 23
Finished Dec 27 12:36:54 PM PST 23
Peak memory 199100 kb
Host smart-3c9c0f8a-9b1c-4726-8b05-f7984ec9fc29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110800005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4110800005
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3686043470
Short name T477
Test name
Test status
Simulation time 41098372 ps
CPU time 0.54 seconds
Started Dec 27 12:36:32 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 185196 kb
Host smart-1f3c4cbf-bf03-4e85-9903-77bceb754e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686043470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3686043470
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2011808788
Short name T1274
Test name
Test status
Simulation time 29702544 ps
CPU time 0.56 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:42 PM PST 23
Peak memory 185112 kb
Host smart-9e34d718-261a-451d-9968-bceffcc57879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011808788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2011808788
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3274248813
Short name T1250
Test name
Test status
Simulation time 94469435 ps
CPU time 0.54 seconds
Started Dec 27 12:36:20 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 185044 kb
Host smart-ace03928-beca-454f-a917-6ee8a2b7087a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274248813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3274248813
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4171538196
Short name T502
Test name
Test status
Simulation time 22954225 ps
CPU time 0.56 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:50 PM PST 23
Peak memory 185112 kb
Host smart-333ca387-79d2-46fa-96aa-64b4da7ac43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171538196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4171538196
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.536381523
Short name T478
Test name
Test status
Simulation time 74455066 ps
CPU time 0.53 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:32 PM PST 23
Peak memory 185064 kb
Host smart-31dacae7-1b92-451a-ac85-667c172390e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536381523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.536381523
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4073315054
Short name T505
Test name
Test status
Simulation time 38411506 ps
CPU time 0.56 seconds
Started Dec 27 12:36:27 PM PST 23
Finished Dec 27 12:36:50 PM PST 23
Peak memory 185204 kb
Host smart-b1e087a3-4152-49ee-bd4d-8f93f328cf5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073315054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4073315054
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.4147147357
Short name T1287
Test name
Test status
Simulation time 40060742 ps
CPU time 0.53 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 194440 kb
Host smart-b28be12a-62f3-43f2-9704-8e49cd71d0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147147357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4147147357
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3328802519
Short name T410
Test name
Test status
Simulation time 29044287 ps
CPU time 0.53 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 185208 kb
Host smart-1d73552f-fc4b-441f-8d3b-7821e6f18e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328802519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3328802519
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.898558652
Short name T480
Test name
Test status
Simulation time 21127791 ps
CPU time 0.53 seconds
Started Dec 27 12:36:39 PM PST 23
Finished Dec 27 12:37:09 PM PST 23
Peak memory 185088 kb
Host smart-5dd693c0-3b8a-4622-be5d-d11edf924a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898558652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.898558652
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3655604757
Short name T1231
Test name
Test status
Simulation time 53943314 ps
CPU time 0.53 seconds
Started Dec 27 12:36:15 PM PST 23
Finished Dec 27 12:36:36 PM PST 23
Peak memory 185088 kb
Host smart-eb404152-37ce-4684-8b33-9ef2dec304d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655604757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3655604757
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3359657227
Short name T494
Test name
Test status
Simulation time 27254798 ps
CPU time 0.78 seconds
Started Dec 27 12:36:05 PM PST 23
Finished Dec 27 12:36:24 PM PST 23
Peak memory 196380 kb
Host smart-ac7dd500-5c35-4c55-a7fc-b3c44f47b781
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359657227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3359657227
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1072037050
Short name T60
Test name
Test status
Simulation time 509626590 ps
CPU time 2.55 seconds
Started Dec 27 12:36:35 PM PST 23
Finished Dec 27 12:37:06 PM PST 23
Peak memory 197524 kb
Host smart-1ce6c66b-23ef-48e2-8ac0-5c8e00a31d85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072037050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1072037050
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4137803960
Short name T31
Test name
Test status
Simulation time 34095000 ps
CPU time 0.54 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:18 PM PST 23
Peak memory 195404 kb
Host smart-18668651-a4d6-4e42-a4a5-3098e31b4dd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137803960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.4137803960
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2531300057
Short name T101
Test name
Test status
Simulation time 50313265 ps
CPU time 0.71 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:36:38 PM PST 23
Peak memory 198264 kb
Host smart-3f855906-dfce-462e-be35-afd4bef39228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531300057 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2531300057
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1157279450
Short name T64
Test name
Test status
Simulation time 81834789 ps
CPU time 0.59 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 195416 kb
Host smart-94dd1407-e0e2-49fa-8602-86a5325faee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157279450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1157279450
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4128337392
Short name T481
Test name
Test status
Simulation time 24781167 ps
CPU time 0.55 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:43 PM PST 23
Peak memory 185072 kb
Host smart-48814822-cb09-48d5-9a24-87e6e685c9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128337392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4128337392
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.132817438
Short name T49
Test name
Test status
Simulation time 39458399 ps
CPU time 0.71 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:35:53 PM PST 23
Peak memory 196948 kb
Host smart-67fc877b-f459-4e10-9799-741081423729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132817438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.132817438
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3053948827
Short name T39
Test name
Test status
Simulation time 265425875 ps
CPU time 1.6 seconds
Started Dec 27 12:35:50 PM PST 23
Finished Dec 27 12:36:11 PM PST 23
Peak memory 199996 kb
Host smart-daa1d337-9316-444b-9ff0-af959a47d432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053948827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3053948827
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.163585478
Short name T406
Test name
Test status
Simulation time 257515806 ps
CPU time 0.92 seconds
Started Dec 27 12:35:49 PM PST 23
Finished Dec 27 12:36:09 PM PST 23
Peak memory 198800 kb
Host smart-9e188a0e-b719-42d1-8c52-d44bfe5fe288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163585478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.163585478
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2198829635
Short name T1273
Test name
Test status
Simulation time 25824195 ps
CPU time 0.54 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:36:30 PM PST 23
Peak memory 194416 kb
Host smart-2f87cba1-3a77-4ecc-a456-840685489985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198829635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2198829635
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1745602981
Short name T1280
Test name
Test status
Simulation time 50504306 ps
CPU time 0.55 seconds
Started Dec 27 12:36:18 PM PST 23
Finished Dec 27 12:36:39 PM PST 23
Peak memory 185100 kb
Host smart-08c9467c-f06b-4267-867f-15ebad1c85de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745602981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1745602981
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3140194702
Short name T1272
Test name
Test status
Simulation time 16738875 ps
CPU time 0.56 seconds
Started Dec 27 12:36:03 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 185092 kb
Host smart-a78349b3-bac9-4cfc-a9b8-bc38859a402e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140194702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3140194702
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.157755913
Short name T498
Test name
Test status
Simulation time 15423934 ps
CPU time 0.54 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 185164 kb
Host smart-cc9b49ad-3cc2-46b5-ab0a-1831c75fc9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157755913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.157755913
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1228195611
Short name T1248
Test name
Test status
Simulation time 34029242 ps
CPU time 0.54 seconds
Started Dec 27 12:36:15 PM PST 23
Finished Dec 27 12:36:38 PM PST 23
Peak memory 185112 kb
Host smart-3db0fc1f-ba23-4f1c-a421-abf2ab7880c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228195611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1228195611
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2484701756
Short name T475
Test name
Test status
Simulation time 16962832 ps
CPU time 0.55 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:42 PM PST 23
Peak memory 185108 kb
Host smart-7af58ca1-9d28-4665-8290-d01b9efdfb61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484701756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2484701756
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.782168011
Short name T8
Test name
Test status
Simulation time 14659571 ps
CPU time 0.53 seconds
Started Dec 27 12:36:41 PM PST 23
Finished Dec 27 12:37:11 PM PST 23
Peak memory 194228 kb
Host smart-bf13c644-2ff4-4f45-b05a-11778fda0d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782168011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.782168011
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3332938765
Short name T412
Test name
Test status
Simulation time 51176406 ps
CPU time 0.55 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:28 PM PST 23
Peak memory 185096 kb
Host smart-ab43cb50-ad3b-4a66-8d89-53f1cab969a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332938765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3332938765
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3333070914
Short name T1285
Test name
Test status
Simulation time 14849975 ps
CPU time 0.52 seconds
Started Dec 27 12:36:24 PM PST 23
Finished Dec 27 12:36:46 PM PST 23
Peak memory 185068 kb
Host smart-9816e5d0-ff9a-4a3f-bab2-3b0f8976a1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333070914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3333070914
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.60397888
Short name T1255
Test name
Test status
Simulation time 12120087 ps
CPU time 0.62 seconds
Started Dec 27 12:36:19 PM PST 23
Finished Dec 27 12:36:41 PM PST 23
Peak memory 196184 kb
Host smart-412f5c77-e7f3-4906-b9ad-4f4c2bd80788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60397888 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.60397888
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1156167604
Short name T1269
Test name
Test status
Simulation time 14265513 ps
CPU time 0.56 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 195408 kb
Host smart-aa576579-6093-481b-8254-e4f4dd517a73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156167604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1156167604
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1976049371
Short name T1292
Test name
Test status
Simulation time 12708088 ps
CPU time 0.57 seconds
Started Dec 27 12:35:52 PM PST 23
Finished Dec 27 12:36:12 PM PST 23
Peak memory 185088 kb
Host smart-2562d3b7-3170-4cc7-a1ec-3ea6659e6b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976049371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1976049371
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1195900037
Short name T496
Test name
Test status
Simulation time 108511961 ps
CPU time 0.61 seconds
Started Dec 27 12:36:49 PM PST 23
Finished Dec 27 12:37:17 PM PST 23
Peak memory 194812 kb
Host smart-424dcd3d-f6c7-4f0a-9ce9-8433190f0a67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195900037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1195900037
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.287257575
Short name T497
Test name
Test status
Simulation time 195680395 ps
CPU time 2.4 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 200052 kb
Host smart-2e9005f7-e6e8-4124-a51a-f2d68e9b1c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287257575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.287257575
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.195284552
Short name T36
Test name
Test status
Simulation time 153460861 ps
CPU time 0.89 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 198872 kb
Host smart-fd72d40a-ea88-4115-bdc9-7ddcfe2b59f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195284552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.195284552
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.451161522
Short name T1291
Test name
Test status
Simulation time 29842773 ps
CPU time 0.77 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:14 PM PST 23
Peak memory 199796 kb
Host smart-0918ed0f-065b-49d6-8395-f86d5b3b628c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451161522 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.451161522
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3059067568
Short name T1241
Test name
Test status
Simulation time 34024714 ps
CPU time 0.56 seconds
Started Dec 27 12:37:23 PM PST 23
Finished Dec 27 12:37:42 PM PST 23
Peak memory 195340 kb
Host smart-86545803-b429-45eb-9f5b-fe345ddaad9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059067568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3059067568
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1433306238
Short name T503
Test name
Test status
Simulation time 31047230 ps
CPU time 0.58 seconds
Started Dec 27 12:36:01 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 185100 kb
Host smart-44b3a666-8a74-4571-9c7c-b8989c143ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433306238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1433306238
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2784001326
Short name T1233
Test name
Test status
Simulation time 22336249 ps
CPU time 0.66 seconds
Started Dec 27 12:36:04 PM PST 23
Finished Dec 27 12:36:23 PM PST 23
Peak memory 195544 kb
Host smart-49be6d8b-7553-4a40-9196-3863594e29d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784001326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2784001326
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1517293397
Short name T1232
Test name
Test status
Simulation time 123279398 ps
CPU time 1.97 seconds
Started Dec 27 12:37:19 PM PST 23
Finished Dec 27 12:37:40 PM PST 23
Peak memory 199908 kb
Host smart-f05c315a-7a07-424e-bf11-88ec74904642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517293397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1517293397
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1432416300
Short name T487
Test name
Test status
Simulation time 360036159 ps
CPU time 0.89 seconds
Started Dec 27 12:36:31 PM PST 23
Finished Dec 27 12:36:57 PM PST 23
Peak memory 198448 kb
Host smart-72e87466-5b27-43cd-b73e-a8c4ef221a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432416300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1432416300
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2261014567
Short name T1265
Test name
Test status
Simulation time 157068820 ps
CPU time 0.79 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:43 PM PST 23
Peak memory 199300 kb
Host smart-a75e9f8f-6433-4cb0-baa8-1cc13bcfa3e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261014567 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2261014567
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1637754090
Short name T65
Test name
Test status
Simulation time 28304938 ps
CPU time 0.61 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 195568 kb
Host smart-9f62aa05-f335-46af-a842-a8bf5aeaec12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637754090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1637754090
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1307599013
Short name T1243
Test name
Test status
Simulation time 71492161 ps
CPU time 0.53 seconds
Started Dec 27 12:36:19 PM PST 23
Finished Dec 27 12:36:39 PM PST 23
Peak memory 194404 kb
Host smart-3e91d76f-5d7e-493b-944a-43dc7988f83b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307599013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1307599013
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1841309075
Short name T70
Test name
Test status
Simulation time 49022822 ps
CPU time 0.63 seconds
Started Dec 27 12:36:51 PM PST 23
Finished Dec 27 12:37:18 PM PST 23
Peak memory 196640 kb
Host smart-3e512599-697e-4ca7-9d59-d303b1324af9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841309075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1841309075
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3319080254
Short name T40
Test name
Test status
Simulation time 21396760 ps
CPU time 1.08 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:44 PM PST 23
Peak memory 199772 kb
Host smart-bf26da6d-31c4-4953-ada0-e8191992fd17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319080254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3319080254
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3586459958
Short name T81
Test name
Test status
Simulation time 173938942 ps
CPU time 1.2 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 199132 kb
Host smart-f3d397ea-2117-4dc0-9237-d0af1b28d786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586459958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3586459958
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2961883884
Short name T1258
Test name
Test status
Simulation time 16560672 ps
CPU time 0.76 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:35:47 PM PST 23
Peak memory 199236 kb
Host smart-2f90bb81-12b3-4105-9ad4-cf776610f1f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961883884 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2961883884
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.145249713
Short name T48
Test name
Test status
Simulation time 15581662 ps
CPU time 0.57 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:11 PM PST 23
Peak memory 195504 kb
Host smart-0b90439e-0a1d-46ea-9fa4-fde96ba3dbb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145249713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.145249713
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.433843899
Short name T474
Test name
Test status
Simulation time 43806945 ps
CPU time 0.54 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:37:41 PM PST 23
Peak memory 194232 kb
Host smart-7885b2e5-c927-4a12-86f6-e4cdecd99575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433843899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.433843899
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3322504333
Short name T1236
Test name
Test status
Simulation time 43803928 ps
CPU time 0.66 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:33 PM PST 23
Peak memory 195500 kb
Host smart-b65bba8a-68fb-4518-9901-48472a8f5106
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322504333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3322504333
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.526741111
Short name T1267
Test name
Test status
Simulation time 134638432 ps
CPU time 1.34 seconds
Started Dec 27 12:36:47 PM PST 23
Finished Dec 27 12:37:16 PM PST 23
Peak memory 200100 kb
Host smart-300d442f-7dfc-4d09-a94c-a53211809b34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526741111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.526741111
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2889354518
Short name T1275
Test name
Test status
Simulation time 188827931 ps
CPU time 0.95 seconds
Started Dec 27 12:36:32 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 199132 kb
Host smart-6a5dcf48-1acd-4362-a2aa-eb63f58f5fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889354518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2889354518
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.809698470
Short name T473
Test name
Test status
Simulation time 20657330 ps
CPU time 0.69 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 197668 kb
Host smart-3854792b-ca51-4619-b574-bd065e67c023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809698470 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.809698470
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4067241145
Short name T1284
Test name
Test status
Simulation time 14381770 ps
CPU time 0.58 seconds
Started Dec 27 12:36:09 PM PST 23
Finished Dec 27 12:36:30 PM PST 23
Peak memory 195420 kb
Host smart-f3e1700e-3547-419d-94d1-1b06ec96f32e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067241145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4067241145
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3300370127
Short name T1282
Test name
Test status
Simulation time 12540459 ps
CPU time 0.54 seconds
Started Dec 27 12:36:03 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 185052 kb
Host smart-b1b95cc5-4d44-4826-9dd0-1cf403f8c5a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300370127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3300370127
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.525381659
Short name T508
Test name
Test status
Simulation time 90696274 ps
CPU time 0.72 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:36:03 PM PST 23
Peak memory 197012 kb
Host smart-5f0625fe-b74a-4492-b596-292817c67ad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525381659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.525381659
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.787323474
Short name T1261
Test name
Test status
Simulation time 201648220 ps
CPU time 1.7 seconds
Started Dec 27 12:36:13 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 200012 kb
Host smart-2ca41e7c-87e5-4095-a8eb-2cfab3ede635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787323474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.787323474
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1757391396
Short name T1271
Test name
Test status
Simulation time 153984994 ps
CPU time 1.28 seconds
Started Dec 27 12:36:24 PM PST 23
Finished Dec 27 12:36:47 PM PST 23
Peak memory 199212 kb
Host smart-e4bb36d7-9f26-4824-83a6-50ab252cbde6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757391396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1757391396
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1428979430
Short name T924
Test name
Test status
Simulation time 112691534 ps
CPU time 0.54 seconds
Started Dec 27 01:03:26 PM PST 23
Finished Dec 27 01:03:30 PM PST 23
Peak memory 195524 kb
Host smart-105099f4-7ea1-499c-bc12-b13c230b3daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428979430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1428979430
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1731938880
Short name T350
Test name
Test status
Simulation time 185329752210 ps
CPU time 83.7 seconds
Started Dec 27 01:03:05 PM PST 23
Finished Dec 27 01:04:42 PM PST 23
Peak memory 200200 kb
Host smart-b57bd468-03f7-417b-9ecc-0a7db1100afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731938880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1731938880
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.73089685
Short name T109
Test name
Test status
Simulation time 14852832914 ps
CPU time 12.9 seconds
Started Dec 27 01:03:03 PM PST 23
Finished Dec 27 01:03:29 PM PST 23
Peak memory 200116 kb
Host smart-59cee2c4-f517-41d3-80a3-bbcc40d5421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73089685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.73089685
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.626879073
Short name T560
Test name
Test status
Simulation time 565432875389 ps
CPU time 827.86 seconds
Started Dec 27 01:03:06 PM PST 23
Finished Dec 27 01:17:06 PM PST 23
Peak memory 200064 kb
Host smart-0e920c8f-7dd7-43f8-92bd-2f34831a3ff9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626879073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.626879073
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.418111101
Short name T878
Test name
Test status
Simulation time 125115450939 ps
CPU time 132.41 seconds
Started Dec 27 01:03:05 PM PST 23
Finished Dec 27 01:05:30 PM PST 23
Peak memory 200252 kb
Host smart-75109421-ffa2-438f-93da-45bd21156735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=418111101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.418111101
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.642586814
Short name T778
Test name
Test status
Simulation time 7500865341 ps
CPU time 14.28 seconds
Started Dec 27 01:03:11 PM PST 23
Finished Dec 27 01:03:34 PM PST 23
Peak memory 198808 kb
Host smart-de2b2a49-9b05-43a5-a020-633aae1a9bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642586814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.642586814
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1772019385
Short name T94
Test name
Test status
Simulation time 52587330391 ps
CPU time 31.85 seconds
Started Dec 27 01:03:07 PM PST 23
Finished Dec 27 01:03:50 PM PST 23
Peak memory 199616 kb
Host smart-f2424101-d1d6-4255-a9a3-e9faf1682d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772019385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1772019385
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.884920379
Short name T985
Test name
Test status
Simulation time 14938678378 ps
CPU time 167.15 seconds
Started Dec 27 01:03:04 PM PST 23
Finished Dec 27 01:06:04 PM PST 23
Peak memory 200284 kb
Host smart-e6dd2485-c73c-477e-9960-744bf568f92c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884920379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.884920379
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.589313171
Short name T77
Test name
Test status
Simulation time 2051202030 ps
CPU time 19.91 seconds
Started Dec 27 01:03:00 PM PST 23
Finished Dec 27 01:03:34 PM PST 23
Peak memory 198316 kb
Host smart-bd097dbf-a734-4025-83d6-1a5d8dd5c2da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589313171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.589313171
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.701762254
Short name T332
Test name
Test status
Simulation time 71290808433 ps
CPU time 94.13 seconds
Started Dec 27 01:03:02 PM PST 23
Finished Dec 27 01:04:49 PM PST 23
Peak memory 200232 kb
Host smart-3f9efb29-144c-4670-8e33-455620aecc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701762254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.701762254
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2315439891
Short name T1176
Test name
Test status
Simulation time 26856536321 ps
CPU time 12.43 seconds
Started Dec 27 01:03:04 PM PST 23
Finished Dec 27 01:03:29 PM PST 23
Peak memory 195952 kb
Host smart-82a342d5-f42f-4fd4-94ab-98b38d0f8708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315439891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2315439891
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3846516508
Short name T516
Test name
Test status
Simulation time 294236295 ps
CPU time 1 seconds
Started Dec 27 01:02:59 PM PST 23
Finished Dec 27 01:03:14 PM PST 23
Peak memory 198148 kb
Host smart-386f195f-104e-4ccf-b697-0b3ed4c1702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846516508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3846516508
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.857721290
Short name T628
Test name
Test status
Simulation time 222369258440 ps
CPU time 426.47 seconds
Started Dec 27 01:03:21 PM PST 23
Finished Dec 27 01:10:30 PM PST 23
Peak memory 208708 kb
Host smart-9902324e-a53c-4448-968f-cddf99c6062c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857721290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.857721290
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3252384839
Short name T1163
Test name
Test status
Simulation time 62475840795 ps
CPU time 650.76 seconds
Started Dec 27 01:03:24 PM PST 23
Finished Dec 27 01:14:18 PM PST 23
Peak memory 216992 kb
Host smart-59d45c50-639c-4c40-87df-980289ff93be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252384839 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3252384839
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1924884277
Short name T451
Test name
Test status
Simulation time 7131057306 ps
CPU time 21.38 seconds
Started Dec 27 01:03:04 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 199536 kb
Host smart-3d675e56-fd3c-4cdd-8e6d-e4710063a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924884277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1924884277
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2470398345
Short name T172
Test name
Test status
Simulation time 52188994367 ps
CPU time 45.59 seconds
Started Dec 27 01:03:05 PM PST 23
Finished Dec 27 01:04:04 PM PST 23
Peak memory 200252 kb
Host smart-56f60be5-6523-41c6-bf69-ca882a8fd8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470398345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2470398345
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1625331523
Short name T1064
Test name
Test status
Simulation time 13721955 ps
CPU time 0.55 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 194532 kb
Host smart-8eaf7be0-4a51-4d33-9782-231e64205392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625331523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1625331523
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4101317776
Short name T419
Test name
Test status
Simulation time 107776634174 ps
CPU time 178.14 seconds
Started Dec 27 01:03:24 PM PST 23
Finished Dec 27 01:06:24 PM PST 23
Peak memory 200188 kb
Host smart-4b23e410-b4ef-4bc6-9579-a2b043107cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101317776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4101317776
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.915084129
Short name T696
Test name
Test status
Simulation time 43970091945 ps
CPU time 68.47 seconds
Started Dec 27 01:03:15 PM PST 23
Finished Dec 27 01:04:30 PM PST 23
Peak memory 200184 kb
Host smart-4837b305-e610-4ec5-b6bf-e6018436cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915084129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.915084129
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2189274339
Short name T1105
Test name
Test status
Simulation time 158949592124 ps
CPU time 164.14 seconds
Started Dec 27 01:03:24 PM PST 23
Finished Dec 27 01:06:11 PM PST 23
Peak memory 200152 kb
Host smart-f38a185d-7f6b-4386-a5cc-23c601760c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189274339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2189274339
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3081097004
Short name T643
Test name
Test status
Simulation time 514677341687 ps
CPU time 903.58 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:18:28 PM PST 23
Peak memory 200224 kb
Host smart-64b15921-519d-4b5a-9e8a-c6c7179986f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081097004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3081097004
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2917290193
Short name T863
Test name
Test status
Simulation time 121199620213 ps
CPU time 152.33 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:06:04 PM PST 23
Peak memory 200176 kb
Host smart-ec25aedf-16f8-4ac5-a950-9521e41a9a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2917290193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2917290193
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1285749196
Short name T600
Test name
Test status
Simulation time 1251993562 ps
CPU time 3.5 seconds
Started Dec 27 01:03:09 PM PST 23
Finished Dec 27 01:03:23 PM PST 23
Peak memory 198328 kb
Host smart-5b65781c-4de7-4ae3-94d1-e3dbb798b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285749196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1285749196
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.1379596301
Short name T549
Test name
Test status
Simulation time 11261114052 ps
CPU time 151.01 seconds
Started Dec 27 01:03:44 PM PST 23
Finished Dec 27 01:06:20 PM PST 23
Peak memory 200240 kb
Host smart-3b877ca6-d483-466b-9252-bfb206d34bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379596301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1379596301
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.87137026
Short name T544
Test name
Test status
Simulation time 101028750066 ps
CPU time 303.27 seconds
Started Dec 27 01:03:24 PM PST 23
Finished Dec 27 01:08:28 PM PST 23
Peak memory 199876 kb
Host smart-52b3398b-88ad-41af-a8f5-c2f617296c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87137026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.87137026
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1021142328
Short name T751
Test name
Test status
Simulation time 2421784345 ps
CPU time 2.65 seconds
Started Dec 27 01:03:16 PM PST 23
Finished Dec 27 01:03:24 PM PST 23
Peak memory 195624 kb
Host smart-a0cc6080-0a37-4f73-9edd-16f9bfd79e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021142328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1021142328
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1849938972
Short name T88
Test name
Test status
Simulation time 71458589 ps
CPU time 0.83 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:03:35 PM PST 23
Peak memory 217780 kb
Host smart-d4ad6d07-6865-4d5f-854c-1caeebfe83ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849938972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1849938972
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3157721148
Short name T556
Test name
Test status
Simulation time 5314504841 ps
CPU time 8.61 seconds
Started Dec 27 01:03:15 PM PST 23
Finished Dec 27 01:03:30 PM PST 23
Peak memory 199628 kb
Host smart-7b24e4b0-42dd-43a3-aa61-dcbb71f14317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157721148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3157721148
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3844252577
Short name T263
Test name
Test status
Simulation time 99866767572 ps
CPU time 816.58 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:17:20 PM PST 23
Peak memory 200164 kb
Host smart-815f4a15-9e10-4489-8274-b6628537c476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844252577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3844252577
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1205337156
Short name T347
Test name
Test status
Simulation time 123766328251 ps
CPU time 937.45 seconds
Started Dec 27 01:03:15 PM PST 23
Finished Dec 27 01:18:59 PM PST 23
Peak memory 226644 kb
Host smart-6438265e-7411-4b2f-8c88-6db8fe1c0568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205337156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1205337156
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3889786655
Short name T517
Test name
Test status
Simulation time 806853806 ps
CPU time 2.35 seconds
Started Dec 27 01:03:15 PM PST 23
Finished Dec 27 01:03:24 PM PST 23
Peak memory 197824 kb
Host smart-f8668e1c-12b7-4f9e-a0fa-d64efdecad62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889786655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3889786655
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.412028367
Short name T740
Test name
Test status
Simulation time 152665010828 ps
CPU time 44.28 seconds
Started Dec 27 01:03:16 PM PST 23
Finished Dec 27 01:04:06 PM PST 23
Peak memory 200232 kb
Host smart-477ffd76-1b0b-4004-ad2c-1360e9e3bdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412028367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.412028367
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.453722595
Short name T221
Test name
Test status
Simulation time 38764916241 ps
CPU time 59.28 seconds
Started Dec 27 01:03:35 PM PST 23
Finished Dec 27 01:04:36 PM PST 23
Peak memory 200160 kb
Host smart-a5b33834-f81e-4037-b504-fc4650a8140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453722595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.453722595
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3761429780
Short name T634
Test name
Test status
Simulation time 17324152313 ps
CPU time 32.8 seconds
Started Dec 27 01:03:30 PM PST 23
Finished Dec 27 01:04:04 PM PST 23
Peak memory 200136 kb
Host smart-1eff012b-290a-4528-9092-1b118827407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761429780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3761429780
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.504013905
Short name T670
Test name
Test status
Simulation time 55665848685 ps
CPU time 27.42 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:04:02 PM PST 23
Peak memory 200176 kb
Host smart-15c2b88f-4746-4178-b889-d58256126b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504013905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.504013905
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1022833588
Short name T928
Test name
Test status
Simulation time 669103831918 ps
CPU time 1206.83 seconds
Started Dec 27 01:03:35 PM PST 23
Finished Dec 27 01:23:44 PM PST 23
Peak memory 200164 kb
Host smart-fb271adb-4fd1-4ee5-8742-756ab9ba893c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022833588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1022833588
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2058072502
Short name T760
Test name
Test status
Simulation time 118168655717 ps
CPU time 264.82 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:08:19 PM PST 23
Peak memory 200160 kb
Host smart-de33566b-7c1b-4881-aec0-6661799492cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058072502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2058072502
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2719741945
Short name T599
Test name
Test status
Simulation time 2605804334 ps
CPU time 1.34 seconds
Started Dec 27 01:03:41 PM PST 23
Finished Dec 27 01:03:47 PM PST 23
Peak memory 195836 kb
Host smart-a61392a9-7961-432d-a64e-f4a41389809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719741945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2719741945
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1507817532
Short name T955
Test name
Test status
Simulation time 64496625814 ps
CPU time 25.91 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:04:00 PM PST 23
Peak memory 198212 kb
Host smart-8fa02ee4-6176-4d28-a834-ad6e526a8dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507817532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1507817532
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.781892890
Short name T807
Test name
Test status
Simulation time 3413417660 ps
CPU time 168.53 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:06:30 PM PST 23
Peak memory 200164 kb
Host smart-07fca605-d52c-49ed-87bf-cc585f843f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781892890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.781892890
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1442081700
Short name T1030
Test name
Test status
Simulation time 414498380683 ps
CPU time 32.54 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:04:06 PM PST 23
Peak memory 199636 kb
Host smart-8e49244a-5f54-4a9e-b5af-bdd03931b0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442081700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1442081700
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1910135631
Short name T590
Test name
Test status
Simulation time 45646940324 ps
CPU time 17.27 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:53 PM PST 23
Peak memory 195616 kb
Host smart-0df5b8e0-388d-4f64-b97f-3e48ce2dc573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910135631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1910135631
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2340484538
Short name T708
Test name
Test status
Simulation time 457818596 ps
CPU time 1.4 seconds
Started Dec 27 01:03:41 PM PST 23
Finished Dec 27 01:03:48 PM PST 23
Peak memory 198236 kb
Host smart-f7979587-5502-4d96-8bff-1f8ff68e9f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340484538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2340484538
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.838083888
Short name T1221
Test name
Test status
Simulation time 370513912975 ps
CPU time 983.63 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:19:56 PM PST 23
Peak memory 200196 kb
Host smart-8faffbd9-cc10-469e-bcf6-b1205e31851a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838083888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.838083888
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2107533257
Short name T1057
Test name
Test status
Simulation time 29463927094 ps
CPU time 231.06 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:07:32 PM PST 23
Peak memory 216012 kb
Host smart-7f542c52-1a4a-4b3e-8ebf-0d00ff4df423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107533257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2107533257
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1497901936
Short name T917
Test name
Test status
Simulation time 1061947135 ps
CPU time 1.44 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 198564 kb
Host smart-a5311942-d1de-42c3-b2d5-b0aa2df05d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497901936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1497901936
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1593666921
Short name T887
Test name
Test status
Simulation time 62730165970 ps
CPU time 144.92 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:06:01 PM PST 23
Peak memory 200192 kb
Host smart-b0ea5b1d-d5f9-4cc6-89f6-b5f5612dc0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593666921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1593666921
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1841539859
Short name T765
Test name
Test status
Simulation time 30826709817 ps
CPU time 12.14 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:05 PM PST 23
Peak memory 200216 kb
Host smart-63146318-2bde-409a-86ad-014fe34501e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841539859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1841539859
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.412843402
Short name T262
Test name
Test status
Simulation time 182126416898 ps
CPU time 294.04 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:10:44 PM PST 23
Peak memory 200192 kb
Host smart-b814ed58-cce2-4e20-9cce-f1caa8b7874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412843402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.412843402
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3031154227
Short name T1038
Test name
Test status
Simulation time 16244479424 ps
CPU time 27.85 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:20 PM PST 23
Peak memory 199312 kb
Host smart-90f1f9d1-7c6a-4d04-ae9f-857309718056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031154227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3031154227
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1563040708
Short name T801
Test name
Test status
Simulation time 24708214054 ps
CPU time 49.16 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:40 PM PST 23
Peak memory 200252 kb
Host smart-b0860c5f-3cf5-46e9-86f0-b797593e094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563040708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1563040708
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2856851890
Short name T396
Test name
Test status
Simulation time 81290210720 ps
CPU time 41.25 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:31 PM PST 23
Peak memory 200156 kb
Host smart-e0269a11-24f4-4da2-89b6-2f60d96316af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856851890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2856851890
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.114806655
Short name T548
Test name
Test status
Simulation time 29013118 ps
CPU time 0.55 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:36 PM PST 23
Peak memory 194708 kb
Host smart-b0930f97-3145-488c-a4c2-45ef1ea59c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114806655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.114806655
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1781900340
Short name T1152
Test name
Test status
Simulation time 121885371692 ps
CPU time 184.31 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:06:44 PM PST 23
Peak memory 200228 kb
Host smart-e2798f20-0c0f-4de4-8acf-c8e80175145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781900340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1781900340
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.627744093
Short name T383
Test name
Test status
Simulation time 91094027040 ps
CPU time 139.36 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:06:16 PM PST 23
Peak memory 200152 kb
Host smart-3fd587e6-bcb6-4d34-a690-a63af975a3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627744093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.627744093
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3850651378
Short name T1174
Test name
Test status
Simulation time 121056414498 ps
CPU time 52.65 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:04:25 PM PST 23
Peak memory 200072 kb
Host smart-09badd5f-0590-4a6f-b40f-07810b6956ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850651378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3850651378
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1913954448
Short name T966
Test name
Test status
Simulation time 141562810549 ps
CPU time 242.42 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:07:35 PM PST 23
Peak memory 199808 kb
Host smart-de62c993-6310-41cf-bf8e-e6b4e6ada835
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913954448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1913954448
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2637605549
Short name T925
Test name
Test status
Simulation time 103767888285 ps
CPU time 591.37 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:13:27 PM PST 23
Peak memory 200092 kb
Host smart-309c4f17-695f-441a-ab42-797fca64113d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637605549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2637605549
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1632628844
Short name T513
Test name
Test status
Simulation time 5363277451 ps
CPU time 12.4 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:48 PM PST 23
Peak memory 199216 kb
Host smart-d0eb952b-ae0d-4fd5-9ec5-2fa92ad5981a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632628844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1632628844
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3825910313
Short name T532
Test name
Test status
Simulation time 163950210505 ps
CPU time 76.33 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 208680 kb
Host smart-9e2011b2-b577-4d31-b01e-d47e57640612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825910313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3825910313
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1720731027
Short name T1155
Test name
Test status
Simulation time 10250893854 ps
CPU time 214.4 seconds
Started Dec 27 01:03:42 PM PST 23
Finished Dec 27 01:07:23 PM PST 23
Peak memory 200200 kb
Host smart-13ae43ab-84d9-4f69-b9ce-2f83ef9d5ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720731027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1720731027
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2947093910
Short name T859
Test name
Test status
Simulation time 3856809842 ps
CPU time 38.74 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:04:15 PM PST 23
Peak memory 199096 kb
Host smart-1da55bc4-af55-4c77-89b1-bf23ef6be4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2947093910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2947093910
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3414576522
Short name T685
Test name
Test status
Simulation time 41350946106 ps
CPU time 63.02 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:04:52 PM PST 23
Peak memory 200232 kb
Host smart-54ed8165-dc25-4bdf-b71c-7c7b72a9f502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414576522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3414576522
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2904265885
Short name T514
Test name
Test status
Simulation time 3361548018 ps
CPU time 2.02 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 195944 kb
Host smart-fb73ff34-1b10-4175-a8e7-103f1a5389ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904265885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2904265885
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1468930336
Short name T529
Test name
Test status
Simulation time 308118994 ps
CPU time 0.96 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:03:33 PM PST 23
Peak memory 198172 kb
Host smart-2ce3e8fd-614c-4e89-bcc6-baf5e71871d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468930336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1468930336
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3382624321
Short name T723
Test name
Test status
Simulation time 161466089837 ps
CPU time 672.9 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:14:46 PM PST 23
Peak memory 200516 kb
Host smart-e7a97cb6-71d8-4d24-9198-cf39ae79ea0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382624321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3382624321
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3264069982
Short name T808
Test name
Test status
Simulation time 1664371936 ps
CPU time 3.72 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:03:54 PM PST 23
Peak memory 198852 kb
Host smart-36e099a9-1449-463a-a728-23dadd95e551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264069982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3264069982
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2933407632
Short name T114
Test name
Test status
Simulation time 46498892808 ps
CPU time 16.42 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:51 PM PST 23
Peak memory 200096 kb
Host smart-9cc30688-69e2-4d0f-92aa-76446d5ad594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933407632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2933407632
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.708167425
Short name T138
Test name
Test status
Simulation time 45850665491 ps
CPU time 43.18 seconds
Started Dec 27 01:05:41 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 200256 kb
Host smart-f6bfb9e2-24a7-432c-b70c-0bf1eef0b1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708167425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.708167425
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2507694956
Short name T151
Test name
Test status
Simulation time 56366625437 ps
CPU time 26.33 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:21 PM PST 23
Peak memory 200212 kb
Host smart-b1560477-515b-4260-8195-9ab91d9c345f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507694956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2507694956
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2971802958
Short name T153
Test name
Test status
Simulation time 97161300920 ps
CPU time 72.6 seconds
Started Dec 27 01:05:47 PM PST 23
Finished Dec 27 01:07:01 PM PST 23
Peak memory 199976 kb
Host smart-de2be3e8-7623-4e0a-aa84-db009e79f388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971802958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2971802958
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.217706572
Short name T871
Test name
Test status
Simulation time 22037118568 ps
CPU time 43.68 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:34 PM PST 23
Peak memory 200212 kb
Host smart-986e827a-1ac2-49df-a52b-728541a31002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217706572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.217706572
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2342555932
Short name T1081
Test name
Test status
Simulation time 50884499614 ps
CPU time 24.35 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:14 PM PST 23
Peak memory 198640 kb
Host smart-a579b62c-3719-4646-a76e-b06a2a89d952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342555932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2342555932
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1642328261
Short name T83
Test name
Test status
Simulation time 23029120 ps
CPU time 0.56 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:03:37 PM PST 23
Peak memory 195644 kb
Host smart-dea9a61e-4cf5-4a85-9410-cedf44200c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642328261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1642328261
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1115914232
Short name T597
Test name
Test status
Simulation time 121116346603 ps
CPU time 147.03 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:06:03 PM PST 23
Peak memory 200192 kb
Host smart-27f07977-b12e-4ad8-baa9-b9ddf9ee2b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115914232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1115914232
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2776254088
Short name T398
Test name
Test status
Simulation time 168808934015 ps
CPU time 71.39 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:04:46 PM PST 23
Peak memory 199548 kb
Host smart-a0469ce1-2f98-441f-9567-c0bdb227008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776254088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2776254088
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.872127839
Short name T825
Test name
Test status
Simulation time 51129258503 ps
CPU time 40.64 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:04:16 PM PST 23
Peak memory 200164 kb
Host smart-5505b2de-acb2-44ab-9947-628fedacfccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872127839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.872127839
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.182939802
Short name T665
Test name
Test status
Simulation time 426760138271 ps
CPU time 1023.7 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:20:39 PM PST 23
Peak memory 199524 kb
Host smart-f7897c66-c75f-48f1-815c-8acbf75e4177
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182939802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.182939802
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.427421546
Short name T1125
Test name
Test status
Simulation time 129770064193 ps
CPU time 312.43 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:08:55 PM PST 23
Peak memory 200200 kb
Host smart-00e96def-8126-422b-a08b-b10ad0aecfd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427421546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.427421546
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.171890582
Short name T627
Test name
Test status
Simulation time 5212160135 ps
CPU time 2.41 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:44 PM PST 23
Peak memory 198444 kb
Host smart-07227fc4-49c8-4909-8f0e-8d3764bbcf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171890582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.171890582
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2482994263
Short name T995
Test name
Test status
Simulation time 211660788677 ps
CPU time 125.14 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:05:40 PM PST 23
Peak memory 200484 kb
Host smart-81e50db3-8d16-4df2-b158-bc4eb211dee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482994263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2482994263
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3916556255
Short name T558
Test name
Test status
Simulation time 9585769519 ps
CPU time 148.12 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:06:24 PM PST 23
Peak memory 200164 kb
Host smart-7473bced-3272-42b1-85d7-8228fe265e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916556255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3916556255
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1733953050
Short name T201
Test name
Test status
Simulation time 54800974149 ps
CPU time 72.94 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:05:01 PM PST 23
Peak memory 199980 kb
Host smart-9f3af937-2e2b-4454-89b8-6522f1748b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733953050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1733953050
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2020531837
Short name T1197
Test name
Test status
Simulation time 37355500346 ps
CPU time 43.58 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:04:19 PM PST 23
Peak memory 195844 kb
Host smart-2b681c67-f805-4d4a-83e4-9fe02501e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020531837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2020531837
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2626455364
Short name T533
Test name
Test status
Simulation time 704676993 ps
CPU time 2.13 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 198348 kb
Host smart-7039b203-6fc1-45b6-ad2d-82cfb5a3fe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626455364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2626455364
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3085405686
Short name T384
Test name
Test status
Simulation time 199534230361 ps
CPU time 98.28 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 200244 kb
Host smart-fd199b1f-f2cd-4bc5-ae73-279af3283736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085405686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3085405686
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1947197540
Short name T1206
Test name
Test status
Simulation time 186266307336 ps
CPU time 747.69 seconds
Started Dec 27 01:03:42 PM PST 23
Finished Dec 27 01:16:14 PM PST 23
Peak memory 225172 kb
Host smart-059bbae6-1982-4c1e-82c5-5a63c0920e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947197540 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1947197540
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3776900326
Short name T1135
Test name
Test status
Simulation time 1069820926 ps
CPU time 2.32 seconds
Started Dec 27 01:03:42 PM PST 23
Finished Dec 27 01:03:49 PM PST 23
Peak memory 198540 kb
Host smart-2690c460-04d0-4b8a-877c-4a970c9ab10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776900326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3776900326
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1567433771
Short name T931
Test name
Test status
Simulation time 41569845643 ps
CPU time 71.73 seconds
Started Dec 27 01:03:35 PM PST 23
Finished Dec 27 01:04:49 PM PST 23
Peak memory 200224 kb
Host smart-321d7d3b-504c-4bf5-9821-9cf527b750aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567433771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1567433771
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.793180480
Short name T794
Test name
Test status
Simulation time 95269856068 ps
CPU time 73.95 seconds
Started Dec 27 01:05:46 PM PST 23
Finished Dec 27 01:07:02 PM PST 23
Peak memory 200160 kb
Host smart-477d4c01-b00d-4179-8543-707ee9a9bbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793180480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.793180480
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1613968890
Short name T706
Test name
Test status
Simulation time 19081513198 ps
CPU time 20.07 seconds
Started Dec 27 01:05:54 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 200228 kb
Host smart-82b63019-049b-4a77-8303-45345ead4dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613968890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1613968890
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2037674704
Short name T308
Test name
Test status
Simulation time 22351316624 ps
CPU time 16.91 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:09 PM PST 23
Peak memory 200112 kb
Host smart-a35afcd4-ece1-44e5-a7dc-9ab1a3af1bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037674704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2037674704
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1130959484
Short name T1037
Test name
Test status
Simulation time 208321217222 ps
CPU time 78.75 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:07:10 PM PST 23
Peak memory 200152 kb
Host smart-cad65204-8e4e-4b25-9145-fe7f6cbb3826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130959484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1130959484
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3264691906
Short name T541
Test name
Test status
Simulation time 12951151 ps
CPU time 0.56 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 195660 kb
Host smart-3ba76561-bef2-42bb-a9d5-ff96dc3fa0ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264691906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3264691906
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.741106913
Short name T454
Test name
Test status
Simulation time 153493176363 ps
CPU time 105.46 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 200136 kb
Host smart-e23757a8-d206-4bd3-bbb0-1eebd159402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741106913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.741106913
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.378789726
Short name T343
Test name
Test status
Simulation time 40056572559 ps
CPU time 78.44 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:05:01 PM PST 23
Peak memory 199776 kb
Host smart-84bf1876-8dd7-4a1c-9941-1fa42f9269b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378789726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.378789726
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3617651614
Short name T946
Test name
Test status
Simulation time 125033441012 ps
CPU time 813.21 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:17:17 PM PST 23
Peak memory 200172 kb
Host smart-6c6383f6-a4f1-48f0-9624-610b13694fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3617651614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3617651614
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_noise_filter.602697151
Short name T561
Test name
Test status
Simulation time 109560225854 ps
CPU time 41.15 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:04:23 PM PST 23
Peak memory 199476 kb
Host smart-2db38ac0-1e75-4d49-9fe6-9bdb88ac5673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602697151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.602697151
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.4275378159
Short name T1098
Test name
Test status
Simulation time 13600473009 ps
CPU time 369.94 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:09:52 PM PST 23
Peak memory 200176 kb
Host smart-b837024e-7c27-446f-8702-bedcb4eefaf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275378159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4275378159
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.844346720
Short name T945
Test name
Test status
Simulation time 198517215540 ps
CPU time 311.68 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:08:57 PM PST 23
Peak memory 200260 kb
Host smart-d790dfe4-837a-4894-83d4-661bcdfaa61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844346720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.844346720
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.388261770
Short name T449
Test name
Test status
Simulation time 48186563158 ps
CPU time 23.06 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:04:05 PM PST 23
Peak memory 195672 kb
Host smart-ec826d03-cb18-4255-8851-d2f23b925f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388261770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.388261770
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2830986532
Short name T545
Test name
Test status
Simulation time 266950068 ps
CPU time 1.47 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:03:56 PM PST 23
Peak memory 198524 kb
Host smart-72ef4d74-1ed1-4629-9b0d-b43e192be658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830986532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2830986532
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.911025995
Short name T1111
Test name
Test status
Simulation time 181703226827 ps
CPU time 260.08 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:08:00 PM PST 23
Peak memory 200220 kb
Host smart-26edbf8d-a2e8-4d99-b8d2-9256e7dcb841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911025995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.911025995
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2160516387
Short name T797
Test name
Test status
Simulation time 30679183702 ps
CPU time 639.9 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:14:39 PM PST 23
Peak memory 216056 kb
Host smart-064fd560-5392-4ede-b6ac-1ea08e84285e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160516387 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2160516387
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1454061914
Short name T957
Test name
Test status
Simulation time 948432321 ps
CPU time 1.79 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 198176 kb
Host smart-d99d6802-ecc7-430a-b367-d2aabd1ab202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454061914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1454061914
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2170169982
Short name T191
Test name
Test status
Simulation time 38114734462 ps
CPU time 31.46 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:25 PM PST 23
Peak memory 199716 kb
Host smart-55288301-c8a0-446c-9e9b-9d26da1536c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170169982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2170169982
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.110824015
Short name T121
Test name
Test status
Simulation time 20415431247 ps
CPU time 35.82 seconds
Started Dec 27 01:05:47 PM PST 23
Finished Dec 27 01:06:24 PM PST 23
Peak memory 200188 kb
Host smart-58a67f2c-7213-44a0-a2f2-6c72d15eb230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110824015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.110824015
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2918818252
Short name T731
Test name
Test status
Simulation time 109981679841 ps
CPU time 181.75 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:08:52 PM PST 23
Peak memory 199964 kb
Host smart-94c36d7d-03b4-4bcb-9fbd-8420340dec54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918818252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2918818252
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1683906140
Short name T804
Test name
Test status
Simulation time 41702040678 ps
CPU time 16.69 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:06:15 PM PST 23
Peak memory 199576 kb
Host smart-b6ca23a1-a689-4f4f-a600-f1f9e68019da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683906140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1683906140
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.491235646
Short name T989
Test name
Test status
Simulation time 17263816306 ps
CPU time 30.87 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:28 PM PST 23
Peak memory 200104 kb
Host smart-b3d0fb88-1cf7-4f62-967a-7513a7429f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491235646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.491235646
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3032348739
Short name T468
Test name
Test status
Simulation time 28926428236 ps
CPU time 23.41 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:17 PM PST 23
Peak memory 199904 kb
Host smart-59dbc322-197b-407a-9568-163e1e96aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032348739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3032348739
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2453390889
Short name T741
Test name
Test status
Simulation time 94584080555 ps
CPU time 38.88 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:32 PM PST 23
Peak memory 200216 kb
Host smart-d8d69318-797a-4582-8b9c-bee1a81da120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453390889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2453390889
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.913194011
Short name T681
Test name
Test status
Simulation time 22702205 ps
CPU time 0.58 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 195672 kb
Host smart-c84f8e8e-ef8b-4647-b048-88b2a876561d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913194011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.913194011
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2897059141
Short name T418
Test name
Test status
Simulation time 131467645015 ps
CPU time 192.8 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:06:55 PM PST 23
Peak memory 199896 kb
Host smart-3bf08e7f-7fb8-44f7-9d75-398debdea17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897059141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2897059141
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2876583162
Short name T1165
Test name
Test status
Simulation time 168113844041 ps
CPU time 66.56 seconds
Started Dec 27 01:03:41 PM PST 23
Finished Dec 27 01:04:53 PM PST 23
Peak memory 200104 kb
Host smart-5f6f7667-d9fa-4e18-a34f-5894fa94dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876583162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2876583162
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.3048689513
Short name T431
Test name
Test status
Simulation time 587921409601 ps
CPU time 524.59 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:12:20 PM PST 23
Peak memory 200132 kb
Host smart-7a39c7d1-efab-4e79-b2d7-df70ae076ec7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048689513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3048689513
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1471629195
Short name T852
Test name
Test status
Simulation time 45916690024 ps
CPU time 268.46 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:08:18 PM PST 23
Peak memory 200208 kb
Host smart-df716073-52d7-46d6-9428-e097ec29b3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1471629195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1471629195
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.231300867
Short name T703
Test name
Test status
Simulation time 4058204644 ps
CPU time 2.58 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 195832 kb
Host smart-8b532750-70d8-41ef-aef1-1e27a889fec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231300867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.231300867
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.93407307
Short name T1218
Test name
Test status
Simulation time 66243451288 ps
CPU time 126.96 seconds
Started Dec 27 01:03:44 PM PST 23
Finished Dec 27 01:05:57 PM PST 23
Peak memory 198888 kb
Host smart-27579558-d1e8-41eb-9065-8d447e1e301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93407307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.93407307
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1248253148
Short name T1202
Test name
Test status
Simulation time 8290939075 ps
CPU time 464.05 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:11:44 PM PST 23
Peak memory 200136 kb
Host smart-1d4eed82-e057-4fbf-9ba7-db8841a3ec07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248253148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1248253148
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3144957623
Short name T181
Test name
Test status
Simulation time 97154975624 ps
CPU time 60.64 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:44 PM PST 23
Peak memory 200212 kb
Host smart-8ba87683-e4e2-4dcd-90d7-2e296ae6b677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144957623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3144957623
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.885233897
Short name T961
Test name
Test status
Simulation time 30054198603 ps
CPU time 51.76 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:04:27 PM PST 23
Peak memory 196104 kb
Host smart-f1401925-041a-4b1a-9dea-5ad012290b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885233897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.885233897
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2231866369
Short name T745
Test name
Test status
Simulation time 726998121 ps
CPU time 1.6 seconds
Started Dec 27 01:03:51 PM PST 23
Finished Dec 27 01:04:03 PM PST 23
Peak memory 198572 kb
Host smart-baf79cb9-c77c-43f5-a1ec-6437966e9777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231866369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2231866369
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3758931872
Short name T130
Test name
Test status
Simulation time 162720733610 ps
CPU time 1449.37 seconds
Started Dec 27 01:03:44 PM PST 23
Finished Dec 27 01:27:59 PM PST 23
Peak memory 216864 kb
Host smart-c3415e0b-7d10-4c7f-ac9d-147e5aa07818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758931872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3758931872
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3522758490
Short name T1220
Test name
Test status
Simulation time 29606512466 ps
CPU time 259.76 seconds
Started Dec 27 01:03:48 PM PST 23
Finished Dec 27 01:08:16 PM PST 23
Peak memory 212328 kb
Host smart-c10b51d3-642c-45ee-bd83-2fbbe7e6df16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522758490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3522758490
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2255124572
Short name T653
Test name
Test status
Simulation time 6842269417 ps
CPU time 22.79 seconds
Started Dec 27 01:03:35 PM PST 23
Finished Dec 27 01:04:00 PM PST 23
Peak memory 199048 kb
Host smart-d1b08583-2c9f-476d-954d-3372e020ee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255124572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2255124572
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2297386700
Short name T950
Test name
Test status
Simulation time 62181161666 ps
CPU time 13.72 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:03 PM PST 23
Peak memory 199824 kb
Host smart-e1c5bcae-ba7d-4ccf-a6e5-650486fd1780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297386700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2297386700
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2993672250
Short name T317
Test name
Test status
Simulation time 9383027011 ps
CPU time 16.57 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:06 PM PST 23
Peak memory 199928 kb
Host smart-7de1fb7d-05e5-47e0-a2a5-457e92c3b00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993672250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2993672250
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2876138960
Short name T185
Test name
Test status
Simulation time 12026927932 ps
CPU time 10.32 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:01 PM PST 23
Peak memory 200240 kb
Host smart-c0094300-620e-4913-9114-05975714ed6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876138960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2876138960
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1507043689
Short name T738
Test name
Test status
Simulation time 81002357547 ps
CPU time 31.13 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:23 PM PST 23
Peak memory 200124 kb
Host smart-ef3b0430-f0e2-4d70-97ba-f44660c6005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507043689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1507043689
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1205347176
Short name T397
Test name
Test status
Simulation time 61043525212 ps
CPU time 21.08 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:17 PM PST 23
Peak memory 200164 kb
Host smart-8fe9435a-bd32-4d62-a7c2-679af424623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205347176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1205347176
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3461726108
Short name T318
Test name
Test status
Simulation time 12193359750 ps
CPU time 20.36 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:10 PM PST 23
Peak memory 199916 kb
Host smart-a429c229-5ddc-40ee-bc10-3f8c5bbb97f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461726108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3461726108
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2088935547
Short name T840
Test name
Test status
Simulation time 21748962328 ps
CPU time 37.56 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:35 PM PST 23
Peak memory 199128 kb
Host smart-964657bf-aee2-47bb-a559-a516418d7adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088935547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2088935547
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2551007158
Short name T701
Test name
Test status
Simulation time 15317649 ps
CPU time 0.55 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:42 PM PST 23
Peak memory 194556 kb
Host smart-7dacdec9-d27e-4ce3-95dd-2dcf6dbc9850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551007158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2551007158
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1784226262
Short name T577
Test name
Test status
Simulation time 62517066701 ps
CPU time 103.68 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:05:33 PM PST 23
Peak memory 200180 kb
Host smart-822c201e-c732-4e99-97da-81c7a9a8753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784226262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1784226262
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1451650035
Short name T235
Test name
Test status
Simulation time 88465334094 ps
CPU time 22.15 seconds
Started Dec 27 01:03:44 PM PST 23
Finished Dec 27 01:04:12 PM PST 23
Peak memory 199632 kb
Host smart-6e4d8ba2-142b-4bbe-9739-72740c22b115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451650035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1451650035
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1972801567
Short name T833
Test name
Test status
Simulation time 29814792810 ps
CPU time 3.27 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 197144 kb
Host smart-4d633484-78f1-43c2-93f3-2d6b2d262a89
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972801567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1972801567
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.116323915
Short name T576
Test name
Test status
Simulation time 139493293810 ps
CPU time 346.42 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:09:29 PM PST 23
Peak memory 200256 kb
Host smart-02c5d29e-00cc-4d70-8891-3021bf2032ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116323915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.116323915
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3904332415
Short name T998
Test name
Test status
Simulation time 5920140840 ps
CPU time 13.24 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:03:56 PM PST 23
Peak memory 199224 kb
Host smart-8c2fd48a-9e51-42cd-96a6-7056f6d02c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904332415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3904332415
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3176433285
Short name T960
Test name
Test status
Simulation time 129093912123 ps
CPU time 263.02 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:08:05 PM PST 23
Peak memory 208732 kb
Host smart-c6008a62-0424-49bd-bc9c-38d334be6f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176433285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3176433285
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3990332272
Short name T787
Test name
Test status
Simulation time 11441370140 ps
CPU time 597.82 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:13:40 PM PST 23
Peak memory 200132 kb
Host smart-c9e39bf8-8e7a-40cb-95bb-e0ddc85bbbb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990332272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3990332272
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.804041864
Short name T1004
Test name
Test status
Simulation time 2878280518 ps
CPU time 16.93 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:03:58 PM PST 23
Peak memory 198728 kb
Host smart-45397a91-af2d-4753-8de3-7c175d16f5b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804041864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.804041864
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1697855668
Short name T296
Test name
Test status
Simulation time 318021661268 ps
CPU time 90.06 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:05:12 PM PST 23
Peak memory 200112 kb
Host smart-792b8c0d-4068-4463-b0d4-a325b52d3918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697855668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1697855668
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3789194542
Short name T515
Test name
Test status
Simulation time 5696940896 ps
CPU time 2.64 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:03:46 PM PST 23
Peak memory 196040 kb
Host smart-c8fd05e0-6b09-4ec9-b1e7-b8b5e3ff61ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789194542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3789194542
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2448654579
Short name T791
Test name
Test status
Simulation time 5814023616 ps
CPU time 20.8 seconds
Started Dec 27 01:03:44 PM PST 23
Finished Dec 27 01:04:10 PM PST 23
Peak memory 200176 kb
Host smart-74c73e92-0597-4133-a13d-ef022a11c881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448654579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2448654579
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2811025245
Short name T929
Test name
Test status
Simulation time 3176738181185 ps
CPU time 1426.44 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:27:28 PM PST 23
Peak memory 200204 kb
Host smart-3d5fb39a-da70-481f-be53-374244d94542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811025245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2811025245
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.785146786
Short name T357
Test name
Test status
Simulation time 66407806228 ps
CPU time 1167.43 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:23:24 PM PST 23
Peak memory 225124 kb
Host smart-5a8d880e-ef2a-4c36-991c-943dc106a1b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785146786 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.785146786
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3132566625
Short name T659
Test name
Test status
Simulation time 706652085 ps
CPU time 1.39 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:03:56 PM PST 23
Peak memory 197804 kb
Host smart-55cb7d37-71d9-4e4f-8bba-61a810b879da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132566625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3132566625
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3762657342
Short name T622
Test name
Test status
Simulation time 32595661982 ps
CPU time 14.44 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:03:59 PM PST 23
Peak memory 200180 kb
Host smart-b56e1471-8adc-484a-b590-fb37bcefac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762657342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3762657342
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1514325174
Short name T180
Test name
Test status
Simulation time 297016912877 ps
CPU time 26.52 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:19 PM PST 23
Peak memory 200016 kb
Host smart-791e047d-d9cf-4db6-a683-335f4d3ed06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514325174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1514325174
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.167218066
Short name T1003
Test name
Test status
Simulation time 66586167798 ps
CPU time 11.05 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:06 PM PST 23
Peak memory 199872 kb
Host smart-e1f63e39-219d-40e0-be24-c86e1f14dbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167218066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.167218066
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1211461043
Short name T149
Test name
Test status
Simulation time 206987583044 ps
CPU time 208.27 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:09:23 PM PST 23
Peak memory 200180 kb
Host smart-c63d4e43-c66f-4ad1-bde5-050f50f44155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211461043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1211461043
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.409994002
Short name T907
Test name
Test status
Simulation time 28392112639 ps
CPU time 40.62 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:06:30 PM PST 23
Peak memory 200248 kb
Host smart-ff5ee77d-9619-4a2a-a2b9-c06a864647fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409994002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.409994002
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3588878919
Short name T437
Test name
Test status
Simulation time 145472888341 ps
CPU time 47.64 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:41 PM PST 23
Peak memory 200152 kb
Host smart-8520d50d-9cc4-4d8f-b31a-ba4f9726b9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588878919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3588878919
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4255468250
Short name T1156
Test name
Test status
Simulation time 182959094469 ps
CPU time 109.35 seconds
Started Dec 27 01:05:47 PM PST 23
Finished Dec 27 01:07:38 PM PST 23
Peak memory 200236 kb
Host smart-d0875aea-ad47-4f35-9af2-1f05a3c3fdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255468250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4255468250
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2817700834
Short name T12
Test name
Test status
Simulation time 22468191 ps
CPU time 0.53 seconds
Started Dec 27 01:03:54 PM PST 23
Finished Dec 27 01:04:02 PM PST 23
Peak memory 194620 kb
Host smart-2fcd6c61-d0ef-4ef7-90fd-ce63d09dbc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817700834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2817700834
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.889660932
Short name T553
Test name
Test status
Simulation time 286399763067 ps
CPU time 28.12 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:04:10 PM PST 23
Peak memory 199972 kb
Host smart-fa45ab51-9e84-454c-82ff-1d5b26a59b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889660932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.889660932
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3305268984
Short name T624
Test name
Test status
Simulation time 63945410397 ps
CPU time 91.61 seconds
Started Dec 27 01:03:48 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 200188 kb
Host smart-eaedbca9-f07b-4522-aef4-6c2ffbc6ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305268984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3305268984
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1535274288
Short name T773
Test name
Test status
Simulation time 64367845104 ps
CPU time 191.9 seconds
Started Dec 27 01:03:42 PM PST 23
Finished Dec 27 01:06:58 PM PST 23
Peak memory 200188 kb
Host smart-2c0c2268-d15a-421e-8f07-f557f06c8ea3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535274288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1535274288
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.776023572
Short name T894
Test name
Test status
Simulation time 154576413997 ps
CPU time 432.09 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:11:09 PM PST 23
Peak memory 200232 kb
Host smart-d845993f-fd52-4d34-bce5-f4ae5aeb7369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776023572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.776023572
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1519965221
Short name T1116
Test name
Test status
Simulation time 2995342131 ps
CPU time 5.29 seconds
Started Dec 27 01:03:48 PM PST 23
Finished Dec 27 01:04:02 PM PST 23
Peak memory 197200 kb
Host smart-1bfd7df0-6b5c-484c-9c7b-84c7516c4d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519965221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1519965221
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1073967276
Short name T1129
Test name
Test status
Simulation time 48077743405 ps
CPU time 23.03 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:04:08 PM PST 23
Peak memory 198496 kb
Host smart-57380353-858c-4ff9-b92c-21b67c8aef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073967276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1073967276
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2902605399
Short name T689
Test name
Test status
Simulation time 12783476092 ps
CPU time 170.83 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:06:32 PM PST 23
Peak memory 200212 kb
Host smart-6f753bf2-fa2f-4e6c-9965-fe197c33af90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902605399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2902605399
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3922211352
Short name T809
Test name
Test status
Simulation time 4780530718 ps
CPU time 43.05 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:04:32 PM PST 23
Peak memory 199076 kb
Host smart-8c88ede7-a2e0-4d48-b434-d5bdf873f250
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922211352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3922211352
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3106921888
Short name T858
Test name
Test status
Simulation time 45299998247 ps
CPU time 75.26 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:05:15 PM PST 23
Peak memory 199820 kb
Host smart-81cfbb35-03e4-4be8-a780-da48422f7d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106921888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3106921888
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2222085666
Short name T1103
Test name
Test status
Simulation time 3379794892 ps
CPU time 1.23 seconds
Started Dec 27 01:03:45 PM PST 23
Finished Dec 27 01:03:51 PM PST 23
Peak memory 195936 kb
Host smart-e4b8f4e0-b7f1-4a70-b87f-73554eeb4a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222085666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2222085666
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3440671763
Short name T1045
Test name
Test status
Simulation time 6084615620 ps
CPU time 19.77 seconds
Started Dec 27 01:03:45 PM PST 23
Finished Dec 27 01:04:10 PM PST 23
Peak memory 199764 kb
Host smart-01e7edc9-ee01-4e4a-8055-7999a26cbaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440671763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3440671763
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1427987017
Short name T1084
Test name
Test status
Simulation time 390718505378 ps
CPU time 176.67 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:06:42 PM PST 23
Peak memory 200260 kb
Host smart-7ec00991-7681-4fc5-9300-d8453b94e6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427987017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1427987017
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1508734493
Short name T1072
Test name
Test status
Simulation time 93710494107 ps
CPU time 422.16 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:10:45 PM PST 23
Peak memory 210208 kb
Host smart-69fc4560-ff12-4fc5-a78b-f2cd0b8fc684
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508734493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1508734493
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3352165176
Short name T525
Test name
Test status
Simulation time 680405944 ps
CPU time 1.54 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:03:41 PM PST 23
Peak memory 200088 kb
Host smart-071076c5-f98c-43d3-a4b7-39fe7473cca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352165176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3352165176
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.444736333
Short name T827
Test name
Test status
Simulation time 23258490008 ps
CPU time 19.98 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:04:02 PM PST 23
Peak memory 199732 kb
Host smart-97addd39-22c5-4199-b070-3e214ac808c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444736333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.444736333
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3944274637
Short name T248
Test name
Test status
Simulation time 109570214173 ps
CPU time 29.53 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:20 PM PST 23
Peak memory 200192 kb
Host smart-4dfdbbcc-e1b3-466a-889e-0ae1adefb793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944274637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3944274637
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1821455447
Short name T435
Test name
Test status
Simulation time 61526433012 ps
CPU time 58.14 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:50 PM PST 23
Peak memory 200220 kb
Host smart-a057b218-2d68-4c83-83e0-f8b757b0453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821455447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1821455447
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.141220370
Short name T182
Test name
Test status
Simulation time 43163842814 ps
CPU time 24.79 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 200196 kb
Host smart-42327541-74c9-4af0-9340-91c851955453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141220370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.141220370
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4014410993
Short name T1160
Test name
Test status
Simulation time 83403672567 ps
CPU time 25.31 seconds
Started Dec 27 01:05:47 PM PST 23
Finished Dec 27 01:06:14 PM PST 23
Peak memory 198436 kb
Host smart-ece0f220-2244-4846-ad37-4f272c1c7ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014410993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4014410993
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2798461262
Short name T800
Test name
Test status
Simulation time 25908085286 ps
CPU time 44.21 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:39 PM PST 23
Peak memory 200252 kb
Host smart-30d9f475-6dfa-4225-b904-4614901acb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798461262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2798461262
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1733635404
Short name T743
Test name
Test status
Simulation time 41067426799 ps
CPU time 32.63 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:28 PM PST 23
Peak memory 198228 kb
Host smart-bd4c072c-74b2-4358-b3e8-d51cf44a9f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733635404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1733635404
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3008857745
Short name T304
Test name
Test status
Simulation time 68052834877 ps
CPU time 29.45 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 200152 kb
Host smart-47c95906-b7ec-4aed-a165-220dfd7c714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008857745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3008857745
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1829813299
Short name T85
Test name
Test status
Simulation time 60876940 ps
CPU time 0.56 seconds
Started Dec 27 01:03:41 PM PST 23
Finished Dec 27 01:03:46 PM PST 23
Peak memory 195592 kb
Host smart-9297adbf-4d5f-4f32-a711-339aa4ff6152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829813299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1829813299
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3878761413
Short name T1225
Test name
Test status
Simulation time 94691854403 ps
CPU time 38.4 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:04:27 PM PST 23
Peak memory 200248 kb
Host smart-1013433a-a357-480e-a005-dd71619b222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878761413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3878761413
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3294257661
Short name T644
Test name
Test status
Simulation time 37149277351 ps
CPU time 16.61 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:04:07 PM PST 23
Peak memory 200184 kb
Host smart-22ef39ef-fae0-4291-acbb-a6a35fb04b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294257661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3294257661
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2276980872
Short name T1193
Test name
Test status
Simulation time 35020171853 ps
CPU time 65.37 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:04:51 PM PST 23
Peak memory 200184 kb
Host smart-f126a494-965e-4115-abb6-cc63f4254f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276980872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2276980872
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2486450972
Short name T968
Test name
Test status
Simulation time 535265015124 ps
CPU time 222.3 seconds
Started Dec 27 01:03:41 PM PST 23
Finished Dec 27 01:07:29 PM PST 23
Peak memory 200084 kb
Host smart-689a5b49-1fc1-4e49-8a63-30e3c2003fd4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486450972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2486450972
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2513633199
Short name T534
Test name
Test status
Simulation time 17865009662 ps
CPU time 29.6 seconds
Started Dec 27 01:04:00 PM PST 23
Finished Dec 27 01:04:37 PM PST 23
Peak memory 198180 kb
Host smart-150cc07a-7ded-47cb-8014-d42cbbba2a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513633199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2513633199
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3053145555
Short name T421
Test name
Test status
Simulation time 18892540896 ps
CPU time 266.54 seconds
Started Dec 27 01:03:54 PM PST 23
Finished Dec 27 01:08:28 PM PST 23
Peak memory 200184 kb
Host smart-34c902e6-c4ca-4187-859f-09a445f4128c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053145555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3053145555
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.418110011
Short name T1027
Test name
Test status
Simulation time 61717599104 ps
CPU time 17.6 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:04:14 PM PST 23
Peak memory 199696 kb
Host smart-7d579d92-22f4-4237-b18c-273f3658bbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418110011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.418110011
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3421287909
Short name T434
Test name
Test status
Simulation time 4581799448 ps
CPU time 2.21 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:03:47 PM PST 23
Peak memory 196012 kb
Host smart-e08d4d18-11c9-456c-9a3f-1691f5364003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421287909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3421287909
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.642649616
Short name T865
Test name
Test status
Simulation time 5907833637 ps
CPU time 16.41 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:03:59 PM PST 23
Peak memory 199828 kb
Host smart-cb4eeee5-e2fd-47f4-aab3-cd64b9b0d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642649616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.642649616
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2125468482
Short name T1144
Test name
Test status
Simulation time 424835106718 ps
CPU time 174.04 seconds
Started Dec 27 01:03:58 PM PST 23
Finished Dec 27 01:07:00 PM PST 23
Peak memory 200440 kb
Host smart-b83105b7-0340-48bf-881c-c59c71c6773a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125468482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2125468482
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.28931108
Short name T387
Test name
Test status
Simulation time 606364525588 ps
CPU time 621.71 seconds
Started Dec 27 01:03:56 PM PST 23
Finished Dec 27 01:14:25 PM PST 23
Peak memory 225088 kb
Host smart-6ce31043-ca3d-4500-862b-b919a00c1e4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28931108 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.28931108
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1627872514
Short name T668
Test name
Test status
Simulation time 2241580250 ps
CPU time 1.88 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:03:53 PM PST 23
Peak memory 198296 kb
Host smart-a405b87e-8078-4475-a403-1b00b7b94177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627872514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1627872514
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3873556298
Short name T17
Test name
Test status
Simulation time 1324199034 ps
CPU time 1.75 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:03:58 PM PST 23
Peak memory 196992 kb
Host smart-086b2956-e553-4a6b-9052-469acec9da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873556298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3873556298
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3969620343
Short name T238
Test name
Test status
Simulation time 26165140651 ps
CPU time 29.63 seconds
Started Dec 27 01:05:58 PM PST 23
Finished Dec 27 01:06:30 PM PST 23
Peak memory 200208 kb
Host smart-1e7b1588-9536-446a-a662-63f79ca9f559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969620343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3969620343
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.634861143
Short name T844
Test name
Test status
Simulation time 10345982257 ps
CPU time 17.72 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:11 PM PST 23
Peak memory 200156 kb
Host smart-ac2dfb04-27a2-4d39-bac9-9b43f33fba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634861143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.634861143
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.497742360
Short name T958
Test name
Test status
Simulation time 8733660798 ps
CPU time 14.51 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:08 PM PST 23
Peak memory 200104 kb
Host smart-9616abd9-31b8-4154-bd70-923fcf3d1d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497742360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.497742360
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1327505135
Short name T271
Test name
Test status
Simulation time 154355744652 ps
CPU time 40.56 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:33 PM PST 23
Peak memory 200196 kb
Host smart-efc87c86-0ed6-4068-b8c4-87d3a916d91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327505135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1327505135
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1671296472
Short name T148
Test name
Test status
Simulation time 18121899902 ps
CPU time 12.19 seconds
Started Dec 27 01:05:56 PM PST 23
Finished Dec 27 01:06:11 PM PST 23
Peak memory 200088 kb
Host smart-b562acaa-4b3c-4180-a9a6-3200141c40b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671296472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1671296472
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.366652611
Short name T1157
Test name
Test status
Simulation time 29132807686 ps
CPU time 22.11 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:19 PM PST 23
Peak memory 200088 kb
Host smart-3a7c33c8-5e64-4db7-8270-1e1a1910aa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366652611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.366652611
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.665861377
Short name T313
Test name
Test status
Simulation time 17234343748 ps
CPU time 25.57 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:06:24 PM PST 23
Peak memory 200056 kb
Host smart-660c8a6c-a531-454e-b1ed-3bf3e8521df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665861377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.665861377
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2439014911
Short name T322
Test name
Test status
Simulation time 80383982122 ps
CPU time 89.25 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:07:26 PM PST 23
Peak memory 200260 kb
Host smart-b25ba752-419f-4063-a31c-38ba8c9c4863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439014911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2439014911
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3641106121
Short name T242
Test name
Test status
Simulation time 56435396471 ps
CPU time 44.6 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:41 PM PST 23
Peak memory 200208 kb
Host smart-4eb599e9-c86c-443e-8c01-074c4d1746ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641106121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3641106121
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1339326253
Short name T766
Test name
Test status
Simulation time 31521922 ps
CPU time 0.55 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:03:57 PM PST 23
Peak memory 194300 kb
Host smart-af87243a-7d29-405d-992c-141d28db6e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339326253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1339326253
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.865247912
Short name T875
Test name
Test status
Simulation time 80954524396 ps
CPU time 34.53 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:04:31 PM PST 23
Peak memory 199960 kb
Host smart-67a5532e-86fe-41a6-98e3-b8edacb87bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865247912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.865247912
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.723530646
Short name T264
Test name
Test status
Simulation time 20035422385 ps
CPU time 16.01 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:04:13 PM PST 23
Peak memory 200104 kb
Host smart-955fb13d-50a5-4981-a4b2-bc6849551986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723530646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.723530646
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1649884767
Short name T639
Test name
Test status
Simulation time 38837319544 ps
CPU time 26.04 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:04:23 PM PST 23
Peak memory 200076 kb
Host smart-fb87ae1d-4150-4cd9-8d4f-cd0d39ed1844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649884767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1649884767
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1648648537
Short name T1148
Test name
Test status
Simulation time 96559258026 ps
CPU time 486.9 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:12:04 PM PST 23
Peak memory 200208 kb
Host smart-a9357c71-c468-4209-90ba-42f3bcb1a0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648648537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1648648537
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.749976844
Short name T528
Test name
Test status
Simulation time 3286186447 ps
CPU time 11.35 seconds
Started Dec 27 01:03:51 PM PST 23
Finished Dec 27 01:04:13 PM PST 23
Peak memory 199172 kb
Host smart-f2252e70-8128-4c22-9b46-ce56d0fc7d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749976844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.749976844
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.4207727417
Short name T610
Test name
Test status
Simulation time 18379195781 ps
CPU time 13.2 seconds
Started Dec 27 01:03:53 PM PST 23
Finished Dec 27 01:04:15 PM PST 23
Peak memory 194952 kb
Host smart-5a44c501-54aa-4bfd-a2ff-7c91a418ddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207727417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.4207727417
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3158403625
Short name T174
Test name
Test status
Simulation time 26011162628 ps
CPU time 209.64 seconds
Started Dec 27 01:03:54 PM PST 23
Finished Dec 27 01:07:32 PM PST 23
Peak memory 200188 kb
Host smart-d2fec045-b139-4109-ae4f-b6f4fe4efed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158403625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3158403625
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3461658718
Short name T566
Test name
Test status
Simulation time 147980993020 ps
CPU time 212.55 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:07:23 PM PST 23
Peak memory 200116 kb
Host smart-82bf9a6b-f8c3-422e-bbdd-ef4366d348b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461658718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3461658718
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1687932831
Short name T586
Test name
Test status
Simulation time 1625741634 ps
CPU time 1.2 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:03:57 PM PST 23
Peak memory 195668 kb
Host smart-abe3b3d9-00da-4533-9bd9-ef86f2646971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687932831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1687932831
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2253355592
Short name T573
Test name
Test status
Simulation time 539589959 ps
CPU time 1.15 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:03:57 PM PST 23
Peak memory 198440 kb
Host smart-e9b44d6d-35a8-44ff-bf74-eeb2df741f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253355592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2253355592
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3930910131
Short name T1073
Test name
Test status
Simulation time 150377422098 ps
CPU time 269.39 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:08:27 PM PST 23
Peak memory 216592 kb
Host smart-5fbfd69f-060e-4113-b6cb-8f23a8e2d0ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930910131 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3930910131
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2412038743
Short name T440
Test name
Test status
Simulation time 1811999134 ps
CPU time 1.8 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:03:59 PM PST 23
Peak memory 198200 kb
Host smart-b914b8ba-aa6d-4eab-8558-a815912372f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412038743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2412038743
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3164971484
Short name T1179
Test name
Test status
Simulation time 51302593948 ps
CPU time 94.51 seconds
Started Dec 27 01:03:42 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 200180 kb
Host smart-22e19c54-3cb9-46b9-a9b1-4886e3b97a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164971484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3164971484
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1088039351
Short name T125
Test name
Test status
Simulation time 77297246295 ps
CPU time 32.25 seconds
Started Dec 27 01:05:58 PM PST 23
Finished Dec 27 01:06:33 PM PST 23
Peak memory 200208 kb
Host smart-64b6939a-6061-4d0d-9144-bec5eb12f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088039351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1088039351
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3595736218
Short name T237
Test name
Test status
Simulation time 34868011925 ps
CPU time 63.67 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:07:00 PM PST 23
Peak memory 200144 kb
Host smart-26284833-8972-4099-973d-8e70af5e92cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595736218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3595736218
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3267646899
Short name T207
Test name
Test status
Simulation time 16818422549 ps
CPU time 27.85 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 200188 kb
Host smart-1380eaa8-d6f5-4854-937e-90977570c165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267646899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3267646899
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.4190803956
Short name T1141
Test name
Test status
Simulation time 123443118271 ps
CPU time 22.01 seconds
Started Dec 27 01:05:55 PM PST 23
Finished Dec 27 01:06:21 PM PST 23
Peak memory 199920 kb
Host smart-7a484422-e30b-486a-87e2-90d0926b4b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190803956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4190803956
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1897306169
Short name T220
Test name
Test status
Simulation time 22258439868 ps
CPU time 39.64 seconds
Started Dec 27 01:05:54 PM PST 23
Finished Dec 27 01:06:38 PM PST 23
Peak memory 199988 kb
Host smart-680c0a36-2e77-455a-81dd-39b4e0942719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897306169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1897306169
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3522552908
Short name T737
Test name
Test status
Simulation time 156433926483 ps
CPU time 34.73 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:06:31 PM PST 23
Peak memory 200224 kb
Host smart-46bebec5-aa26-4f30-baf4-be1808487341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522552908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3522552908
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1565167848
Short name T903
Test name
Test status
Simulation time 115206082107 ps
CPU time 185.67 seconds
Started Dec 27 01:05:58 PM PST 23
Finished Dec 27 01:09:07 PM PST 23
Peak memory 200116 kb
Host smart-4556992a-1360-4e47-8c95-9a80b603cf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565167848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1565167848
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.417220551
Short name T746
Test name
Test status
Simulation time 60219685278 ps
CPU time 83.91 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:07:19 PM PST 23
Peak memory 200216 kb
Host smart-eeacbba3-87ac-443d-9fb8-2d0848ed9966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417220551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.417220551
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1970286175
Short name T327
Test name
Test status
Simulation time 21248431513 ps
CPU time 10.87 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:04 PM PST 23
Peak memory 200192 kb
Host smart-2d20ddc0-7884-4b2c-9751-6b5f1b3ecca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970286175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1970286175
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1385657873
Short name T1131
Test name
Test status
Simulation time 11983396 ps
CPU time 0.56 seconds
Started Dec 27 01:03:51 PM PST 23
Finished Dec 27 01:04:01 PM PST 23
Peak memory 195644 kb
Host smart-6cd2fecd-d81d-4b1a-8a63-4bb2c25a03c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385657873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1385657873
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1334272386
Short name T346
Test name
Test status
Simulation time 130433821889 ps
CPU time 198.24 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:07:09 PM PST 23
Peak memory 200216 kb
Host smart-5821776e-0c95-40e8-be9b-bd581933530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334272386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1334272386
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.4273686473
Short name T255
Test name
Test status
Simulation time 129165524023 ps
CPU time 39.92 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:04:30 PM PST 23
Peak memory 200228 kb
Host smart-240fb095-f7d0-4453-881a-cedb3d20c566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273686473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4273686473
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.1204513616
Short name T1118
Test name
Test status
Simulation time 24196752491 ps
CPU time 16.97 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:04:17 PM PST 23
Peak memory 199144 kb
Host smart-9affeed6-928b-4ff5-b7e7-d148a1c25a8d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204513616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1204513616
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1993909167
Short name T976
Test name
Test status
Simulation time 57398037193 ps
CPU time 173.29 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:06:52 PM PST 23
Peak memory 200208 kb
Host smart-9086ecb1-9d89-486a-8c52-aaf757367f2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993909167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1993909167
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2603282753
Short name T1121
Test name
Test status
Simulation time 1266229551 ps
CPU time 1.7 seconds
Started Dec 27 01:03:59 PM PST 23
Finished Dec 27 01:04:08 PM PST 23
Peak memory 195612 kb
Host smart-d0378466-d4fa-417b-b4ad-6c7d6e01c92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603282753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2603282753
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2287987784
Short name T631
Test name
Test status
Simulation time 272095302261 ps
CPU time 106.65 seconds
Started Dec 27 01:03:59 PM PST 23
Finished Dec 27 01:05:54 PM PST 23
Peak memory 198780 kb
Host smart-32331957-6924-4605-82c5-f9480210a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287987784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2287987784
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3312381958
Short name T864
Test name
Test status
Simulation time 9285177703 ps
CPU time 137.19 seconds
Started Dec 27 01:04:02 PM PST 23
Finished Dec 27 01:06:25 PM PST 23
Peak memory 200216 kb
Host smart-aff10ce1-b3ab-4539-a0c7-39f38db24d52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312381958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3312381958
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1130483769
Short name T667
Test name
Test status
Simulation time 4316802069 ps
CPU time 34.78 seconds
Started Dec 27 01:03:58 PM PST 23
Finished Dec 27 01:04:41 PM PST 23
Peak memory 198704 kb
Host smart-9ca1c7a1-2601-43a4-8e36-0e803ca94db6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1130483769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1130483769
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1449183612
Short name T526
Test name
Test status
Simulation time 1941865366 ps
CPU time 3.68 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:04:01 PM PST 23
Peak memory 195568 kb
Host smart-f1dd8e79-9b96-4aa6-9be5-4828208a6c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449183612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1449183612
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2505399158
Short name T458
Test name
Test status
Simulation time 656656737 ps
CPU time 1.6 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:03:58 PM PST 23
Peak memory 198960 kb
Host smart-c50bc601-7bc2-47bd-83e6-28d86843d38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505399158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2505399158
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2536445075
Short name T962
Test name
Test status
Simulation time 119193857440 ps
CPU time 1194.02 seconds
Started Dec 27 01:03:56 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 216704 kb
Host smart-358b2e68-fa6c-456a-9cbb-5d1787f5cc87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536445075 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2536445075
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.710984767
Short name T1134
Test name
Test status
Simulation time 1850434511 ps
CPU time 2.08 seconds
Started Dec 27 01:03:53 PM PST 23
Finished Dec 27 01:04:04 PM PST 23
Peak memory 198828 kb
Host smart-1d3e061d-24b9-4b46-a1b5-50680c038dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710984767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.710984767
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1272009879
Short name T618
Test name
Test status
Simulation time 47476459651 ps
CPU time 187.98 seconds
Started Dec 27 01:03:51 PM PST 23
Finished Dec 27 01:07:09 PM PST 23
Peak memory 200180 kb
Host smart-65f4a1c9-01a0-416f-bdae-5582c36230a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272009879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1272009879
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3734636167
Short name T171
Test name
Test status
Simulation time 68065077371 ps
CPU time 25.09 seconds
Started Dec 27 01:06:02 PM PST 23
Finished Dec 27 01:06:28 PM PST 23
Peak memory 200172 kb
Host smart-4d6f2c40-2084-480a-a431-38f1d1d8dc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734636167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3734636167
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.937078968
Short name T947
Test name
Test status
Simulation time 172329182498 ps
CPU time 49.29 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:06:46 PM PST 23
Peak memory 200232 kb
Host smart-448332ec-48de-46af-9534-59ee45eed786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937078968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.937078968
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3516730139
Short name T144
Test name
Test status
Simulation time 119233050971 ps
CPU time 12.18 seconds
Started Dec 27 01:05:50 PM PST 23
Finished Dec 27 01:06:08 PM PST 23
Peak memory 200172 kb
Host smart-da9ae1f8-d6d9-49a6-afb2-e0608dbcab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516730139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3516730139
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3519414292
Short name T230
Test name
Test status
Simulation time 117024264401 ps
CPU time 28.12 seconds
Started Dec 27 01:05:53 PM PST 23
Finished Dec 27 01:06:26 PM PST 23
Peak memory 200248 kb
Host smart-8fbb163f-4e95-42be-a9b7-c3fcb6ab980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519414292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3519414292
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1777130607
Short name T245
Test name
Test status
Simulation time 248354712064 ps
CPU time 475.74 seconds
Started Dec 27 01:05:56 PM PST 23
Finished Dec 27 01:13:55 PM PST 23
Peak memory 200252 kb
Host smart-a40486d0-39b2-4bb9-b403-c47c6eb452af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777130607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1777130607
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3926118967
Short name T311
Test name
Test status
Simulation time 351247231122 ps
CPU time 71.01 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:07:07 PM PST 23
Peak memory 200116 kb
Host smart-7682a7ba-b3eb-42ac-bae3-dcbd3b2fb81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926118967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3926118967
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.615250668
Short name T911
Test name
Test status
Simulation time 14531296 ps
CPU time 0.55 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:25 PM PST 23
Peak memory 195552 kb
Host smart-a57c987f-ed18-4904-b41d-8eddf33e9978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615250668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.615250668
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.492572467
Short name T425
Test name
Test status
Simulation time 130470137309 ps
CPU time 64.45 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:04:29 PM PST 23
Peak memory 200152 kb
Host smart-f9558753-e655-47b2-8f8a-37381c03753e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492572467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.492572467
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.529648492
Short name T755
Test name
Test status
Simulation time 108182593776 ps
CPU time 163.36 seconds
Started Dec 27 01:03:16 PM PST 23
Finished Dec 27 01:06:05 PM PST 23
Peak memory 200116 kb
Host smart-44a964b5-4c2c-4805-8524-f37561ce4f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529648492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.529648492
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1720400563
Short name T1034
Test name
Test status
Simulation time 71303046362 ps
CPU time 105.46 seconds
Started Dec 27 01:03:25 PM PST 23
Finished Dec 27 01:05:15 PM PST 23
Peak memory 200212 kb
Host smart-e5e8d549-f3f6-4752-9a3f-7d447851775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720400563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1720400563
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1283005477
Short name T562
Test name
Test status
Simulation time 126406537277 ps
CPU time 125.41 seconds
Started Dec 27 01:03:35 PM PST 23
Finished Dec 27 01:05:42 PM PST 23
Peak memory 200236 kb
Host smart-6d6b3473-6816-4438-9db3-faf1cc81eb5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283005477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1283005477
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2293383013
Short name T814
Test name
Test status
Simulation time 99771640719 ps
CPU time 955.11 seconds
Started Dec 27 01:03:12 PM PST 23
Finished Dec 27 01:19:16 PM PST 23
Peak memory 200176 kb
Host smart-03f59899-5c2f-43e2-9465-a0e95c011240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293383013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2293383013
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1228878687
Short name T444
Test name
Test status
Simulation time 50673113723 ps
CPU time 90.5 seconds
Started Dec 27 01:03:15 PM PST 23
Finished Dec 27 01:04:52 PM PST 23
Peak memory 198540 kb
Host smart-5dd8f97f-a1d0-4ac6-b275-38a92d67f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228878687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1228878687
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2419432554
Short name T879
Test name
Test status
Simulation time 9281384144 ps
CPU time 583.7 seconds
Started Dec 27 01:03:11 PM PST 23
Finished Dec 27 01:13:04 PM PST 23
Peak memory 200008 kb
Host smart-a23d1374-6762-4cd5-9b88-04266d6abd97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419432554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2419432554
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.54285692
Short name T996
Test name
Test status
Simulation time 22546027725 ps
CPU time 18.76 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 199508 kb
Host smart-4d405e12-054c-4d43-a479-27b222553604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54285692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.54285692
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1764639460
Short name T918
Test name
Test status
Simulation time 39806619719 ps
CPU time 9.28 seconds
Started Dec 27 01:03:25 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 195736 kb
Host smart-46dea805-dd9b-40b6-8489-518480ba9318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764639460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1764639460
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3177716115
Short name T73
Test name
Test status
Simulation time 30853679 ps
CPU time 0.76 seconds
Started Dec 27 01:03:22 PM PST 23
Finished Dec 27 01:03:25 PM PST 23
Peak memory 217776 kb
Host smart-c1d6f120-bce8-44c1-9ed8-9490a95f8e62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177716115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3177716115
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2275667152
Short name T630
Test name
Test status
Simulation time 100575121 ps
CPU time 0.75 seconds
Started Dec 27 01:03:25 PM PST 23
Finished Dec 27 01:03:30 PM PST 23
Peak memory 196648 kb
Host smart-bd675713-d1ba-4683-b4a8-b403a8e0a36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275667152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2275667152
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2794239030
Short name T299
Test name
Test status
Simulation time 1519417839822 ps
CPU time 1381.87 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:26:46 PM PST 23
Peak memory 200208 kb
Host smart-7bf7bcde-75f4-40bc-9da6-373cd5b677f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794239030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2794239030
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3017282438
Short name T1177
Test name
Test status
Simulation time 12486041488 ps
CPU time 40.27 seconds
Started Dec 27 01:03:20 PM PST 23
Finished Dec 27 01:04:03 PM PST 23
Peak memory 199188 kb
Host smart-c60d8b90-9abd-4e66-aa67-5ba8f5274161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017282438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3017282438
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1413129150
Short name T940
Test name
Test status
Simulation time 20919130694 ps
CPU time 18.02 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:03:54 PM PST 23
Peak memory 200224 kb
Host smart-439b7852-8ac8-41e7-98e7-54ccc7ee33f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413129150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1413129150
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3645307537
Short name T521
Test name
Test status
Simulation time 16759206 ps
CPU time 0.54 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:04:09 PM PST 23
Peak memory 195608 kb
Host smart-6abc12b3-d2ea-4f6a-b9b5-257545efa5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645307537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3645307537
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.778906874
Short name T16
Test name
Test status
Simulation time 51513784088 ps
CPU time 86.86 seconds
Started Dec 27 01:04:07 PM PST 23
Finished Dec 27 01:05:41 PM PST 23
Peak memory 200168 kb
Host smart-6ce97e02-030a-4f3d-8754-e3fa5f1b7c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778906874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.778906874
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.4264730976
Short name T682
Test name
Test status
Simulation time 35012630017 ps
CPU time 26.11 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:04:24 PM PST 23
Peak memory 200136 kb
Host smart-89b4a5a7-79fb-4971-a887-e4a199372e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264730976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.4264730976
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1335395520
Short name T225
Test name
Test status
Simulation time 70281432937 ps
CPU time 257.69 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:08:16 PM PST 23
Peak memory 200132 kb
Host smart-e96937b8-2d90-4533-8317-c2e092eb4b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335395520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1335395520
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.578284061
Short name T913
Test name
Test status
Simulation time 60998177555 ps
CPU time 87.3 seconds
Started Dec 27 01:03:57 PM PST 23
Finished Dec 27 01:05:32 PM PST 23
Peak memory 200212 kb
Host smart-5be4b1c4-cfbb-4cb3-aa6b-91ed0d6e7ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578284061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.578284061
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.798201449
Short name T612
Test name
Test status
Simulation time 1417270382 ps
CPU time 1.59 seconds
Started Dec 27 01:03:59 PM PST 23
Finished Dec 27 01:04:08 PM PST 23
Peak memory 198280 kb
Host smart-eb3cf2ea-5ec6-421c-a4ee-cf809c5891e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798201449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.798201449
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3067522020
Short name T1002
Test name
Test status
Simulation time 267458803407 ps
CPU time 55.25 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:04:54 PM PST 23
Peak memory 199336 kb
Host smart-5df039b0-babe-459b-8cb9-261db81e8027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067522020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3067522020
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2297472247
Short name T904
Test name
Test status
Simulation time 22859134851 ps
CPU time 1324.88 seconds
Started Dec 27 01:03:57 PM PST 23
Finished Dec 27 01:26:10 PM PST 23
Peak memory 200196 kb
Host smart-cf15dcfd-99df-4ab4-aae2-0887c175ab27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297472247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2297472247
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.330319981
Short name T897
Test name
Test status
Simulation time 1322742490 ps
CPU time 5.33 seconds
Started Dec 27 01:04:00 PM PST 23
Finished Dec 27 01:04:13 PM PST 23
Peak memory 198392 kb
Host smart-b9974409-8848-4dc9-891b-c13127e70c75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330319981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.330319981
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3834927938
Short name T1108
Test name
Test status
Simulation time 234962430053 ps
CPU time 233.77 seconds
Started Dec 27 01:03:54 PM PST 23
Finished Dec 27 01:07:57 PM PST 23
Peak memory 200236 kb
Host smart-a8c3d275-1684-4b20-b7f5-6784632cfbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834927938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3834927938
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1201618379
Short name T1043
Test name
Test status
Simulation time 2475146698 ps
CPU time 2.2 seconds
Started Dec 27 01:03:56 PM PST 23
Finished Dec 27 01:04:05 PM PST 23
Peak memory 195668 kb
Host smart-46750920-d18f-413a-85e6-ad799dca90f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201618379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1201618379
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3173162244
Short name T967
Test name
Test status
Simulation time 499455567 ps
CPU time 2.19 seconds
Started Dec 27 01:03:56 PM PST 23
Finished Dec 27 01:04:05 PM PST 23
Peak memory 198380 kb
Host smart-7a796eb0-c031-4772-8db0-4cfaf45d07d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173162244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3173162244
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1106562625
Short name T872
Test name
Test status
Simulation time 238445508668 ps
CPU time 744.7 seconds
Started Dec 27 01:03:55 PM PST 23
Finished Dec 27 01:16:27 PM PST 23
Peak memory 200172 kb
Host smart-c27eabaf-d57f-4e56-81cb-d9dc528f7f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106562625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1106562625
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.464069083
Short name T734
Test name
Test status
Simulation time 75917453912 ps
CPU time 1068.11 seconds
Started Dec 27 01:04:04 PM PST 23
Finished Dec 27 01:21:57 PM PST 23
Peak memory 216416 kb
Host smart-660ca11c-ba3a-4b9a-ae49-1c61588a3da4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464069083 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.464069083
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.131545420
Short name T855
Test name
Test status
Simulation time 6750638997 ps
CPU time 12.29 seconds
Started Dec 27 01:03:52 PM PST 23
Finished Dec 27 01:04:13 PM PST 23
Peak memory 199180 kb
Host smart-202ff708-1d2b-4eb0-b640-052227d6f39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131545420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.131545420
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.135054752
Short name T595
Test name
Test status
Simulation time 61350523569 ps
CPU time 113 seconds
Started Dec 27 01:04:01 PM PST 23
Finished Dec 27 01:06:01 PM PST 23
Peak memory 200168 kb
Host smart-cbed17e2-8bf7-4bf6-b3d0-9b1d88bf5792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135054752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.135054752
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1142267491
Short name T1059
Test name
Test status
Simulation time 55309904328 ps
CPU time 24.99 seconds
Started Dec 27 01:05:55 PM PST 23
Finished Dec 27 01:06:24 PM PST 23
Peak memory 199860 kb
Host smart-e4759f6b-1481-486b-8e15-97391d2695d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142267491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1142267491
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2455579526
Short name T169
Test name
Test status
Simulation time 39733027875 ps
CPU time 16.08 seconds
Started Dec 27 01:05:52 PM PST 23
Finished Dec 27 01:06:13 PM PST 23
Peak memory 200220 kb
Host smart-78a99b4a-914c-49e0-a052-1377d72b8037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455579526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2455579526
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2517716465
Short name T1065
Test name
Test status
Simulation time 16878904079 ps
CPU time 12.89 seconds
Started Dec 27 01:05:55 PM PST 23
Finished Dec 27 01:06:12 PM PST 23
Peak memory 199796 kb
Host smart-ca42fe79-1f97-4ff2-bd0b-7bfeb0654507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517716465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2517716465
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3419077524
Short name T306
Test name
Test status
Simulation time 103080320201 ps
CPU time 79.88 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:07:16 PM PST 23
Peak memory 200020 kb
Host smart-ae219bf3-ac6f-452b-9f0c-eff960647fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419077524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3419077524
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4275601539
Short name T690
Test name
Test status
Simulation time 14017341905 ps
CPU time 13.38 seconds
Started Dec 27 01:05:51 PM PST 23
Finished Dec 27 01:06:10 PM PST 23
Peak memory 199944 kb
Host smart-2e90721f-ae2f-4673-a679-3513e3fac6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275601539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4275601539
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2509516494
Short name T818
Test name
Test status
Simulation time 34336812 ps
CPU time 0.55 seconds
Started Dec 27 01:03:59 PM PST 23
Finished Dec 27 01:04:08 PM PST 23
Peak memory 195624 kb
Host smart-e121fefa-22ff-445f-a893-92d3fd603d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509516494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2509516494
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2421740044
Short name T684
Test name
Test status
Simulation time 24867211295 ps
CPU time 41.1 seconds
Started Dec 27 01:04:01 PM PST 23
Finished Dec 27 01:04:49 PM PST 23
Peak memory 200224 kb
Host smart-6cc234f7-68b3-4832-a980-f6db60433c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421740044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2421740044
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2581572180
Short name T718
Test name
Test status
Simulation time 125655295604 ps
CPU time 82 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:05:30 PM PST 23
Peak memory 199436 kb
Host smart-da91eec3-771b-4843-8390-75f1f02da2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581572180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2581572180
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.167267515
Short name T160
Test name
Test status
Simulation time 22560181750 ps
CPU time 17.03 seconds
Started Dec 27 01:03:57 PM PST 23
Finished Dec 27 01:04:22 PM PST 23
Peak memory 200056 kb
Host smart-c49f5a5b-f8da-49a6-93c6-e3b1e7448938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167267515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.167267515
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2187523312
Short name T1086
Test name
Test status
Simulation time 94419023028 ps
CPU time 231.48 seconds
Started Dec 27 01:03:53 PM PST 23
Finished Dec 27 01:07:53 PM PST 23
Peak memory 200156 kb
Host smart-a8aa7caf-47d9-42c9-b87c-05659a207fbd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187523312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2187523312
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2486504492
Short name T603
Test name
Test status
Simulation time 87175561661 ps
CPU time 226.12 seconds
Started Dec 27 01:03:59 PM PST 23
Finished Dec 27 01:07:53 PM PST 23
Peak memory 200116 kb
Host smart-a8c43ff5-bde1-46a6-9340-4a1ac9e40e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486504492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2486504492
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1676249676
Short name T589
Test name
Test status
Simulation time 6433336411 ps
CPU time 3.56 seconds
Started Dec 27 01:04:05 PM PST 23
Finished Dec 27 01:04:13 PM PST 23
Peak memory 198240 kb
Host smart-155d099f-3b15-46ad-9d71-5008bdb7db57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676249676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1676249676
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.287892564
Short name T581
Test name
Test status
Simulation time 219191012397 ps
CPU time 742.73 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:16:31 PM PST 23
Peak memory 208692 kb
Host smart-721a619b-58e8-4f7b-9cd0-362700f2a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287892564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.287892564
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2232637642
Short name T912
Test name
Test status
Simulation time 18430274290 ps
CPU time 111.31 seconds
Started Dec 27 01:03:53 PM PST 23
Finished Dec 27 01:05:53 PM PST 23
Peak memory 200180 kb
Host smart-0b8a24dc-e806-454c-a408-2038ffa8a76b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232637642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2232637642
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2366875727
Short name T868
Test name
Test status
Simulation time 106290242188 ps
CPU time 38.16 seconds
Started Dec 27 01:04:00 PM PST 23
Finished Dec 27 01:04:46 PM PST 23
Peak memory 200292 kb
Host smart-ead08b73-6726-4a25-9b9c-4db1f14d67e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366875727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2366875727
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.874396542
Short name T704
Test name
Test status
Simulation time 2705820782 ps
CPU time 4.69 seconds
Started Dec 27 01:03:53 PM PST 23
Finished Dec 27 01:04:06 PM PST 23
Peak memory 195656 kb
Host smart-53e59c1f-4ced-482b-a8af-93770aee61ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874396542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.874396542
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.4236443664
Short name T971
Test name
Test status
Simulation time 90523571 ps
CPU time 1.08 seconds
Started Dec 27 01:03:56 PM PST 23
Finished Dec 27 01:04:05 PM PST 23
Peak memory 198124 kb
Host smart-a107f188-7483-4853-ae97-197241ae4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236443664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.4236443664
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.4151686773
Short name T1040
Test name
Test status
Simulation time 490849110959 ps
CPU time 1164.75 seconds
Started Dec 27 01:03:56 PM PST 23
Finished Dec 27 01:23:28 PM PST 23
Peak memory 200496 kb
Host smart-2d5dec77-2a29-4229-ab26-65ed71e1cad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151686773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.4151686773
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.925464569
Short name T712
Test name
Test status
Simulation time 87122248846 ps
CPU time 629.08 seconds
Started Dec 27 01:03:58 PM PST 23
Finished Dec 27 01:14:36 PM PST 23
Peak memory 216688 kb
Host smart-094adadb-542b-428a-ab90-0c763e2dcd5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925464569 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.925464569
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2637163087
Short name T798
Test name
Test status
Simulation time 1424449226 ps
CPU time 2.09 seconds
Started Dec 27 01:03:59 PM PST 23
Finished Dec 27 01:04:09 PM PST 23
Peak memory 198116 kb
Host smart-5f70f0ab-736e-47e4-8f77-95c1e4d025bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637163087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2637163087
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1742494737
Short name T459
Test name
Test status
Simulation time 214197838444 ps
CPU time 68.25 seconds
Started Dec 27 01:04:02 PM PST 23
Finished Dec 27 01:05:16 PM PST 23
Peak memory 200156 kb
Host smart-072d2024-dad9-4604-b601-f1b75d379146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742494737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1742494737
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2258453895
Short name T692
Test name
Test status
Simulation time 12127971217 ps
CPU time 11.68 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:19 PM PST 23
Peak memory 200112 kb
Host smart-e295c2dc-9ca3-4009-815a-30f4e2ec61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258453895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2258453895
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2624348753
Short name T120
Test name
Test status
Simulation time 117221014771 ps
CPU time 182.78 seconds
Started Dec 27 01:06:04 PM PST 23
Finished Dec 27 01:09:07 PM PST 23
Peak memory 200108 kb
Host smart-313e44a0-9c09-4815-b1e7-9c2ee4aed237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624348753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2624348753
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1964487383
Short name T226
Test name
Test status
Simulation time 92803594327 ps
CPU time 78.86 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:07:29 PM PST 23
Peak memory 199880 kb
Host smart-c9d4203c-a849-45cd-bd30-5a0953482d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964487383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1964487383
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2881619062
Short name T331
Test name
Test status
Simulation time 192553774675 ps
CPU time 143.11 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:08:32 PM PST 23
Peak memory 199608 kb
Host smart-1bae50f2-9de7-42fa-8857-226ceecf766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881619062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2881619062
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1279742105
Short name T205
Test name
Test status
Simulation time 12605594080 ps
CPU time 19.74 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:28 PM PST 23
Peak memory 199564 kb
Host smart-e39aa696-c0b1-4835-b561-63298988e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279742105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1279742105
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1337186804
Short name T270
Test name
Test status
Simulation time 20249787533 ps
CPU time 32.31 seconds
Started Dec 27 01:06:05 PM PST 23
Finished Dec 27 01:06:39 PM PST 23
Peak memory 199668 kb
Host smart-8516e8b5-0cea-472b-a5d0-f10e9a35fa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337186804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1337186804
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2903496633
Short name T152
Test name
Test status
Simulation time 13010620957 ps
CPU time 22.73 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:06:33 PM PST 23
Peak memory 200188 kb
Host smart-bd290c0e-2026-4251-97ac-9c3d16b7d07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903496633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2903496633
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4121759077
Short name T86
Test name
Test status
Simulation time 32701227 ps
CPU time 0.53 seconds
Started Dec 27 01:04:02 PM PST 23
Finished Dec 27 01:04:09 PM PST 23
Peak memory 194544 kb
Host smart-3b31be2e-965c-433f-a625-ddc6fd5a0d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121759077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4121759077
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1797325882
Short name T848
Test name
Test status
Simulation time 34839532099 ps
CPU time 25.18 seconds
Started Dec 27 01:04:02 PM PST 23
Finished Dec 27 01:04:33 PM PST 23
Peak memory 200248 kb
Host smart-9d4cb0b4-d8bd-4e0f-822e-a00055349a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797325882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1797325882
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4202001362
Short name T616
Test name
Test status
Simulation time 43598281667 ps
CPU time 71.38 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:05:20 PM PST 23
Peak memory 199496 kb
Host smart-ce861371-bf6a-4736-97b7-cf7409134a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202001362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4202001362
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3249391746
Short name T219
Test name
Test status
Simulation time 208073686570 ps
CPU time 28.27 seconds
Started Dec 27 01:03:55 PM PST 23
Finished Dec 27 01:04:30 PM PST 23
Peak memory 200184 kb
Host smart-306e1843-21e5-41f5-bac1-a037b6e72c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249391746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3249391746
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1088827694
Short name T439
Test name
Test status
Simulation time 98868379268 ps
CPU time 178.68 seconds
Started Dec 27 01:04:00 PM PST 23
Finished Dec 27 01:07:06 PM PST 23
Peak memory 198696 kb
Host smart-58a96a21-8d3f-42b2-9172-2e8cbd4dbb25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088827694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1088827694
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2765974206
Short name T426
Test name
Test status
Simulation time 126844868051 ps
CPU time 287.14 seconds
Started Dec 27 01:04:01 PM PST 23
Finished Dec 27 01:08:55 PM PST 23
Peak memory 200216 kb
Host smart-fef75d7e-0e8a-4d0c-9e99-ced35240587e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765974206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2765974206
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.416701374
Short name T664
Test name
Test status
Simulation time 9021951469 ps
CPU time 6.58 seconds
Started Dec 27 01:03:59 PM PST 23
Finished Dec 27 01:04:13 PM PST 23
Peak memory 199264 kb
Host smart-7b75a802-609d-4fc2-beb7-553912d57b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416701374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.416701374
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3949410065
Short name T1060
Test name
Test status
Simulation time 145513159317 ps
CPU time 133.77 seconds
Started Dec 27 01:03:55 PM PST 23
Finished Dec 27 01:06:16 PM PST 23
Peak memory 200588 kb
Host smart-4d0e097c-bc97-47c3-913c-699d093d936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949410065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3949410065
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.696882434
Short name T905
Test name
Test status
Simulation time 7730425067 ps
CPU time 149.44 seconds
Started Dec 27 01:04:06 PM PST 23
Finished Dec 27 01:06:42 PM PST 23
Peak memory 200204 kb
Host smart-9a185e37-761e-4781-a384-5d93adf0bcc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696882434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.696882434
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2301372860
Short name T941
Test name
Test status
Simulation time 3898608497 ps
CPU time 14.36 seconds
Started Dec 27 01:03:58 PM PST 23
Finished Dec 27 01:04:21 PM PST 23
Peak memory 198744 kb
Host smart-68df4640-0b49-4ea7-b766-96ff385ebdaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301372860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2301372860
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2217664156
Short name T784
Test name
Test status
Simulation time 32305480674 ps
CPU time 52.11 seconds
Started Dec 27 01:03:55 PM PST 23
Finished Dec 27 01:04:55 PM PST 23
Peak memory 200164 kb
Host smart-afb59211-c75c-425b-9a13-d82cc8679431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217664156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2217664156
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3487651813
Short name T662
Test name
Test status
Simulation time 31770660028 ps
CPU time 50.13 seconds
Started Dec 27 01:03:58 PM PST 23
Finished Dec 27 01:04:56 PM PST 23
Peak memory 195680 kb
Host smart-ac290d3a-18b3-4ea1-83f2-5161d9be88bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487651813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3487651813
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3524476292
Short name T768
Test name
Test status
Simulation time 453218893 ps
CPU time 2.02 seconds
Started Dec 27 01:04:04 PM PST 23
Finished Dec 27 01:04:11 PM PST 23
Peak memory 199476 kb
Host smart-ed6375c5-8314-4405-8e6c-7c67f3857382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524476292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3524476292
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3641315740
Short name T328
Test name
Test status
Simulation time 753468320969 ps
CPU time 2154.85 seconds
Started Dec 27 01:04:01 PM PST 23
Finished Dec 27 01:40:03 PM PST 23
Peak memory 200288 kb
Host smart-25d3b454-958e-4ae2-bf81-1c36d1c848be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641315740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3641315740
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.421435824
Short name T1009
Test name
Test status
Simulation time 876098815 ps
CPU time 3.58 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:04:12 PM PST 23
Peak memory 199344 kb
Host smart-529261b4-b558-4ad3-878e-a36638d9317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421435824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.421435824
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3470753314
Short name T1106
Test name
Test status
Simulation time 68374946505 ps
CPU time 35.09 seconds
Started Dec 27 01:03:55 PM PST 23
Finished Dec 27 01:04:37 PM PST 23
Peak memory 200212 kb
Host smart-875220d0-44cc-4981-b2cb-8aaf6e8c7079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470753314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3470753314
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.838782583
Short name T93
Test name
Test status
Simulation time 61212746144 ps
CPU time 33.37 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:06:44 PM PST 23
Peak memory 200192 kb
Host smart-775735fe-12cc-43e3-8289-a6bbfb05482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838782583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.838782583
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1171649227
Short name T886
Test name
Test status
Simulation time 80030064587 ps
CPU time 61.15 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:07:10 PM PST 23
Peak memory 200180 kb
Host smart-d3b93658-145a-4631-8cbf-4a90c24d12fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171649227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1171649227
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2466048394
Short name T906
Test name
Test status
Simulation time 52607665460 ps
CPU time 84.84 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:07:33 PM PST 23
Peak memory 200204 kb
Host smart-03a2bb04-7c7f-4570-8c06-c53e6188a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466048394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2466048394
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1979470314
Short name T1023
Test name
Test status
Simulation time 95385509889 ps
CPU time 202.26 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:09:32 PM PST 23
Peak memory 200180 kb
Host smart-c3c5d384-293f-4371-8513-ae54dd124c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979470314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1979470314
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1446133145
Short name T795
Test name
Test status
Simulation time 39928600970 ps
CPU time 60.57 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:07:08 PM PST 23
Peak memory 200156 kb
Host smart-c8ed0199-ad47-4ccb-912d-d82dfffa95e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446133145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1446133145
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1555678398
Short name T914
Test name
Test status
Simulation time 123688595176 ps
CPU time 210.41 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:09:38 PM PST 23
Peak memory 200176 kb
Host smart-5a796bb7-eb4a-4cd5-97ae-9a5d0486d760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555678398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1555678398
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1357530404
Short name T828
Test name
Test status
Simulation time 220708403349 ps
CPU time 28.08 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:36 PM PST 23
Peak memory 200272 kb
Host smart-c71b1f33-db3c-41ce-9baa-da01e867526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357530404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1357530404
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3034217155
Short name T1075
Test name
Test status
Simulation time 107309467039 ps
CPU time 189.84 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:09:18 PM PST 23
Peak memory 200168 kb
Host smart-107a6943-e65a-466e-881f-cd320a9e4f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034217155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3034217155
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3033240715
Short name T829
Test name
Test status
Simulation time 79850476232 ps
CPU time 106.83 seconds
Started Dec 27 01:06:09 PM PST 23
Finished Dec 27 01:07:59 PM PST 23
Peak memory 199628 kb
Host smart-d8e26eca-95b9-4003-8edc-935f308617a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033240715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3033240715
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2151443112
Short name T938
Test name
Test status
Simulation time 43641440 ps
CPU time 0.57 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:04:49 PM PST 23
Peak memory 195644 kb
Host smart-e913c70f-fa88-4569-b306-1ea7b7a289d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151443112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2151443112
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.353131402
Short name T901
Test name
Test status
Simulation time 34497057512 ps
CPU time 61.71 seconds
Started Dec 27 01:04:16 PM PST 23
Finished Dec 27 01:05:20 PM PST 23
Peak memory 199980 kb
Host smart-26d98542-1462-4f03-8d0c-defffa9bf3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353131402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.353131402
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3359973915
Short name T1196
Test name
Test status
Simulation time 38914176824 ps
CPU time 32.34 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:04:41 PM PST 23
Peak memory 200252 kb
Host smart-d9f8038a-b602-468b-bff5-c0f09628a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359973915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3359973915
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3470318569
Short name T227
Test name
Test status
Simulation time 83925333132 ps
CPU time 165.38 seconds
Started Dec 27 01:04:04 PM PST 23
Finished Dec 27 01:06:54 PM PST 23
Peak memory 200180 kb
Host smart-e889ce13-4d28-42e4-bedf-574fa2988d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470318569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3470318569
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.497828751
Short name T1077
Test name
Test status
Simulation time 67526391971 ps
CPU time 72.55 seconds
Started Dec 27 01:04:06 PM PST 23
Finished Dec 27 01:05:24 PM PST 23
Peak memory 199168 kb
Host smart-7cbbe00d-2bb6-4453-9c7f-b1f5a499b3f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497828751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.497828751
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3745972992
Short name T422
Test name
Test status
Simulation time 71496969081 ps
CPU time 448.32 seconds
Started Dec 27 01:04:10 PM PST 23
Finished Dec 27 01:11:44 PM PST 23
Peak memory 200236 kb
Host smart-1285ceb0-2e51-4857-bb0d-1568dfa681c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745972992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3745972992
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.95747285
Short name T831
Test name
Test status
Simulation time 4697698287 ps
CPU time 18.38 seconds
Started Dec 27 01:04:08 PM PST 23
Finished Dec 27 01:04:33 PM PST 23
Peak memory 198880 kb
Host smart-fcf51785-40b4-4580-b311-ca105db1e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95747285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.95747285
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.613208431
Short name T927
Test name
Test status
Simulation time 497387505057 ps
CPU time 97.12 seconds
Started Dec 27 01:04:11 PM PST 23
Finished Dec 27 01:05:53 PM PST 23
Peak memory 208980 kb
Host smart-0a6b793c-3e74-4c06-bc71-118d4ff1f0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613208431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.613208431
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.4126871161
Short name T694
Test name
Test status
Simulation time 12733772791 ps
CPU time 57.71 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:05:06 PM PST 23
Peak memory 200192 kb
Host smart-7d1bc95e-2ff5-46da-b8d7-d470e58db3ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126871161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4126871161
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1600833268
Short name T1150
Test name
Test status
Simulation time 1882149736 ps
CPU time 4.39 seconds
Started Dec 27 01:04:07 PM PST 23
Finished Dec 27 01:04:19 PM PST 23
Peak memory 198132 kb
Host smart-8c2a3356-0e2e-43cd-9b60-0100d86f138c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600833268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1600833268
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1158190100
Short name T1161
Test name
Test status
Simulation time 49663862188 ps
CPU time 44.27 seconds
Started Dec 27 01:03:58 PM PST 23
Finished Dec 27 01:04:51 PM PST 23
Peak memory 200296 kb
Host smart-757f734f-b537-4143-acee-e6346b71e085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158190100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1158190100
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.716765427
Short name T1204
Test name
Test status
Simulation time 4039740811 ps
CPU time 6.68 seconds
Started Dec 27 01:04:05 PM PST 23
Finished Dec 27 01:04:16 PM PST 23
Peak memory 195980 kb
Host smart-a0da9852-bc1b-4743-85cf-b58552450b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716765427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.716765427
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3463875727
Short name T687
Test name
Test status
Simulation time 668812897 ps
CPU time 3.11 seconds
Started Dec 27 01:04:20 PM PST 23
Finished Dec 27 01:04:24 PM PST 23
Peak memory 198256 kb
Host smart-5c601563-9680-4f20-a58a-b71fdf1af739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463875727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3463875727
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4060003483
Short name T1195
Test name
Test status
Simulation time 164397323615 ps
CPU time 272.59 seconds
Started Dec 27 01:03:56 PM PST 23
Finished Dec 27 01:08:36 PM PST 23
Peak memory 216480 kb
Host smart-19517af8-13d9-4ed6-aae4-b26b0c88d0f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060003483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4060003483
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.79159516
Short name T55
Test name
Test status
Simulation time 115972247482 ps
CPU time 676.09 seconds
Started Dec 27 01:04:10 PM PST 23
Finished Dec 27 01:15:32 PM PST 23
Peak memory 208460 kb
Host smart-b48c383d-ea4b-43de-9804-7badee3cc2ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79159516 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.79159516
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3212471684
Short name T753
Test name
Test status
Simulation time 1924612056 ps
CPU time 2.76 seconds
Started Dec 27 01:04:08 PM PST 23
Finished Dec 27 01:04:18 PM PST 23
Peak memory 198156 kb
Host smart-f9257a60-4ec8-45e4-991a-89d1863613e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212471684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3212471684
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2792769936
Short name T882
Test name
Test status
Simulation time 20637405743 ps
CPU time 31.53 seconds
Started Dec 27 01:04:00 PM PST 23
Finished Dec 27 01:04:39 PM PST 23
Peak memory 198592 kb
Host smart-011badc4-56a6-4303-ba1c-e047247f492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792769936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2792769936
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1779605936
Short name T206
Test name
Test status
Simulation time 23920576224 ps
CPU time 19.67 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:27 PM PST 23
Peak memory 200128 kb
Host smart-375fa615-6ce4-42e3-ae93-77d210d42f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779605936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1779605936
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3727006040
Short name T253
Test name
Test status
Simulation time 105424367203 ps
CPU time 42.17 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:51 PM PST 23
Peak memory 200160 kb
Host smart-10a8a64e-35ee-4a15-a4e4-381006179244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727006040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3727006040
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3392954721
Short name T951
Test name
Test status
Simulation time 24951633526 ps
CPU time 31.86 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:40 PM PST 23
Peak memory 200172 kb
Host smart-d3855f0a-19a0-4b31-96ef-8a729dcea5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392954721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3392954721
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2006556906
Short name T1016
Test name
Test status
Simulation time 12528637335 ps
CPU time 22.01 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:29 PM PST 23
Peak memory 200212 kb
Host smart-b9d70ba6-3a92-4afc-9253-77ed01dc50cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006556906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2006556906
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1337807337
Short name T1028
Test name
Test status
Simulation time 95574250881 ps
CPU time 78.5 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:07:27 PM PST 23
Peak memory 200180 kb
Host smart-2765eb90-d937-404a-aa4c-4860b7ed2e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337807337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1337807337
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2390605639
Short name T184
Test name
Test status
Simulation time 19807765247 ps
CPU time 30.04 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:06:40 PM PST 23
Peak memory 199996 kb
Host smart-c4468480-c910-485a-a96c-5b2879172d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390605639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2390605639
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2540137756
Short name T215
Test name
Test status
Simulation time 137288388259 ps
CPU time 221.74 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:09:55 PM PST 23
Peak memory 200268 kb
Host smart-cad57268-227c-4777-80bd-215c25edae59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540137756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2540137756
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.629311206
Short name T232
Test name
Test status
Simulation time 6994435341 ps
CPU time 12.38 seconds
Started Dec 27 01:06:05 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 200200 kb
Host smart-19fe45cd-be1c-4735-a958-a44f17d2ac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629311206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.629311206
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1413671064
Short name T853
Test name
Test status
Simulation time 39205573922 ps
CPU time 16.28 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:06:25 PM PST 23
Peak memory 200208 kb
Host smart-c59a7229-4f4a-4ff8-9cbc-fcefce5e8642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413671064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1413671064
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.462441237
Short name T1136
Test name
Test status
Simulation time 59641891508 ps
CPU time 22.93 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:30 PM PST 23
Peak memory 200244 kb
Host smart-3938d9c7-9f43-4d0d-bd49-9d28c09e3fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462441237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.462441237
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3156074786
Short name T847
Test name
Test status
Simulation time 23154653 ps
CPU time 0.53 seconds
Started Dec 27 01:04:04 PM PST 23
Finished Dec 27 01:04:09 PM PST 23
Peak memory 194604 kb
Host smart-ac55082a-397d-4f50-aae0-04acc1fbe0cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156074786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3156074786
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2980252649
Short name T721
Test name
Test status
Simulation time 48853747111 ps
CPU time 19.04 seconds
Started Dec 27 01:04:08 PM PST 23
Finished Dec 27 01:04:34 PM PST 23
Peak memory 200196 kb
Host smart-6807938b-e6e4-41ea-aa3c-3a247950d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980252649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2980252649
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4214074666
Short name T786
Test name
Test status
Simulation time 135932383368 ps
CPU time 1054.92 seconds
Started Dec 27 01:04:01 PM PST 23
Finished Dec 27 01:21:43 PM PST 23
Peak memory 200160 kb
Host smart-8c994ed3-8769-4cac-9615-46bef7383f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214074666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4214074666
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_noise_filter.98931107
Short name T1137
Test name
Test status
Simulation time 36486244670 ps
CPU time 46.07 seconds
Started Dec 27 01:04:12 PM PST 23
Finished Dec 27 01:05:02 PM PST 23
Peak memory 199744 kb
Host smart-371c3dd3-4621-48ee-9a18-059ff12992f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98931107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.98931107
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2858048644
Short name T224
Test name
Test status
Simulation time 16613430535 ps
CPU time 856.75 seconds
Started Dec 27 01:04:08 PM PST 23
Finished Dec 27 01:18:32 PM PST 23
Peak memory 200168 kb
Host smart-421eb128-908d-4697-a021-e96534d7245b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858048644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2858048644
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.587776592
Short name T922
Test name
Test status
Simulation time 5271608719 ps
CPU time 42.14 seconds
Started Dec 27 01:04:06 PM PST 23
Finished Dec 27 01:04:55 PM PST 23
Peak memory 198532 kb
Host smart-dbf1a0e7-2221-44a0-bec6-bb3fdbe6ce42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587776592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.587776592
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1457681476
Short name T605
Test name
Test status
Simulation time 40401940678 ps
CPU time 33.29 seconds
Started Dec 27 01:04:03 PM PST 23
Finished Dec 27 01:04:42 PM PST 23
Peak memory 200140 kb
Host smart-890cf477-6a58-4771-a534-05dfaaa71fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457681476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1457681476
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3949864327
Short name T1207
Test name
Test status
Simulation time 37140721562 ps
CPU time 52.57 seconds
Started Dec 27 01:04:10 PM PST 23
Finished Dec 27 01:05:09 PM PST 23
Peak memory 195924 kb
Host smart-4984bd24-df6a-4bac-8111-e971952684cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949864327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3949864327
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.539209083
Short name T519
Test name
Test status
Simulation time 498173474 ps
CPU time 1.51 seconds
Started Dec 27 01:04:09 PM PST 23
Finished Dec 27 01:04:18 PM PST 23
Peak memory 198092 kb
Host smart-14bf844c-6091-48f2-ba28-2ece7b30bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539209083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.539209083
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1650707942
Short name T438
Test name
Test status
Simulation time 125629141567 ps
CPU time 59.47 seconds
Started Dec 27 01:04:06 PM PST 23
Finished Dec 27 01:05:12 PM PST 23
Peak memory 200152 kb
Host smart-17522b23-62d1-4a58-8133-d0ed4649c8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650707942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1650707942
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2576203013
Short name T861
Test name
Test status
Simulation time 6023447755 ps
CPU time 14.98 seconds
Started Dec 27 01:04:13 PM PST 23
Finished Dec 27 01:04:31 PM PST 23
Peak memory 198996 kb
Host smart-0bf65655-1a84-444f-8e73-09dc637fb46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576203013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2576203013
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3516871667
Short name T789
Test name
Test status
Simulation time 51197877454 ps
CPU time 111.26 seconds
Started Dec 27 01:04:11 PM PST 23
Finished Dec 27 01:06:07 PM PST 23
Peak memory 200140 kb
Host smart-fd6e8f9f-ba64-472c-b448-aa4dc785cad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516871667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3516871667
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.421677022
Short name T954
Test name
Test status
Simulation time 12559540693 ps
CPU time 13.97 seconds
Started Dec 27 01:06:05 PM PST 23
Finished Dec 27 01:06:20 PM PST 23
Peak memory 199096 kb
Host smart-b08d4972-a6ec-455c-9d24-21482ca643b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421677022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.421677022
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.793221949
Short name T272
Test name
Test status
Simulation time 24015977747 ps
CPU time 10.3 seconds
Started Dec 27 01:06:05 PM PST 23
Finished Dec 27 01:06:16 PM PST 23
Peak memory 198804 kb
Host smart-e47bab59-97bd-4f71-aec7-f362cafc48ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793221949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.793221949
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1513273505
Short name T330
Test name
Test status
Simulation time 12371761433 ps
CPU time 15.44 seconds
Started Dec 27 01:06:05 PM PST 23
Finished Dec 27 01:06:22 PM PST 23
Peak memory 199360 kb
Host smart-f0bc02ec-0997-4dcb-ba98-38e13bfa9b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513273505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1513273505
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1982073130
Short name T771
Test name
Test status
Simulation time 93715397003 ps
CPU time 34.91 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:06:45 PM PST 23
Peak memory 199996 kb
Host smart-3cf047e0-4648-4345-9d4a-64a99fc22753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982073130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1982073130
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.757013591
Short name T716
Test name
Test status
Simulation time 150396539953 ps
CPU time 60.88 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:07:10 PM PST 23
Peak memory 200232 kb
Host smart-2d95db3f-bd65-47ef-a2ed-774f96ede266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757013591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.757013591
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1369551140
Short name T128
Test name
Test status
Simulation time 67137603942 ps
CPU time 60.48 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:07:08 PM PST 23
Peak memory 200128 kb
Host smart-22d167a8-b8b4-4496-a9d5-c2119553a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369551140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1369551140
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2939128685
Short name T822
Test name
Test status
Simulation time 33392209374 ps
CPU time 14.61 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:06:24 PM PST 23
Peak memory 200116 kb
Host smart-14811800-5685-4560-b395-27d170c49b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939128685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2939128685
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2664992174
Short name T135
Test name
Test status
Simulation time 107806089985 ps
CPU time 45.72 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:54 PM PST 23
Peak memory 200224 kb
Host smart-a3437c5e-086a-4140-a038-83658fab3d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664992174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2664992174
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3017887718
Short name T675
Test name
Test status
Simulation time 19942122 ps
CPU time 0.54 seconds
Started Dec 27 01:04:19 PM PST 23
Finished Dec 27 01:04:21 PM PST 23
Peak memory 194712 kb
Host smart-4ec1c366-db56-45ff-acb1-5fc52f665634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017887718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3017887718
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2709990492
Short name T880
Test name
Test status
Simulation time 159889126562 ps
CPU time 370.11 seconds
Started Dec 27 01:04:10 PM PST 23
Finished Dec 27 01:10:26 PM PST 23
Peak memory 200192 kb
Host smart-0bef057d-bc28-492a-bd1b-10b76c731e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709990492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2709990492
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2232814951
Short name T373
Test name
Test status
Simulation time 114242711799 ps
CPU time 65.57 seconds
Started Dec 27 01:03:55 PM PST 23
Finished Dec 27 01:05:08 PM PST 23
Peak memory 200144 kb
Host smart-f673afe5-a3fc-45d8-a62b-8b975dd90eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232814951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2232814951
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.158895920
Short name T999
Test name
Test status
Simulation time 61537531948 ps
CPU time 143.88 seconds
Started Dec 27 01:04:15 PM PST 23
Finished Dec 27 01:06:41 PM PST 23
Peak memory 200172 kb
Host smart-dc4726ee-c96f-4a4a-b039-7fdffb1e4b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158895920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.158895920
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3096469761
Short name T1213
Test name
Test status
Simulation time 268587471083 ps
CPU time 229.25 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:08:38 PM PST 23
Peak memory 200228 kb
Host smart-423914f4-6d51-4c61-badb-1939e3f8dc17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096469761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3096469761
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.686578448
Short name T1151
Test name
Test status
Simulation time 165506879471 ps
CPU time 1400.75 seconds
Started Dec 27 01:04:21 PM PST 23
Finished Dec 27 01:27:43 PM PST 23
Peak memory 200156 kb
Host smart-be1e9bde-0c60-408b-9e14-2eda8b09ccda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686578448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.686578448
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.681706762
Short name T465
Test name
Test status
Simulation time 4069548348 ps
CPU time 4.82 seconds
Started Dec 27 01:04:10 PM PST 23
Finished Dec 27 01:04:21 PM PST 23
Peak memory 198872 kb
Host smart-0c6b6b26-dcec-443c-baee-d38d9f63bb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681706762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.681706762
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3110404770
Short name T839
Test name
Test status
Simulation time 19588033277 ps
CPU time 16.66 seconds
Started Dec 27 01:04:09 PM PST 23
Finished Dec 27 01:04:32 PM PST 23
Peak memory 195048 kb
Host smart-3a1ca85a-8f02-447a-8291-65f08495331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110404770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3110404770
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1953626523
Short name T754
Test name
Test status
Simulation time 38076932073 ps
CPU time 1767.04 seconds
Started Dec 27 01:04:20 PM PST 23
Finished Dec 27 01:33:48 PM PST 23
Peak memory 200116 kb
Host smart-3418ef44-3545-4ab8-9dcb-ffd30b415ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953626523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1953626523
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2652662533
Short name T730
Test name
Test status
Simulation time 3587563176 ps
CPU time 28.41 seconds
Started Dec 27 01:04:12 PM PST 23
Finished Dec 27 01:04:45 PM PST 23
Peak memory 198796 kb
Host smart-24133e13-970b-4561-85ff-13cff2a1d33b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652662533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2652662533
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2218423191
Short name T862
Test name
Test status
Simulation time 178504486736 ps
CPU time 28.59 seconds
Started Dec 27 01:04:06 PM PST 23
Finished Dec 27 01:04:42 PM PST 23
Peak memory 200028 kb
Host smart-dbe22aba-feaa-4a03-abc5-1a5fc5f9fb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218423191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2218423191
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3544908639
Short name T980
Test name
Test status
Simulation time 45373136385 ps
CPU time 13.78 seconds
Started Dec 27 01:04:16 PM PST 23
Finished Dec 27 01:04:31 PM PST 23
Peak memory 195976 kb
Host smart-6e139c91-2c42-4d70-bcc7-3a397e6a4511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544908639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3544908639
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1799711699
Short name T1224
Test name
Test status
Simulation time 514455826 ps
CPU time 2.24 seconds
Started Dec 27 01:04:13 PM PST 23
Finished Dec 27 01:04:18 PM PST 23
Peak memory 198628 kb
Host smart-598e0e0b-932d-477d-9a6d-840193b1a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799711699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1799711699
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2425786389
Short name T61
Test name
Test status
Simulation time 72026055667 ps
CPU time 831.37 seconds
Started Dec 27 01:04:21 PM PST 23
Finished Dec 27 01:18:14 PM PST 23
Peak memory 216880 kb
Host smart-156a4dee-e931-4f82-930b-0beb44bd2ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425786389 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2425786389
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2115786562
Short name T698
Test name
Test status
Simulation time 7761135848 ps
CPU time 11.48 seconds
Started Dec 27 01:04:00 PM PST 23
Finished Dec 27 01:04:19 PM PST 23
Peak memory 199092 kb
Host smart-b7823fa4-9a84-42a1-ba12-4073ec915884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115786562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2115786562
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3444784784
Short name T154
Test name
Test status
Simulation time 42062653382 ps
CPU time 39.98 seconds
Started Dec 27 01:04:16 PM PST 23
Finished Dec 27 01:04:58 PM PST 23
Peak memory 200232 kb
Host smart-a6a1bceb-622c-45ca-8c6f-5c2a8594d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444784784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3444784784
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3603570547
Short name T176
Test name
Test status
Simulation time 155798362444 ps
CPU time 62.45 seconds
Started Dec 27 01:06:05 PM PST 23
Finished Dec 27 01:07:10 PM PST 23
Peak memory 200220 kb
Host smart-17d42ade-98f5-426b-a85d-172724e1675b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603570547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3603570547
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3253779597
Short name T107
Test name
Test status
Simulation time 82019415587 ps
CPU time 136.78 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:08:25 PM PST 23
Peak memory 200216 kb
Host smart-f204a294-1d23-47fc-adda-84e285bf29ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253779597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3253779597
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1350778498
Short name T626
Test name
Test status
Simulation time 83781525098 ps
CPU time 67.73 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:07:16 PM PST 23
Peak memory 200124 kb
Host smart-7b2e8bec-b475-4ca2-b6cb-3c81cdf4b32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350778498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1350778498
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1437385786
Short name T189
Test name
Test status
Simulation time 121132354638 ps
CPU time 103.19 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:07:52 PM PST 23
Peak memory 200000 kb
Host smart-11b2ff56-bb03-41ab-9379-d401bded63f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437385786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1437385786
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3915033919
Short name T453
Test name
Test status
Simulation time 41204975311 ps
CPU time 32.23 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:06:42 PM PST 23
Peak memory 200248 kb
Host smart-352014b8-b913-4ac5-8e94-1d1f109f7ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915033919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3915033919
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2724973307
Short name T1205
Test name
Test status
Simulation time 42443299326 ps
CPU time 55.32 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:07:03 PM PST 23
Peak memory 200168 kb
Host smart-d3ce165a-dcfd-42b3-82e8-dce643b94d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724973307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2724973307
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2422785229
Short name T857
Test name
Test status
Simulation time 79979503115 ps
CPU time 28.97 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:06:37 PM PST 23
Peak memory 199820 kb
Host smart-60daed16-0214-4135-9263-2b53fd3f5e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422785229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2422785229
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1838007416
Short name T876
Test name
Test status
Simulation time 43718751 ps
CPU time 0.54 seconds
Started Dec 27 01:04:17 PM PST 23
Finished Dec 27 01:04:20 PM PST 23
Peak memory 195580 kb
Host smart-d7a828a4-3e4a-4a2e-8237-201c699374bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838007416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1838007416
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3148805954
Short name T697
Test name
Test status
Simulation time 246303129701 ps
CPU time 72.95 seconds
Started Dec 27 01:04:09 PM PST 23
Finished Dec 27 01:05:29 PM PST 23
Peak memory 200244 kb
Host smart-4defb4a9-3783-4ed5-9fc7-fa86f1726786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148805954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3148805954
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2842290493
Short name T216
Test name
Test status
Simulation time 174733348382 ps
CPU time 95.56 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:06:34 PM PST 23
Peak memory 200068 kb
Host smart-fbd647b8-c5ed-4ad2-9892-d4ab4ea39c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842290493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2842290493
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1671260487
Short name T259
Test name
Test status
Simulation time 108675441637 ps
CPU time 10.09 seconds
Started Dec 27 01:04:14 PM PST 23
Finished Dec 27 01:04:27 PM PST 23
Peak memory 199620 kb
Host smart-c14b3eb7-5426-419e-963a-82d8320c8e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671260487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1671260487
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.509943913
Short name T24
Test name
Test status
Simulation time 354148099779 ps
CPU time 299.57 seconds
Started Dec 27 01:04:08 PM PST 23
Finished Dec 27 01:09:14 PM PST 23
Peak memory 200008 kb
Host smart-08c62f18-3046-45a3-a492-3d0e2eb757a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509943913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.509943913
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2270114285
Short name T1007
Test name
Test status
Simulation time 100681986592 ps
CPU time 793.65 seconds
Started Dec 27 01:04:20 PM PST 23
Finished Dec 27 01:17:35 PM PST 23
Peak memory 200196 kb
Host smart-1edc4511-f140-4922-bb7f-c5bd96aac442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270114285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2270114285
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.395809997
Short name T557
Test name
Test status
Simulation time 6642076526 ps
CPU time 7.53 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:05:06 PM PST 23
Peak memory 198640 kb
Host smart-fe8b4446-2780-4f46-a691-a5951f306594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395809997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.395809997
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1915819153
Short name T1104
Test name
Test status
Simulation time 135081570939 ps
CPU time 214.86 seconds
Started Dec 27 01:04:21 PM PST 23
Finished Dec 27 01:07:57 PM PST 23
Peak memory 208804 kb
Host smart-e1bc7a80-df5b-4321-8c82-4499cecfb53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915819153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1915819153
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1948417038
Short name T1032
Test name
Test status
Simulation time 11295557818 ps
CPU time 156.15 seconds
Started Dec 27 01:04:10 PM PST 23
Finished Dec 27 01:06:52 PM PST 23
Peak memory 200204 kb
Host smart-d9496c2e-69fe-4fa9-941e-a4c73b241fd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948417038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1948417038
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4068436386
Short name T28
Test name
Test status
Simulation time 2698468303 ps
CPU time 6.85 seconds
Started Dec 27 01:04:21 PM PST 23
Finished Dec 27 01:04:29 PM PST 23
Peak memory 198756 kb
Host smart-970ac03f-68d3-42b2-a0f1-074e46384de3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068436386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4068436386
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1955453996
Short name T34
Test name
Test status
Simulation time 36169487652 ps
CPU time 16.39 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 195684 kb
Host smart-ee856897-c671-4d1d-9642-a6e9fec11149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955453996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1955453996
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1059806596
Short name T617
Test name
Test status
Simulation time 283674635 ps
CPU time 1.11 seconds
Started Dec 27 01:04:24 PM PST 23
Finished Dec 27 01:04:27 PM PST 23
Peak memory 199092 kb
Host smart-fa9191bc-f4db-48c5-afd2-949bec0746aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059806596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1059806596
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.141431676
Short name T574
Test name
Test status
Simulation time 26280653961 ps
CPU time 47.39 seconds
Started Dec 27 01:04:11 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 200204 kb
Host smart-674141d7-4801-4e47-b046-6bd265acf55d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141431676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.141431676
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3960256238
Short name T975
Test name
Test status
Simulation time 217393499135 ps
CPU time 668.06 seconds
Started Dec 27 01:04:22 PM PST 23
Finished Dec 27 01:15:31 PM PST 23
Peak memory 227972 kb
Host smart-3640e55b-210b-4682-87f4-8a9f7fa69633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960256238 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3960256238
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3766607782
Short name T1021
Test name
Test status
Simulation time 2367894213 ps
CPU time 1.77 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:46 PM PST 23
Peak memory 198172 kb
Host smart-1ed2f7f0-8bc4-4f47-9367-50f434819bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766607782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3766607782
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2161831295
Short name T837
Test name
Test status
Simulation time 10124995898 ps
CPU time 15.51 seconds
Started Dec 27 01:04:23 PM PST 23
Finished Dec 27 01:04:40 PM PST 23
Peak memory 198312 kb
Host smart-193ea362-0d72-4f5a-b375-8498780994c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161831295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2161831295
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1028817786
Short name T155
Test name
Test status
Simulation time 7321938043 ps
CPU time 13.8 seconds
Started Dec 27 01:06:09 PM PST 23
Finished Dec 27 01:06:25 PM PST 23
Peak memory 199956 kb
Host smart-b85f7e8a-63f2-44d4-8755-b04e7d454df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028817786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1028817786
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3369493316
Short name T257
Test name
Test status
Simulation time 22823927882 ps
CPU time 20.29 seconds
Started Dec 27 01:06:09 PM PST 23
Finished Dec 27 01:06:32 PM PST 23
Peak memory 200176 kb
Host smart-1161b0a0-3390-4be2-918b-aaca434d3eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369493316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3369493316
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2540822173
Short name T908
Test name
Test status
Simulation time 148811861419 ps
CPU time 63.43 seconds
Started Dec 27 01:06:12 PM PST 23
Finished Dec 27 01:07:18 PM PST 23
Peak memory 200200 kb
Host smart-9c780573-cf8c-4c77-91f5-bf4ae9615566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540822173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2540822173
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2715634642
Short name T197
Test name
Test status
Simulation time 45378724808 ps
CPU time 33.48 seconds
Started Dec 27 01:06:09 PM PST 23
Finished Dec 27 01:06:45 PM PST 23
Peak memory 200168 kb
Host smart-da1f8bd8-d159-4201-bb2d-1df751775b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715634642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2715634642
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.202986543
Short name T249
Test name
Test status
Simulation time 188490789551 ps
CPU time 49.79 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:06:59 PM PST 23
Peak memory 200124 kb
Host smart-2284d948-9327-4512-b402-3ef702cc9f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202986543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.202986543
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1327967460
Short name T243
Test name
Test status
Simulation time 63246894432 ps
CPU time 20.54 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:06:31 PM PST 23
Peak memory 200232 kb
Host smart-eb5d64c3-c516-473d-976e-0c81b3648e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327967460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1327967460
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2099156763
Short name T326
Test name
Test status
Simulation time 10380784928 ps
CPU time 17.08 seconds
Started Dec 27 01:06:07 PM PST 23
Finished Dec 27 01:06:27 PM PST 23
Peak memory 200108 kb
Host smart-edf8f630-e9e0-4757-bac5-9d9c48223cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099156763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2099156763
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.980691341
Short name T1010
Test name
Test status
Simulation time 21623893 ps
CPU time 0.54 seconds
Started Dec 27 01:04:16 PM PST 23
Finished Dec 27 01:04:18 PM PST 23
Peak memory 194624 kb
Host smart-dcbc2daf-fb87-4188-955b-c4f731480d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980691341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.980691341
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1564841512
Short name T923
Test name
Test status
Simulation time 55197131919 ps
CPU time 49.03 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:05:31 PM PST 23
Peak memory 200192 kb
Host smart-06a329d1-19f6-4bf5-b3b4-65fe13591441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564841512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1564841512
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.384627558
Short name T1055
Test name
Test status
Simulation time 80869595117 ps
CPU time 124.07 seconds
Started Dec 27 01:04:18 PM PST 23
Finished Dec 27 01:06:24 PM PST 23
Peak memory 200220 kb
Host smart-cb76b349-6b75-4a18-9bfe-d923ca53879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384627558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.384627558
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1989802264
Short name T134
Test name
Test status
Simulation time 42161301675 ps
CPU time 65.5 seconds
Started Dec 27 01:04:10 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 200200 kb
Host smart-ad2d8e68-baa6-4f76-8bf5-57dbd87712ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989802264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1989802264
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.204691008
Short name T669
Test name
Test status
Simulation time 306158056949 ps
CPU time 590.19 seconds
Started Dec 27 01:04:21 PM PST 23
Finished Dec 27 01:14:12 PM PST 23
Peak memory 200228 kb
Host smart-f8d3c17f-a2f0-4e5a-a7d4-85a6fd0b606c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204691008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.204691008
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4159428780
Short name T783
Test name
Test status
Simulation time 89655424869 ps
CPU time 550.8 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:13:56 PM PST 23
Peak memory 200208 kb
Host smart-30d2efb2-93b2-4825-8abd-e2febdd7afbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159428780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4159428780
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.848908404
Short name T1166
Test name
Test status
Simulation time 4275166162 ps
CPU time 2.55 seconds
Started Dec 27 01:04:21 PM PST 23
Finished Dec 27 01:04:25 PM PST 23
Peak memory 197596 kb
Host smart-d378b71a-e2b4-4694-be71-edae365e0803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848908404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.848908404
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1868723372
Short name T832
Test name
Test status
Simulation time 71265319485 ps
CPU time 129.27 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:06:53 PM PST 23
Peak memory 208744 kb
Host smart-b1f35d66-3609-4308-8ba7-688073fea6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868723372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1868723372
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2658960771
Short name T686
Test name
Test status
Simulation time 16431540736 ps
CPU time 126.52 seconds
Started Dec 27 01:04:18 PM PST 23
Finished Dec 27 01:06:27 PM PST 23
Peak memory 200264 kb
Host smart-1e2e3613-9404-445c-91fc-2f8b45650be7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658960771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2658960771
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.32584394
Short name T531
Test name
Test status
Simulation time 514658373 ps
CPU time 1.63 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:48 PM PST 23
Peak memory 197860 kb
Host smart-cc15ecc9-c17b-4910-adf4-f094601eb033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32584394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.32584394
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3573713249
Short name T268
Test name
Test status
Simulation time 88602632869 ps
CPU time 37.72 seconds
Started Dec 27 01:04:23 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 199892 kb
Host smart-9dc2dc06-2592-4fdd-95f6-02323c9e095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573713249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3573713249
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1374864582
Short name T1132
Test name
Test status
Simulation time 2405354353 ps
CPU time 4.56 seconds
Started Dec 27 01:04:15 PM PST 23
Finished Dec 27 01:04:21 PM PST 23
Peak memory 195784 kb
Host smart-620c53ec-ebd7-4d38-9bbf-79149a91c9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374864582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1374864582
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2306092364
Short name T443
Test name
Test status
Simulation time 1001327764 ps
CPU time 1.72 seconds
Started Dec 27 01:04:22 PM PST 23
Finished Dec 27 01:04:24 PM PST 23
Peak memory 198124 kb
Host smart-6b6d83dd-c162-48f9-b92c-9c35fbb785b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306092364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2306092364
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2132167720
Short name T1000
Test name
Test status
Simulation time 63960197856 ps
CPU time 314.81 seconds
Started Dec 27 01:04:34 PM PST 23
Finished Dec 27 01:09:53 PM PST 23
Peak memory 216828 kb
Host smart-17cdbe2c-263b-4719-870c-6633a11f76f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132167720 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2132167720
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1414324982
Short name T430
Test name
Test status
Simulation time 6776924205 ps
CPU time 19.59 seconds
Started Dec 27 01:04:22 PM PST 23
Finished Dec 27 01:04:42 PM PST 23
Peak memory 199448 kb
Host smart-7ef46167-c1b4-4a02-a5a3-6b2f46516ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414324982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1414324982
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1987886120
Short name T416
Test name
Test status
Simulation time 49637259418 ps
CPU time 82.5 seconds
Started Dec 27 01:04:15 PM PST 23
Finished Dec 27 01:05:39 PM PST 23
Peak memory 200196 kb
Host smart-e9910913-c1b2-4426-9a36-dfea434f3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987886120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1987886120
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1506438718
Short name T752
Test name
Test status
Simulation time 93291700468 ps
CPU time 42.13 seconds
Started Dec 27 01:06:11 PM PST 23
Finished Dec 27 01:06:56 PM PST 23
Peak memory 200192 kb
Host smart-fde511d2-2ac3-4418-941a-c5b7b12e6285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506438718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1506438718
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3630379420
Short name T142
Test name
Test status
Simulation time 22706518526 ps
CPU time 51.09 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:07:04 PM PST 23
Peak memory 200168 kb
Host smart-e220bdea-9368-45aa-b421-11298766c450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630379420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3630379420
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.886161747
Short name T1011
Test name
Test status
Simulation time 18629496859 ps
CPU time 15.56 seconds
Started Dec 27 01:06:09 PM PST 23
Finished Dec 27 01:06:27 PM PST 23
Peak memory 198908 kb
Host smart-0e4b852d-7478-471e-b746-f3413769f152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886161747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.886161747
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.331403689
Short name T112
Test name
Test status
Simulation time 32452292103 ps
CPU time 40.43 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:06:54 PM PST 23
Peak memory 200092 kb
Host smart-11e9a7fb-e569-43d2-a309-7cbe83a9ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331403689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.331403689
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.259353011
Short name T193
Test name
Test status
Simulation time 111216635255 ps
CPU time 76.61 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:07:30 PM PST 23
Peak memory 200184 kb
Host smart-6da69666-7c0b-494b-b5ec-f2d67b9cf92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259353011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.259353011
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1623103594
Short name T1061
Test name
Test status
Simulation time 146766854380 ps
CPU time 61.13 seconds
Started Dec 27 01:06:08 PM PST 23
Finished Dec 27 01:07:11 PM PST 23
Peak memory 200020 kb
Host smart-1088291a-87d2-422c-b619-7ac2ee356abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623103594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1623103594
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3758601503
Short name T361
Test name
Test status
Simulation time 21544184593 ps
CPU time 29.35 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:06:42 PM PST 23
Peak memory 200272 kb
Host smart-755f2140-8dd0-48d4-aef6-790de1f014bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758601503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3758601503
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.396926402
Short name T823
Test name
Test status
Simulation time 29417195914 ps
CPU time 54.42 seconds
Started Dec 27 01:06:15 PM PST 23
Finished Dec 27 01:07:12 PM PST 23
Peak memory 200272 kb
Host smart-f155ac76-3718-4bf3-9cc9-15404ed62287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396926402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.396926402
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.729341914
Short name T1025
Test name
Test status
Simulation time 33764979 ps
CPU time 0.6 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:04 PM PST 23
Peak memory 195600 kb
Host smart-944a9ade-0643-484a-8f95-5da1c6d7c801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729341914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.729341914
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2533013340
Short name T986
Test name
Test status
Simulation time 126612141303 ps
CPU time 44.01 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:05:31 PM PST 23
Peak memory 200140 kb
Host smart-b17763df-c2c1-4265-bed1-00ef366f6b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533013340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2533013340
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3249845415
Short name T196
Test name
Test status
Simulation time 28535751077 ps
CPU time 46.01 seconds
Started Dec 27 01:04:20 PM PST 23
Finished Dec 27 01:05:07 PM PST 23
Peak memory 199344 kb
Host smart-6135a605-ff78-479f-9c0d-d9102174a29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249845415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3249845415
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1214836085
Short name T275
Test name
Test status
Simulation time 81109375933 ps
CPU time 59.55 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:06:04 PM PST 23
Peak memory 200188 kb
Host smart-fec93193-2777-468c-b3db-87efb152c34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214836085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1214836085
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2538299099
Short name T650
Test name
Test status
Simulation time 186844551288 ps
CPU time 293.63 seconds
Started Dec 27 01:04:35 PM PST 23
Finished Dec 27 01:09:32 PM PST 23
Peak memory 200164 kb
Host smart-81f12891-242d-4969-a294-1bb172b4b34a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538299099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2538299099
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3671457370
Short name T1217
Test name
Test status
Simulation time 275924737796 ps
CPU time 134.44 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:06:59 PM PST 23
Peak memory 200176 kb
Host smart-88885648-cb7d-471a-a394-d9b91a3ea17e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671457370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3671457370
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.4148423749
Short name T13
Test name
Test status
Simulation time 8113050474 ps
CPU time 5 seconds
Started Dec 27 01:04:48 PM PST 23
Finished Dec 27 01:04:59 PM PST 23
Peak memory 199260 kb
Host smart-dec21d6b-e4e6-435e-ad18-248a3ddf0ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148423749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.4148423749
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.4019123068
Short name T1052
Test name
Test status
Simulation time 69240987358 ps
CPU time 115.86 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:06:39 PM PST 23
Peak memory 199508 kb
Host smart-4a9a3d5a-86d8-400a-bc77-ef968a8e2db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019123068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.4019123068
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1750194565
Short name T806
Test name
Test status
Simulation time 18314054050 ps
CPU time 438.85 seconds
Started Dec 27 01:04:48 PM PST 23
Finished Dec 27 01:12:13 PM PST 23
Peak memory 200164 kb
Host smart-ab1c0415-a2d3-499c-99d1-1683e179031a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750194565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1750194565
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2359524453
Short name T512
Test name
Test status
Simulation time 1579523079 ps
CPU time 5.09 seconds
Started Dec 27 01:04:35 PM PST 23
Finished Dec 27 01:04:45 PM PST 23
Peak memory 198224 kb
Host smart-16b4de88-ec2c-4147-8012-e4d753536929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359524453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2359524453
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3810887837
Short name T386
Test name
Test status
Simulation time 15446261326 ps
CPU time 29.14 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:26 PM PST 23
Peak memory 200288 kb
Host smart-daec8792-80cb-4d9e-b193-eb1da2d93fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810887837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3810887837
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2003533841
Short name T567
Test name
Test status
Simulation time 36657057938 ps
CPU time 18.09 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:05:04 PM PST 23
Peak memory 195704 kb
Host smart-ffe89f9a-609d-470b-8e9b-eeaeff41a313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003533841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2003533841
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1450354789
Short name T1054
Test name
Test status
Simulation time 949922987 ps
CPU time 2.39 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:04:58 PM PST 23
Peak memory 198568 kb
Host smart-762c68a5-26b0-4dfe-a45a-0d1118e45290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450354789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1450354789
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.4128475799
Short name T163
Test name
Test status
Simulation time 340992275437 ps
CPU time 144.15 seconds
Started Dec 27 01:05:05 PM PST 23
Finished Dec 27 01:07:39 PM PST 23
Peak memory 200280 kb
Host smart-2876e8f6-d635-47a5-922e-9645ae4a218a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128475799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4128475799
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2739631068
Short name T705
Test name
Test status
Simulation time 93713852018 ps
CPU time 1214.05 seconds
Started Dec 27 01:04:48 PM PST 23
Finished Dec 27 01:25:08 PM PST 23
Peak memory 227336 kb
Host smart-3aa74ca5-5db5-40dd-8180-fcf737ed72be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739631068 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2739631068
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2126928294
Short name T536
Test name
Test status
Simulation time 1288338822 ps
CPU time 2.15 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 198196 kb
Host smart-6652a37f-458b-4b82-90bb-cfa453e94960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126928294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2126928294
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.76098599
Short name T770
Test name
Test status
Simulation time 31870824534 ps
CPU time 25.74 seconds
Started Dec 27 01:04:22 PM PST 23
Finished Dec 27 01:04:48 PM PST 23
Peak memory 200200 kb
Host smart-f29038fd-af15-45fb-b99c-a147d21997fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76098599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.76098599
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3063555881
Short name T990
Test name
Test status
Simulation time 21601843165 ps
CPU time 41.48 seconds
Started Dec 27 01:06:15 PM PST 23
Finished Dec 27 01:06:59 PM PST 23
Peak memory 200268 kb
Host smart-137e8e33-773b-4c0c-9906-3e219415f01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063555881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3063555881
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.249381573
Short name T1109
Test name
Test status
Simulation time 219858646313 ps
CPU time 170.13 seconds
Started Dec 27 01:06:11 PM PST 23
Finished Dec 27 01:09:04 PM PST 23
Peak memory 200152 kb
Host smart-cb5668ad-3d26-4965-95cc-d79943e5fd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249381573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.249381573
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2330534269
Short name T162
Test name
Test status
Simulation time 59713301025 ps
CPU time 55.37 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:07:09 PM PST 23
Peak memory 200156 kb
Host smart-1ff8cb9b-d509-4383-97be-b1feaa85b571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330534269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2330534269
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.226512569
Short name T1185
Test name
Test status
Simulation time 105770430770 ps
CPU time 176.33 seconds
Started Dec 27 01:06:18 PM PST 23
Finished Dec 27 01:09:15 PM PST 23
Peak memory 200268 kb
Host smart-76463235-f659-4cb0-b6e5-25512489d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226512569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.226512569
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3262295101
Short name T252
Test name
Test status
Simulation time 90870619282 ps
CPU time 323.85 seconds
Started Dec 27 01:06:12 PM PST 23
Finished Dec 27 01:11:38 PM PST 23
Peak memory 200268 kb
Host smart-6c7a0bbf-cce8-4cec-9630-7489d9848a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262295101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3262295101
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1698290635
Short name T1013
Test name
Test status
Simulation time 57497856501 ps
CPU time 18.09 seconds
Started Dec 27 01:06:13 PM PST 23
Finished Dec 27 01:06:34 PM PST 23
Peak memory 198936 kb
Host smart-6d9ff990-0711-495e-a8cd-ffacde033918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698290635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1698290635
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.499038702
Short name T390
Test name
Test status
Simulation time 110912521016 ps
CPU time 84.59 seconds
Started Dec 27 01:06:23 PM PST 23
Finished Dec 27 01:07:53 PM PST 23
Peak memory 200260 kb
Host smart-fe810919-ee91-4b6c-bb85-9847b2c8a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499038702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.499038702
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1425223190
Short name T725
Test name
Test status
Simulation time 21851798 ps
CPU time 0.53 seconds
Started Dec 27 01:04:59 PM PST 23
Finished Dec 27 01:05:12 PM PST 23
Peak memory 194600 kb
Host smart-4100482c-599c-47f5-b411-881dd5c573d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425223190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1425223190
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.4048931456
Short name T420
Test name
Test status
Simulation time 33978764459 ps
CPU time 27.64 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:05:45 PM PST 23
Peak memory 200260 kb
Host smart-98e83250-70d2-4223-a0e0-72b84afab7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048931456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.4048931456
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3801280443
Short name T796
Test name
Test status
Simulation time 32778884850 ps
CPU time 51.16 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:05:57 PM PST 23
Peak memory 199440 kb
Host smart-63331e24-58b0-4581-bcd2-b0c58379846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801280443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3801280443
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.4140850863
Short name T319
Test name
Test status
Simulation time 35769697391 ps
CPU time 53.27 seconds
Started Dec 27 01:04:16 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 200192 kb
Host smart-56946c84-e876-49ef-989c-d24476be6c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140850863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.4140850863
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1515762650
Short name T569
Test name
Test status
Simulation time 428484572085 ps
CPU time 165.83 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:08:00 PM PST 23
Peak memory 196664 kb
Host smart-a628619d-d4d5-42b0-9626-3d3fce24495c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515762650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1515762650
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.786336876
Short name T849
Test name
Test status
Simulation time 121374705996 ps
CPU time 196.91 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:08:18 PM PST 23
Peak memory 200148 kb
Host smart-dea66d7c-fea5-4213-8265-54f723c05644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786336876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.786336876
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1419028305
Short name T843
Test name
Test status
Simulation time 111954004 ps
CPU time 0.76 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:05:09 PM PST 23
Peak memory 196672 kb
Host smart-48566d09-508f-4f25-aa24-ea47359e2074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419028305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1419028305
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2221019262
Short name T997
Test name
Test status
Simulation time 314015799870 ps
CPU time 215.62 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:08:42 PM PST 23
Peak memory 200508 kb
Host smart-f8e440d4-763c-4985-a856-f2dc4cc0560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221019262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2221019262
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.664400176
Short name T212
Test name
Test status
Simulation time 20914969326 ps
CPU time 299.7 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:10:08 PM PST 23
Peak memory 200180 kb
Host smart-3f573088-eb88-4182-b224-f35eb9be7160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664400176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.664400176
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3936631509
Short name T680
Test name
Test status
Simulation time 1740946865 ps
CPU time 14.61 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 198356 kb
Host smart-a9f2c9a0-6b9d-452d-b3fb-e49e2752831f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936631509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3936631509
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3954545882
Short name T1214
Test name
Test status
Simulation time 62724004401 ps
CPU time 38.6 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:05:36 PM PST 23
Peak memory 200116 kb
Host smart-1c2102af-d8b9-4560-ab70-380e7485ca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954545882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3954545882
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1887277090
Short name T447
Test name
Test status
Simulation time 24769557298 ps
CPU time 34.43 seconds
Started Dec 27 01:04:22 PM PST 23
Finished Dec 27 01:04:58 PM PST 23
Peak memory 196012 kb
Host smart-a1ce649e-2d87-42bf-a849-2ca79e0120b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887277090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1887277090
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2784655422
Short name T933
Test name
Test status
Simulation time 11114253090 ps
CPU time 9.52 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:11 PM PST 23
Peak memory 200232 kb
Host smart-f14ab3b8-9294-4c12-bdaf-6dc7c0958111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784655422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2784655422
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.588268553
Short name T1068
Test name
Test status
Simulation time 93988145057 ps
CPU time 189.43 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:08:15 PM PST 23
Peak memory 208540 kb
Host smart-95bcfe8d-9c77-4362-a938-a8a395de869c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588268553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.588268553
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.716346081
Short name T620
Test name
Test status
Simulation time 7182505985 ps
CPU time 14.07 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 199740 kb
Host smart-1c6d2b54-45f7-4d9e-8e26-8523ecc8dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716346081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.716346081
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3206384477
Short name T423
Test name
Test status
Simulation time 115257555094 ps
CPU time 46.4 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:06:03 PM PST 23
Peak memory 200176 kb
Host smart-4eb8d764-5249-431c-a846-22c560c80fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206384477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3206384477
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3103712939
Short name T217
Test name
Test status
Simulation time 111834358706 ps
CPU time 87.45 seconds
Started Dec 27 01:06:13 PM PST 23
Finished Dec 27 01:07:43 PM PST 23
Peak memory 200008 kb
Host smart-bd9a46e4-d293-4537-aef4-ebda715e70d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103712939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3103712939
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1107625847
Short name T150
Test name
Test status
Simulation time 21364166115 ps
CPU time 32.95 seconds
Started Dec 27 01:06:10 PM PST 23
Finished Dec 27 01:06:46 PM PST 23
Peak memory 200172 kb
Host smart-62824d0d-723c-4b70-bc99-f0161e85ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107625847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1107625847
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.689331908
Short name T302
Test name
Test status
Simulation time 15559658006 ps
CPU time 22.7 seconds
Started Dec 27 01:06:13 PM PST 23
Finished Dec 27 01:06:38 PM PST 23
Peak memory 198392 kb
Host smart-9b03cccb-2aa9-47a1-b3de-6886ef88fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689331908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.689331908
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.537033066
Short name T392
Test name
Test status
Simulation time 13449256781 ps
CPU time 21.23 seconds
Started Dec 27 01:06:22 PM PST 23
Finished Dec 27 01:06:48 PM PST 23
Peak memory 200192 kb
Host smart-8956cf86-505d-46d0-82a4-25eee81b7935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537033066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.537033066
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.506678371
Short name T209
Test name
Test status
Simulation time 116638912497 ps
CPU time 32.88 seconds
Started Dec 27 01:06:23 PM PST 23
Finished Dec 27 01:07:01 PM PST 23
Peak memory 200228 kb
Host smart-6f9835e4-cd01-40d8-8eb7-564efafe8e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506678371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.506678371
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1316660671
Short name T866
Test name
Test status
Simulation time 71860002441 ps
CPU time 32.72 seconds
Started Dec 27 01:06:21 PM PST 23
Finished Dec 27 01:06:55 PM PST 23
Peak memory 200108 kb
Host smart-46f08d80-adf0-4c46-aeb3-6515dcd765e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316660671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1316660671
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.4283018724
Short name T763
Test name
Test status
Simulation time 93217646328 ps
CPU time 136 seconds
Started Dec 27 01:06:11 PM PST 23
Finished Dec 27 01:08:30 PM PST 23
Peak memory 199764 kb
Host smart-ab5e9fc9-9f93-4b07-9e61-bcfc08e932a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283018724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4283018724
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2960985909
Short name T290
Test name
Test status
Simulation time 59498570048 ps
CPU time 118.03 seconds
Started Dec 27 01:06:06 PM PST 23
Finished Dec 27 01:08:06 PM PST 23
Peak memory 200256 kb
Host smart-1ffd8c99-4e2f-4ca0-aa68-740e25b94358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960985909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2960985909
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3692514121
Short name T170
Test name
Test status
Simulation time 34863725595 ps
CPU time 53.45 seconds
Started Dec 27 01:06:26 PM PST 23
Finished Dec 27 01:07:25 PM PST 23
Peak memory 200224 kb
Host smart-8faedb94-0e5d-4597-b7b1-10663046fdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692514121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3692514121
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1974128229
Short name T1097
Test name
Test status
Simulation time 57125853 ps
CPU time 0.56 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:25 PM PST 23
Peak memory 195608 kb
Host smart-3531c494-a206-4949-8fb2-d0be5afafc5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974128229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1974128229
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3253308403
Short name T1083
Test name
Test status
Simulation time 47001769204 ps
CPU time 19.4 seconds
Started Dec 27 01:03:16 PM PST 23
Finished Dec 27 01:03:41 PM PST 23
Peak memory 200236 kb
Host smart-c7615977-5b88-4938-81f8-0f475a59721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253308403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3253308403
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.119743282
Short name T891
Test name
Test status
Simulation time 152828383622 ps
CPU time 39.7 seconds
Started Dec 27 01:03:22 PM PST 23
Finished Dec 27 01:04:04 PM PST 23
Peak memory 200200 kb
Host smart-5e92346f-c2e4-4ab7-95e8-fcf38e2a362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119743282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.119743282
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2789230777
Short name T21
Test name
Test status
Simulation time 130547422675 ps
CPU time 59.21 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:04:35 PM PST 23
Peak memory 200296 kb
Host smart-cea8205a-43fc-49ec-959a-5769c4f1beba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789230777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2789230777
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.506755419
Short name T604
Test name
Test status
Simulation time 26362207347 ps
CPU time 27.91 seconds
Started Dec 27 01:03:14 PM PST 23
Finished Dec 27 01:03:49 PM PST 23
Peak memory 199640 kb
Host smart-efa34119-d300-4342-8afe-5d5d9f86eb5a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506755419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.506755419
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3987819815
Short name T1019
Test name
Test status
Simulation time 99642696097 ps
CPU time 197.24 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:06:41 PM PST 23
Peak memory 200120 kb
Host smart-5644eb59-0c33-4830-9824-c78661a8ebb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987819815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3987819815
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1466323426
Short name T91
Test name
Test status
Simulation time 183260732134 ps
CPU time 98.04 seconds
Started Dec 27 01:03:24 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 208692 kb
Host smart-29266460-612a-4c76-a288-209177d7c9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466323426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1466323426
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2929402918
Short name T428
Test name
Test status
Simulation time 17291535871 ps
CPU time 203.62 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:06:59 PM PST 23
Peak memory 200180 kb
Host smart-66103d5e-5f9d-4126-adee-815af98326c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929402918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2929402918
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3564286776
Short name T1189
Test name
Test status
Simulation time 145030586 ps
CPU time 0.66 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:25 PM PST 23
Peak memory 195720 kb
Host smart-e4845199-a6eb-4c21-9a44-5aa2e6e91154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564286776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3564286776
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.686965744
Short name T677
Test name
Test status
Simulation time 110623779603 ps
CPU time 38.95 seconds
Started Dec 27 01:03:21 PM PST 23
Finished Dec 27 01:04:02 PM PST 23
Peak memory 200088 kb
Host smart-566c813b-aecd-4a75-affa-c874e70fe4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686965744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.686965744
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3515005924
Short name T1008
Test name
Test status
Simulation time 3389025281 ps
CPU time 1.76 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:26 PM PST 23
Peak memory 195988 kb
Host smart-85470038-fb38-4629-9e61-7e17a35b55b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515005924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3515005924
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.4029001614
Short name T75
Test name
Test status
Simulation time 145311470 ps
CPU time 0.79 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:03:35 PM PST 23
Peak memory 218704 kb
Host smart-ce64de00-d2c0-4613-b850-9b940f537dc4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029001614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.4029001614
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.197437329
Short name T415
Test name
Test status
Simulation time 5360961956 ps
CPU time 14.34 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:39 PM PST 23
Peak memory 200220 kb
Host smart-a3774b9f-a406-4dfe-a9bc-78f90627a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197437329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.197437329
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2748409225
Short name T953
Test name
Test status
Simulation time 127588545978 ps
CPU time 692.22 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:15:06 PM PST 23
Peak memory 216788 kb
Host smart-3cbe4ce8-e9a7-41df-bf69-34e8ea178b71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748409225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2748409225
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.943048263
Short name T810
Test name
Test status
Simulation time 1467366817 ps
CPU time 1.38 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:26 PM PST 23
Peak memory 197712 kb
Host smart-352eca15-6091-4f00-bad1-b1855ac9eaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943048263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.943048263
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2513781699
Short name T646
Test name
Test status
Simulation time 72277644684 ps
CPU time 155.69 seconds
Started Dec 27 01:03:15 PM PST 23
Finished Dec 27 01:05:57 PM PST 23
Peak memory 200280 kb
Host smart-77e79536-ea98-47f6-9243-ba3c6ed7c23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513781699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2513781699
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4013127785
Short name T1090
Test name
Test status
Simulation time 10856731 ps
CPU time 0.55 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 194588 kb
Host smart-5d8d8fbd-87e0-4f82-aac9-c465022f2afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013127785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4013127785
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2448692534
Short name T167
Test name
Test status
Simulation time 78737739498 ps
CPU time 114.59 seconds
Started Dec 27 01:05:01 PM PST 23
Finished Dec 27 01:07:07 PM PST 23
Peak memory 200188 kb
Host smart-5a31cde5-d16f-47b3-b7db-7c31222a9f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448692534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2448692534
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.290947988
Short name T1145
Test name
Test status
Simulation time 140118135382 ps
CPU time 195.45 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:08:31 PM PST 23
Peak memory 199312 kb
Host smart-828b39f2-d325-4853-ab96-cae545e53ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290947988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.290947988
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1497061298
Short name T540
Test name
Test status
Simulation time 29117526804 ps
CPU time 52.1 seconds
Started Dec 27 01:04:25 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 200196 kb
Host smart-20cfd60c-7485-40cf-afa3-44590b810796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497061298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1497061298
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2853123216
Short name T461
Test name
Test status
Simulation time 118780036875 ps
CPU time 13.74 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:59 PM PST 23
Peak memory 199960 kb
Host smart-153585cf-fd6b-40f7-aaf0-36e3ae24b64d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853123216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2853123216
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2746470773
Short name T559
Test name
Test status
Simulation time 59039301089 ps
CPU time 100.82 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:06:31 PM PST 23
Peak memory 200244 kb
Host smart-ea9b098a-8b03-47e5-98a0-5397bfbcfcd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746470773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2746470773
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3433692743
Short name T722
Test name
Test status
Simulation time 8652297061 ps
CPU time 18.55 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 199776 kb
Host smart-0812c580-ccc8-4dfa-83db-704eeb122692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433692743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3433692743
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.663049804
Short name T1183
Test name
Test status
Simulation time 71217488728 ps
CPU time 31.33 seconds
Started Dec 27 01:04:21 PM PST 23
Finished Dec 27 01:04:54 PM PST 23
Peak memory 199744 kb
Host smart-a32d387d-e4ce-4e6c-a482-0a2b5b9b246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663049804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.663049804
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2703742201
Short name T952
Test name
Test status
Simulation time 21641360901 ps
CPU time 119.63 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:06:48 PM PST 23
Peak memory 199924 kb
Host smart-5fb44ea4-eb68-4b3b-833f-af85e9807747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703742201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2703742201
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3343423054
Short name T1119
Test name
Test status
Simulation time 3932169765 ps
CPU time 31.99 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:05:41 PM PST 23
Peak memory 198200 kb
Host smart-07ccb319-57b7-47ea-8c3a-fddf6f44f961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343423054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3343423054
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3978107411
Short name T652
Test name
Test status
Simulation time 81865761852 ps
CPU time 124.57 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:07:00 PM PST 23
Peak memory 200156 kb
Host smart-2357d9bc-cc87-494e-8cb7-fbb963c4faf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978107411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3978107411
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1855961987
Short name T608
Test name
Test status
Simulation time 86410366882 ps
CPU time 55.94 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:57 PM PST 23
Peak memory 196020 kb
Host smart-1e2a9b0a-dc6b-4e48-80c9-66af8e204f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855961987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1855961987
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1873924519
Short name T965
Test name
Test status
Simulation time 5381751800 ps
CPU time 21.88 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:05:44 PM PST 23
Peak memory 199696 kb
Host smart-ef2439db-739c-4723-9ba0-c81ceef74c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873924519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1873924519
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.325587118
Short name T464
Test name
Test status
Simulation time 50764066193 ps
CPU time 561.11 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:14:04 PM PST 23
Peak memory 216580 kb
Host smart-09903974-fd5f-41af-b806-70ce6045d12c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325587118 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.325587118
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3435725518
Short name T588
Test name
Test status
Simulation time 1111349362 ps
CPU time 5.99 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:05:01 PM PST 23
Peak memory 198256 kb
Host smart-ac633e99-951f-4656-bf24-c80f99599091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435725518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3435725518
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2211659573
Short name T944
Test name
Test status
Simulation time 69282838189 ps
CPU time 132.47 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:07:36 PM PST 23
Peak memory 200116 kb
Host smart-b00ccf4d-c501-4dce-be32-bf85687e3904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211659573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2211659573
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1509004985
Short name T890
Test name
Test status
Simulation time 16448889 ps
CPU time 0.61 seconds
Started Dec 27 01:04:25 PM PST 23
Finished Dec 27 01:04:27 PM PST 23
Peak memory 195580 kb
Host smart-686281a8-1031-404c-a759-d791f44fcbf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509004985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1509004985
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3086252839
Short name T1095
Test name
Test status
Simulation time 36351875160 ps
CPU time 56.04 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:05:39 PM PST 23
Peak memory 200184 kb
Host smart-4c40b901-6516-44c9-b715-077a82e4f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086252839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3086252839
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.782295220
Short name T757
Test name
Test status
Simulation time 250489288739 ps
CPU time 104.21 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:06:28 PM PST 23
Peak memory 198884 kb
Host smart-6d4161f1-c31e-4d96-ab6c-5cacace8d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782295220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.782295220
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1570157207
Short name T1029
Test name
Test status
Simulation time 136085187963 ps
CPU time 60.86 seconds
Started Dec 27 01:05:05 PM PST 23
Finished Dec 27 01:06:15 PM PST 23
Peak memory 200216 kb
Host smart-c585ed82-2b15-4eaf-ab7f-ddb6e444c87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570157207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1570157207
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1405206238
Short name T836
Test name
Test status
Simulation time 108803515026 ps
CPU time 22.25 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:26 PM PST 23
Peak memory 199336 kb
Host smart-61994d73-d87e-46a6-aa1d-016a3b1d7880
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405206238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1405206238
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1928294528
Short name T1041
Test name
Test status
Simulation time 134107636229 ps
CPU time 988.3 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:21:23 PM PST 23
Peak memory 200204 kb
Host smart-a4ace762-2791-4c3e-a043-b321d8a10c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928294528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1928294528
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2566994182
Short name T715
Test name
Test status
Simulation time 8229864689 ps
CPU time 8.59 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 199560 kb
Host smart-0d833d02-e88e-4821-8f06-61f302d73f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566994182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2566994182
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3089025130
Short name T1085
Test name
Test status
Simulation time 83298888951 ps
CPU time 134.9 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:07:03 PM PST 23
Peak memory 200444 kb
Host smart-c0e9b842-faed-44f7-b7e0-248739a093c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089025130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3089025130
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2000727108
Short name T657
Test name
Test status
Simulation time 27865086454 ps
CPU time 91.1 seconds
Started Dec 27 01:04:39 PM PST 23
Finished Dec 27 01:06:20 PM PST 23
Peak memory 200244 kb
Host smart-7781ed07-629c-43dc-ac05-fe35f614c55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000727108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2000727108
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1675381965
Short name T395
Test name
Test status
Simulation time 160306786932 ps
CPU time 50.75 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:05:33 PM PST 23
Peak memory 200224 kb
Host smart-b4c81cf2-8b63-4037-b6a0-cb3c1d9ab68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675381965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1675381965
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2895227174
Short name T916
Test name
Test status
Simulation time 29508983497 ps
CPU time 9.75 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:05:07 PM PST 23
Peak memory 196072 kb
Host smart-26cc5d13-a836-44fc-8c16-34f4a2f36a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895227174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2895227174
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1956596917
Short name T845
Test name
Test status
Simulation time 746234299 ps
CPU time 1.47 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:04:43 PM PST 23
Peak memory 198376 kb
Host smart-166eab1d-6c59-4d08-a79a-8a8232423c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956596917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1956596917
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1253467883
Short name T25
Test name
Test status
Simulation time 730525512457 ps
CPU time 333.42 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:10:31 PM PST 23
Peak memory 200232 kb
Host smart-9bcf72f2-5ba8-4544-aa8c-eee08d60f227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253467883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1253467883
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.4019772873
Short name T1022
Test name
Test status
Simulation time 78438728791 ps
CPU time 215.24 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:08:30 PM PST 23
Peak memory 204744 kb
Host smart-7c576421-4f5a-45df-b28d-a1ffb427d60e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019772873 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.4019772873
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3865876008
Short name T788
Test name
Test status
Simulation time 6747978376 ps
CPU time 18.27 seconds
Started Dec 27 01:04:39 PM PST 23
Finished Dec 27 01:05:08 PM PST 23
Peak memory 199092 kb
Host smart-9f8fb5c2-132f-466f-b4c4-51b97b522b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865876008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3865876008
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3694012207
Short name T1162
Test name
Test status
Simulation time 65603614220 ps
CPU time 45.12 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:05:26 PM PST 23
Peak memory 200172 kb
Host smart-c82846a5-c2cb-4ae8-97b8-e9bcb6437fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694012207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3694012207
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3486595904
Short name T1078
Test name
Test status
Simulation time 23065065 ps
CPU time 0.55 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:45 PM PST 23
Peak memory 194592 kb
Host smart-74a33226-6729-404c-91f7-94640bab03a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486595904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3486595904
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.989520856
Short name T830
Test name
Test status
Simulation time 47972009042 ps
CPU time 74.42 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:06:01 PM PST 23
Peak memory 200156 kb
Host smart-7e530810-c9da-4aff-b786-4e1af6ccab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989520856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.989520856
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.431702353
Short name T1035
Test name
Test status
Simulation time 38973525810 ps
CPU time 69.02 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:05:59 PM PST 23
Peak memory 200140 kb
Host smart-38af24e7-e555-49aa-a586-9ef75b1f51fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431702353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.431702353
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3120701
Short name T305
Test name
Test status
Simulation time 115328250531 ps
CPU time 35.61 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 200164 kb
Host smart-7bd33f59-9268-4f2c-bcba-c9688b4e5779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3120701
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.736025944
Short name T884
Test name
Test status
Simulation time 140171192337 ps
CPU time 47.46 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:48 PM PST 23
Peak memory 198320 kb
Host smart-baa585a5-cfd6-4190-ba8c-837bf00fbcb8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736025944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.736025944
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1952880095
Short name T614
Test name
Test status
Simulation time 71773271077 ps
CPU time 152.09 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:07:38 PM PST 23
Peak memory 200248 kb
Host smart-31e695ba-cf98-4e82-a309-0dd9a7db81e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952880095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1952880095
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2600230594
Short name T699
Test name
Test status
Simulation time 145607605 ps
CPU time 0.65 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:06 PM PST 23
Peak memory 195780 kb
Host smart-38f0e39c-65f3-451d-b9a9-2c05c7aa8771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600230594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2600230594
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2899851152
Short name T762
Test name
Test status
Simulation time 115011916243 ps
CPU time 17.59 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:05:08 PM PST 23
Peak memory 197592 kb
Host smart-bd29515c-1ef3-4f77-b62f-d64b561f0a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899851152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2899851152
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1762818100
Short name T640
Test name
Test status
Simulation time 13767027854 ps
CPU time 117.12 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:06:54 PM PST 23
Peak memory 200164 kb
Host smart-bb7ed511-b2d0-4d48-9e31-52e0eec07810
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762818100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1762818100
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2233992452
Short name T572
Test name
Test status
Simulation time 2974135170 ps
CPU time 8.97 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 198164 kb
Host smart-26836939-96de-4e41-bcd7-be7eaff91f04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233992452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2233992452
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1643883878
Short name T693
Test name
Test status
Simulation time 5807617238 ps
CPU time 10.47 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:05:29 PM PST 23
Peak memory 195972 kb
Host smart-8028a745-caab-4143-885a-07274d6099f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643883878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1643883878
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.188312386
Short name T649
Test name
Test status
Simulation time 302859614 ps
CPU time 1.12 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:04:49 PM PST 23
Peak memory 199140 kb
Host smart-0909cd3a-3c50-4b0c-ad4b-1399af4ff55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188312386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.188312386
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3157776333
Short name T621
Test name
Test status
Simulation time 168282917877 ps
CPU time 142.87 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:07:23 PM PST 23
Peak memory 200156 kb
Host smart-f1a5c139-4b7a-41cc-a19d-30ba7e19723b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157776333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3157776333
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2026878027
Short name T1215
Test name
Test status
Simulation time 46820388015 ps
CPU time 919.52 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:20:04 PM PST 23
Peak memory 225112 kb
Host smart-7e281382-01c3-4cd6-9e0d-295a1f701aa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026878027 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2026878027
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4161880706
Short name T714
Test name
Test status
Simulation time 1869218836 ps
CPU time 2.71 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:05:11 PM PST 23
Peak memory 198588 kb
Host smart-091f6dd5-e9d8-4df2-b993-a298195eff08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161880706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4161880706
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3294595023
Short name T841
Test name
Test status
Simulation time 4951261715 ps
CPU time 9.19 seconds
Started Dec 27 01:04:21 PM PST 23
Finished Dec 27 01:04:32 PM PST 23
Peak memory 200132 kb
Host smart-bcd6045b-ad5c-4255-bc08-f07b3857e456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294595023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3294595023
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.603302550
Short name T779
Test name
Test status
Simulation time 19148923 ps
CPU time 0.59 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:04:43 PM PST 23
Peak memory 194644 kb
Host smart-bade5282-43ff-46ea-9139-318428f71502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603302550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.603302550
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2886583634
Short name T1227
Test name
Test status
Simulation time 22028606735 ps
CPU time 36.96 seconds
Started Dec 27 01:04:22 PM PST 23
Finished Dec 27 01:05:01 PM PST 23
Peak memory 200220 kb
Host smart-05cbce8f-e703-4eb7-a11a-d2cddb2d1f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886583634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2886583634
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2562038112
Short name T1082
Test name
Test status
Simulation time 161031639792 ps
CPU time 55.41 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:05:46 PM PST 23
Peak memory 200152 kb
Host smart-f93d7061-a199-4c72-beb7-7eec9e3ca9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562038112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2562038112
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2169116312
Short name T661
Test name
Test status
Simulation time 102647789084 ps
CPU time 242.75 seconds
Started Dec 27 01:04:19 PM PST 23
Finished Dec 27 01:08:23 PM PST 23
Peak memory 200180 kb
Host smart-b1735022-7057-4d14-b86c-27e7025c3b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169116312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2169116312
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2795378638
Short name T11
Test name
Test status
Simulation time 138815344811 ps
CPU time 56.14 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:06:11 PM PST 23
Peak memory 200212 kb
Host smart-f567b95e-bd15-4b38-a5be-40344be657f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795378638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2795378638
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.4022366633
Short name T92
Test name
Test status
Simulation time 94503386430 ps
CPU time 237.62 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:08:46 PM PST 23
Peak memory 200232 kb
Host smart-a999570e-56d1-4e84-8f17-a6675429fd09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022366633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.4022366633
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3119229895
Short name T538
Test name
Test status
Simulation time 105927886 ps
CPU time 0.78 seconds
Started Dec 27 01:04:35 PM PST 23
Finished Dec 27 01:04:40 PM PST 23
Peak memory 195728 kb
Host smart-fa75e999-63d1-42f1-8aac-95ad0125ba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119229895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3119229895
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3583742616
Short name T1167
Test name
Test status
Simulation time 59440064543 ps
CPU time 50.74 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:48 PM PST 23
Peak memory 198328 kb
Host smart-e08d3638-5ee9-4070-ac13-a6732fef8cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583742616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3583742616
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.4175447897
Short name T1219
Test name
Test status
Simulation time 4759112230 ps
CPU time 269.49 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:09:34 PM PST 23
Peak memory 200244 kb
Host smart-e1b430f8-d88e-482b-ba69-b3c2e9073c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175447897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.4175447897
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2992205746
Short name T811
Test name
Test status
Simulation time 2915669243 ps
CPU time 19.91 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:17 PM PST 23
Peak memory 198652 kb
Host smart-964d9602-e933-460b-971b-01a04954ee41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992205746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2992205746
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2342832165
Short name T584
Test name
Test status
Simulation time 180335189484 ps
CPU time 23.79 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:05:12 PM PST 23
Peak memory 200040 kb
Host smart-cd469f70-78cd-45d7-9a08-35f23fbcf4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342832165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2342832165
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.4091080769
Short name T785
Test name
Test status
Simulation time 45242585312 ps
CPU time 17.82 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:05:06 PM PST 23
Peak memory 195728 kb
Host smart-7a6a5b38-7e1e-4c14-b731-52496fa7a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091080769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4091080769
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.835504439
Short name T1056
Test name
Test status
Simulation time 249885897 ps
CPU time 1.46 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:04:44 PM PST 23
Peak memory 199324 kb
Host smart-095f9f1a-c99e-4554-bc31-fe8ca341fb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835504439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.835504439
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3343136851
Short name T915
Test name
Test status
Simulation time 459579728010 ps
CPU time 917.65 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:20:08 PM PST 23
Peak memory 200160 kb
Host smart-ab9610ea-6c63-485a-9c0c-6fdf909e43de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343136851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3343136851
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2292240042
Short name T1091
Test name
Test status
Simulation time 6744538627 ps
CPU time 16.84 seconds
Started Dec 27 01:04:34 PM PST 23
Finished Dec 27 01:04:54 PM PST 23
Peak memory 199196 kb
Host smart-3221ae2b-5b6d-41dc-a44f-9aaafe6833bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292240042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2292240042
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.873852631
Short name T456
Test name
Test status
Simulation time 25264361051 ps
CPU time 31.81 seconds
Started Dec 27 01:04:19 PM PST 23
Finished Dec 27 01:04:52 PM PST 23
Peak memory 200272 kb
Host smart-ef052bb3-15cf-4458-a218-66bb755c79cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873852631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.873852631
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1760967286
Short name T709
Test name
Test status
Simulation time 11811083 ps
CPU time 0.55 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:04:49 PM PST 23
Peak memory 195624 kb
Host smart-07b87f9a-be12-4d12-a07d-191507153ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760967286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1760967286
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1435782173
Short name T1187
Test name
Test status
Simulation time 79813486474 ps
CPU time 115.22 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:07:00 PM PST 23
Peak memory 200144 kb
Host smart-cdb4eaa0-16ff-4827-a8d9-1b03f670bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435782173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1435782173
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.775259845
Short name T919
Test name
Test status
Simulation time 178795490682 ps
CPU time 67.46 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:05:50 PM PST 23
Peak memory 200200 kb
Host smart-5eb5974f-8643-4952-8036-4b5ce32bb82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775259845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.775259845
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2330518778
Short name T158
Test name
Test status
Simulation time 105163946349 ps
CPU time 45.83 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:05:43 PM PST 23
Peak memory 200216 kb
Host smart-b938ecb5-e783-49ed-8421-2e7e40cb5cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330518778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2330518778
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2769981490
Short name T942
Test name
Test status
Simulation time 355446020189 ps
CPU time 210.21 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:08:26 PM PST 23
Peak memory 200216 kb
Host smart-794cfdcb-13c2-40ba-9360-54394d71dfa9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769981490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2769981490
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1161305110
Short name T1079
Test name
Test status
Simulation time 64311416452 ps
CPU time 126.39 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:06:54 PM PST 23
Peak memory 200208 kb
Host smart-a060676b-d450-4ee9-bddc-35580b76d73a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161305110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1161305110
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2811550444
Short name T726
Test name
Test status
Simulation time 4805295205 ps
CPU time 8.61 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:55 PM PST 23
Peak memory 197928 kb
Host smart-49137ee3-7c6b-47b1-b736-a1b20d00ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811550444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2811550444
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2917192871
Short name T987
Test name
Test status
Simulation time 20661702478 ps
CPU time 47.66 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:48 PM PST 23
Peak memory 198124 kb
Host smart-d85e44f5-0f10-4e42-a97c-d25e0863a76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917192871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2917192871
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3845713796
Short name T1112
Test name
Test status
Simulation time 20481161701 ps
CPU time 205.74 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:08:23 PM PST 23
Peak memory 200156 kb
Host smart-500d8b7f-fbea-4bb8-abc0-21aeec2115de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845713796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3845713796
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3292039516
Short name T978
Test name
Test status
Simulation time 2548097614 ps
CPU time 6.14 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:05:04 PM PST 23
Peak memory 198268 kb
Host smart-835f284c-20eb-484a-92f9-f06eeacb5e6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292039516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3292039516
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.732253007
Short name T895
Test name
Test status
Simulation time 402780116364 ps
CPU time 312.94 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:10:22 PM PST 23
Peak memory 200156 kb
Host smart-e39e4ed7-8ce3-4ba2-9a1f-83c58a46c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732253007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.732253007
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1184317968
Short name T596
Test name
Test status
Simulation time 3902647674 ps
CPU time 2.23 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 196156 kb
Host smart-3879271e-a022-4001-86e7-bb3ccf9fc0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184317968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1184317968
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1521455920
Short name T555
Test name
Test status
Simulation time 753107455 ps
CPU time 1.26 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:00 PM PST 23
Peak memory 198064 kb
Host smart-3859b9e1-d3db-406b-9e56-9b53412ca034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521455920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1521455920
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2111526960
Short name T1143
Test name
Test status
Simulation time 80539879580 ps
CPU time 69.65 seconds
Started Dec 27 01:04:39 PM PST 23
Finished Dec 27 01:05:59 PM PST 23
Peak memory 208660 kb
Host smart-04e98a78-de12-4a34-9570-46a6a1b34427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111526960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2111526960
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3030180130
Short name T1080
Test name
Test status
Simulation time 215744497582 ps
CPU time 1329.16 seconds
Started Dec 27 01:04:34 PM PST 23
Finished Dec 27 01:26:46 PM PST 23
Peak memory 225212 kb
Host smart-02331899-5c40-4505-8101-631e1f8ff726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030180130 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3030180130
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1427167086
Short name T656
Test name
Test status
Simulation time 8708609233 ps
CPU time 4.92 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 199648 kb
Host smart-b530596a-59a6-4545-9f1d-9229a2e135ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427167086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1427167086
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.4249794317
Short name T429
Test name
Test status
Simulation time 17917793229 ps
CPU time 14.99 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 200228 kb
Host smart-d456c763-30a4-4b89-877a-226338aad2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249794317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4249794317
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2066675561
Short name T673
Test name
Test status
Simulation time 68725214 ps
CPU time 0.56 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:47 PM PST 23
Peak memory 195680 kb
Host smart-05250cf1-fcd5-42f0-9ffd-91dd149a1a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066675561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2066675561
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3009777512
Short name T672
Test name
Test status
Simulation time 16591721196 ps
CPU time 12.57 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:05:00 PM PST 23
Peak memory 197580 kb
Host smart-c3039a3f-e996-404e-be7d-eafda684a937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009777512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3009777512
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3752761649
Short name T349
Test name
Test status
Simulation time 160984713086 ps
CPU time 57.09 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:05:45 PM PST 23
Peak memory 200188 kb
Host smart-f0c46a23-9b73-4f3e-93c0-5c72bdd551da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752761649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3752761649
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2889247071
Short name T898
Test name
Test status
Simulation time 36686191803 ps
CPU time 18.54 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:14 PM PST 23
Peak memory 200212 kb
Host smart-234b805b-581f-4626-9883-c4b486faaad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889247071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2889247071
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2760612542
Short name T469
Test name
Test status
Simulation time 6567014909 ps
CPU time 11.61 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:05:06 PM PST 23
Peak memory 195808 kb
Host smart-5b3e53ae-a111-46eb-aac1-9d3e374c1442
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760612542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2760612542
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.123157478
Short name T550
Test name
Test status
Simulation time 50679293130 ps
CPU time 236.89 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:08:52 PM PST 23
Peak memory 200176 kb
Host smart-8ce5aa86-aa81-4648-bbac-194b3e4934a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123157478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.123157478
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3510498266
Short name T702
Test name
Test status
Simulation time 4264984443 ps
CPU time 6.92 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:05:02 PM PST 23
Peak memory 198468 kb
Host smart-b3ec624f-aa50-4c6e-a804-9d9d4c809773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510498266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3510498266
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2315629082
Short name T974
Test name
Test status
Simulation time 32094555131 ps
CPU time 12.61 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 194956 kb
Host smart-db26ccab-3944-4c90-aac0-ee1d250390d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315629082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2315629082
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2447806297
Short name T250
Test name
Test status
Simulation time 16486694251 ps
CPU time 885.85 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:19:41 PM PST 23
Peak memory 200132 kb
Host smart-cea9fcbf-1d0f-4cce-ab18-24503d894d71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447806297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2447806297
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2209447355
Short name T1216
Test name
Test status
Simulation time 719692637 ps
CPU time 5.67 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:04:56 PM PST 23
Peak memory 198328 kb
Host smart-2a0cddc7-2dd9-43df-94c9-9f2772844435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209447355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2209447355
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3421146438
Short name T358
Test name
Test status
Simulation time 84053927221 ps
CPU time 127.36 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:06:53 PM PST 23
Peak memory 200184 kb
Host smart-b81346cc-a9ef-414a-9b21-d01a88bfad84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421146438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3421146438
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2244598504
Short name T524
Test name
Test status
Simulation time 4285759828 ps
CPU time 7.77 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:13 PM PST 23
Peak memory 196004 kb
Host smart-bb08a2c7-14cc-4870-afbb-e3d1b376de2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244598504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2244598504
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2047580247
Short name T817
Test name
Test status
Simulation time 5444931380 ps
CPU time 7.54 seconds
Started Dec 27 01:04:39 PM PST 23
Finished Dec 27 01:04:57 PM PST 23
Peak memory 199524 kb
Host smart-45bd315e-922c-4f2a-91cb-64fccec245ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047580247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2047580247
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.4142810857
Short name T369
Test name
Test status
Simulation time 188932138199 ps
CPU time 174.13 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:08:01 PM PST 23
Peak memory 200204 kb
Host smart-ace19c5b-5d1b-4f5b-bac3-995cac3043d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142810857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.4142810857
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2700446758
Short name T320
Test name
Test status
Simulation time 153972383007 ps
CPU time 1373.92 seconds
Started Dec 27 01:04:48 PM PST 23
Finished Dec 27 01:27:47 PM PST 23
Peak memory 226276 kb
Host smart-43ede3db-50e7-4e70-953b-e64c98e889d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700446758 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2700446758
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.806293844
Short name T1178
Test name
Test status
Simulation time 1056118278 ps
CPU time 1.46 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:06 PM PST 23
Peak memory 198204 kb
Host smart-8f674f9f-dc47-4126-b22f-c2f0ec535bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806293844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.806293844
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.4147489628
Short name T969
Test name
Test status
Simulation time 168043268285 ps
CPU time 40.99 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:05:24 PM PST 23
Peak memory 200112 kb
Host smart-0da496bf-6782-4d98-8c40-91f7b022cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147489628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.4147489628
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1999538549
Short name T542
Test name
Test status
Simulation time 36108092 ps
CPU time 0.55 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:04:59 PM PST 23
Peak memory 195656 kb
Host smart-76356469-99cb-44ba-b466-1b1ab9c49ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999538549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1999538549
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.416998659
Short name T301
Test name
Test status
Simulation time 73368813349 ps
CPU time 15.35 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:11 PM PST 23
Peak memory 200292 kb
Host smart-c2e08420-0234-4796-a4c3-a7c86b7c624c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416998659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.416998659
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.659832716
Short name T537
Test name
Test status
Simulation time 29595174797 ps
CPU time 49.52 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:05:45 PM PST 23
Peak memory 200136 kb
Host smart-002842d6-1c71-4748-8455-293bb8eab9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659832716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.659832716
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2184976923
Short name T869
Test name
Test status
Simulation time 101451642458 ps
CPU time 167.53 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:07:54 PM PST 23
Peak memory 200216 kb
Host smart-55ddfd29-c812-414f-a033-d02d67bf56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184976923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2184976923
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2090347231
Short name T601
Test name
Test status
Simulation time 120671909103 ps
CPU time 188.58 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:08:07 PM PST 23
Peak memory 200188 kb
Host smart-a073eed1-2a7d-417f-9b05-25749c15b36a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090347231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2090347231
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2104408018
Short name T539
Test name
Test status
Simulation time 159613220395 ps
CPU time 809.47 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:18:14 PM PST 23
Peak memory 200272 kb
Host smart-428ddef6-95c0-45c1-9245-8541fb335baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104408018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2104408018
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1278473354
Short name T466
Test name
Test status
Simulation time 4601476309 ps
CPU time 6.26 seconds
Started Dec 27 01:04:49 PM PST 23
Finished Dec 27 01:05:02 PM PST 23
Peak memory 199116 kb
Host smart-bd12fac5-92ae-4230-9aa2-ff904e6b4812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278473354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1278473354
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2692592483
Short name T856
Test name
Test status
Simulation time 134545412405 ps
CPU time 76.2 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:06:23 PM PST 23
Peak memory 200328 kb
Host smart-b193fde1-e615-49b9-a302-051a80bafe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692592483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2692592483
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3141618095
Short name T1173
Test name
Test status
Simulation time 12718090644 ps
CPU time 152.69 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:07:29 PM PST 23
Peak memory 200136 kb
Host smart-822521db-e6f4-456c-86b7-5a1ac26a772b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141618095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3141618095
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3865596488
Short name T511
Test name
Test status
Simulation time 1673624364 ps
CPU time 14.46 seconds
Started Dec 27 01:04:35 PM PST 23
Finished Dec 27 01:04:53 PM PST 23
Peak memory 197860 kb
Host smart-75340489-a1da-4d6a-84a5-7bc4dc152516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865596488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3865596488
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3062069414
Short name T666
Test name
Test status
Simulation time 204300728359 ps
CPU time 68.32 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:06:15 PM PST 23
Peak memory 200240 kb
Host smart-28fe3b68-e013-4aec-a9ef-8ca632c2feee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062069414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3062069414
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3069800337
Short name T551
Test name
Test status
Simulation time 3196064575 ps
CPU time 3.06 seconds
Started Dec 27 01:04:35 PM PST 23
Finished Dec 27 01:04:42 PM PST 23
Peak memory 195960 kb
Host smart-65672153-1189-4aa0-aa70-aebed949a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069800337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3069800337
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3974509701
Short name T1001
Test name
Test status
Simulation time 6212807147 ps
CPU time 6.78 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:05:13 PM PST 23
Peak memory 200056 kb
Host smart-8308d543-ddd2-4963-a061-d3370c4d997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974509701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3974509701
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4076646267
Short name T377
Test name
Test status
Simulation time 446072909030 ps
CPU time 111.24 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:06:51 PM PST 23
Peak memory 200224 kb
Host smart-dbb2f4e3-ab1f-4960-a57d-00c9fd734a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076646267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4076646267
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3397212936
Short name T289
Test name
Test status
Simulation time 334090550455 ps
CPU time 369.36 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:10:58 PM PST 23
Peak memory 216504 kb
Host smart-2240c2f8-981b-4ee4-9578-cb79738d3b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397212936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3397212936
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2467950959
Short name T564
Test name
Test status
Simulation time 832231659 ps
CPU time 2.76 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:04:51 PM PST 23
Peak memory 198200 kb
Host smart-343d6335-eea8-493a-bfac-4c46e1578655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467950959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2467950959
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3694723549
Short name T873
Test name
Test status
Simulation time 14285345610 ps
CPU time 24.44 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:05:30 PM PST 23
Peak memory 200264 kb
Host smart-9227c383-007b-4c21-aceb-3db6eed8d42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694723549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3694723549
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3929307147
Short name T1203
Test name
Test status
Simulation time 39921750 ps
CPU time 0.53 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:05:09 PM PST 23
Peak memory 194592 kb
Host smart-17fd7664-2304-406c-8d8d-c0e3e03d9d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929307147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3929307147
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.628116930
Short name T1153
Test name
Test status
Simulation time 134324480660 ps
CPU time 213.47 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:08:32 PM PST 23
Peak memory 200168 kb
Host smart-d20189b6-22c5-4e00-8de3-4ff91af02541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628116930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.628116930
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1817630418
Short name T860
Test name
Test status
Simulation time 22633674547 ps
CPU time 24.66 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:29 PM PST 23
Peak memory 199408 kb
Host smart-315f18e4-83d2-4ac9-9847-a58af886b6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817630418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1817630418
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2002440835
Short name T188
Test name
Test status
Simulation time 346838117160 ps
CPU time 110.99 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:06:36 PM PST 23
Peak memory 200240 kb
Host smart-1aeeb299-a060-4ae2-afce-68a5214e4021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002440835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2002440835
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3681696402
Short name T660
Test name
Test status
Simulation time 935661120833 ps
CPU time 1273.36 seconds
Started Dec 27 01:04:47 PM PST 23
Finished Dec 27 01:26:07 PM PST 23
Peak memory 198760 kb
Host smart-5fb126b4-497b-4726-882d-35879ae6d19a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681696402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3681696402
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.11872198
Short name T1076
Test name
Test status
Simulation time 184285303975 ps
CPU time 422.87 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:12:10 PM PST 23
Peak memory 200176 kb
Host smart-1125d3df-bcbd-48c3-a6c5-b9d09795ee82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11872198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.11872198
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3032609008
Short name T756
Test name
Test status
Simulation time 8368483715 ps
CPU time 13.44 seconds
Started Dec 27 01:04:39 PM PST 23
Finished Dec 27 01:05:03 PM PST 23
Peak memory 200108 kb
Host smart-f0396aba-7d9a-4ba1-abb5-8131e193d2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032609008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3032609008
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2158359177
Short name T651
Test name
Test status
Simulation time 48260669416 ps
CPU time 32.59 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:29 PM PST 23
Peak memory 200124 kb
Host smart-02c99caf-cac9-463a-962d-52158d4dcd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158359177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2158359177
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2933064159
Short name T554
Test name
Test status
Simulation time 26913753838 ps
CPU time 122.88 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:07:05 PM PST 23
Peak memory 200180 kb
Host smart-6d96fcef-4aef-49a0-b893-75d383f807ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933064159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2933064159
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.247947993
Short name T775
Test name
Test status
Simulation time 4260681226 ps
CPU time 13.52 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 198912 kb
Host smart-0e21cc98-87a4-4099-8ead-5d396e7ac80f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247947993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.247947993
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2256309009
Short name T294
Test name
Test status
Simulation time 114777479075 ps
CPU time 233.21 seconds
Started Dec 27 01:04:48 PM PST 23
Finished Dec 27 01:08:47 PM PST 23
Peak memory 200200 kb
Host smart-5f7e3263-d948-4767-908c-cfd04e54ba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256309009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2256309009
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2689785377
Short name T867
Test name
Test status
Simulation time 5072902494 ps
CPU time 8.64 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:06 PM PST 23
Peak memory 196096 kb
Host smart-385249a8-c82d-4f3a-80e9-1b70450eb464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689785377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2689785377
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.495305671
Short name T816
Test name
Test status
Simulation time 696941478 ps
CPU time 1.18 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:04:58 PM PST 23
Peak memory 198356 kb
Host smart-10fbaaa2-f471-4361-bf42-7202cbbc6b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495305671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.495305671
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1847041952
Short name T339
Test name
Test status
Simulation time 223466639665 ps
CPU time 130.04 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:07:17 PM PST 23
Peak memory 208804 kb
Host smart-6c8a4fe9-26eb-4ae4-a908-0aaa6d729c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847041952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1847041952
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1532267650
Short name T254
Test name
Test status
Simulation time 165378823829 ps
CPU time 550.95 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:14:19 PM PST 23
Peak memory 216564 kb
Host smart-b2640755-44de-4c95-8c78-824a2475602a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532267650 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1532267650
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4064341191
Short name T594
Test name
Test status
Simulation time 540153181 ps
CPU time 1.65 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:07 PM PST 23
Peak memory 197564 kb
Host smart-931392cb-9a39-4c7e-b76a-1c0e2c0baba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064341191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4064341191
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3171976928
Short name T764
Test name
Test status
Simulation time 12780657174 ps
CPU time 18.47 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:34 PM PST 23
Peak memory 199976 kb
Host smart-b1107ba2-08d0-40ce-a88f-23889240849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171976928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3171976928
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1855236815
Short name T943
Test name
Test status
Simulation time 14877442 ps
CPU time 0.55 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:04:58 PM PST 23
Peak memory 194724 kb
Host smart-36fd0c71-eefd-45b7-952c-88c6ec505717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855236815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1855236815
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2001279299
Short name T199
Test name
Test status
Simulation time 46689412593 ps
CPU time 15.94 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 198632 kb
Host smart-5c9a8e86-e3db-4be2-95c4-e47ec3ee1e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001279299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2001279299
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1183211307
Short name T368
Test name
Test status
Simulation time 250993139795 ps
CPU time 41.39 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:05:30 PM PST 23
Peak memory 199772 kb
Host smart-2fa2ed16-2dcd-47b1-ac42-2ef64b1bd747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183211307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1183211307
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4085088040
Short name T340
Test name
Test status
Simulation time 99459061600 ps
CPU time 45.73 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:05:44 PM PST 23
Peak memory 200188 kb
Host smart-805f12ee-ec4f-4cb0-81cd-b7e4f5dde62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085088040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4085088040
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3495586447
Short name T979
Test name
Test status
Simulation time 644802490801 ps
CPU time 565.65 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:14:16 PM PST 23
Peak memory 200084 kb
Host smart-11c34740-4636-488d-a0b8-4f203c900434
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495586447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3495586447
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1987655104
Short name T1114
Test name
Test status
Simulation time 82702684090 ps
CPU time 164.14 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:07:32 PM PST 23
Peak memory 200136 kb
Host smart-2f64f261-d8ca-4d91-a0ae-acff58c8aa5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987655104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1987655104
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1488315408
Short name T735
Test name
Test status
Simulation time 4357669119 ps
CPU time 7.43 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:54 PM PST 23
Peak memory 195912 kb
Host smart-f233bb15-4629-42ea-830f-82a8b1591e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488315408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1488315408
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.651840206
Short name T177
Test name
Test status
Simulation time 128613062116 ps
CPU time 227.22 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:08:34 PM PST 23
Peak memory 208148 kb
Host smart-6288d986-ee17-4142-b607-280e963edcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651840206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.651840206
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1329089371
Short name T1100
Test name
Test status
Simulation time 817466656 ps
CPU time 2.43 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:04:45 PM PST 23
Peak memory 198220 kb
Host smart-a4fb0951-2dc2-4db7-8e03-8e862e910f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329089371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1329089371
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.732969638
Short name T436
Test name
Test status
Simulation time 2736303986 ps
CPU time 5.34 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:07 PM PST 23
Peak memory 195688 kb
Host smart-0cfea676-7d4d-4f94-baee-66847c73d27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732969638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.732969638
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.708191659
Short name T1194
Test name
Test status
Simulation time 472156630 ps
CPU time 2.78 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 199044 kb
Host smart-6e3cae90-f70b-477e-9b0a-273dcef06394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708191659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.708191659
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2270256301
Short name T720
Test name
Test status
Simulation time 190759991763 ps
CPU time 254.23 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:09:12 PM PST 23
Peak memory 200192 kb
Host smart-b2d0e3a8-6397-41b3-8de4-ed293ad5acce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270256301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2270256301
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.938043007
Short name T316
Test name
Test status
Simulation time 236096509704 ps
CPU time 943.61 seconds
Started Dec 27 01:04:41 PM PST 23
Finished Dec 27 01:20:35 PM PST 23
Peak memory 216720 kb
Host smart-83a58438-337f-450d-a0ce-880f108f1fad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938043007 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.938043007
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3648814222
Short name T460
Test name
Test status
Simulation time 4405850371 ps
CPU time 1.92 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:48 PM PST 23
Peak memory 199088 kb
Host smart-c1f1df10-dafd-438b-9133-b75f35fffa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648814222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3648814222
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.778745762
Short name T433
Test name
Test status
Simulation time 148580191693 ps
CPU time 41.85 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 200200 kb
Host smart-b51057b4-6e15-4f30-a3fc-0976034967aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778745762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.778745762
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1999902981
Short name T1017
Test name
Test status
Simulation time 14737094 ps
CPU time 0.57 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 195612 kb
Host smart-8bc80787-e921-4bcf-8236-e9117a6675d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999902981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1999902981
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1890813105
Short name T991
Test name
Test status
Simulation time 58788710884 ps
CPU time 26.04 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 200232 kb
Host smart-7ba6e898-fc39-4018-87c8-7e748d8d2594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890813105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1890813105
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1667288888
Short name T707
Test name
Test status
Simulation time 82830862735 ps
CPU time 65.57 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:06:05 PM PST 23
Peak memory 199224 kb
Host smart-8a602eea-c08b-461a-83a3-72d37d263524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667288888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1667288888
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1544410605
Short name T106
Test name
Test status
Simulation time 190316656267 ps
CPU time 34.51 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 199984 kb
Host smart-0013ccdc-69ec-4bd9-becd-ee97567f5c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544410605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1544410605
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.278689239
Short name T984
Test name
Test status
Simulation time 238668859661 ps
CPU time 103.24 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:06:48 PM PST 23
Peak memory 199964 kb
Host smart-f9709cbe-b32a-43f2-bb82-480ea072d5e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278689239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.278689239
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3179890330
Short name T1212
Test name
Test status
Simulation time 75148379218 ps
CPU time 281.1 seconds
Started Dec 27 01:04:38 PM PST 23
Finished Dec 27 01:09:28 PM PST 23
Peak memory 200232 kb
Host smart-8b9153c4-3f5f-4fc0-98e1-6abe25293866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179890330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3179890330
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2345836548
Short name T633
Test name
Test status
Simulation time 47233546368 ps
CPU time 82.27 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:06:12 PM PST 23
Peak memory 198592 kb
Host smart-614f83c4-70b6-45b0-8f71-a57aaafc3c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345836548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2345836548
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2984751537
Short name T625
Test name
Test status
Simulation time 20473173288 ps
CPU time 978.69 seconds
Started Dec 27 01:04:40 PM PST 23
Finished Dec 27 01:21:09 PM PST 23
Peak memory 199892 kb
Host smart-941ac44a-370d-41e8-ac7e-630b7242f079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984751537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2984751537
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3314060210
Short name T892
Test name
Test status
Simulation time 644163372 ps
CPU time 4.02 seconds
Started Dec 27 01:04:36 PM PST 23
Finished Dec 27 01:04:47 PM PST 23
Peak memory 197792 kb
Host smart-bff26611-78b5-4291-88bb-09e70c2c9b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314060210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3314060210
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1539082866
Short name T352
Test name
Test status
Simulation time 77278864030 ps
CPU time 24.14 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 199812 kb
Host smart-e471cb3e-d250-4a66-99b8-dabc7b6e92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539082866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1539082866
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.324523056
Short name T769
Test name
Test status
Simulation time 37338225712 ps
CPU time 9.43 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:09 PM PST 23
Peak memory 195760 kb
Host smart-e7d5fe5f-5448-423d-a903-0ddf4da95fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324523056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.324523056
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.4019512193
Short name T20
Test name
Test status
Simulation time 688720271 ps
CPU time 2.15 seconds
Started Dec 27 01:04:37 PM PST 23
Finished Dec 27 01:04:48 PM PST 23
Peak memory 198540 kb
Host smart-f1aabf27-14c8-42b7-842f-026379dd6c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019512193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.4019512193
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4246132785
Short name T935
Test name
Test status
Simulation time 193177036617 ps
CPU time 789.59 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:18:31 PM PST 23
Peak memory 229260 kb
Host smart-1442e5c9-fdfc-4e1b-8006-ded2c34228b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246132785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4246132785
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2981838906
Short name T1122
Test name
Test status
Simulation time 12936773428 ps
CPU time 15.61 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:20 PM PST 23
Peak memory 199804 kb
Host smart-66f5dc01-d742-4296-b4cf-335fb721e14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981838906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2981838906
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3602456663
Short name T552
Test name
Test status
Simulation time 9999868559 ps
CPU time 16.17 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:12 PM PST 23
Peak memory 197008 kb
Host smart-11c66f97-a139-4bee-b57e-f50bdb34efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602456663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3602456663
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4053387234
Short name T522
Test name
Test status
Simulation time 19093741 ps
CPU time 0.62 seconds
Started Dec 27 01:03:24 PM PST 23
Finished Dec 27 01:03:28 PM PST 23
Peak memory 194544 kb
Host smart-cae207be-55f8-44ac-9c56-d509066c7ac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053387234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4053387234
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2505982777
Short name T781
Test name
Test status
Simulation time 219415751977 ps
CPU time 342.05 seconds
Started Dec 27 01:03:22 PM PST 23
Finished Dec 27 01:09:06 PM PST 23
Peak memory 200108 kb
Host smart-e1ff8cb1-77e1-495b-a91d-e9b3934b147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505982777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2505982777
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.90842214
Short name T388
Test name
Test status
Simulation time 145429545066 ps
CPU time 49.27 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:04:14 PM PST 23
Peak memory 199416 kb
Host smart-df924366-0b17-4b7e-9162-583e68ace6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90842214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.90842214
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2645182110
Short name T874
Test name
Test status
Simulation time 95501766614 ps
CPU time 152.08 seconds
Started Dec 27 01:03:19 PM PST 23
Finished Dec 27 01:05:55 PM PST 23
Peak memory 200252 kb
Host smart-35eb26a7-6b27-474e-a686-1882569e4839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645182110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2645182110
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.32493839
Short name T530
Test name
Test status
Simulation time 436515732447 ps
CPU time 337.52 seconds
Started Dec 27 01:03:19 PM PST 23
Finished Dec 27 01:09:00 PM PST 23
Peak memory 200068 kb
Host smart-81e1a41e-3583-40fc-a26d-396cf3a43993
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32493839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.32493839
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1394156450
Short name T23
Test name
Test status
Simulation time 46307534694 ps
CPU time 312.52 seconds
Started Dec 27 01:03:25 PM PST 23
Finished Dec 27 01:08:41 PM PST 23
Peak memory 200152 kb
Host smart-669758d3-bc53-49c4-bb9e-c0e38a29fabd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394156450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1394156450
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_noise_filter.59900441
Short name T732
Test name
Test status
Simulation time 238828228163 ps
CPU time 59.78 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:04:24 PM PST 23
Peak memory 208724 kb
Host smart-65061fe6-38ed-4232-b9ba-7915a000230e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59900441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.59900441
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2096027326
Short name T1036
Test name
Test status
Simulation time 16042776035 ps
CPU time 370.72 seconds
Started Dec 27 01:03:35 PM PST 23
Finished Dec 27 01:09:48 PM PST 23
Peak memory 200008 kb
Host smart-1734ae67-98a8-4ada-9912-ffcadf9ad143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096027326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2096027326
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2478493208
Short name T1094
Test name
Test status
Simulation time 4911378333 ps
CPU time 44.23 seconds
Started Dec 27 01:03:15 PM PST 23
Finished Dec 27 01:04:06 PM PST 23
Peak memory 198860 kb
Host smart-683b7059-c8f0-49c1-9a3f-7bd5a4630d78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478493208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2478493208
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.556938273
Short name T523
Test name
Test status
Simulation time 78642766710 ps
CPU time 27.92 seconds
Started Dec 27 01:03:17 PM PST 23
Finished Dec 27 01:03:50 PM PST 23
Peak memory 200224 kb
Host smart-10084417-b449-4db2-becb-1041074a987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556938273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.556938273
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.852035154
Short name T1102
Test name
Test status
Simulation time 28027666012 ps
CPU time 10.82 seconds
Started Dec 27 01:03:24 PM PST 23
Finished Dec 27 01:03:37 PM PST 23
Peak memory 195980 kb
Host smart-dae1e944-4626-4c79-af5f-288243958dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852035154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.852035154
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2249068813
Short name T87
Test name
Test status
Simulation time 70256357 ps
CPU time 0.76 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:03:37 PM PST 23
Peak memory 217676 kb
Host smart-a569dcdf-37b2-4855-b0b4-b10d6a7aabb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249068813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2249068813
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3242530161
Short name T1067
Test name
Test status
Simulation time 693974924 ps
CPU time 1.79 seconds
Started Dec 27 01:03:15 PM PST 23
Finished Dec 27 01:03:23 PM PST 23
Peak memory 199132 kb
Host smart-bcaec75b-b6d0-4dee-9046-e8582141745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242530161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3242530161
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2461184509
Short name T455
Test name
Test status
Simulation time 1892532245293 ps
CPU time 1546.53 seconds
Started Dec 27 01:03:27 PM PST 23
Finished Dec 27 01:29:16 PM PST 23
Peak memory 200156 kb
Host smart-b2871398-9a40-47e0-9e49-956fb1df96bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461184509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2461184509
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3221989996
Short name T724
Test name
Test status
Simulation time 26826697192 ps
CPU time 230.73 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:07:25 PM PST 23
Peak memory 216648 kb
Host smart-b0508454-e9af-4e80-a30e-434fd98b65fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221989996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3221989996
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3137255057
Short name T568
Test name
Test status
Simulation time 7658606578 ps
CPU time 6.69 seconds
Started Dec 27 01:03:16 PM PST 23
Finished Dec 27 01:03:28 PM PST 23
Peak memory 199856 kb
Host smart-426986b0-643b-4ca1-af8e-6a4340b8173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137255057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3137255057
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.356494685
Short name T632
Test name
Test status
Simulation time 24122369999 ps
CPU time 10.8 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:36 PM PST 23
Peak memory 200188 kb
Host smart-7d43d2fc-053f-4133-90ea-3c913f9479d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356494685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.356494685
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1802696727
Short name T520
Test name
Test status
Simulation time 38276365 ps
CPU time 0.54 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:05:07 PM PST 23
Peak memory 194528 kb
Host smart-92306c6f-9097-4a1e-81bd-9a53b59110b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802696727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1802696727
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2412909682
Short name T147
Test name
Test status
Simulation time 112569689350 ps
CPU time 17.63 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 199816 kb
Host smart-dc67a8f1-9aab-4dfa-9721-116b3da6e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412909682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2412909682
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.476326488
Short name T749
Test name
Test status
Simulation time 137093583948 ps
CPU time 25.84 seconds
Started Dec 27 01:04:47 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 200180 kb
Host smart-e7be4015-3c13-488f-8eee-ce378e87b78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476326488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.476326488
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3852805619
Short name T1199
Test name
Test status
Simulation time 22672819176 ps
CPU time 11.16 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 200212 kb
Host smart-0b33ae2e-5f13-46bf-919b-2e17f5b1815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852805619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3852805619
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1668406099
Short name T629
Test name
Test status
Simulation time 186687948517 ps
CPU time 329.21 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:10:34 PM PST 23
Peak memory 199984 kb
Host smart-f430e364-d9a7-481a-ac62-c74edefff6f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668406099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1668406099
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1120061405
Short name T570
Test name
Test status
Simulation time 239541117829 ps
CPU time 172.44 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:08:00 PM PST 23
Peak memory 200104 kb
Host smart-8e7cb8f9-ddc4-4047-b160-8c414970676a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120061405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1120061405
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3748068600
Short name T1031
Test name
Test status
Simulation time 6681514773 ps
CPU time 8.88 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:09 PM PST 23
Peak memory 198632 kb
Host smart-4a4cbb87-efbe-4287-948b-d65fe4227987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748068600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3748068600
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.616740124
Short name T90
Test name
Test status
Simulation time 88294664412 ps
CPU time 118.95 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:07:02 PM PST 23
Peak memory 200240 kb
Host smart-8e4f98a8-c7d0-478a-a6af-1032d2dc99af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616740124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.616740124
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3668910222
Short name T240
Test name
Test status
Simulation time 35986782397 ps
CPU time 488.59 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:13:14 PM PST 23
Peak memory 200212 kb
Host smart-cdda511d-c9e4-4c19-9a29-e19dc7ff98c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668910222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3668910222
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1325618276
Short name T691
Test name
Test status
Simulation time 1284450419 ps
CPU time 6.34 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 198008 kb
Host smart-5ea0926d-4bab-406d-b77d-0e2d5c1a6b07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325618276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1325618276
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1249297126
Short name T380
Test name
Test status
Simulation time 37452509399 ps
CPU time 16.42 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:05:25 PM PST 23
Peak memory 200020 kb
Host smart-16e86a13-ad94-4f9d-b569-3484bcf8a54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249297126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1249297126
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.4263008383
Short name T671
Test name
Test status
Simulation time 2794518751 ps
CPU time 5.19 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:05:11 PM PST 23
Peak memory 195704 kb
Host smart-ff3b09f5-ba16-4bcf-bd0d-8d22589529a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263008383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.4263008383
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1242331995
Short name T759
Test name
Test status
Simulation time 493106505 ps
CPU time 1.96 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:04 PM PST 23
Peak memory 198656 kb
Host smart-23e21208-2450-4f8c-b07c-5ad9bc2c7e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242331995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1242331995
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.243668048
Short name T747
Test name
Test status
Simulation time 161349587810 ps
CPU time 470.85 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:13:06 PM PST 23
Peak memory 212148 kb
Host smart-4026916b-a2bd-4caa-883c-dc073b888386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243668048 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.243668048
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1158962856
Short name T645
Test name
Test status
Simulation time 2438149871 ps
CPU time 1.61 seconds
Started Dec 27 01:05:05 PM PST 23
Finished Dec 27 01:05:16 PM PST 23
Peak memory 198552 kb
Host smart-57dabdf9-0550-4a2a-9087-6eb2281db316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158962856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1158962856
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3003918946
Short name T1101
Test name
Test status
Simulation time 76291777192 ps
CPU time 130.86 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:07:27 PM PST 23
Peak memory 200268 kb
Host smart-e45c911a-b03c-4e14-956e-61aa34f6bc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003918946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3003918946
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3011368258
Short name T1147
Test name
Test status
Simulation time 22297897 ps
CPU time 0.56 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:01 PM PST 23
Peak memory 195568 kb
Host smart-d6231618-9865-4917-a742-52105b467bfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011368258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3011368258
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1969948535
Short name T325
Test name
Test status
Simulation time 139628708953 ps
CPU time 65.81 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:06:12 PM PST 23
Peak memory 200116 kb
Host smart-07948b0a-c302-4e95-b170-9819c6f1a69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969948535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1969948535
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2840876254
Short name T143
Test name
Test status
Simulation time 174350837300 ps
CPU time 397.91 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:11:35 PM PST 23
Peak memory 200196 kb
Host smart-e02fecd3-a70a-48e6-8522-5861f8e44d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840876254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2840876254
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1028320808
Short name T1128
Test name
Test status
Simulation time 180397526819 ps
CPU time 18.51 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:05:25 PM PST 23
Peak memory 200200 kb
Host smart-92fd45c1-0d8f-48a5-8fe7-6091da13deec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028320808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1028320808
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3536565706
Short name T748
Test name
Test status
Simulation time 191366324416 ps
CPU time 312.59 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:10:31 PM PST 23
Peak memory 195872 kb
Host smart-cffa7dc3-cad2-490a-b008-cb8ecf06521e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536565706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3536565706
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.305329200
Short name T758
Test name
Test status
Simulation time 198098125890 ps
CPU time 423.15 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:12:22 PM PST 23
Peak memory 200144 kb
Host smart-4a2c81a6-bbe1-4887-8590-e31936ab5dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305329200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.305329200
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1318551767
Short name T993
Test name
Test status
Simulation time 5007280734 ps
CPU time 3.57 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 198996 kb
Host smart-131061f1-c2a8-4992-b1e8-68f2bc32e0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318551767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1318551767
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2206971856
Short name T1139
Test name
Test status
Simulation time 115370607861 ps
CPU time 98.46 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:06:55 PM PST 23
Peak memory 200648 kb
Host smart-801873b5-514c-454f-b9b2-6bb9ffc3fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206971856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2206971856
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1869795830
Short name T161
Test name
Test status
Simulation time 13775225932 ps
CPU time 90.54 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:06:46 PM PST 23
Peak memory 200128 kb
Host smart-4acc17d2-07b3-4e60-987d-f84518516e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1869795830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1869795830
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.999381694
Short name T981
Test name
Test status
Simulation time 1483243756 ps
CPU time 6.95 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 197864 kb
Host smart-b9c9209b-4e43-4260-a271-a93866c9e0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999381694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.999381694
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2514835738
Short name T354
Test name
Test status
Simulation time 32195535231 ps
CPU time 14.01 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:05:34 PM PST 23
Peak memory 199764 kb
Host smart-2cbff674-5a71-4219-a2e7-c516d2e5b9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514835738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2514835738
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.163326197
Short name T1039
Test name
Test status
Simulation time 5069200426 ps
CPU time 2.5 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 196096 kb
Host smart-47e1b1cd-acf7-4994-9d56-d10a99cfe57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163326197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.163326197
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3502135632
Short name T580
Test name
Test status
Simulation time 475051417 ps
CPU time 3.25 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:08 PM PST 23
Peak memory 198224 kb
Host smart-5054afd1-8657-4560-adb9-0e21e54aaca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502135632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3502135632
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.922626323
Short name T372
Test name
Test status
Simulation time 34765616598 ps
CPU time 65.14 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:06:09 PM PST 23
Peak memory 200116 kb
Host smart-862144a1-00e4-4ba9-b8b6-489f6ee57ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922626323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.922626323
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2621415150
Short name T1058
Test name
Test status
Simulation time 71300544413 ps
CPU time 182.28 seconds
Started Dec 27 01:05:15 PM PST 23
Finished Dec 27 01:08:26 PM PST 23
Peak memory 208600 kb
Host smart-0362cb8a-0688-426f-8931-8fac4f534cc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621415150 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2621415150
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2393708479
Short name T585
Test name
Test status
Simulation time 1293003981 ps
CPU time 3.88 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:05:21 PM PST 23
Peak memory 198120 kb
Host smart-076e7eae-b5e1-4e1a-8f89-e3096d4f3563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393708479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2393708479
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3893095740
Short name T592
Test name
Test status
Simulation time 242314616913 ps
CPU time 123.12 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:07:18 PM PST 23
Peak memory 200244 kb
Host smart-3e446de2-9be0-4a39-af49-4f88ab063192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893095740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3893095740
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2742141444
Short name T619
Test name
Test status
Simulation time 12094286 ps
CPU time 0.53 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:05:18 PM PST 23
Peak memory 194584 kb
Host smart-0e6a96ba-fe56-4d29-81d8-f0b0092d571f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742141444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2742141444
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3093009194
Short name T1018
Test name
Test status
Simulation time 113838924334 ps
CPU time 29.89 seconds
Started Dec 27 01:04:51 PM PST 23
Finished Dec 27 01:05:27 PM PST 23
Peak memory 200212 kb
Host smart-3a77878f-2122-4fd3-9b89-a1d91683b41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093009194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3093009194
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3647647975
Short name T1138
Test name
Test status
Simulation time 33238504281 ps
CPU time 50.42 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:53 PM PST 23
Peak memory 200096 kb
Host smart-fd63c43b-e0fc-4014-952b-3fcfb387f94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647647975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3647647975
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2254891123
Short name T1191
Test name
Test status
Simulation time 87326462577 ps
CPU time 237.59 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:09:03 PM PST 23
Peak memory 200152 kb
Host smart-7044b4ff-31d0-4428-88f1-ef82be8a529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254891123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2254891123
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3200935903
Short name T988
Test name
Test status
Simulation time 140390590685 ps
CPU time 27.92 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:33 PM PST 23
Peak memory 200140 kb
Host smart-3e20f90d-2985-47d2-b69e-25d1361f9deb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200935903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3200935903
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1497405956
Short name T717
Test name
Test status
Simulation time 146644901695 ps
CPU time 448.85 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:12:46 PM PST 23
Peak memory 200204 kb
Host smart-6e33f929-7339-4824-bb67-ed9d91409182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497405956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1497405956
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3458844907
Short name T638
Test name
Test status
Simulation time 5641633173 ps
CPU time 4.05 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:20 PM PST 23
Peak memory 198072 kb
Host smart-e363f5b1-7c4a-4dd3-be77-f86cccf8e760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458844907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3458844907
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3884046914
Short name T932
Test name
Test status
Simulation time 11217387539 ps
CPU time 19.62 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:05:34 PM PST 23
Peak memory 199156 kb
Host smart-0e1c6e99-5e54-4638-a5e2-9701e97a1f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884046914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3884046914
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3740562148
Short name T211
Test name
Test status
Simulation time 21045079877 ps
CPU time 67.83 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:06:15 PM PST 23
Peak memory 200056 kb
Host smart-189cb73f-3009-4003-a261-017f0520965b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740562148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3740562148
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3769325099
Short name T1012
Test name
Test status
Simulation time 2278822279 ps
CPU time 3.44 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 198028 kb
Host smart-dbdbe7cb-6c23-46b3-97c6-afa625a9c0bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769325099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3769325099
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1190590027
Short name T648
Test name
Test status
Simulation time 58801171787 ps
CPU time 85.26 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:06:42 PM PST 23
Peak memory 200084 kb
Host smart-aa3e7b46-c754-4f16-a459-6cf2b73c33e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190590027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1190590027
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.750373239
Short name T939
Test name
Test status
Simulation time 3715495231 ps
CPU time 1.78 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:05:17 PM PST 23
Peak memory 195712 kb
Host smart-1457c871-dd31-436b-830f-963966fcc532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750373239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.750373239
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.109732395
Short name T739
Test name
Test status
Simulation time 6015672962 ps
CPU time 14.6 seconds
Started Dec 27 01:04:52 PM PST 23
Finished Dec 27 01:05:13 PM PST 23
Peak memory 199104 kb
Host smart-c2469e4a-df2a-41e1-a453-9d838de73b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109732395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.109732395
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2414087068
Short name T926
Test name
Test status
Simulation time 88675315887 ps
CPU time 31.61 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:05:48 PM PST 23
Peak memory 200148 kb
Host smart-0d361982-acbe-47fa-ab93-f6764ee5a71c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414087068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2414087068
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3924144625
Short name T700
Test name
Test status
Simulation time 21344515164 ps
CPU time 235.02 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:09:03 PM PST 23
Peak memory 216964 kb
Host smart-fe50d2b7-8e78-445a-84d3-249dcedfb644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924144625 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3924144625
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3495414288
Short name T888
Test name
Test status
Simulation time 1182979696 ps
CPU time 1.65 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:05:16 PM PST 23
Peak memory 198184 kb
Host smart-be9a674e-5905-475c-9da7-7f20cf9772ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495414288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3495414288
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2584109482
Short name T1062
Test name
Test status
Simulation time 42141808662 ps
CPU time 17.54 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:05:13 PM PST 23
Peak memory 200196 kb
Host smart-412d179d-5b32-434c-8783-e0e4076a3142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584109482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2584109482
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1852698602
Short name T635
Test name
Test status
Simulation time 61711520 ps
CPU time 0.55 seconds
Started Dec 27 01:04:50 PM PST 23
Finished Dec 27 01:04:57 PM PST 23
Peak memory 195636 kb
Host smart-004a755f-f646-4de6-a42e-fb8a1edfb64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852698602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1852698602
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4059129918
Short name T391
Test name
Test status
Simulation time 335086462163 ps
CPU time 332.9 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:10:49 PM PST 23
Peak memory 200248 kb
Host smart-d40988ef-5687-429e-9c08-ec998ca27077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059129918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4059129918
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2885927605
Short name T846
Test name
Test status
Simulation time 38953341158 ps
CPU time 16.44 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:05:26 PM PST 23
Peak memory 199332 kb
Host smart-440b5e11-28f1-4375-95e7-d4459f044da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885927605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2885927605
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.550684243
Short name T1142
Test name
Test status
Simulation time 545654186360 ps
CPU time 296.68 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:10:14 PM PST 23
Peak memory 200180 kb
Host smart-059cf1f8-2e03-4f80-b8d0-6c3c65e3d296
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550684243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.550684243
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3022026338
Short name T417
Test name
Test status
Simulation time 117872953324 ps
CPU time 172.33 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:07:59 PM PST 23
Peak memory 200160 kb
Host smart-b274efdf-4c4a-49ae-805d-0a5ee01284a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022026338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3022026338
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.801672509
Short name T470
Test name
Test status
Simulation time 7304823532 ps
CPU time 4.93 seconds
Started Dec 27 01:04:55 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 198976 kb
Host smart-c6b10ac5-4cc3-4613-a350-a73da5c2afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801672509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.801672509
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3547987489
Short name T899
Test name
Test status
Simulation time 162515598243 ps
CPU time 45.17 seconds
Started Dec 27 01:05:16 PM PST 23
Finished Dec 27 01:06:09 PM PST 23
Peak memory 200508 kb
Host smart-4d1f13ce-de24-4434-8e22-ea0d3b623b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547987489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3547987489
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3356295728
Short name T1044
Test name
Test status
Simulation time 16411162412 ps
CPU time 875.56 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:19:54 PM PST 23
Peak memory 200224 kb
Host smart-88a7ad68-a8bc-4480-a584-a8873c2225a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356295728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3356295728
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1763343047
Short name T1089
Test name
Test status
Simulation time 56972714660 ps
CPU time 59.03 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 200232 kb
Host smart-034ac8a8-66fb-4626-b743-3babceda5ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763343047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1763343047
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2322766475
Short name T934
Test name
Test status
Simulation time 3633053091 ps
CPU time 6.79 seconds
Started Dec 27 01:05:16 PM PST 23
Finished Dec 27 01:05:31 PM PST 23
Peak memory 196000 kb
Host smart-6d570913-f9ca-4836-8a4f-25816c55bd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322766475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2322766475
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3941940318
Short name T805
Test name
Test status
Simulation time 265708926 ps
CPU time 1.36 seconds
Started Dec 27 01:05:00 PM PST 23
Finished Dec 27 01:05:13 PM PST 23
Peak memory 198036 kb
Host smart-b604a969-1968-46f1-a54c-ba3e8c1b185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941940318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3941940318
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2483162021
Short name T364
Test name
Test status
Simulation time 395309373797 ps
CPU time 1302.21 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:26:47 PM PST 23
Peak memory 228924 kb
Host smart-25aef9a1-b51c-4b89-b320-252435beecd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483162021 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2483162021
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.4015134215
Short name T452
Test name
Test status
Simulation time 573996746 ps
CPU time 2.09 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:05:21 PM PST 23
Peak memory 198496 kb
Host smart-c894cc72-3284-4c20-a9e8-ff67233f4621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015134215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.4015134215
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3704951434
Short name T793
Test name
Test status
Simulation time 103594179030 ps
CPU time 68.8 seconds
Started Dec 27 01:05:00 PM PST 23
Finished Dec 27 01:06:21 PM PST 23
Peak memory 200236 kb
Host smart-00c42f37-f113-4df8-b925-9d9822bdc871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704951434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3704951434
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2335634530
Short name T655
Test name
Test status
Simulation time 70114163 ps
CPU time 0.54 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:05:18 PM PST 23
Peak memory 195632 kb
Host smart-ff401b78-13d3-4632-aa9a-2b5338df2feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335634530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2335634530
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2092011883
Short name T1113
Test name
Test status
Simulation time 84211490668 ps
CPU time 164.33 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:07:46 PM PST 23
Peak memory 200240 kb
Host smart-3151a504-eeaa-4abd-bf9d-bc256276a0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092011883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2092011883
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3358133750
Short name T401
Test name
Test status
Simulation time 33909770403 ps
CPU time 53.11 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:06:08 PM PST 23
Peak memory 200236 kb
Host smart-bfeaf0b9-6bea-4cf9-9620-aece47595eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358133750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3358133750
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.746809667
Short name T1026
Test name
Test status
Simulation time 175972336544 ps
CPU time 327.27 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:10:43 PM PST 23
Peak memory 200172 kb
Host smart-4d2b7f54-d3e5-4b55-9eda-55f797caffb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746809667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.746809667
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.513358380
Short name T1050
Test name
Test status
Simulation time 71576367411 ps
CPU time 116.74 seconds
Started Dec 27 01:05:15 PM PST 23
Finished Dec 27 01:07:20 PM PST 23
Peak memory 200232 kb
Host smart-691ce481-d7d9-4ab8-a725-4786d47611a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513358380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.513358380
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2968395180
Short name T1124
Test name
Test status
Simulation time 10215733592 ps
CPU time 14.46 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:05:33 PM PST 23
Peak memory 199892 kb
Host smart-3a4aeaf3-05dd-4d59-b5b6-048bd9dfbfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968395180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2968395180
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3337762167
Short name T1192
Test name
Test status
Simulation time 132762597555 ps
CPU time 57.17 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:06:06 PM PST 23
Peak memory 200468 kb
Host smart-640c061c-ff9d-4d45-b66e-be97c678bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337762167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3337762167
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2961888495
Short name T850
Test name
Test status
Simulation time 18902954437 ps
CPU time 183.8 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:08:22 PM PST 23
Peak memory 200192 kb
Host smart-649d7555-4843-4d00-8951-5508099dd765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961888495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2961888495
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2436412502
Short name T615
Test name
Test status
Simulation time 812036087 ps
CPU time 1.44 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:05:17 PM PST 23
Peak memory 198380 kb
Host smart-027b7088-3fac-472f-a688-054756f5b87d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436412502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2436412502
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1488506789
Short name T842
Test name
Test status
Simulation time 8542603224 ps
CPU time 7.39 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:05:14 PM PST 23
Peak memory 197864 kb
Host smart-c5a8afce-c388-4f4a-b9df-fa6ad27ed9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488506789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1488506789
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1892332545
Short name T18
Test name
Test status
Simulation time 50584286579 ps
CPU time 13.45 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 195680 kb
Host smart-8ecab6ee-84af-48c3-88db-ff83d1c297bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892332545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1892332545
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.4141696545
Short name T676
Test name
Test status
Simulation time 484083664 ps
CPU time 2.5 seconds
Started Dec 27 01:04:53 PM PST 23
Finished Dec 27 01:05:05 PM PST 23
Peak memory 198532 kb
Host smart-3a65339d-8564-4a3e-8c02-cfd9d1402975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141696545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4141696545
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3946102849
Short name T949
Test name
Test status
Simulation time 291007697384 ps
CPU time 215.02 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:08:44 PM PST 23
Peak memory 208688 kb
Host smart-3e0c22ac-da99-42c4-a513-9800381a43b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946102849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3946102849
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2019991220
Short name T1133
Test name
Test status
Simulation time 82374519223 ps
CPU time 830.34 seconds
Started Dec 27 01:05:00 PM PST 23
Finished Dec 27 01:19:02 PM PST 23
Peak memory 225144 kb
Host smart-fef118ca-23ff-4754-9fae-ff28774c6140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019991220 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2019991220
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2306376183
Short name T711
Test name
Test status
Simulation time 655983818 ps
CPU time 2.44 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:05:12 PM PST 23
Peak memory 198648 kb
Host smart-4fbfee43-6226-4f95-96c0-c01f089118ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306376183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2306376183
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.216791052
Short name T139
Test name
Test status
Simulation time 16612268469 ps
CPU time 24.18 seconds
Started Dec 27 01:04:54 PM PST 23
Finished Dec 27 01:05:29 PM PST 23
Peak memory 200136 kb
Host smart-f783e6ae-ec75-4e1f-9fec-04865c6821aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216791052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.216791052
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2606587701
Short name T854
Test name
Test status
Simulation time 17375024 ps
CPU time 0.55 seconds
Started Dec 27 01:05:00 PM PST 23
Finished Dec 27 01:05:12 PM PST 23
Peak memory 195624 kb
Host smart-988303a0-436d-43a0-b545-a43aaf612b5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606587701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2606587701
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3591641998
Short name T1046
Test name
Test status
Simulation time 124632984841 ps
CPU time 781.01 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:18:21 PM PST 23
Peak memory 200232 kb
Host smart-2fe23bef-7614-47e1-a054-65b35a5ec2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591641998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3591641998
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.892742463
Short name T1093
Test name
Test status
Simulation time 79093410065 ps
CPU time 64.56 seconds
Started Dec 27 01:04:57 PM PST 23
Finished Dec 27 01:06:13 PM PST 23
Peak memory 200268 kb
Host smart-273d1c04-c399-4f2e-b609-4de712008d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892742463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.892742463
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2650893946
Short name T261
Test name
Test status
Simulation time 7304125605 ps
CPU time 11.85 seconds
Started Dec 27 01:04:59 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 199856 kb
Host smart-a6498815-f598-4eca-8c0b-82753d4d53da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650893946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2650893946
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2169277863
Short name T1198
Test name
Test status
Simulation time 55691864782 ps
CPU time 47.07 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:06:08 PM PST 23
Peak memory 200060 kb
Host smart-50f74b93-c302-49a8-80bb-50c63dc05384
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169277863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2169277863
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1442666161
Short name T602
Test name
Test status
Simulation time 71755384233 ps
CPU time 334.83 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:10:53 PM PST 23
Peak memory 200208 kb
Host smart-f1ac17a5-813a-417e-91b1-f8f25ea84775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442666161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1442666161
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.249390241
Short name T547
Test name
Test status
Simulation time 25625324 ps
CPU time 0.61 seconds
Started Dec 27 01:04:58 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 195632 kb
Host smart-abf3c5e7-82ad-4ea2-90c4-72acffb28655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249390241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.249390241
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.191702173
Short name T432
Test name
Test status
Simulation time 66963186186 ps
CPU time 119.73 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:07:16 PM PST 23
Peak memory 198852 kb
Host smart-d7b083a7-da27-4f1f-b911-f61c4b34d6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191702173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.191702173
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2960648633
Short name T688
Test name
Test status
Simulation time 37001286380 ps
CPU time 1907.29 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:37:09 PM PST 23
Peak memory 200192 kb
Host smart-17676925-818d-49aa-9d52-30efaaf33e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960648633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2960648633
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2013483757
Short name T1051
Test name
Test status
Simulation time 1495929160 ps
CPU time 0.65 seconds
Started Dec 27 01:04:58 PM PST 23
Finished Dec 27 01:05:10 PM PST 23
Peak memory 195624 kb
Host smart-6aeb04b4-9ef1-4854-9941-e002a476f424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013483757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2013483757
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2321372059
Short name T379
Test name
Test status
Simulation time 46678397049 ps
CPU time 38.15 seconds
Started Dec 27 01:04:59 PM PST 23
Finished Dec 27 01:05:49 PM PST 23
Peak memory 199260 kb
Host smart-1019ce9d-01ca-4336-bbcd-df1141c3513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321372059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2321372059
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2931684104
Short name T636
Test name
Test status
Simulation time 67574314275 ps
CPU time 49.33 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:06:09 PM PST 23
Peak memory 195936 kb
Host smart-df8cd4ee-2b69-4d53-bb82-1762d3e2a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931684104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2931684104
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1877223942
Short name T448
Test name
Test status
Simulation time 766346905 ps
CPU time 1.91 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:18 PM PST 23
Peak memory 200072 kb
Host smart-05539866-4d42-48a7-998b-65c89a125e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877223942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1877223942
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2538779501
Short name T963
Test name
Test status
Simulation time 125108088819 ps
CPU time 96.46 seconds
Started Dec 27 01:05:00 PM PST 23
Finished Dec 27 01:06:48 PM PST 23
Peak memory 200212 kb
Host smart-02c4038a-424d-4544-a9e5-626b6b9e075c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538779501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2538779501
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3269452692
Short name T1159
Test name
Test status
Simulation time 79080194606 ps
CPU time 2497.76 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:46:57 PM PST 23
Peak memory 216704 kb
Host smart-1bc22499-d4ed-47cd-85ff-f0c3ab868f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269452692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3269452692
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2730491069
Short name T606
Test name
Test status
Simulation time 258238639 ps
CPU time 1.12 seconds
Started Dec 27 01:04:59 PM PST 23
Finished Dec 27 01:05:12 PM PST 23
Peak memory 195808 kb
Host smart-2a787260-ca89-49f5-8134-470e00d10ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730491069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2730491069
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2804434587
Short name T710
Test name
Test status
Simulation time 104189001903 ps
CPU time 47.1 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:06:10 PM PST 23
Peak memory 200164 kb
Host smart-51b9344c-4349-41f0-9dcc-373460ab0f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804434587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2804434587
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.436741042
Short name T582
Test name
Test status
Simulation time 12286424 ps
CPU time 0.55 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:05:17 PM PST 23
Peak memory 195652 kb
Host smart-2d6df5af-a4fc-4520-9481-c532ca5f4119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436741042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.436741042
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2679369204
Short name T450
Test name
Test status
Simulation time 108754767076 ps
CPU time 82.57 seconds
Started Dec 27 01:05:01 PM PST 23
Finished Dec 27 01:06:35 PM PST 23
Peak memory 200140 kb
Host smart-7a25ad32-6265-41fd-a33a-4885cd8c80d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679369204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2679369204
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3401859604
Short name T900
Test name
Test status
Simulation time 77453195201 ps
CPU time 70.38 seconds
Started Dec 27 01:05:00 PM PST 23
Finished Dec 27 01:06:22 PM PST 23
Peak memory 200188 kb
Host smart-c2e70352-f8bf-48d5-83fb-ad187a99c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401859604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3401859604
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2380974295
Short name T324
Test name
Test status
Simulation time 74599237244 ps
CPU time 16.45 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:05:37 PM PST 23
Peak memory 200000 kb
Host smart-ac2f85b4-fc46-44bc-8c26-f61d9ae5ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380974295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2380974295
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2687849242
Short name T776
Test name
Test status
Simulation time 194760968184 ps
CPU time 305.53 seconds
Started Dec 27 01:04:56 PM PST 23
Finished Dec 27 01:10:13 PM PST 23
Peak memory 199652 kb
Host smart-73b00bd7-468b-4f3d-aea8-9e75778d6dff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687849242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2687849242
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3311636108
Short name T851
Test name
Test status
Simulation time 149303456591 ps
CPU time 488.26 seconds
Started Dec 27 01:05:15 PM PST 23
Finished Dec 27 01:13:32 PM PST 23
Peak memory 199808 kb
Host smart-283089b3-f893-4c78-ac77-e9d50c4cc134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311636108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3311636108
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2207941838
Short name T654
Test name
Test status
Simulation time 11174530857 ps
CPU time 20.17 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:05:41 PM PST 23
Peak memory 200152 kb
Host smart-cb523f24-9200-4fb7-95a3-8c1a3e18ae11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207941838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2207941838
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2507943560
Short name T22
Test name
Test status
Simulation time 9520627803 ps
CPU time 16.99 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:05:32 PM PST 23
Peak memory 197944 kb
Host smart-42dbe447-dc05-4ca0-9059-6b5f69680c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507943560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2507943560
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1977209327
Short name T1092
Test name
Test status
Simulation time 4614198242 ps
CPU time 114.04 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:07:09 PM PST 23
Peak memory 200088 kb
Host smart-2202c912-f25f-41d2-9faa-dcd1a14be279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977209327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1977209327
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2584311891
Short name T727
Test name
Test status
Simulation time 2132277637 ps
CPU time 11.41 seconds
Started Dec 27 01:04:59 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 198268 kb
Host smart-e3d09af3-de8f-4e2c-81f1-feb8474140c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584311891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2584311891
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3270392350
Short name T400
Test name
Test status
Simulation time 84122788481 ps
CPU time 35.69 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:05:53 PM PST 23
Peak memory 199764 kb
Host smart-d9e5eb63-455f-4bab-9341-0184ebb0c746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270392350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3270392350
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1800128017
Short name T920
Test name
Test status
Simulation time 4259013443 ps
CPU time 2.54 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:05:24 PM PST 23
Peak memory 195984 kb
Host smart-aa25c4dd-ccb4-43fe-8ae2-e9ff97e8b653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800128017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1800128017
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1089135553
Short name T637
Test name
Test status
Simulation time 6243248156 ps
CPU time 9.27 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:05:32 PM PST 23
Peak memory 199048 kb
Host smart-e4e3b924-1e33-4f30-8e10-9829183ae0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089135553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1089135553
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1533666035
Short name T269
Test name
Test status
Simulation time 130505606487 ps
CPU time 652.68 seconds
Started Dec 27 01:04:58 PM PST 23
Finished Dec 27 01:16:02 PM PST 23
Peak memory 225152 kb
Host smart-d34160e8-9098-4052-bc58-f41ba782201d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533666035 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1533666035
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2873556767
Short name T790
Test name
Test status
Simulation time 2094741171 ps
CPU time 2.88 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 198500 kb
Host smart-9c8aea57-5db7-4169-abad-43b5744287a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873556767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2873556767
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.843027014
Short name T713
Test name
Test status
Simulation time 248560486176 ps
CPU time 125.25 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:07:27 PM PST 23
Peak memory 200140 kb
Host smart-822bf021-562f-4ce4-a3fa-139bd0be3d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843027014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.843027014
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1108781728
Short name T84
Test name
Test status
Simulation time 12851162 ps
CPU time 0.54 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:05:17 PM PST 23
Peak memory 194584 kb
Host smart-b22c2eca-8895-45af-ae71-ce8906adcf5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108781728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1108781728
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3180027223
Short name T360
Test name
Test status
Simulation time 29617641788 ps
CPU time 29.56 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:05:47 PM PST 23
Peak memory 200204 kb
Host smart-3cf85c01-bba1-478d-9895-6c6ee5b80555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180027223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3180027223
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4023125418
Short name T382
Test name
Test status
Simulation time 95195249877 ps
CPU time 37.66 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:05:53 PM PST 23
Peak memory 199092 kb
Host smart-bbec7245-23b5-4492-b8bc-401cd60153d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023125418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4023125418
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1757063596
Short name T1169
Test name
Test status
Simulation time 76303691834 ps
CPU time 35.33 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:06:00 PM PST 23
Peak memory 200204 kb
Host smart-68e21ca3-89ca-49fc-b7c8-2f5ac401cb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757063596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1757063596
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4161390321
Short name T889
Test name
Test status
Simulation time 110343312632 ps
CPU time 156.25 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:07:58 PM PST 23
Peak memory 199644 kb
Host smart-5469c380-b97c-48df-a8c4-0b109962701e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161390321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4161390321
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.840026072
Short name T1154
Test name
Test status
Simulation time 166710452131 ps
CPU time 74.82 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:06:30 PM PST 23
Peak memory 200208 kb
Host smart-42e587d2-715f-446b-856a-bfdbb651f673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840026072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.840026072
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.109959663
Short name T948
Test name
Test status
Simulation time 8691578846 ps
CPU time 6.33 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:23 PM PST 23
Peak memory 199544 kb
Host smart-cfc4cc1d-4e43-4bd2-bee8-ad01d606752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109959663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.109959663
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1648034744
Short name T1171
Test name
Test status
Simulation time 73831739318 ps
CPU time 28.88 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:05:44 PM PST 23
Peak memory 198836 kb
Host smart-242d0f25-001d-489d-b619-3595b654a6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648034744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1648034744
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.691048117
Short name T1181
Test name
Test status
Simulation time 25622489000 ps
CPU time 285.31 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:10:00 PM PST 23
Peak memory 200176 kb
Host smart-ae9c7318-29d8-476c-a9cd-e0e65e8dfaca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691048117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.691048117
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3974405228
Short name T729
Test name
Test status
Simulation time 1923021370 ps
CPU time 5.42 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 198284 kb
Host smart-0e120b72-0886-4005-9d34-65bc87d3f279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974405228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3974405228
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1450046826
Short name T774
Test name
Test status
Simulation time 222813479893 ps
CPU time 130.26 seconds
Started Dec 27 01:07:10 PM PST 23
Finished Dec 27 01:09:21 PM PST 23
Peak memory 200204 kb
Host smart-7d245cd6-0784-4929-86cd-081a245ca107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450046826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1450046826
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3790277601
Short name T994
Test name
Test status
Simulation time 3081742305 ps
CPU time 3.16 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:05:23 PM PST 23
Peak memory 196064 kb
Host smart-f1269f28-9f05-43c9-b6a8-c420eb9ee12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790277601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3790277601
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1953396010
Short name T527
Test name
Test status
Simulation time 297558816 ps
CPU time 0.87 seconds
Started Dec 27 01:05:05 PM PST 23
Finished Dec 27 01:05:15 PM PST 23
Peak memory 196980 kb
Host smart-ce75e545-b1e3-405c-bbb9-7bd8669289e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953396010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1953396010
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1393649039
Short name T213
Test name
Test status
Simulation time 156735969652 ps
CPU time 51.41 seconds
Started Dec 27 01:05:05 PM PST 23
Finished Dec 27 01:06:06 PM PST 23
Peak memory 200224 kb
Host smart-d110fa63-1953-414e-b0d4-4fdd2655a1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393649039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1393649039
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2985446827
Short name T970
Test name
Test status
Simulation time 30369259071 ps
CPU time 305.75 seconds
Started Dec 27 01:05:05 PM PST 23
Finished Dec 27 01:10:20 PM PST 23
Peak memory 216656 kb
Host smart-95b179dd-36d3-4efa-bced-331f904462e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985446827 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2985446827
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.330814891
Short name T583
Test name
Test status
Simulation time 280945053 ps
CPU time 0.98 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:05:23 PM PST 23
Peak memory 197632 kb
Host smart-d55a47cc-d687-41f8-89a6-b9123302e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330814891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.330814891
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.942005924
Short name T457
Test name
Test status
Simulation time 4501912085 ps
CPU time 5.44 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:21 PM PST 23
Peak memory 200188 kb
Host smart-89547482-2d3a-493e-ae74-73fe874e24d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942005924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.942005924
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3667682067
Short name T824
Test name
Test status
Simulation time 42168405 ps
CPU time 0.55 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:17 PM PST 23
Peak memory 195652 kb
Host smart-5213ff3d-67a1-4e02-b057-f7968e0f78ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667682067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3667682067
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.580790572
Short name T1149
Test name
Test status
Simulation time 254336341578 ps
CPU time 245.83 seconds
Started Dec 27 01:05:15 PM PST 23
Finished Dec 27 01:09:30 PM PST 23
Peak memory 200256 kb
Host smart-67f6148d-c9ef-44f4-86e6-55e58361a4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580790572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.580790572
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2843625069
Short name T733
Test name
Test status
Simulation time 124846437847 ps
CPU time 102.8 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:06:58 PM PST 23
Peak memory 199672 kb
Host smart-cdc89729-51a5-48e0-91e9-2add74ce9d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843625069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2843625069
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.4003134
Short name T310
Test name
Test status
Simulation time 271587353037 ps
CPU time 48.92 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:06:11 PM PST 23
Peak memory 200140 kb
Host smart-17d55348-68e2-4c07-a898-ab2b9ed38fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.4003134
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.152309451
Short name T983
Test name
Test status
Simulation time 43240105776 ps
CPU time 21.35 seconds
Started Dec 27 01:05:15 PM PST 23
Finished Dec 27 01:05:45 PM PST 23
Peak memory 199468 kb
Host smart-6fc17ef3-b5bb-43bc-800b-39e2a4c1f676
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152309451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.152309451
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1238165310
Short name T802
Test name
Test status
Simulation time 250173739063 ps
CPU time 378.84 seconds
Started Dec 27 01:05:15 PM PST 23
Finished Dec 27 01:11:43 PM PST 23
Peak memory 200232 kb
Host smart-d0ad4d7a-2b9b-4e29-b66b-75056727cd6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238165310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1238165310
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2449945901
Short name T1107
Test name
Test status
Simulation time 11061387930 ps
CPU time 11.77 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:05:27 PM PST 23
Peak memory 198608 kb
Host smart-1e11ecc3-ef53-4397-b390-10232bf92fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449945901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2449945901
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1210439807
Short name T110
Test name
Test status
Simulation time 207419696217 ps
CPU time 166.24 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:08:01 PM PST 23
Peak memory 208604 kb
Host smart-3dedec13-a8b4-4eec-a8f1-e75d3ba93eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210439807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1210439807
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1849300392
Short name T1168
Test name
Test status
Simulation time 17974329963 ps
CPU time 195.21 seconds
Started Dec 27 01:05:08 PM PST 23
Finished Dec 27 01:08:31 PM PST 23
Peak memory 200132 kb
Host smart-d0c06851-321a-439b-8137-c606c9266051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849300392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1849300392
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.942708021
Short name T1130
Test name
Test status
Simulation time 40102702190 ps
CPU time 15.6 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:05:34 PM PST 23
Peak memory 200236 kb
Host smart-3bc23374-0d50-4cdf-8a63-8877e2889ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942708021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.942708021
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.184380130
Short name T772
Test name
Test status
Simulation time 37781197197 ps
CPU time 59.17 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:06:14 PM PST 23
Peak memory 195956 kb
Host smart-a6055dd0-3ca5-4cc1-af60-d8dc5d8b3fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184380130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.184380130
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.971527252
Short name T647
Test name
Test status
Simulation time 730320864 ps
CPU time 1.43 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:05:24 PM PST 23
Peak memory 198140 kb
Host smart-ff0508da-14ed-4199-bcf8-a4a4c1ac8de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971527252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.971527252
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.343747222
Short name T403
Test name
Test status
Simulation time 421305717029 ps
CPU time 85.48 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:06:47 PM PST 23
Peak memory 200148 kb
Host smart-1f48f9ea-aa31-4e1a-ae23-550fb0a09fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343747222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.343747222
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1714976967
Short name T658
Test name
Test status
Simulation time 82865467240 ps
CPU time 1824.15 seconds
Started Dec 27 01:05:16 PM PST 23
Finished Dec 27 01:35:48 PM PST 23
Peak memory 225112 kb
Host smart-4af4abbc-e926-4363-8ab0-75e4853a8444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714976967 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1714976967
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.795796318
Short name T870
Test name
Test status
Simulation time 3789458842 ps
CPU time 1.84 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:05:25 PM PST 23
Peak memory 198348 kb
Host smart-4a4af349-0bb9-485e-a3c7-5276022228bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795796318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.795796318
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2487628016
Short name T518
Test name
Test status
Simulation time 26142596164 ps
CPU time 10.81 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:05:31 PM PST 23
Peak memory 196080 kb
Host smart-472ed43e-e169-4f64-9dc1-11d3e8c91acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487628016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2487628016
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.969894695
Short name T877
Test name
Test status
Simulation time 56986452 ps
CPU time 0.55 seconds
Started Dec 27 01:05:16 PM PST 23
Finished Dec 27 01:05:24 PM PST 23
Peak memory 194672 kb
Host smart-4461b417-9bbe-48ca-b038-c077e1d0f335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969894695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.969894695
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.186148305
Short name T335
Test name
Test status
Simulation time 82415466508 ps
CPU time 10.84 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:05:33 PM PST 23
Peak memory 200092 kb
Host smart-067f84d7-49ab-430e-bbe4-270d08c2f114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186148305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.186148305
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2335464519
Short name T1226
Test name
Test status
Simulation time 69594889363 ps
CPU time 26.04 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:05:48 PM PST 23
Peak memory 200220 kb
Host smart-b563ce20-65b0-4f0c-a546-ba2677f85f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335464519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2335464519
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3990082315
Short name T137
Test name
Test status
Simulation time 167411718850 ps
CPU time 177.74 seconds
Started Dec 27 01:05:06 PM PST 23
Finished Dec 27 01:08:13 PM PST 23
Peak memory 200144 kb
Host smart-316c8718-5920-4a87-9e47-00cdb935fa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990082315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3990082315
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1741458794
Short name T910
Test name
Test status
Simulation time 142662094824 ps
CPU time 131.24 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:07:29 PM PST 23
Peak memory 200196 kb
Host smart-bf6beb53-2802-4157-aff7-a43b43a11ea6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741458794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1741458794
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2680491189
Short name T683
Test name
Test status
Simulation time 57013715214 ps
CPU time 206.45 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:08:45 PM PST 23
Peak memory 200176 kb
Host smart-607acc02-92a3-4575-8fb2-b1e965612d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2680491189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2680491189
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.941671567
Short name T641
Test name
Test status
Simulation time 6914178698 ps
CPU time 2.99 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:05:28 PM PST 23
Peak memory 199488 kb
Host smart-7e927f36-fbc1-4c93-8494-9aecca88439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941671567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.941671567
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3239563015
Short name T742
Test name
Test status
Simulation time 46570617678 ps
CPU time 74.14 seconds
Started Dec 27 01:05:18 PM PST 23
Finished Dec 27 01:06:39 PM PST 23
Peak memory 199444 kb
Host smart-66100103-a1b4-4594-b284-d485c8a88a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239563015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3239563015
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.709514455
Short name T815
Test name
Test status
Simulation time 20011569952 ps
CPU time 1086.62 seconds
Started Dec 27 01:05:13 PM PST 23
Finished Dec 27 01:23:28 PM PST 23
Peak memory 200220 kb
Host smart-a1e46857-0411-4c4f-b5fb-1973d59e8d66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709514455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.709514455
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.291529798
Short name T921
Test name
Test status
Simulation time 831654262 ps
CPU time 4.44 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:05:25 PM PST 23
Peak memory 197952 kb
Host smart-ab863f7b-7017-4ab6-a466-449b4d0280af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291529798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.291529798
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3288777610
Short name T1069
Test name
Test status
Simulation time 58800065047 ps
CPU time 100.68 seconds
Started Dec 27 01:05:16 PM PST 23
Finished Dec 27 01:07:05 PM PST 23
Peak memory 200180 kb
Host smart-179c7062-d134-46e8-bf55-a1e10c5417b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288777610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3288777610
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.4153853892
Short name T973
Test name
Test status
Simulation time 40705453738 ps
CPU time 60.5 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:06:20 PM PST 23
Peak memory 195716 kb
Host smart-f05b18f6-1f07-4165-9586-6812f1c8b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153853892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.4153853892
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3382167464
Short name T761
Test name
Test status
Simulation time 283756323 ps
CPU time 0.97 seconds
Started Dec 27 01:05:07 PM PST 23
Finished Dec 27 01:05:16 PM PST 23
Peak memory 198204 kb
Host smart-d0df5722-d162-4909-9ff4-d5b6355a1d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382167464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3382167464
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2131528167
Short name T282
Test name
Test status
Simulation time 137695500073 ps
CPU time 217.77 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:08:58 PM PST 23
Peak memory 200448 kb
Host smart-6b8a7a54-67be-4b0c-be03-e60c75bc62a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131528167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2131528167
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3885721958
Short name T1190
Test name
Test status
Simulation time 529596828538 ps
CPU time 705.04 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:17:03 PM PST 23
Peak memory 226604 kb
Host smart-078be7b9-87d3-4117-9bab-08c3e48366a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885721958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3885721958
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2840247789
Short name T1015
Test name
Test status
Simulation time 994375078 ps
CPU time 3.73 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:05:22 PM PST 23
Peak memory 198796 kb
Host smart-ace493bc-f31b-4c80-a334-172fed75b673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840247789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2840247789
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3599411461
Short name T1211
Test name
Test status
Simulation time 97475585155 ps
CPU time 205.06 seconds
Started Dec 27 01:05:09 PM PST 23
Finished Dec 27 01:08:42 PM PST 23
Peak memory 200220 kb
Host smart-65439453-6ec8-46cc-ba9c-1f612dfaf8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599411461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3599411461
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3404016897
Short name T719
Test name
Test status
Simulation time 27823564 ps
CPU time 0.58 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:03:41 PM PST 23
Peak memory 195592 kb
Host smart-651e537d-a02e-48b4-bb2e-531a951d0133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404016897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3404016897
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1621530817
Short name T728
Test name
Test status
Simulation time 190970433761 ps
CPU time 275.73 seconds
Started Dec 27 01:03:16 PM PST 23
Finished Dec 27 01:07:57 PM PST 23
Peak memory 200296 kb
Host smart-44528a81-8966-47d3-8f8b-39291f7e98f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621530817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1621530817
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.445196875
Short name T679
Test name
Test status
Simulation time 26417598573 ps
CPU time 13.04 seconds
Started Dec 27 01:03:22 PM PST 23
Finished Dec 27 01:03:36 PM PST 23
Peak memory 198216 kb
Host smart-7ef56fad-1405-4ae6-9c70-107ee04a7807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445196875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.445196875
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1835351421
Short name T1210
Test name
Test status
Simulation time 95083810678 ps
CPU time 16.33 seconds
Started Dec 27 01:03:27 PM PST 23
Finished Dec 27 01:03:46 PM PST 23
Peak memory 199932 kb
Host smart-a5432a72-d56f-4a82-ad57-26f251cd2ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835351421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1835351421
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.199118644
Short name T1005
Test name
Test status
Simulation time 1511762906794 ps
CPU time 870.39 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:17:55 PM PST 23
Peak memory 200204 kb
Host smart-d55e3e50-9735-44a7-8139-fb01a5ae63e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199118644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.199118644
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1020733565
Short name T1066
Test name
Test status
Simulation time 155870975042 ps
CPU time 657.55 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:14:30 PM PST 23
Peak memory 200216 kb
Host smart-8f76242f-d503-41b5-8b97-cacfd57e736c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020733565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1020733565
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2357168789
Short name T1223
Test name
Test status
Simulation time 34696850782 ps
CPU time 16.79 seconds
Started Dec 27 01:03:23 PM PST 23
Finished Dec 27 01:03:41 PM PST 23
Peak memory 198008 kb
Host smart-e5132702-82e5-4dc6-8e75-989a1aecac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357168789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2357168789
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2912257640
Short name T613
Test name
Test status
Simulation time 30678816756 ps
CPU time 1353.54 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:26:16 PM PST 23
Peak memory 199920 kb
Host smart-62fe8e2b-ad08-4a8d-a04d-361662bd158f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912257640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2912257640
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3729957029
Short name T29
Test name
Test status
Simulation time 148241206 ps
CPU time 0.61 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:36 PM PST 23
Peak memory 195644 kb
Host smart-c3e022ff-95f4-4272-b2a6-be6824637bf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729957029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3729957029
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1432798989
Short name T1047
Test name
Test status
Simulation time 153282966528 ps
CPU time 94.11 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:05:15 PM PST 23
Peak memory 200172 kb
Host smart-2e84db9c-9ffa-40d1-a826-4220026261e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432798989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1432798989
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.623718603
Short name T1096
Test name
Test status
Simulation time 625173318 ps
CPU time 1.82 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:03:34 PM PST 23
Peak memory 195592 kb
Host smart-4ea84f06-37ce-4d27-b962-1336a88fb4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623718603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.623718603
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3208905196
Short name T424
Test name
Test status
Simulation time 632745320 ps
CPU time 1.75 seconds
Started Dec 27 01:03:25 PM PST 23
Finished Dec 27 01:03:31 PM PST 23
Peak memory 199580 kb
Host smart-5fb9c142-af97-4422-823f-f6d0b188d5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208905196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3208905196
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2882278190
Short name T267
Test name
Test status
Simulation time 148302586203 ps
CPU time 1308.02 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:25:36 PM PST 23
Peak memory 225116 kb
Host smart-40702d15-da0c-496a-b447-39f7d51d4481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882278190 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2882278190
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2595969510
Short name T1188
Test name
Test status
Simulation time 1816307559 ps
CPU time 2.24 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:38 PM PST 23
Peak memory 198704 kb
Host smart-a67104a6-aa89-4c14-af29-89d05a0876f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595969510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2595969510
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1706633642
Short name T834
Test name
Test status
Simulation time 62794886609 ps
CPU time 104.13 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:05:18 PM PST 23
Peak memory 200180 kb
Host smart-710e6daf-efdc-4e6c-a56c-fc7afbbe964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706633642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1706633642
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3243423060
Short name T278
Test name
Test status
Simulation time 169960044635 ps
CPU time 220.47 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:08:58 PM PST 23
Peak memory 199788 kb
Host smart-de06ad6c-06db-48bd-b659-ea2820e883c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243423060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3243423060
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1739288636
Short name T813
Test name
Test status
Simulation time 349437719757 ps
CPU time 1312.3 seconds
Started Dec 27 01:05:18 PM PST 23
Finished Dec 27 01:27:17 PM PST 23
Peak memory 225688 kb
Host smart-e509f7b8-0714-470f-9539-b24dee2d05be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739288636 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1739288636
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1963763051
Short name T821
Test name
Test status
Simulation time 118159518382 ps
CPU time 100.65 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:06:58 PM PST 23
Peak memory 200244 kb
Host smart-64bb8a90-575b-486b-953c-54d58fe08e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963763051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1963763051
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2002626154
Short name T1070
Test name
Test status
Simulation time 59241624165 ps
CPU time 472.02 seconds
Started Dec 27 01:05:12 PM PST 23
Finished Dec 27 01:13:12 PM PST 23
Peak memory 216636 kb
Host smart-0102ede5-9050-468a-b91d-951f147c943a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002626154 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2002626154
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.840937233
Short name T274
Test name
Test status
Simulation time 151926224069 ps
CPU time 111.93 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:07:17 PM PST 23
Peak memory 199384 kb
Host smart-7fe3c081-40a1-4ff0-a8f4-073cd6f5cebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840937233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.840937233
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3076835627
Short name T591
Test name
Test status
Simulation time 49188265610 ps
CPU time 14.63 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:05:40 PM PST 23
Peak memory 199616 kb
Host smart-a0b627f5-7a5c-4e97-80b2-d198c223220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076835627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3076835627
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1292564338
Short name T767
Test name
Test status
Simulation time 20444244791 ps
CPU time 215.03 seconds
Started Dec 27 01:05:11 PM PST 23
Finished Dec 27 01:08:54 PM PST 23
Peak memory 216936 kb
Host smart-c7be7e0c-6a66-4320-8c88-8df366385118
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292564338 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1292564338
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2835579688
Short name T1042
Test name
Test status
Simulation time 61554391010 ps
CPU time 33.39 seconds
Started Dec 27 01:05:10 PM PST 23
Finished Dec 27 01:05:51 PM PST 23
Peak memory 200160 kb
Host smart-c0442590-71af-42a4-a5b3-aae2156e41a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835579688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2835579688
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3458365797
Short name T59
Test name
Test status
Simulation time 245061080453 ps
CPU time 441.07 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:12:46 PM PST 23
Peak memory 216928 kb
Host smart-171c67d2-3ac3-47ca-bb63-f0f7f8c47fe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458365797 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3458365797
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2907928123
Short name T936
Test name
Test status
Simulation time 104695495794 ps
CPU time 12.34 seconds
Started Dec 27 01:05:15 PM PST 23
Finished Dec 27 01:05:36 PM PST 23
Peak memory 200188 kb
Host smart-904379f3-0aa5-4ad1-9a1d-a94769b613ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907928123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2907928123
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3147702613
Short name T1208
Test name
Test status
Simulation time 700922140585 ps
CPU time 1154.12 seconds
Started Dec 27 01:05:16 PM PST 23
Finished Dec 27 01:24:38 PM PST 23
Peak memory 225136 kb
Host smart-ab1c8aa1-1fce-4bb9-91d1-5214140c727e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147702613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3147702613
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3121627312
Short name T1172
Test name
Test status
Simulation time 124972469755 ps
CPU time 330.06 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:10:55 PM PST 23
Peak memory 215912 kb
Host smart-7a14cfa4-a8d7-4a72-a102-079999cde1fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121627312 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3121627312
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1194131037
Short name T203
Test name
Test status
Simulation time 97439999782 ps
CPU time 16.87 seconds
Started Dec 27 01:05:18 PM PST 23
Finished Dec 27 01:05:43 PM PST 23
Peak memory 199416 kb
Host smart-8255c2a4-0f5e-47eb-a51c-de924c04a8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194131037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1194131037
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1796450663
Short name T1048
Test name
Test status
Simulation time 14653761968 ps
CPU time 581.9 seconds
Started Dec 27 01:05:14 PM PST 23
Finished Dec 27 01:15:05 PM PST 23
Peak memory 208960 kb
Host smart-850bad4d-9059-46d2-81b0-da173c19e12d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796450663 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1796450663
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.364893337
Short name T838
Test name
Test status
Simulation time 20329332 ps
CPU time 0.54 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:49 PM PST 23
Peak memory 194628 kb
Host smart-2a68aa7d-3896-4a7f-8871-54d590ae3cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364893337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.364893337
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3564082033
Short name T736
Test name
Test status
Simulation time 239747455382 ps
CPU time 195.8 seconds
Started Dec 27 01:03:41 PM PST 23
Finished Dec 27 01:07:02 PM PST 23
Peak memory 200096 kb
Host smart-1cee01fd-1733-4cf7-a3fc-75ae261535ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564082033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3564082033
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.671959104
Short name T1099
Test name
Test status
Simulation time 129055316810 ps
CPU time 253.06 seconds
Started Dec 27 01:03:43 PM PST 23
Finished Dec 27 01:08:02 PM PST 23
Peak memory 200248 kb
Host smart-d011df9e-da3d-41a6-877f-dcc5f2ddce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671959104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.671959104
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.92530004
Short name T959
Test name
Test status
Simulation time 1246686338285 ps
CPU time 1632.23 seconds
Started Dec 27 01:03:45 PM PST 23
Finished Dec 27 01:31:02 PM PST 23
Peak memory 200116 kb
Host smart-0f16b91b-9008-486c-aedf-b520637fd24e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92530004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.92530004
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2284994501
Short name T1140
Test name
Test status
Simulation time 122407275921 ps
CPU time 218.14 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:07:38 PM PST 23
Peak memory 200188 kb
Host smart-40e96e52-933d-4bbf-ae78-8b37ba798fce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284994501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2284994501
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1671237905
Short name T744
Test name
Test status
Simulation time 5664501598 ps
CPU time 6.35 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:03:50 PM PST 23
Peak memory 197808 kb
Host smart-f6c906de-7010-4a2c-ba09-b5a72a5af230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671237905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1671237905
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2810825584
Short name T893
Test name
Test status
Simulation time 29773719366 ps
CPU time 57.82 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:04:55 PM PST 23
Peak memory 199392 kb
Host smart-ac98cd05-2808-4267-83ce-19bdfcc360db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810825584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2810825584
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.410069398
Short name T1209
Test name
Test status
Simulation time 25398015491 ps
CPU time 702.66 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:15:28 PM PST 23
Peak memory 200204 kb
Host smart-e26b5385-6009-4abb-a966-5afd6e5dbdc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410069398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.410069398
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3203452515
Short name T467
Test name
Test status
Simulation time 861125081 ps
CPU time 8.14 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:03:51 PM PST 23
Peak memory 198424 kb
Host smart-f6324da9-8e79-4478-9445-5f7802a308d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203452515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3203452515
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.944785504
Short name T351
Test name
Test status
Simulation time 67388467639 ps
CPU time 12.63 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:54 PM PST 23
Peak memory 199596 kb
Host smart-d76ca59c-64a2-44f2-92ed-efea5bb043fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944785504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.944785504
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2333416668
Short name T571
Test name
Test status
Simulation time 1567677759 ps
CPU time 1.75 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:03:45 PM PST 23
Peak memory 195608 kb
Host smart-8e793d42-acc9-47ec-b4bb-28a0602732ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333416668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2333416668
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1012519346
Short name T1087
Test name
Test status
Simulation time 292672924 ps
CPU time 1.63 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 198544 kb
Host smart-4a574ad5-c448-46cf-bbdc-e3a01b96cb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012519346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1012519346
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3203673660
Short name T930
Test name
Test status
Simulation time 170875665046 ps
CPU time 380.41 seconds
Started Dec 27 01:03:17 PM PST 23
Finished Dec 27 01:09:42 PM PST 23
Peak memory 216920 kb
Host smart-280694ab-c02d-4d5f-9c9d-b2b2b9a0f11b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203673660 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3203673660
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1688094591
Short name T446
Test name
Test status
Simulation time 6371674696 ps
CPU time 20.15 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:03 PM PST 23
Peak memory 199720 kb
Host smart-34932c61-a698-4659-a372-5a534de28db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688094591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1688094591
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2796212277
Short name T1115
Test name
Test status
Simulation time 137258057603 ps
CPU time 33.85 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:17 PM PST 23
Peak memory 200204 kb
Host smart-34f2f5f8-a588-4a59-a3fb-6831f92f95ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796212277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2796212277
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2367783133
Short name T223
Test name
Test status
Simulation time 78677803504 ps
CPU time 80.61 seconds
Started Dec 27 01:05:17 PM PST 23
Finished Dec 27 01:06:46 PM PST 23
Peak memory 200208 kb
Host smart-2c082e70-a9f9-4bfc-b7cb-beb0efd6f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367783133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2367783133
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2827731618
Short name T1024
Test name
Test status
Simulation time 193147024010 ps
CPU time 385.85 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:12:01 PM PST 23
Peak memory 211652 kb
Host smart-cf91a320-6859-453c-8257-7315a3f65635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827731618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2827731618
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3848988105
Short name T314
Test name
Test status
Simulation time 88974970511 ps
CPU time 61.85 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:06:34 PM PST 23
Peak memory 200044 kb
Host smart-d6e7d432-cc1c-4e62-89a5-8f16f4daa73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848988105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3848988105
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3819510906
Short name T363
Test name
Test status
Simulation time 268462043976 ps
CPU time 449.37 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:13:02 PM PST 23
Peak memory 225160 kb
Host smart-8775a822-d84d-4ab1-b7b1-b5e62f203e65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819510906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3819510906
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2971011808
Short name T902
Test name
Test status
Simulation time 9172877989 ps
CPU time 14.17 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:05:46 PM PST 23
Peak memory 200120 kb
Host smart-91776ab9-104e-45aa-be83-ab624347589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971011808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2971011808
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2108783186
Short name T442
Test name
Test status
Simulation time 79202353502 ps
CPU time 708.1 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:17:20 PM PST 23
Peak memory 216076 kb
Host smart-6f282f15-7bd9-44e0-bb9a-19e15f977102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108783186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2108783186
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3841551740
Short name T141
Test name
Test status
Simulation time 118345001331 ps
CPU time 17.68 seconds
Started Dec 27 01:05:20 PM PST 23
Finished Dec 27 01:05:44 PM PST 23
Peak memory 200152 kb
Host smart-c3e0da2a-a951-466c-9599-9944514dfa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841551740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3841551740
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3850296094
Short name T338
Test name
Test status
Simulation time 22075768634 ps
CPU time 9.52 seconds
Started Dec 27 01:05:31 PM PST 23
Finished Dec 27 01:05:43 PM PST 23
Peak memory 200248 kb
Host smart-a3ba06c6-3b9a-43f9-943f-0867b8a1805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850296094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3850296094
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.738843484
Short name T623
Test name
Test status
Simulation time 248797187903 ps
CPU time 635.37 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:16:08 PM PST 23
Peak memory 229752 kb
Host smart-14e930cd-9e9f-43cc-8bae-25f287c80f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738843484 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.738843484
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3315786449
Short name T782
Test name
Test status
Simulation time 167769651649 ps
CPU time 143.72 seconds
Started Dec 27 01:05:27 PM PST 23
Finished Dec 27 01:07:55 PM PST 23
Peak memory 199744 kb
Host smart-806aa850-82ce-4dd6-9591-5ec3b1de0448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315786449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3315786449
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3218512554
Short name T315
Test name
Test status
Simulation time 31735522174 ps
CPU time 380.56 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:11:52 PM PST 23
Peak memory 216616 kb
Host smart-d065a499-0cc7-4547-8984-998c2a5b95f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218512554 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3218512554
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.117781477
Short name T812
Test name
Test status
Simulation time 53322968208 ps
CPU time 23.47 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:05:55 PM PST 23
Peak memory 199788 kb
Host smart-65aa234e-6c82-4838-b2f3-fb0750e10d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117781477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.117781477
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2783267770
Short name T427
Test name
Test status
Simulation time 51203399890 ps
CPU time 844.8 seconds
Started Dec 27 01:05:38 PM PST 23
Finished Dec 27 01:19:45 PM PST 23
Peak memory 225028 kb
Host smart-b238565a-0899-4e77-b697-91682b0f056d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783267770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2783267770
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.970982913
Short name T1063
Test name
Test status
Simulation time 58583808786 ps
CPU time 177.62 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:08:30 PM PST 23
Peak memory 216996 kb
Host smart-f5b6ee4f-0c9c-4d60-89ad-e3efae8c1931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970982913 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.970982913
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2370730719
Short name T126
Test name
Test status
Simulation time 250803769299 ps
CPU time 128.97 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:07:40 PM PST 23
Peak memory 200184 kb
Host smart-1ad5ead7-ffc2-4257-8301-905a7a234119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370730719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2370730719
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1261713792
Short name T1200
Test name
Test status
Simulation time 337377984127 ps
CPU time 859.36 seconds
Started Dec 27 01:05:27 PM PST 23
Finished Dec 27 01:19:49 PM PST 23
Peak memory 225080 kb
Host smart-b9d11132-ed3e-440f-8642-da16ef1cb4fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261713792 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1261713792
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.462744422
Short name T1186
Test name
Test status
Simulation time 167436766286 ps
CPU time 136.56 seconds
Started Dec 27 01:05:30 PM PST 23
Finished Dec 27 01:07:49 PM PST 23
Peak memory 200292 kb
Host smart-19f4924e-fa6a-4cd8-ab96-811380440f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462744422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.462744422
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1023216071
Short name T329
Test name
Test status
Simulation time 263564892529 ps
CPU time 820.44 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:19:15 PM PST 23
Peak memory 216676 kb
Host smart-168935a1-1de1-411a-a777-1dd42fa942a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023216071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1023216071
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2687419979
Short name T1033
Test name
Test status
Simulation time 19789171 ps
CPU time 0.56 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:42 PM PST 23
Peak memory 195664 kb
Host smart-1c3ac4b4-6183-485a-be31-56b62b147403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687419979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2687419979
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.48903504
Short name T345
Test name
Test status
Simulation time 109674713966 ps
CPU time 17.75 seconds
Started Dec 27 01:03:24 PM PST 23
Finished Dec 27 01:03:44 PM PST 23
Peak memory 199864 kb
Host smart-2b80c506-4428-49bc-8a57-3da798b8f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48903504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.48903504
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4272966312
Short name T1088
Test name
Test status
Simulation time 11183063892 ps
CPU time 4.64 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:40 PM PST 23
Peak memory 198768 kb
Host smart-ab894630-74a7-4670-bf9f-e130d98687fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272966312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4272966312
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1233283344
Short name T565
Test name
Test status
Simulation time 115687566208 ps
CPU time 517.78 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:12:19 PM PST 23
Peak memory 200220 kb
Host smart-91d32310-b9c8-4702-b514-d06a0dbe60cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233283344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1233283344
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1259141793
Short name T937
Test name
Test status
Simulation time 3695865668 ps
CPU time 7.05 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:03:39 PM PST 23
Peak memory 197480 kb
Host smart-ac72a7dc-2423-44bb-ad32-4dc1a9940ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259141793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1259141793
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1064785666
Short name T1180
Test name
Test status
Simulation time 58559337275 ps
CPU time 133.49 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:05:50 PM PST 23
Peak memory 199664 kb
Host smart-a3f0a3c2-682b-4321-aa0f-2e3582f8215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064785666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1064785666
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2911818957
Short name T587
Test name
Test status
Simulation time 15516034882 ps
CPU time 332.09 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:09:15 PM PST 23
Peak memory 200228 kb
Host smart-13df7193-f825-41ee-8340-8a9908e76816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2911818957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2911818957
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1897156129
Short name T563
Test name
Test status
Simulation time 3524956168 ps
CPU time 1.91 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:03:42 PM PST 23
Peak memory 195900 kb
Host smart-7851fead-62fe-46f9-beab-214322c1b5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897156129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1897156129
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2377661120
Short name T1074
Test name
Test status
Simulation time 5310589122 ps
CPU time 10.85 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:46 PM PST 23
Peak memory 199816 kb
Host smart-641541bd-bc2c-4a6f-8fd5-4c922a9c9697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377661120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2377661120
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3694777368
Short name T1175
Test name
Test status
Simulation time 561747557645 ps
CPU time 173.52 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:06:30 PM PST 23
Peak memory 200156 kb
Host smart-fb3bec06-93f8-4534-8c60-e8c09fe6ce98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694777368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3694777368
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.866671842
Short name T200
Test name
Test status
Simulation time 33021336830 ps
CPU time 521.89 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:12:22 PM PST 23
Peak memory 208512 kb
Host smart-02290ccb-bd60-478f-b76f-57e4d2177f3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866671842 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.866671842
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1849170237
Short name T1117
Test name
Test status
Simulation time 530491892 ps
CPU time 1.91 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:03:47 PM PST 23
Peak memory 199372 kb
Host smart-ebe7535b-e1bc-4d21-b2fd-f2a1b6fd06e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849170237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1849170237
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3084668608
Short name T896
Test name
Test status
Simulation time 18352430417 ps
CPU time 32.49 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:16 PM PST 23
Peak memory 200188 kb
Host smart-2a784f49-f502-4089-8ac0-23edc2d05023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084668608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3084668608
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3642008763
Short name T228
Test name
Test status
Simulation time 35732074952 ps
CPU time 13.62 seconds
Started Dec 27 01:05:30 PM PST 23
Finished Dec 27 01:05:46 PM PST 23
Peak memory 200172 kb
Host smart-4bc265a0-df7b-4840-8f69-86b9c24f298b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642008763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3642008763
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2994163014
Short name T63
Test name
Test status
Simulation time 265741556080 ps
CPU time 1277.09 seconds
Started Dec 27 01:05:30 PM PST 23
Finished Dec 27 01:26:50 PM PST 23
Peak memory 224788 kb
Host smart-e909dab0-5bb3-4b73-8713-b7ec84dd5c45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994163014 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2994163014
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1761947977
Short name T367
Test name
Test status
Simulation time 44373024988 ps
CPU time 64.69 seconds
Started Dec 27 01:05:34 PM PST 23
Finished Dec 27 01:06:42 PM PST 23
Peak memory 200188 kb
Host smart-56128cf5-47e9-492a-9d09-6ef55a4dd8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761947977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1761947977
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2074051067
Short name T1120
Test name
Test status
Simulation time 17845989471 ps
CPU time 227.58 seconds
Started Dec 27 01:05:34 PM PST 23
Finished Dec 27 01:09:25 PM PST 23
Peak memory 215984 kb
Host smart-efe4ec27-643d-414e-81db-e5248a73f193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074051067 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2074051067
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1528762971
Short name T1182
Test name
Test status
Simulation time 29433695018 ps
CPU time 48.1 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:06:20 PM PST 23
Peak memory 200152 kb
Host smart-a1a21fe9-0582-49fa-b1b0-5ceee38c8ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528762971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1528762971
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.4189061008
Short name T1222
Test name
Test status
Simulation time 33452232610 ps
CPU time 85.49 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:07:00 PM PST 23
Peak memory 216720 kb
Host smart-4110b247-e6bc-48e6-9987-2827987cd7e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189061008 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.4189061008
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2959327028
Short name T277
Test name
Test status
Simulation time 30664541199 ps
CPU time 24.15 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:05:56 PM PST 23
Peak memory 200092 kb
Host smart-fd72f3aa-920c-4f6b-b3b8-c026625a4d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959327028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2959327028
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1970778430
Short name T777
Test name
Test status
Simulation time 8440629965 ps
CPU time 7.58 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:05:40 PM PST 23
Peak memory 199332 kb
Host smart-a47710b9-f2eb-4952-9c5d-7505a8e7c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970778430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1970778430
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.813968285
Short name T750
Test name
Test status
Simulation time 50338814191 ps
CPU time 927.22 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:20:59 PM PST 23
Peak memory 216580 kb
Host smart-8f5f00ce-3b1a-41d2-8c5d-e5f130b53da1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813968285 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.813968285
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3212475684
Short name T115
Test name
Test status
Simulation time 64953895539 ps
CPU time 172.57 seconds
Started Dec 27 01:05:31 PM PST 23
Finished Dec 27 01:08:26 PM PST 23
Peak memory 200176 kb
Host smart-66de5bf4-de04-45bb-bfc7-de62170d3b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212475684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3212475684
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1395642741
Short name T579
Test name
Test status
Simulation time 25821530972 ps
CPU time 157.62 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:08:10 PM PST 23
Peak memory 211024 kb
Host smart-c40dc8df-1d5f-4fba-baa8-3e8f0fac0d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395642741 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1395642741
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2137005204
Short name T194
Test name
Test status
Simulation time 160007596824 ps
CPU time 279.9 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:10:12 PM PST 23
Peak memory 200204 kb
Host smart-d572664d-16a0-4d7a-b2c1-1a4732a30117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137005204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2137005204
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2308497917
Short name T956
Test name
Test status
Simulation time 31712431012 ps
CPU time 119.75 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:07:31 PM PST 23
Peak memory 200412 kb
Host smart-8741ef9e-76d7-4539-9961-783a35cc890b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308497917 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2308497917
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1699477025
Short name T1164
Test name
Test status
Simulation time 18770367364 ps
CPU time 30.29 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:06:03 PM PST 23
Peak memory 200088 kb
Host smart-a218820c-52bb-4e36-a957-554fbec5b0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699477025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1699477025
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1592420072
Short name T239
Test name
Test status
Simulation time 73247993410 ps
CPU time 380.06 seconds
Started Dec 27 01:05:31 PM PST 23
Finished Dec 27 01:11:53 PM PST 23
Peak memory 216252 kb
Host smart-6dffd8f6-fad7-4fff-9ff7-8f7f2d56268a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592420072 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1592420072
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1241176132
Short name T792
Test name
Test status
Simulation time 3951189865 ps
CPU time 6.88 seconds
Started Dec 27 01:05:30 PM PST 23
Finished Dec 27 01:05:39 PM PST 23
Peak memory 197248 kb
Host smart-67bab953-8f41-404e-956b-27713bbf08c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241176132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1241176132
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3084342583
Short name T678
Test name
Test status
Simulation time 70594070905 ps
CPU time 614.07 seconds
Started Dec 27 01:05:33 PM PST 23
Finished Dec 27 01:15:50 PM PST 23
Peak memory 208492 kb
Host smart-eb03fcac-53a1-4425-90c2-9c6ea2dacb03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084342583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3084342583
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1658596752
Short name T309
Test name
Test status
Simulation time 54447948174 ps
CPU time 82.37 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:06:55 PM PST 23
Peak memory 200268 kb
Host smart-3a57e3f4-b6eb-4116-8538-3c378d96137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658596752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1658596752
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2412366962
Short name T992
Test name
Test status
Simulation time 24294245 ps
CPU time 0.55 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 195632 kb
Host smart-7c37a4e3-9ed5-4dd0-80fb-f80000cfb48a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412366962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2412366962
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2804798448
Short name T1126
Test name
Test status
Simulation time 110482714770 ps
CPU time 84.34 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:05:08 PM PST 23
Peak memory 199984 kb
Host smart-7219b03e-cfa8-4945-b628-eaf5fe4f06b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804798448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2804798448
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2349247297
Short name T1049
Test name
Test status
Simulation time 33148962870 ps
CPU time 13.69 seconds
Started Dec 27 01:03:47 PM PST 23
Finished Dec 27 01:04:10 PM PST 23
Peak memory 199572 kb
Host smart-64eb0c75-a746-4ccd-847a-2a0308e5f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349247297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2349247297
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.437440420
Short name T342
Test name
Test status
Simulation time 79013876437 ps
CPU time 33.97 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:04:15 PM PST 23
Peak memory 200224 kb
Host smart-e8f6ae87-71c9-4ea4-a1b0-9005996c6b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437440420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.437440420
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.672848719
Short name T799
Test name
Test status
Simulation time 52801594084 ps
CPU time 43.26 seconds
Started Dec 27 01:03:37 PM PST 23
Finished Dec 27 01:04:31 PM PST 23
Peak memory 200196 kb
Host smart-b9456de6-eedf-4639-ae17-cd46abff0b57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672848719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.672848719
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3428808632
Short name T972
Test name
Test status
Simulation time 184767214469 ps
CPU time 212.7 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:07:18 PM PST 23
Peak memory 200236 kb
Host smart-2c4907d6-fb1f-4855-8488-e8d7190206df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428808632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3428808632
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2448299855
Short name T803
Test name
Test status
Simulation time 12763068084 ps
CPU time 7.69 seconds
Started Dec 27 01:03:49 PM PST 23
Finished Dec 27 01:04:05 PM PST 23
Peak memory 199944 kb
Host smart-1cc2abaf-9ea9-4e19-bb1e-0466b7a014dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448299855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2448299855
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3380481034
Short name T909
Test name
Test status
Simulation time 91088303462 ps
CPU time 174.97 seconds
Started Dec 27 01:03:45 PM PST 23
Finished Dec 27 01:06:45 PM PST 23
Peak memory 208688 kb
Host smart-04161685-d7d2-4304-bdda-f7547efbe397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380481034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3380481034
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2521086546
Short name T165
Test name
Test status
Simulation time 17048327304 ps
CPU time 952.37 seconds
Started Dec 27 01:03:41 PM PST 23
Finished Dec 27 01:19:38 PM PST 23
Peak memory 200092 kb
Host smart-0814c1a8-19e3-4eb3-b653-e5469f5f7d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521086546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2521086546
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.202910513
Short name T609
Test name
Test status
Simulation time 2660459288 ps
CPU time 22.39 seconds
Started Dec 27 01:03:46 PM PST 23
Finished Dec 27 01:04:13 PM PST 23
Peak memory 198800 kb
Host smart-982971e8-296e-438f-a4a4-3f850fae412a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202910513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.202910513
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3079818969
Short name T1184
Test name
Test status
Simulation time 145814731899 ps
CPU time 115.88 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:05:31 PM PST 23
Peak memory 200180 kb
Host smart-5aa9c7e6-5eaa-4f69-ac12-9df1b253f6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079818969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3079818969
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2875402255
Short name T593
Test name
Test status
Simulation time 3906292422 ps
CPU time 2.13 seconds
Started Dec 27 01:03:50 PM PST 23
Finished Dec 27 01:04:01 PM PST 23
Peak memory 196080 kb
Host smart-bd2411d3-909f-4c14-a256-799c5e438f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875402255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2875402255
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2383809644
Short name T598
Test name
Test status
Simulation time 496671095 ps
CPU time 1.41 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:43 PM PST 23
Peak memory 198684 kb
Host smart-41a01771-f128-4bfd-8f22-1c129fd4bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383809644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2383809644
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1540506951
Short name T246
Test name
Test status
Simulation time 450750087732 ps
CPU time 410.51 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:10:33 PM PST 23
Peak memory 200096 kb
Host smart-9dbe7001-2f74-4f14-b23e-13a12b022b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540506951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1540506951
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.937736485
Short name T67
Test name
Test status
Simulation time 26624150254 ps
CPU time 202.32 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:07:05 PM PST 23
Peak memory 211516 kb
Host smart-370c5f59-08a7-4868-a63d-e5f02d39f700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937736485 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.937736485
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3994060597
Short name T441
Test name
Test status
Simulation time 2818715562 ps
CPU time 2.73 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:45 PM PST 23
Peak memory 199488 kb
Host smart-926ec734-abdd-43ed-ac48-3d7571ced753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994060597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3994060597
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.621174677
Short name T642
Test name
Test status
Simulation time 26301691487 ps
CPU time 42.43 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:04:19 PM PST 23
Peak memory 200140 kb
Host smart-372e026a-e1ae-4c75-b34d-ef0ea10f8070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621174677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.621174677
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2756944802
Short name T333
Test name
Test status
Simulation time 40259348344 ps
CPU time 32.08 seconds
Started Dec 27 01:05:33 PM PST 23
Finished Dec 27 01:06:08 PM PST 23
Peak memory 200204 kb
Host smart-884bb75b-0211-43c8-a5d7-85a00a1b6a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756944802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2756944802
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1698452807
Short name T62
Test name
Test status
Simulation time 67374847108 ps
CPU time 412.12 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:12:24 PM PST 23
Peak memory 216392 kb
Host smart-94d31798-b2b4-4179-9278-3870d02d2174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698452807 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1698452807
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3173513234
Short name T133
Test name
Test status
Simulation time 113025440175 ps
CPU time 165.02 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:08:19 PM PST 23
Peak memory 200164 kb
Host smart-4e9f20dc-e58d-4dbf-bbc4-649fd1c5aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173513234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3173513234
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3473793937
Short name T462
Test name
Test status
Simulation time 3098748504 ps
CPU time 58.82 seconds
Started Dec 27 01:05:28 PM PST 23
Finished Dec 27 01:06:31 PM PST 23
Peak memory 200540 kb
Host smart-04be04e1-44d4-42cf-aec2-7a1296009fb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473793937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3473793937
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.8418271
Short name T663
Test name
Test status
Simulation time 84624718515 ps
CPU time 40.48 seconds
Started Dec 27 01:05:34 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 200188 kb
Host smart-2b77a2f6-2c88-43ac-b70f-5ac8344920b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8418271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.8418271
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1520287506
Short name T58
Test name
Test status
Simulation time 49883112957 ps
CPU time 1562.76 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:31:35 PM PST 23
Peak memory 216772 kb
Host smart-e9ae298d-c75e-4315-85b8-3fb6a5ba6df1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520287506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1520287506
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1345434953
Short name T26
Test name
Test status
Simulation time 34452123228 ps
CPU time 444.78 seconds
Started Dec 27 01:05:31 PM PST 23
Finished Dec 27 01:12:58 PM PST 23
Peak memory 216708 kb
Host smart-9f93809b-6b54-445e-8ee0-3c3165fae5ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345434953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1345434953
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1846983034
Short name T281
Test name
Test status
Simulation time 57345884700 ps
CPU time 29.96 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:06:04 PM PST 23
Peak memory 200252 kb
Host smart-53251656-6f91-4d63-a2ac-f6f55fd84efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846983034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1846983034
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2074930610
Short name T312
Test name
Test status
Simulation time 296429617896 ps
CPU time 917.12 seconds
Started Dec 27 01:05:34 PM PST 23
Finished Dec 27 01:20:54 PM PST 23
Peak memory 225168 kb
Host smart-cff7271c-2ccc-42c5-8bba-be3d87da7baf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074930610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2074930610
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2067121043
Short name T780
Test name
Test status
Simulation time 237059719009 ps
CPU time 156.33 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:08:11 PM PST 23
Peak memory 200276 kb
Host smart-a51da6be-72ba-45d7-af22-43cc37c64667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067121043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2067121043
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2066941754
Short name T964
Test name
Test status
Simulation time 91622185884 ps
CPU time 911.55 seconds
Started Dec 27 01:05:31 PM PST 23
Finished Dec 27 01:20:45 PM PST 23
Peak memory 225128 kb
Host smart-8b1769ce-fcb3-485a-a618-e2d92ebe0b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066941754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2066941754
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3580957224
Short name T57
Test name
Test status
Simulation time 28760582136 ps
CPU time 222.46 seconds
Started Dec 27 01:05:34 PM PST 23
Finished Dec 27 01:09:20 PM PST 23
Peak memory 211556 kb
Host smart-33328187-8617-4caa-b6fb-0a70de80857d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580957224 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3580957224
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1890184325
Short name T164
Test name
Test status
Simulation time 24240340226 ps
CPU time 36.92 seconds
Started Dec 27 01:05:29 PM PST 23
Finished Dec 27 01:06:09 PM PST 23
Peak memory 199744 kb
Host smart-fee11ada-135f-4558-b0db-1b6f0d89d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890184325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1890184325
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2416173204
Short name T674
Test name
Test status
Simulation time 21619285382 ps
CPU time 153.28 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:08:07 PM PST 23
Peak memory 209800 kb
Host smart-7158a56c-85a0-4916-ba16-6f8cf96cec0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416173204 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2416173204
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3842738164
Short name T337
Test name
Test status
Simulation time 12035259809 ps
CPU time 20.81 seconds
Started Dec 27 01:05:38 PM PST 23
Finished Dec 27 01:06:01 PM PST 23
Peak memory 200128 kb
Host smart-a431bb7d-1b16-40c1-89c9-b7327b68eb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842738164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3842738164
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2480084341
Short name T1201
Test name
Test status
Simulation time 633673068105 ps
CPU time 602.44 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:15:37 PM PST 23
Peak memory 216612 kb
Host smart-2f202f22-b232-4d8b-afcf-c91befa05ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480084341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2480084341
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2213028802
Short name T1110
Test name
Test status
Simulation time 49074203355 ps
CPU time 64.59 seconds
Started Dec 27 01:05:38 PM PST 23
Finished Dec 27 01:06:45 PM PST 23
Peak memory 200128 kb
Host smart-03369cf9-5138-47eb-928b-07f0eff52d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213028802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2213028802
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1546216535
Short name T1053
Test name
Test status
Simulation time 10769243697 ps
CPU time 93.16 seconds
Started Dec 27 01:05:38 PM PST 23
Finished Dec 27 01:07:13 PM PST 23
Peak memory 200468 kb
Host smart-f4e71ce9-f6e3-4df7-a9b8-fec3e416e0f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546216535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1546216535
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3823842034
Short name T819
Test name
Test status
Simulation time 25048157 ps
CPU time 0.55 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:36 PM PST 23
Peak memory 195616 kb
Host smart-20365f75-1b73-4241-9621-9d161b85067c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823842034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3823842034
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3906522738
Short name T445
Test name
Test status
Simulation time 166556351316 ps
CPU time 46.41 seconds
Started Dec 27 01:03:44 PM PST 23
Finished Dec 27 01:04:36 PM PST 23
Peak memory 200196 kb
Host smart-dd84ec3c-c92f-4b1c-ab8e-ce32660e2956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906522738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3906522738
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1467433287
Short name T376
Test name
Test status
Simulation time 114212535373 ps
CPU time 40.77 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:23 PM PST 23
Peak memory 200208 kb
Host smart-ec942d01-9729-4b9f-bfa4-5f1d9770599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467433287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1467433287
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2776239918
Short name T1014
Test name
Test status
Simulation time 106271882995 ps
CPU time 11.82 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:03:54 PM PST 23
Peak memory 198328 kb
Host smart-5ba15257-8a21-4292-81b3-4c1f23d80a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776239918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2776239918
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2169688030
Short name T116
Test name
Test status
Simulation time 547398647838 ps
CPU time 900.8 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:18:43 PM PST 23
Peak memory 199688 kb
Host smart-f7c21bf2-05ea-4757-87d3-0d5946ac6f8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169688030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2169688030
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4021400444
Short name T578
Test name
Test status
Simulation time 98206797502 ps
CPU time 236.78 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:07:33 PM PST 23
Peak memory 200120 kb
Host smart-fb303813-db09-45e4-a9a5-5c86c7e848e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021400444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4021400444
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3999731741
Short name T19
Test name
Test status
Simulation time 6879819957 ps
CPU time 6.02 seconds
Started Dec 27 01:03:33 PM PST 23
Finished Dec 27 01:03:41 PM PST 23
Peak memory 199540 kb
Host smart-0b699a1c-fe78-4937-8c54-b2104451e588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999731741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3999731741
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.4043221177
Short name T977
Test name
Test status
Simulation time 127009856988 ps
CPU time 103.26 seconds
Started Dec 27 01:03:32 PM PST 23
Finished Dec 27 01:05:16 PM PST 23
Peak memory 208664 kb
Host smart-9a66644b-9faf-4abc-b7ad-b5fb3374f3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043221177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.4043221177
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2024299792
Short name T288
Test name
Test status
Simulation time 9937799552 ps
CPU time 506.02 seconds
Started Dec 27 01:03:31 PM PST 23
Finished Dec 27 01:11:58 PM PST 23
Peak memory 200188 kb
Host smart-3744d087-084d-47ce-a9c4-060c05c3a5c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024299792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2024299792
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2110237132
Short name T820
Test name
Test status
Simulation time 2809233284 ps
CPU time 20.32 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:04 PM PST 23
Peak memory 198588 kb
Host smart-2dae8d76-a59b-4047-a081-4437dfe6be65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110237132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2110237132
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2815686213
Short name T835
Test name
Test status
Simulation time 141698877793 ps
CPU time 51.65 seconds
Started Dec 27 01:03:34 PM PST 23
Finished Dec 27 01:04:28 PM PST 23
Peak memory 200080 kb
Host smart-fc01647f-f16b-46bd-b5e7-874bf529c28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815686213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2815686213
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1744583844
Short name T607
Test name
Test status
Simulation time 35925619770 ps
CPU time 50.42 seconds
Started Dec 27 01:03:39 PM PST 23
Finished Dec 27 01:04:33 PM PST 23
Peak memory 196048 kb
Host smart-7085113e-f518-41ec-810f-b42d95a331f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744583844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1744583844
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.40505272
Short name T1006
Test name
Test status
Simulation time 699293764 ps
CPU time 1.94 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:03:46 PM PST 23
Peak memory 198604 kb
Host smart-c7ef5e49-912c-47e9-9947-9deab74f7833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40505272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.40505272
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.486023638
Short name T883
Test name
Test status
Simulation time 390817790390 ps
CPU time 977.39 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:20:00 PM PST 23
Peak memory 208568 kb
Host smart-9e1924b9-45b0-4b9f-8bf6-0483f5572c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486023638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.486023638
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3752249420
Short name T1071
Test name
Test status
Simulation time 190266001336 ps
CPU time 236.21 seconds
Started Dec 27 01:03:38 PM PST 23
Finished Dec 27 01:07:38 PM PST 23
Peak memory 216244 kb
Host smart-8f6b2ef0-13f4-4d0a-8c15-568c7196f5a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752249420 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3752249420
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1143390943
Short name T982
Test name
Test status
Simulation time 1235913308 ps
CPU time 1.45 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:03:47 PM PST 23
Peak memory 199216 kb
Host smart-67ffb5cb-c38b-40c9-a168-4074cfc9f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143390943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1143390943
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2591295131
Short name T885
Test name
Test status
Simulation time 57326353135 ps
CPU time 22.13 seconds
Started Dec 27 01:03:40 PM PST 23
Finished Dec 27 01:04:06 PM PST 23
Peak memory 200184 kb
Host smart-ccf5dca1-7342-404d-9ee9-faac4efd53c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591295131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2591295131
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2696488846
Short name T881
Test name
Test status
Simulation time 55455955088 ps
CPU time 22.87 seconds
Started Dec 27 01:05:38 PM PST 23
Finished Dec 27 01:06:03 PM PST 23
Peak memory 200128 kb
Host smart-32c7a64c-3f1d-41a4-9a1d-2994bfda5048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696488846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2696488846
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.4104138234
Short name T76
Test name
Test status
Simulation time 126823037037 ps
CPU time 332.11 seconds
Started Dec 27 01:05:43 PM PST 23
Finished Dec 27 01:11:16 PM PST 23
Peak memory 226084 kb
Host smart-310872b1-cf98-4647-a15e-5084380bedb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104138234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.4104138234
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1927745337
Short name T575
Test name
Test status
Simulation time 52990192913 ps
CPU time 145.31 seconds
Started Dec 27 01:05:41 PM PST 23
Finished Dec 27 01:08:08 PM PST 23
Peak memory 212068 kb
Host smart-28e1f1c1-68d2-4b2e-a696-4814ea47bce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927745337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1927745337
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1000861689
Short name T307
Test name
Test status
Simulation time 96200358780 ps
CPU time 133.94 seconds
Started Dec 27 01:05:41 PM PST 23
Finished Dec 27 01:07:57 PM PST 23
Peak memory 199972 kb
Host smart-a8ece5b5-2a7e-4863-b933-2ac285177a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000861689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1000861689
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2233769293
Short name T1170
Test name
Test status
Simulation time 40053044730 ps
CPU time 360.16 seconds
Started Dec 27 01:05:34 PM PST 23
Finished Dec 27 01:11:37 PM PST 23
Peak memory 216916 kb
Host smart-7f829ed2-5855-427d-b23c-1abcfa739f37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233769293 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2233769293
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1753979026
Short name T214
Test name
Test status
Simulation time 8105745237 ps
CPU time 10.74 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:06:03 PM PST 23
Peak memory 199928 kb
Host smart-902100d1-a35f-405d-9b4c-501c1a31f584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753979026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1753979026
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3473136457
Short name T104
Test name
Test status
Simulation time 24521606490 ps
CPU time 40.93 seconds
Started Dec 27 01:05:33 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 200028 kb
Host smart-5ee74986-b7cd-4b5e-9770-74e100a822e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473136457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3473136457
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3885911199
Short name T826
Test name
Test status
Simulation time 85955783292 ps
CPU time 1294.28 seconds
Started Dec 27 01:05:43 PM PST 23
Finished Dec 27 01:27:18 PM PST 23
Peak memory 232948 kb
Host smart-455f86fd-05f1-4760-90ca-6bb05f8452f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885911199 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3885911199
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.64138926
Short name T611
Test name
Test status
Simulation time 22932772302 ps
CPU time 41.05 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:06:16 PM PST 23
Peak memory 200224 kb
Host smart-114e0f2e-8430-4dd4-8551-76e7517dea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64138926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.64138926
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.439278418
Short name T1127
Test name
Test status
Simulation time 39784157105 ps
CPU time 139.19 seconds
Started Dec 27 01:05:48 PM PST 23
Finished Dec 27 01:08:08 PM PST 23
Peak memory 216032 kb
Host smart-9c61b30f-28cc-4d3a-aebd-4a2520fb71eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439278418 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.439278418
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.4260314075
Short name T187
Test name
Test status
Simulation time 75578043030 ps
CPU time 20.25 seconds
Started Dec 27 01:05:45 PM PST 23
Finished Dec 27 01:06:06 PM PST 23
Peak memory 199664 kb
Host smart-62cae1b5-865b-44f6-936b-77c6d988c318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260314075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.4260314075
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3774000125
Short name T463
Test name
Test status
Simulation time 32554067984 ps
CPU time 568.74 seconds
Started Dec 27 01:05:32 PM PST 23
Finished Dec 27 01:15:04 PM PST 23
Peak memory 214776 kb
Host smart-3e61c9b9-35bf-4bde-9119-74c8d9e22623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774000125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3774000125
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2262978206
Short name T284
Test name
Test status
Simulation time 162036833125 ps
CPU time 96.56 seconds
Started Dec 27 01:05:43 PM PST 23
Finished Dec 27 01:07:21 PM PST 23
Peak memory 200252 kb
Host smart-71a59289-33a3-4cf8-873e-5450a6b858bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262978206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2262978206
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1364006501
Short name T695
Test name
Test status
Simulation time 33815997254 ps
CPU time 58.73 seconds
Started Dec 27 01:05:54 PM PST 23
Finished Dec 27 01:06:57 PM PST 23
Peak memory 200212 kb
Host smart-afeb52af-be73-4570-8bed-75d1f56d9ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364006501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1364006501
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3922918408
Short name T1123
Test name
Test status
Simulation time 137754335190 ps
CPU time 1521.77 seconds
Started Dec 27 01:05:43 PM PST 23
Finished Dec 27 01:31:06 PM PST 23
Peak memory 217420 kb
Host smart-2710aa3e-d6d2-4039-af1e-3d3249923796
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922918408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3922918408
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.765665236
Short name T353
Test name
Test status
Simulation time 58276590747 ps
CPU time 78.91 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:07:11 PM PST 23
Peak memory 200056 kb
Host smart-4e752741-d876-49ec-b908-28262ca4a373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765665236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.765665236
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1511701048
Short name T1146
Test name
Test status
Simulation time 136393332561 ps
CPU time 365.58 seconds
Started Dec 27 01:05:49 PM PST 23
Finished Dec 27 01:11:57 PM PST 23
Peak memory 216936 kb
Host smart-ca0b03df-6753-4d3c-ae3e-3b2f2e0d9a31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511701048 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1511701048
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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