Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	121024	1			T2	5		T3	8		T5	5
all_values[1]	121024	1			T2	5		T3	8		T5	5
all_values[2]	121024	1			T2	5		T3	8		T5	5
all_values[3]	121024	1			T2	5		T3	8		T5	5
all_values[4]	121024	1			T2	5		T3	8		T5	5
all_values[5]	121024	1			T2	5		T3	8		T5	5
all_values[6]	121024	1			T2	5		T3	8		T5	5
all_values[7]	121024	1			T2	5		T3	8		T5	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

494041

1

T2

23

T3

35

T5

24

auto[1]

474151

1

T2

17

T3

29

T5

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

950162

1

T2

19

T3

37

T5

26

auto[1]

18030

1

T2

21

T3

27

T5

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	60214	1			T3	5		T5	1		T38	2
all_values[0]	auto[0]	auto[1]	2666	1			T3	1		T49	1		T97	1
all_values[0]	auto[1]	auto[0]	55761	1			T2	2		T3	2		T5	4
all_values[0]	auto[1]	auto[1]	2383	1			T2	3		T38	4		T96	2
all_values[1]	auto[0]	auto[0]	61531	1			T2	1		T3	1		T5	1
all_values[1]	auto[0]	auto[1]	2565	1			T3	2		T5	3		T38	3
all_values[1]	auto[1]	auto[0]	54202	1			T2	1		T3	1		T5	1
all_values[1]	auto[1]	auto[1]	2726	1			T2	3		T3	4		T38	1
all_values[2]	auto[0]	auto[0]	58647	1			T2	2		T3	4		T38	8
all_values[2]	auto[0]	auto[1]	2712	1			T2	3		T3	2		T49	1
all_values[2]	auto[1]	auto[0]	57354	1			T3	1		T5	3		T49	3
all_values[2]	auto[1]	auto[1]	2311	1			T3	1		T5	2		T111	2
all_values[3]	auto[0]	auto[0]	57836	1			T2	3		T3	2		T5	3
all_values[3]	auto[0]	auto[1]	230	1			T2	2		T3	2		T38	1
all_values[3]	auto[1]	auto[0]	62749	1			T3	1		T96	1		T97	1
all_values[3]	auto[1]	auto[1]	209	1			T3	3		T5	2		T38	2
all_values[4]	auto[0]	auto[0]	62903	1			T2	1		T3	2		T5	3
all_values[4]	auto[0]	auto[1]	528	1			T2	2		T3	3		T5	1
all_values[4]	auto[1]	auto[0]	57162	1			T2	1		T3	2		T38	2
all_values[4]	auto[1]	auto[1]	431	1			T2	1		T3	1		T5	1
all_values[5]	auto[0]	auto[0]	61247	1			T3	1		T5	4		T38	5
all_values[5]	auto[0]	auto[1]	144	1			T3	2		T38	2		T96	3
all_values[5]	auto[1]	auto[0]	59476	1			T2	2		T3	4		T38	1
all_values[5]	auto[1]	auto[1]	157	1			T2	3		T3	1		T5	1
all_values[6]	auto[0]	auto[0]	60513	1			T2	2		T3	1		T5	1
all_values[6]	auto[0]	auto[1]	134	1			T2	2		T5	3		T49	2
all_values[6]	auto[1]	auto[0]	60241	1			T3	7		T38	4		T49	1
all_values[6]	auto[1]	auto[1]	136	1			T2	1		T5	1		T38	2
all_values[7]	auto[0]	auto[0]	61839	1			T2	4		T3	2		T5	4
all_values[7]	auto[0]	auto[1]	332	1			T2	1		T3	5		T38	2
all_values[7]	auto[1]	auto[0]	58487	1			T3	1		T5	1		T96	1
all_values[7]	auto[1]	auto[1]	366	1			T38	1		T96	2		T97	1